4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 /* Sparc MMU emulation */
29 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
33 spin_lock(&global_cpu_lock);
38 spin_unlock(&global_cpu_lock);
41 #if defined(CONFIG_USER_ONLY)
43 int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
44 int is_user, int is_softmmu)
47 env->exception_index = TT_TFAULT;
49 env->exception_index = TT_DFAULT;
55 #define MMUSUFFIX _mmu
56 #define GETPC() (__builtin_return_address(0))
59 #include "softmmu_template.h"
62 #include "softmmu_template.h"
65 #include "softmmu_template.h"
68 #include "softmmu_template.h"
71 /* try to fill the TLB and return an exception if error. If retaddr is
72 NULL, it means that the function was called in C code (i.e. not
73 from generated code or from helper.c) */
74 /* XXX: fix it to restore all registers */
75 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
82 /* XXX: hack to restore env in all cases, even if not called from
87 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
90 /* now we have a real cpu fault */
91 pc = (unsigned long)retaddr;
94 /* the PC is inside the translated code. It means that we have
95 a virtual CPU fault */
96 cpu_restore_state(tb, env, pc, (void *)T2);
104 #ifndef TARGET_SPARC64
105 static const int access_table[8][8] = {
106 { 0, 0, 0, 0, 2, 0, 3, 3 },
107 { 0, 0, 0, 0, 2, 0, 0, 0 },
108 { 2, 2, 0, 0, 0, 2, 3, 3 },
109 { 2, 2, 0, 0, 0, 2, 0, 0 },
110 { 2, 0, 2, 0, 2, 2, 3, 3 },
111 { 2, 0, 2, 0, 2, 0, 2, 0 },
112 { 2, 2, 2, 0, 2, 2, 3, 3 },
113 { 2, 2, 2, 0, 2, 2, 2, 0 }
117 static const int rw_table[2][8] = {
118 { 0, 1, 0, 1, 0, 1, 0, 1 },
119 { 0, 1, 0, 1, 0, 0, 0, 0 }
122 int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
123 int *access_index, target_ulong address, int rw,
126 int access_perms = 0;
127 target_phys_addr_t pde_ptr;
129 target_ulong virt_addr;
130 int error_code = 0, is_dirty;
131 unsigned long page_offset;
133 virt_addr = address & TARGET_PAGE_MASK;
134 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
136 *prot = PAGE_READ | PAGE_WRITE;
140 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
141 *physical = 0xfffff000;
143 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
144 /* Context base + context number */
145 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
146 pde = ldl_phys(pde_ptr);
149 switch (pde & PTE_ENTRYTYPE_MASK) {
151 case 0: /* Invalid */
153 case 2: /* L0 PTE, maybe should not happen? */
154 case 3: /* Reserved */
157 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
158 pde = ldl_phys(pde_ptr);
160 switch (pde & PTE_ENTRYTYPE_MASK) {
162 case 0: /* Invalid */
163 return (1 << 8) | (1 << 2);
164 case 3: /* Reserved */
165 return (1 << 8) | (4 << 2);
167 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
168 pde = ldl_phys(pde_ptr);
170 switch (pde & PTE_ENTRYTYPE_MASK) {
172 case 0: /* Invalid */
173 return (2 << 8) | (1 << 2);
174 case 3: /* Reserved */
175 return (2 << 8) | (4 << 2);
177 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
178 pde = ldl_phys(pde_ptr);
180 switch (pde & PTE_ENTRYTYPE_MASK) {
182 case 0: /* Invalid */
183 return (3 << 8) | (1 << 2);
184 case 1: /* PDE, should not happen */
185 case 3: /* Reserved */
186 return (3 << 8) | (4 << 2);
188 virt_addr = address & TARGET_PAGE_MASK;
189 page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
193 virt_addr = address & ~0x3ffff;
194 page_offset = address & 0x3ffff;
198 virt_addr = address & ~0xffffff;
199 page_offset = address & 0xffffff;
203 /* update page modified and dirty bits */
204 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
205 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
206 pde |= PG_ACCESSED_MASK;
208 pde |= PG_MODIFIED_MASK;
209 stl_phys_notdirty(pde_ptr, pde);
212 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
213 error_code = access_table[*access_index][access_perms];
214 if (error_code && !(env->mmuregs[0] & MMU_NF))
217 /* the page can be put in the TLB */
219 if (pde & PG_MODIFIED_MASK) {
220 /* only set write access if already dirty... otherwise wait
222 if (rw_table[is_user][access_perms])
226 /* Even if large ptes, we map only one 4KB page in the cache to
227 avoid filling it too fast */
228 *physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
232 /* Perform address translation */
233 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
234 int is_user, int is_softmmu)
236 target_ulong virt_addr;
237 target_phys_addr_t paddr;
239 int error_code = 0, prot, ret = 0, access_index;
241 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
242 if (error_code == 0) {
243 virt_addr = address & TARGET_PAGE_MASK;
244 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
245 ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
249 if (env->mmuregs[3]) /* Fault status register */
250 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
251 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
252 env->mmuregs[4] = address; /* Fault address register */
254 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
255 // No fault mode: if a mapping is available, just override
256 // permissions. If no mapping is available, redirect accesses to
257 // neverland. Fake/overridden mappings will be flushed when
258 // switching to normal mode.
259 vaddr = address & TARGET_PAGE_MASK;
260 prot = PAGE_READ | PAGE_WRITE;
261 ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
265 env->exception_index = TT_TFAULT;
267 env->exception_index = TT_DFAULT;
272 static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
273 int *access_index, target_ulong address, int rw,
279 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
280 *physical = address & 0xffffffff;
281 *prot = PAGE_READ | PAGE_WRITE;
285 for (i = 0; i < 64; i++) {
286 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
287 switch (env->dtlb_tte[i] >> 60) {
290 mask = 0xffffffffffffe000ULL;
293 mask = 0xffffffffffff0000ULL;
296 mask = 0xfffffffffff80000ULL;
299 mask = 0xffffffffffc00000ULL;
302 // ctx match, vaddr match?
303 if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
304 (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
306 if (((env->dtlb_tte[i] & 0x4) && !(env->pstate & PS_PRIV)) ||
307 (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
308 env->exception_index = TT_DFAULT;
311 *physical = env->dtlb_tte[i] & 0xffffe000;
313 if (env->dtlb_tte[i] & 0x2)
319 env->exception_index = TT_DFAULT;
323 static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
324 int *access_index, target_ulong address, int rw,
330 if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
331 *physical = address & 0xffffffff;
335 for (i = 0; i < 64; i++) {
336 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
337 switch (env->itlb_tte[i] >> 60) {
340 mask = 0xffffffffffffe000ULL;
343 mask = 0xffffffffffff0000ULL;
346 mask = 0xfffffffffff80000ULL;
349 mask = 0xffffffffffc00000ULL;
352 // ctx match, vaddr match?
353 if (env->immuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
354 (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
356 if ((env->itlb_tte[i] & 0x4) && !(env->pstate & PS_PRIV)) {
357 env->exception_index = TT_TFAULT;
360 *physical = env->itlb_tte[i] & 0xffffe000;
366 env->exception_index = TT_TFAULT;
370 int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
371 int *access_index, target_ulong address, int rw,
375 return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
377 return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
380 /* Perform address translation */
381 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
382 int is_user, int is_softmmu)
384 target_ulong virt_addr;
385 target_phys_addr_t paddr;
387 int error_code = 0, prot, ret = 0, access_index;
389 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
390 if (error_code == 0) {
391 virt_addr = address & TARGET_PAGE_MASK;
392 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
393 ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
403 void memcpy32(target_ulong *dst, const target_ulong *src)
415 void set_cwp(int new_cwp)
417 /* put the modified wrap registers at their proper location */
418 if (env->cwp == (NWINDOWS - 1))
419 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
421 /* put the wrap registers at their temporary location */
422 if (new_cwp == (NWINDOWS - 1))
423 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
424 env->regwptr = env->regbase + (new_cwp * 16);
425 REGWPTR = env->regwptr;
428 void cpu_set_cwp(CPUState *env1, int new_cwp)
432 target_ulong *saved_regwptr;
437 saved_regwptr = REGWPTR;
443 REGWPTR = saved_regwptr;
447 #ifdef TARGET_SPARC64
448 void do_interrupt(int intno)
451 if (loglevel & CPU_LOG_INT) {
453 fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
456 env->npc, env->regwptr[6]);
457 cpu_dump_state(env, logfile, fprintf, 0);
463 fprintf(logfile, " code=");
464 ptr = (uint8_t *)env->pc;
465 for(i = 0; i < 16; i++) {
466 fprintf(logfile, " %02x", ldub(ptr + i));
468 fprintf(logfile, "\n");
474 #if !defined(CONFIG_USER_ONLY)
475 if (env->pstate & PS_IE) {
476 cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
480 env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
481 ((env->pstate & 0xfff) << 8) | (env->cwp & 0xff);
482 env->tpc[env->tl] = env->pc;
483 env->tnpc[env->tl] = env->npc;
484 env->tt[env->tl] = intno;
485 env->tbr = env->tbr | (env->tl > 1) ? 1 << 14 : 0 | (intno << 4);
488 env->npc = env->pc + 4;
489 env->exception_index = 0;
492 void do_interrupt(int intno)
497 if (loglevel & CPU_LOG_INT) {
499 fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
502 env->npc, env->regwptr[6]);
503 cpu_dump_state(env, logfile, fprintf, 0);
509 fprintf(logfile, " code=");
510 ptr = (uint8_t *)env->pc;
511 for(i = 0; i < 16; i++) {
512 fprintf(logfile, " %02x", ldub(ptr + i));
514 fprintf(logfile, "\n");
520 #if !defined(CONFIG_USER_ONLY)
521 if (env->psret == 0) {
522 cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
527 cwp = (env->cwp - 1) & (NWINDOWS - 1);
529 env->regwptr[9] = env->pc;
530 env->regwptr[10] = env->npc;
531 env->psrps = env->psrs;
533 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
535 env->npc = env->pc + 4;
536 env->exception_index = 0;
539 target_ulong mmu_probe(target_ulong address, int mmulev)
541 target_phys_addr_t pde_ptr;
544 /* Context base + context number */
545 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
546 pde = ldl_phys(pde_ptr);
548 switch (pde & PTE_ENTRYTYPE_MASK) {
550 case 0: /* Invalid */
551 case 2: /* PTE, maybe should not happen? */
552 case 3: /* Reserved */
557 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
558 pde = ldl_phys(pde_ptr);
560 switch (pde & PTE_ENTRYTYPE_MASK) {
562 case 0: /* Invalid */
563 case 3: /* Reserved */
570 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
571 pde = ldl_phys(pde_ptr);
573 switch (pde & PTE_ENTRYTYPE_MASK) {
575 case 0: /* Invalid */
576 case 3: /* Reserved */
583 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
584 pde = ldl_phys(pde_ptr);
586 switch (pde & PTE_ENTRYTYPE_MASK) {
588 case 0: /* Invalid */
589 case 1: /* PDE, should not happen */
590 case 3: /* Reserved */
604 target_ulong va, va1, va2;
605 unsigned int n, m, o;
606 target_phys_addr_t pde_ptr, pa;
609 printf("MMU dump:\n");
610 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
611 pde = ldl_phys(pde_ptr);
612 printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
613 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
614 pde_ptr = mmu_probe(va, 2);
616 pa = cpu_get_phys_page_debug(env, va);
617 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
618 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
619 pde_ptr = mmu_probe(va1, 1);
621 pa = cpu_get_phys_page_debug(env, va1);
622 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
623 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
624 pde_ptr = mmu_probe(va2, 0);
626 pa = cpu_get_phys_page_debug(env, va2);
627 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
634 printf("MMU dump ends\n");