4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 /* Sparc MMU emulation */
29 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
33 spin_lock(&global_cpu_lock);
38 spin_unlock(&global_cpu_lock);
41 #if defined(CONFIG_USER_ONLY)
43 int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
44 int is_user, int is_softmmu)
46 env->mmuregs[4] = address;
48 env->exception_index = TT_TFAULT;
50 env->exception_index = TT_DFAULT;
56 #define MMUSUFFIX _mmu
57 #define GETPC() (__builtin_return_address(0))
60 #include "softmmu_template.h"
63 #include "softmmu_template.h"
66 #include "softmmu_template.h"
69 #include "softmmu_template.h"
72 /* try to fill the TLB and return an exception if error. If retaddr is
73 NULL, it means that the function was called in C code (i.e. not
74 from generated code or from helper.c) */
75 /* XXX: fix it to restore all registers */
76 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
83 /* XXX: hack to restore env in all cases, even if not called from
88 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
91 /* now we have a real cpu fault */
92 pc = (unsigned long)retaddr;
95 /* the PC is inside the translated code. It means that we have
96 a virtual CPU fault */
97 cpu_restore_state(tb, env, pc, NULL);
105 static const int access_table[8][8] = {
106 { 0, 0, 0, 0, 2, 0, 3, 3 },
107 { 0, 0, 0, 0, 2, 0, 0, 0 },
108 { 2, 2, 0, 0, 0, 2, 3, 3 },
109 { 2, 2, 0, 0, 0, 2, 0, 0 },
110 { 2, 0, 2, 0, 2, 2, 3, 3 },
111 { 2, 0, 2, 0, 2, 0, 2, 0 },
112 { 2, 2, 2, 0, 2, 2, 3, 3 },
113 { 2, 2, 2, 0, 2, 2, 2, 0 }
117 static const int rw_table[2][8] = {
118 { 0, 1, 0, 1, 0, 1, 0, 1 },
119 { 0, 1, 0, 1, 0, 0, 0, 0 }
122 int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
123 int *access_index, target_ulong address, int rw,
126 int access_perms = 0;
127 target_phys_addr_t pde_ptr;
129 target_ulong virt_addr;
130 int error_code = 0, is_dirty;
131 unsigned long page_offset;
133 virt_addr = address & TARGET_PAGE_MASK;
134 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
136 *prot = PAGE_READ | PAGE_WRITE;
140 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
142 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
143 /* Context base + context number */
144 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
145 pde = ldl_phys(pde_ptr);
148 switch (pde & PTE_ENTRYTYPE_MASK) {
150 case 0: /* Invalid */
152 case 2: /* L0 PTE, maybe should not happen? */
153 case 3: /* Reserved */
156 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
157 pde = ldl_phys(pde_ptr);
159 switch (pde & PTE_ENTRYTYPE_MASK) {
161 case 0: /* Invalid */
162 return (1 << 8) | (1 << 2);
163 case 3: /* Reserved */
164 return (1 << 8) | (4 << 2);
166 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
167 pde = ldl_phys(pde_ptr);
169 switch (pde & PTE_ENTRYTYPE_MASK) {
171 case 0: /* Invalid */
172 return (2 << 8) | (1 << 2);
173 case 3: /* Reserved */
174 return (2 << 8) | (4 << 2);
176 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
177 pde = ldl_phys(pde_ptr);
179 switch (pde & PTE_ENTRYTYPE_MASK) {
181 case 0: /* Invalid */
182 return (3 << 8) | (1 << 2);
183 case 1: /* PDE, should not happen */
184 case 3: /* Reserved */
185 return (3 << 8) | (4 << 2);
187 virt_addr = address & TARGET_PAGE_MASK;
188 page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
192 virt_addr = address & ~0x3ffff;
193 page_offset = address & 0x3ffff;
197 virt_addr = address & ~0xffffff;
198 page_offset = address & 0xffffff;
202 /* update page modified and dirty bits */
203 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
204 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
205 pde |= PG_ACCESSED_MASK;
207 pde |= PG_MODIFIED_MASK;
208 stl_phys_notdirty(pde_ptr, pde);
211 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
212 error_code = access_table[*access_index][access_perms];
216 /* the page can be put in the TLB */
218 if (pde & PG_MODIFIED_MASK) {
219 /* only set write access if already dirty... otherwise wait
221 if (rw_table[is_user][access_perms])
225 /* Even if large ptes, we map only one 4KB page in the cache to
226 avoid filling it too fast */
227 *physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
231 /* Perform address translation */
232 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
233 int is_user, int is_softmmu)
235 target_ulong virt_addr;
236 target_phys_addr_t paddr;
238 int error_code = 0, prot, ret = 0, access_index;
240 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
241 if (error_code == 0) {
242 virt_addr = address & TARGET_PAGE_MASK;
243 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
244 ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
248 if (env->mmuregs[3]) /* Fault status register */
249 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
250 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
251 env->mmuregs[4] = address; /* Fault address register */
253 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
256 vaddr = address & TARGET_PAGE_MASK;
258 prot = PAGE_READ | PAGE_WRITE;
259 ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
262 cpu_abort(env, "MMU no fault case no handled");
267 env->exception_index = TT_TFAULT;
269 env->exception_index = TT_DFAULT;
275 void memcpy32(target_ulong *dst, const target_ulong *src)
287 void set_cwp(int new_cwp)
289 /* put the modified wrap registers at their proper location */
290 if (env->cwp == (NWINDOWS - 1))
291 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
293 /* put the wrap registers at their temporary location */
294 if (new_cwp == (NWINDOWS - 1))
295 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
296 env->regwptr = env->regbase + (new_cwp * 16);
299 void cpu_set_cwp(CPUState *env1, int new_cwp)
308 void do_interrupt(int intno)
313 if (loglevel & CPU_LOG_INT) {
315 fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
318 env->npc, env->regwptr[6]);
320 cpu_dump_state(env, logfile, fprintf, 0);
325 fprintf(logfile, " code=");
326 ptr = (uint8_t *)env->pc;
327 for(i = 0; i < 16; i++) {
328 fprintf(logfile, " %02x", ldub(ptr + i));
330 fprintf(logfile, "\n");
336 #if !defined(CONFIG_USER_ONLY)
337 if (env->psret == 0) {
338 cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
343 cwp = (env->cwp - 1) & (NWINDOWS - 1);
345 env->regwptr[9] = env->pc;
346 env->regwptr[10] = env->npc;
347 env->psrps = env->psrs;
349 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
351 env->npc = env->pc + 4;
352 env->exception_index = 0;
355 target_ulong mmu_probe(target_ulong address, int mmulev)
357 target_phys_addr_t pde_ptr;
360 /* Context base + context number */
361 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
362 pde = ldl_phys(pde_ptr);
364 switch (pde & PTE_ENTRYTYPE_MASK) {
366 case 0: /* Invalid */
367 case 2: /* PTE, maybe should not happen? */
368 case 3: /* Reserved */
373 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
374 pde = ldl_phys(pde_ptr);
376 switch (pde & PTE_ENTRYTYPE_MASK) {
378 case 0: /* Invalid */
379 case 3: /* Reserved */
386 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
387 pde = ldl_phys(pde_ptr);
389 switch (pde & PTE_ENTRYTYPE_MASK) {
391 case 0: /* Invalid */
392 case 3: /* Reserved */
399 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
400 pde = ldl_phys(pde_ptr);
402 switch (pde & PTE_ENTRYTYPE_MASK) {
404 case 0: /* Invalid */
405 case 1: /* PDE, should not happen */
406 case 3: /* Reserved */
420 target_ulong va, va1, va2;
421 unsigned int n, m, o;
422 target_phys_addr_t pde_ptr, pa;
425 printf("MMU dump:\n");
426 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
427 pde = ldl_phys(pde_ptr);
428 printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
429 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
430 pde_ptr = mmu_probe(va, 2);
432 pa = cpu_get_phys_page_debug(env, va);
433 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
434 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
435 pde_ptr = mmu_probe(va1, 1);
437 pa = cpu_get_phys_page_debug(env, va1);
438 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
439 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
440 pde_ptr = mmu_probe(va2, 0);
442 pa = cpu_get_phys_page_debug(env, va2);
443 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
450 printf("MMU dump ends\n");