4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 /* Sparc MMU emulation */
29 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
33 spin_lock(&global_cpu_lock);
38 spin_unlock(&global_cpu_lock);
41 #if defined(CONFIG_USER_ONLY)
43 int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
44 int is_user, int is_softmmu)
46 env->mmuregs[4] = address;
48 env->exception_index = TT_TFAULT;
50 env->exception_index = TT_DFAULT;
56 #define MMUSUFFIX _mmu
57 #define GETPC() (__builtin_return_address(0))
60 #include "softmmu_template.h"
63 #include "softmmu_template.h"
66 #include "softmmu_template.h"
69 #include "softmmu_template.h"
72 /* try to fill the TLB and return an exception if error. If retaddr is
73 NULL, it means that the function was called in C code (i.e. not
74 from generated code or from helper.c) */
75 /* XXX: fix it to restore all registers */
76 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
83 /* XXX: hack to restore env in all cases, even if not called from
88 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
91 /* now we have a real cpu fault */
92 pc = (unsigned long)retaddr;
95 /* the PC is inside the translated code. It means that we have
96 a virtual CPU fault */
97 cpu_restore_state(tb, env, pc, NULL);
105 static const int access_table[8][8] = {
106 { 0, 0, 0, 0, 2, 0, 3, 3 },
107 { 0, 0, 0, 0, 2, 0, 0, 0 },
108 { 2, 2, 0, 0, 0, 2, 3, 3 },
109 { 2, 2, 0, 0, 0, 2, 0, 0 },
110 { 2, 0, 2, 0, 2, 2, 3, 3 },
111 { 2, 0, 2, 0, 2, 0, 2, 0 },
112 { 2, 2, 2, 0, 2, 2, 3, 3 },
113 { 2, 2, 2, 0, 2, 2, 2, 0 }
117 static const int rw_table[2][8] = {
118 { 0, 1, 0, 1, 0, 1, 0, 1 },
119 { 0, 1, 0, 1, 0, 0, 0, 0 }
122 int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
123 int *access_index, target_ulong address, int rw,
126 int access_perms = 0;
127 target_phys_addr_t pde_ptr;
129 target_ulong virt_addr;
130 int error_code = 0, is_dirty;
131 unsigned long page_offset;
133 virt_addr = address & TARGET_PAGE_MASK;
134 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
136 *prot = PAGE_READ | PAGE_WRITE;
140 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
141 /* Context base + context number */
142 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
143 pde = ldl_phys(pde_ptr);
146 switch (pde & PTE_ENTRYTYPE_MASK) {
148 case 0: /* Invalid */
150 case 2: /* L0 PTE, maybe should not happen? */
151 case 3: /* Reserved */
154 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
155 pde = ldl_phys(pde_ptr);
157 switch (pde & PTE_ENTRYTYPE_MASK) {
159 case 0: /* Invalid */
161 case 3: /* Reserved */
164 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
165 pde = ldl_phys(pde_ptr);
167 switch (pde & PTE_ENTRYTYPE_MASK) {
169 case 0: /* Invalid */
171 case 3: /* Reserved */
174 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
175 pde = ldl_phys(pde_ptr);
177 switch (pde & PTE_ENTRYTYPE_MASK) {
179 case 0: /* Invalid */
181 case 1: /* PDE, should not happen */
182 case 3: /* Reserved */
185 virt_addr = address & TARGET_PAGE_MASK;
186 page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
190 virt_addr = address & ~0x3ffff;
191 page_offset = address & 0x3ffff;
195 virt_addr = address & ~0xffffff;
196 page_offset = address & 0xffffff;
200 /* update page modified and dirty bits */
201 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
202 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
203 pde |= PG_ACCESSED_MASK;
205 pde |= PG_MODIFIED_MASK;
206 stl_phys_notdirty(pde_ptr, pde);
209 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
210 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
211 error_code = access_table[*access_index][access_perms];
215 /* the page can be put in the TLB */
217 if (pde & PG_MODIFIED_MASK) {
218 /* only set write access if already dirty... otherwise wait
220 if (rw_table[is_user][access_perms])
224 /* Even if large ptes, we map only one 4KB page in the cache to
225 avoid filling it too fast */
226 *physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
230 /* Perform address translation */
231 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
232 int is_user, int is_softmmu)
234 target_ulong virt_addr;
235 target_phys_addr_t paddr;
237 int error_code = 0, prot, ret = 0, access_index;
239 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
240 if (error_code == 0) {
241 virt_addr = address & TARGET_PAGE_MASK;
242 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
243 ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
247 if (env->mmuregs[3]) /* Fault status register */
248 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
249 env->mmuregs[3] |= (access_index << 5) | (error_code << 2) | 2;
250 env->mmuregs[4] = address; /* Fault address register */
252 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
254 cpu_abort(env, "Unsupported MMU no fault case");
257 env->exception_index = TT_TFAULT;
259 env->exception_index = TT_DFAULT;
264 void memcpy32(target_ulong *dst, const target_ulong *src)
276 void set_cwp(int new_cwp)
278 /* put the modified wrap registers at their proper location */
279 if (env->cwp == (NWINDOWS - 1))
280 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
282 /* put the wrap registers at their temporary location */
283 if (new_cwp == (NWINDOWS - 1))
284 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
285 env->regwptr = env->regbase + (new_cwp * 16);
288 void cpu_set_cwp(CPUState *env1, int new_cwp)
297 void do_interrupt(int intno)
302 if (loglevel & CPU_LOG_INT) {
304 fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
307 env->npc, env->regwptr[6]);
309 cpu_dump_state(env, logfile, fprintf, 0);
314 fprintf(logfile, " code=");
315 ptr = (uint8_t *)env->pc;
316 for(i = 0; i < 16; i++) {
317 fprintf(logfile, " %02x", ldub(ptr + i));
319 fprintf(logfile, "\n");
325 #if !defined(CONFIG_USER_ONLY)
326 if (env->psret == 0) {
327 cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
332 cwp = (env->cwp - 1) & (NWINDOWS - 1);
334 env->regwptr[9] = env->pc;
335 env->regwptr[10] = env->npc;
336 env->psrps = env->psrs;
338 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
340 env->npc = env->pc + 4;
341 env->exception_index = 0;
344 target_ulong mmu_probe(target_ulong address, int mmulev)
346 target_phys_addr_t pde_ptr;
349 /* Context base + context number */
350 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
351 pde = ldl_phys(pde_ptr);
353 switch (pde & PTE_ENTRYTYPE_MASK) {
355 case 0: /* Invalid */
356 case 2: /* PTE, maybe should not happen? */
357 case 3: /* Reserved */
362 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
363 pde = ldl_phys(pde_ptr);
365 switch (pde & PTE_ENTRYTYPE_MASK) {
367 case 0: /* Invalid */
368 case 3: /* Reserved */
375 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
376 pde = ldl_phys(pde_ptr);
378 switch (pde & PTE_ENTRYTYPE_MASK) {
380 case 0: /* Invalid */
381 case 3: /* Reserved */
388 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
389 pde = ldl_phys(pde_ptr);
391 switch (pde & PTE_ENTRYTYPE_MASK) {
393 case 0: /* Invalid */
394 case 1: /* PDE, should not happen */
395 case 3: /* Reserved */
409 target_ulong va, va1, va2;
410 unsigned int n, m, o;
411 target_phys_addr_t pde_ptr, pa;
414 printf("MMU dump:\n");
415 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
416 pde = ldl_phys(pde_ptr);
417 printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
418 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
419 pde_ptr = mmu_probe(va, 2);
421 pa = cpu_get_phys_page_debug(env, va);
422 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
423 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
424 pde_ptr = mmu_probe(va1, 1);
426 pa = cpu_get_phys_page_debug(env, va1);
427 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
428 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
429 pde_ptr = mmu_probe(va2, 0);
431 pa = cpu_get_phys_page_debug(env, va2);
432 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
439 printf("MMU dump ends\n");