4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #define raise_exception_err(a, b)\
27 fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
28 (raise_exception_err)(a, b);\
32 /* Sparc MMU emulation */
33 int cpu_sparc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
34 int is_user, int is_softmmu);
39 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
43 spin_lock(&global_cpu_lock);
48 spin_unlock(&global_cpu_lock);
52 void cpu_loop_exit(void)
54 /* NOTE: the register at this point must be saved by hand because
55 longjmp restore them */
56 longjmp(env->jmp_env, 1);
60 #if !defined(CONFIG_USER_ONLY)
62 #define MMUSUFFIX _mmu
63 #define GETPC() (__builtin_return_address(0))
66 #include "softmmu_template.h"
69 #include "softmmu_template.h"
72 #include "softmmu_template.h"
75 #include "softmmu_template.h"
78 /* try to fill the TLB and return an exception if error. If retaddr is
79 NULL, it means that the function was called in C code (i.e. not
80 from generated code or from helper.c) */
81 /* XXX: fix it to restore all registers */
82 void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
89 /* XXX: hack to restore env in all cases, even if not called from
94 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
97 /* now we have a real cpu fault */
98 pc = (unsigned long)retaddr;
101 /* the PC is inside the translated code. It means that we have
102 a virtual CPU fault */
103 cpu_restore_state(tb, env, pc, NULL);
106 raise_exception_err(ret, env->error_code);
112 static const int access_table[8][8] = {
113 { 0, 0, 0, 0, 2, 0, 3, 3 },
114 { 0, 0, 0, 0, 2, 0, 0, 0 },
115 { 2, 2, 0, 0, 0, 2, 3, 3 },
116 { 2, 2, 0, 0, 0, 2, 0, 0 },
117 { 2, 0, 2, 0, 2, 2, 3, 3 },
118 { 2, 0, 2, 0, 2, 0, 2, 0 },
119 { 2, 2, 2, 0, 2, 2, 3, 3 },
120 { 2, 2, 2, 0, 2, 2, 2, 0 }
124 static const int rw_table[2][8] = {
125 { 0, 1, 0, 1, 0, 1, 0, 1 },
126 { 0, 1, 0, 1, 0, 0, 0, 0 }
130 /* Perform address translation */
131 int cpu_sparc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
132 int is_user, int is_softmmu)
135 int access_perms = 0, access_index = 0;
137 uint32_t pde, virt_addr;
138 int error_code = 0, is_dirty, prot, ret = 0;
139 unsigned long paddr, vaddr, page_offset;
141 if (env->user_mode_only) {
142 /* user mode only emulation */
147 virt_addr = address & TARGET_PAGE_MASK;
148 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
150 page_offset = address & (TARGET_PAGE_SIZE - 1);
151 prot = PAGE_READ | PAGE_WRITE;
155 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
156 /* Context base + context number */
157 pde_ptr = phys_ram_base + (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
158 pde = ldl_raw(pde_ptr);
161 switch (pde & PTE_ENTRYTYPE_MASK) {
162 case 0: /* Invalid */
165 case 2: /* PTE, maybe should not happen? */
166 case 3: /* Reserved */
170 pde_ptr = phys_ram_base + ((address >> 22) & ~3) + ((pde & ~3) << 4);
171 pde = ldl_raw(pde_ptr);
173 switch (pde & PTE_ENTRYTYPE_MASK) {
174 case 0: /* Invalid */
177 case 3: /* Reserved */
181 pde_ptr = phys_ram_base + ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
182 pde = ldl_raw(pde_ptr);
184 switch (pde & PTE_ENTRYTYPE_MASK) {
185 case 0: /* Invalid */
188 case 3: /* Reserved */
192 pde_ptr = phys_ram_base + ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
193 pde = ldl_raw(pde_ptr);
195 switch (pde & PTE_ENTRYTYPE_MASK) {
196 case 0: /* Invalid */
199 case 1: /* PDE, should not happen */
200 case 3: /* Reserved */
204 virt_addr = address & TARGET_PAGE_MASK;
205 page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
209 virt_addr = address & ~0x3ffff;
210 page_offset = address & 0x3ffff;
214 virt_addr = address & ~0xffffff;
215 page_offset = address & 0xffffff;
219 /* update page modified and dirty bits */
220 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
221 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
222 pde |= PG_ACCESSED_MASK;
224 pde |= PG_MODIFIED_MASK;
225 stl_raw(pde_ptr, pde);
229 access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
230 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
231 error_code = access_table[access_index][access_perms];
235 /* the page can be put in the TLB */
237 if (pde & PG_MODIFIED_MASK) {
238 /* only set write access if already dirty... otherwise wait
240 if (rw_table[is_user][access_perms])
244 /* Even if large ptes, we map only one 4KB page in the cache to
245 avoid filling it too fast */
246 virt_addr = address & TARGET_PAGE_MASK;
247 paddr = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
250 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
252 ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
256 if (env->mmuregs[3]) /* Fault status register */
257 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
258 env->mmuregs[3] |= (access_index << 5) | (error_code << 2) | 2;
259 env->mmuregs[4] = address; /* Fault address register */
261 if (env->mmuregs[0] & MMU_NF) // No fault
264 env->exception_index = exception;
265 env->error_code = error_code;
269 void memcpy32(uint32_t *dst, const uint32_t *src)
281 void set_cwp(int new_cwp)
283 /* put the modified wrap registers at their proper location */
284 if (env->cwp == (NWINDOWS - 1))
285 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
287 /* put the wrap registers at their temporary location */
288 if (new_cwp == (NWINDOWS - 1))
289 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
290 env->regwptr = env->regbase + (new_cwp * 16);
294 * Begin execution of an interruption. is_int is TRUE if coming from
295 * the int instruction. next_eip is the EIP value AFTER the interrupt
296 * instruction. It is only relevant if is_int is TRUE.
298 void do_interrupt(int intno, int is_int, int error_code,
299 unsigned int next_eip, int is_hw)
304 if (loglevel & CPU_LOG_INT) {
306 fprintf(logfile, "%6d: v=%02x e=%04x i=%d pc=%08x npc=%08x SP=%08x\n",
307 count, intno, error_code, is_int,
309 env->npc, env->gregs[7]);
311 cpu_sparc_dump_state(env, logfile, 0);
315 fprintf(logfile, " code=");
317 for(i = 0; i < 16; i++) {
318 fprintf(logfile, " %02x", ldub(ptr + i));
320 fprintf(logfile, "\n");
327 cwp = (env->cwp - 1) & (NWINDOWS - 1);
329 env->regwptr[9] = env->pc;
330 env->regwptr[10] = env->npc;
331 env->psrps = env->psrs;
333 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
335 env->npc = env->pc + 4;
336 env->exception_index = 0;
339 void raise_exception_err(int exception_index, int error_code)
341 raise_exception(exception_index);