4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include "qemu-common.h"
34 //#define DEBUG_FEATURES
37 typedef struct sparc_def_t sparc_def_t;
41 target_ulong iu_version;
45 uint32_t mmu_ctpr_mask;
46 uint32_t mmu_cxr_mask;
47 uint32_t mmu_sfsr_mask;
48 uint32_t mmu_trcr_mask;
52 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
54 /* Sparc MMU emulation */
58 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
62 spin_lock(&global_cpu_lock);
67 spin_unlock(&global_cpu_lock);
70 #if defined(CONFIG_USER_ONLY)
72 int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
73 int mmu_idx, int is_softmmu)
76 env1->exception_index = TT_TFAULT;
78 env1->exception_index = TT_DFAULT;
84 #ifndef TARGET_SPARC64
86 * Sparc V8 Reference MMU (SRMMU)
88 static const int access_table[8][8] = {
89 { 0, 0, 0, 0, 2, 0, 3, 3 },
90 { 0, 0, 0, 0, 2, 0, 0, 0 },
91 { 2, 2, 0, 0, 0, 2, 3, 3 },
92 { 2, 2, 0, 0, 0, 2, 0, 0 },
93 { 2, 0, 2, 0, 2, 2, 3, 3 },
94 { 2, 0, 2, 0, 2, 0, 2, 0 },
95 { 2, 2, 2, 0, 2, 2, 3, 3 },
96 { 2, 2, 2, 0, 2, 2, 2, 0 }
99 static const int perm_table[2][8] = {
102 PAGE_READ | PAGE_WRITE,
103 PAGE_READ | PAGE_EXEC,
104 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
106 PAGE_READ | PAGE_WRITE,
107 PAGE_READ | PAGE_EXEC,
108 PAGE_READ | PAGE_WRITE | PAGE_EXEC
112 PAGE_READ | PAGE_WRITE,
113 PAGE_READ | PAGE_EXEC,
114 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
122 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
123 int *prot, int *access_index,
124 target_ulong address, int rw, int mmu_idx)
126 int access_perms = 0;
127 target_phys_addr_t pde_ptr;
129 target_ulong virt_addr;
130 int error_code = 0, is_dirty, is_user;
131 unsigned long page_offset;
133 is_user = mmu_idx == MMU_USER_IDX;
134 virt_addr = address & TARGET_PAGE_MASK;
136 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
137 // Boot mode: instruction fetches are taken from PROM
138 if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
139 *physical = env->prom_addr | (address & 0x7ffffULL);
140 *prot = PAGE_READ | PAGE_EXEC;
144 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
148 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
149 *physical = 0xffffffffffff0000ULL;
151 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
152 /* Context base + context number */
153 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
154 pde = ldl_phys(pde_ptr);
157 switch (pde & PTE_ENTRYTYPE_MASK) {
159 case 0: /* Invalid */
161 case 2: /* L0 PTE, maybe should not happen? */
162 case 3: /* Reserved */
165 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
166 pde = ldl_phys(pde_ptr);
168 switch (pde & PTE_ENTRYTYPE_MASK) {
170 case 0: /* Invalid */
171 return (1 << 8) | (1 << 2);
172 case 3: /* Reserved */
173 return (1 << 8) | (4 << 2);
175 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
176 pde = ldl_phys(pde_ptr);
178 switch (pde & PTE_ENTRYTYPE_MASK) {
180 case 0: /* Invalid */
181 return (2 << 8) | (1 << 2);
182 case 3: /* Reserved */
183 return (2 << 8) | (4 << 2);
185 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
186 pde = ldl_phys(pde_ptr);
188 switch (pde & PTE_ENTRYTYPE_MASK) {
190 case 0: /* Invalid */
191 return (3 << 8) | (1 << 2);
192 case 1: /* PDE, should not happen */
193 case 3: /* Reserved */
194 return (3 << 8) | (4 << 2);
196 virt_addr = address & TARGET_PAGE_MASK;
197 page_offset = (address & TARGET_PAGE_MASK) &
198 (TARGET_PAGE_SIZE - 1);
202 virt_addr = address & ~0x3ffff;
203 page_offset = address & 0x3ffff;
207 virt_addr = address & ~0xffffff;
208 page_offset = address & 0xffffff;
212 /* update page modified and dirty bits */
213 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
214 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
215 pde |= PG_ACCESSED_MASK;
217 pde |= PG_MODIFIED_MASK;
218 stl_phys_notdirty(pde_ptr, pde);
221 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
222 error_code = access_table[*access_index][access_perms];
223 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
226 /* the page can be put in the TLB */
227 *prot = perm_table[is_user][access_perms];
228 if (!(pde & PG_MODIFIED_MASK)) {
229 /* only set write access if already dirty... otherwise wait
231 *prot &= ~PAGE_WRITE;
234 /* Even if large ptes, we map only one 4KB page in the cache to
235 avoid filling it too fast */
236 *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
240 /* Perform address translation */
241 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
242 int mmu_idx, int is_softmmu)
244 target_phys_addr_t paddr;
246 int error_code = 0, prot, ret = 0, access_index;
248 error_code = get_physical_address(env, &paddr, &prot, &access_index,
249 address, rw, mmu_idx);
250 if (error_code == 0) {
251 vaddr = address & TARGET_PAGE_MASK;
252 paddr &= TARGET_PAGE_MASK;
254 printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
255 TARGET_FMT_lx "\n", address, paddr, vaddr);
257 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
261 if (env->mmuregs[3]) /* Fault status register */
262 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
263 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
264 env->mmuregs[4] = address; /* Fault address register */
266 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
267 // No fault mode: if a mapping is available, just override
268 // permissions. If no mapping is available, redirect accesses to
269 // neverland. Fake/overridden mappings will be flushed when
270 // switching to normal mode.
271 vaddr = address & TARGET_PAGE_MASK;
272 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
273 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
277 env->exception_index = TT_TFAULT;
279 env->exception_index = TT_DFAULT;
284 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
286 target_phys_addr_t pde_ptr;
289 /* Context base + context number */
290 pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
291 (env->mmuregs[2] << 2);
292 pde = ldl_phys(pde_ptr);
294 switch (pde & PTE_ENTRYTYPE_MASK) {
296 case 0: /* Invalid */
297 case 2: /* PTE, maybe should not happen? */
298 case 3: /* Reserved */
303 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
304 pde = ldl_phys(pde_ptr);
306 switch (pde & PTE_ENTRYTYPE_MASK) {
308 case 0: /* Invalid */
309 case 3: /* Reserved */
316 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
317 pde = ldl_phys(pde_ptr);
319 switch (pde & PTE_ENTRYTYPE_MASK) {
321 case 0: /* Invalid */
322 case 3: /* Reserved */
329 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
330 pde = ldl_phys(pde_ptr);
332 switch (pde & PTE_ENTRYTYPE_MASK) {
334 case 0: /* Invalid */
335 case 1: /* PDE, should not happen */
336 case 3: /* Reserved */
348 void dump_mmu(CPUState *env)
350 target_ulong va, va1, va2;
351 unsigned int n, m, o;
352 target_phys_addr_t pde_ptr, pa;
355 printf("MMU dump:\n");
356 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
357 pde = ldl_phys(pde_ptr);
358 printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
359 (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
360 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
361 pde = mmu_probe(env, va, 2);
363 pa = cpu_get_phys_page_debug(env, va);
364 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
365 " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
366 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
367 pde = mmu_probe(env, va1, 1);
369 pa = cpu_get_phys_page_debug(env, va1);
370 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
371 " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
372 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
373 pde = mmu_probe(env, va2, 0);
375 pa = cpu_get_phys_page_debug(env, va2);
376 printf(" VA: " TARGET_FMT_lx ", PA: "
377 TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
385 printf("MMU dump ends\n");
387 #endif /* DEBUG_MMU */
389 #else /* !TARGET_SPARC64 */
391 * UltraSparc IIi I/DMMUs
393 static int get_physical_address_data(CPUState *env,
394 target_phys_addr_t *physical, int *prot,
395 target_ulong address, int rw, int is_user)
400 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
402 *prot = PAGE_READ | PAGE_WRITE;
406 for (i = 0; i < 64; i++) {
407 switch ((env->dtlb_tte[i] >> 61) & 3) {
410 mask = 0xffffffffffffe000ULL;
413 mask = 0xffffffffffff0000ULL;
416 mask = 0xfffffffffff80000ULL;
419 mask = 0xffffffffffc00000ULL;
422 // ctx match, vaddr match?
423 if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
424 (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
426 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
427 ((env->dtlb_tte[i] & 0x4) && is_user) ||
428 (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
429 if (env->dmmuregs[3]) /* Fault status register */
430 env->dmmuregs[3] = 2; /* overflow (not read before
432 env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
433 env->dmmuregs[4] = address; /* Fault address register */
434 env->exception_index = TT_DFAULT;
436 printf("DFAULT at 0x%" PRIx64 "\n", address);
440 *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) +
441 (address & ~mask & 0x1fffffff000ULL);
443 if (env->dtlb_tte[i] & 0x2)
449 printf("DMISS at 0x%" PRIx64 "\n", address);
451 env->exception_index = TT_DMISS;
455 static int get_physical_address_code(CPUState *env,
456 target_phys_addr_t *physical, int *prot,
457 target_ulong address, int is_user)
462 if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
468 for (i = 0; i < 64; i++) {
469 switch ((env->itlb_tte[i] >> 61) & 3) {
472 mask = 0xffffffffffffe000ULL;
475 mask = 0xffffffffffff0000ULL;
478 mask = 0xfffffffffff80000ULL;
481 mask = 0xffffffffffc00000ULL;
484 // ctx match, vaddr match?
485 if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
486 (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
488 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
489 ((env->itlb_tte[i] & 0x4) && is_user)) {
490 if (env->immuregs[3]) /* Fault status register */
491 env->immuregs[3] = 2; /* overflow (not read before
493 env->immuregs[3] |= (is_user << 3) | 1;
494 env->exception_index = TT_TFAULT;
496 printf("TFAULT at 0x%" PRIx64 "\n", address);
500 *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) +
501 (address & ~mask & 0x1fffffff000ULL);
507 printf("TMISS at 0x%" PRIx64 "\n", address);
509 env->exception_index = TT_TMISS;
513 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
514 int *prot, int *access_index,
515 target_ulong address, int rw, int mmu_idx)
517 int is_user = mmu_idx == MMU_USER_IDX;
520 return get_physical_address_code(env, physical, prot, address,
523 return get_physical_address_data(env, physical, prot, address, rw,
527 /* Perform address translation */
528 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
529 int mmu_idx, int is_softmmu)
531 target_ulong virt_addr, vaddr;
532 target_phys_addr_t paddr;
533 int error_code = 0, prot, ret = 0, access_index;
535 error_code = get_physical_address(env, &paddr, &prot, &access_index,
536 address, rw, mmu_idx);
537 if (error_code == 0) {
538 virt_addr = address & TARGET_PAGE_MASK;
539 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
540 (TARGET_PAGE_SIZE - 1));
542 printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64
543 "\n", address, paddr, vaddr);
545 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
553 void dump_mmu(CPUState *env)
558 printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n",
559 env->dmmuregs[1], env->dmmuregs[2]);
560 if ((env->lsu & DMMU_E) == 0) {
561 printf("DMMU disabled\n");
563 printf("DMMU dump:\n");
564 for (i = 0; i < 64; i++) {
565 switch ((env->dtlb_tte[i] >> 61) & 3) {
580 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
581 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
582 ", %s, %s, %s, %s, ctx %" PRId64 "\n",
583 env->dtlb_tag[i] & ~0x1fffULL,
584 env->dtlb_tte[i] & 0x1ffffffe000ULL,
586 env->dtlb_tte[i] & 0x4? "priv": "user",
587 env->dtlb_tte[i] & 0x2? "RW": "RO",
588 env->dtlb_tte[i] & 0x40? "locked": "unlocked",
589 env->dtlb_tag[i] & 0x1fffULL);
593 if ((env->lsu & IMMU_E) == 0) {
594 printf("IMMU disabled\n");
596 printf("IMMU dump:\n");
597 for (i = 0; i < 64; i++) {
598 switch ((env->itlb_tte[i] >> 61) & 3) {
613 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
614 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
615 ", %s, %s, %s, ctx %" PRId64 "\n",
616 env->itlb_tag[i] & ~0x1fffULL,
617 env->itlb_tte[i] & 0x1ffffffe000ULL,
619 env->itlb_tte[i] & 0x4? "priv": "user",
620 env->itlb_tte[i] & 0x40? "locked": "unlocked",
621 env->itlb_tag[i] & 0x1fffULL);
626 #endif /* DEBUG_MMU */
628 #endif /* TARGET_SPARC64 */
629 #endif /* !CONFIG_USER_ONLY */
632 #if defined(CONFIG_USER_ONLY)
633 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
639 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
641 target_phys_addr_t phys_addr;
642 int prot, access_index;
644 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
645 MMU_KERNEL_IDX) != 0)
646 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
647 0, MMU_KERNEL_IDX) != 0)
649 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
655 #ifdef TARGET_SPARC64
657 static const char * const excp_names[0x50] = {
658 [TT_TFAULT] = "Instruction Access Fault",
659 [TT_TMISS] = "Instruction Access MMU Miss",
660 [TT_CODE_ACCESS] = "Instruction Access Error",
661 [TT_ILL_INSN] = "Illegal Instruction",
662 [TT_PRIV_INSN] = "Privileged Instruction",
663 [TT_NFPU_INSN] = "FPU Disabled",
664 [TT_FP_EXCP] = "FPU Exception",
665 [TT_TOVF] = "Tag Overflow",
666 [TT_CLRWIN] = "Clean Windows",
667 [TT_DIV_ZERO] = "Division By Zero",
668 [TT_DFAULT] = "Data Access Fault",
669 [TT_DMISS] = "Data Access MMU Miss",
670 [TT_DATA_ACCESS] = "Data Access Error",
671 [TT_DPROT] = "Data Protection Error",
672 [TT_UNALIGNED] = "Unaligned Memory Access",
673 [TT_PRIV_ACT] = "Privileged Action",
674 [TT_EXTINT | 0x1] = "External Interrupt 1",
675 [TT_EXTINT | 0x2] = "External Interrupt 2",
676 [TT_EXTINT | 0x3] = "External Interrupt 3",
677 [TT_EXTINT | 0x4] = "External Interrupt 4",
678 [TT_EXTINT | 0x5] = "External Interrupt 5",
679 [TT_EXTINT | 0x6] = "External Interrupt 6",
680 [TT_EXTINT | 0x7] = "External Interrupt 7",
681 [TT_EXTINT | 0x8] = "External Interrupt 8",
682 [TT_EXTINT | 0x9] = "External Interrupt 9",
683 [TT_EXTINT | 0xa] = "External Interrupt 10",
684 [TT_EXTINT | 0xb] = "External Interrupt 11",
685 [TT_EXTINT | 0xc] = "External Interrupt 12",
686 [TT_EXTINT | 0xd] = "External Interrupt 13",
687 [TT_EXTINT | 0xe] = "External Interrupt 14",
688 [TT_EXTINT | 0xf] = "External Interrupt 15",
692 void do_interrupt(CPUState *env)
694 int intno = env->exception_index;
697 if (loglevel & CPU_LOG_INT) {
701 if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
703 else if (intno >= 0x100)
704 name = "Trap Instruction";
705 else if (intno >= 0xc0)
706 name = "Window Fill";
707 else if (intno >= 0x80)
708 name = "Window Spill";
710 name = excp_names[intno];
715 fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
716 " SP=%016" PRIx64 "\n",
719 env->npc, env->regwptr[6]);
720 cpu_dump_state(env, logfile, fprintf, 0);
726 fprintf(logfile, " code=");
727 ptr = (uint8_t *)env->pc;
728 for(i = 0; i < 16; i++) {
729 fprintf(logfile, " %02x", ldub(ptr + i));
731 fprintf(logfile, "\n");
737 #if !defined(CONFIG_USER_ONLY)
738 if (env->tl == MAXTL) {
739 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state",
740 env->exception_index);
744 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
745 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
747 env->tsptr->tpc = env->pc;
748 env->tsptr->tnpc = env->npc;
749 env->tsptr->tt = intno;
750 change_pstate(PS_PEF | PS_PRIV | PS_AG);
752 if (intno == TT_CLRWIN)
753 cpu_set_cwp(env, (env->cwp - 1) & (NWINDOWS - 1));
754 else if ((intno & 0x1c0) == TT_SPILL)
755 cpu_set_cwp(env, (env->cwp - env->cansave - 2) & (NWINDOWS - 1));
756 else if ((intno & 0x1c0) == TT_FILL)
757 cpu_set_cwp(env, (env->cwp + 1) & (NWINDOWS - 1));
758 env->tbr &= ~0x7fffULL;
759 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
760 if (env->tl < MAXTL - 1) {
763 env->pstate |= PS_RED;
764 if (env->tl != MAXTL)
767 env->tsptr = &env->ts[env->tl];
769 env->npc = env->pc + 4;
770 env->exception_index = 0;
774 static const char * const excp_names[0x80] = {
775 [TT_TFAULT] = "Instruction Access Fault",
776 [TT_ILL_INSN] = "Illegal Instruction",
777 [TT_PRIV_INSN] = "Privileged Instruction",
778 [TT_NFPU_INSN] = "FPU Disabled",
779 [TT_WIN_OVF] = "Window Overflow",
780 [TT_WIN_UNF] = "Window Underflow",
781 [TT_UNALIGNED] = "Unaligned Memory Access",
782 [TT_FP_EXCP] = "FPU Exception",
783 [TT_DFAULT] = "Data Access Fault",
784 [TT_TOVF] = "Tag Overflow",
785 [TT_EXTINT | 0x1] = "External Interrupt 1",
786 [TT_EXTINT | 0x2] = "External Interrupt 2",
787 [TT_EXTINT | 0x3] = "External Interrupt 3",
788 [TT_EXTINT | 0x4] = "External Interrupt 4",
789 [TT_EXTINT | 0x5] = "External Interrupt 5",
790 [TT_EXTINT | 0x6] = "External Interrupt 6",
791 [TT_EXTINT | 0x7] = "External Interrupt 7",
792 [TT_EXTINT | 0x8] = "External Interrupt 8",
793 [TT_EXTINT | 0x9] = "External Interrupt 9",
794 [TT_EXTINT | 0xa] = "External Interrupt 10",
795 [TT_EXTINT | 0xb] = "External Interrupt 11",
796 [TT_EXTINT | 0xc] = "External Interrupt 12",
797 [TT_EXTINT | 0xd] = "External Interrupt 13",
798 [TT_EXTINT | 0xe] = "External Interrupt 14",
799 [TT_EXTINT | 0xf] = "External Interrupt 15",
800 [TT_TOVF] = "Tag Overflow",
801 [TT_CODE_ACCESS] = "Instruction Access Error",
802 [TT_DATA_ACCESS] = "Data Access Error",
803 [TT_DIV_ZERO] = "Division By Zero",
804 [TT_NCP_INSN] = "Coprocessor Disabled",
808 void do_interrupt(CPUState *env)
810 int cwp, intno = env->exception_index;
813 if (loglevel & CPU_LOG_INT) {
817 if (intno < 0 || intno >= 0x100)
819 else if (intno >= 0x80)
820 name = "Trap Instruction";
822 name = excp_names[intno];
827 fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
830 env->npc, env->regwptr[6]);
831 cpu_dump_state(env, logfile, fprintf, 0);
837 fprintf(logfile, " code=");
838 ptr = (uint8_t *)env->pc;
839 for(i = 0; i < 16; i++) {
840 fprintf(logfile, " %02x", ldub(ptr + i));
842 fprintf(logfile, "\n");
848 #if !defined(CONFIG_USER_ONLY)
849 if (env->psret == 0) {
850 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
851 env->exception_index);
856 cwp = (env->cwp - 1) & (NWINDOWS - 1);
857 cpu_set_cwp(env, cwp);
858 env->regwptr[9] = env->pc;
859 env->regwptr[10] = env->npc;
860 env->psrps = env->psrs;
862 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
864 env->npc = env->pc + 4;
865 env->exception_index = 0;
869 void memcpy32(target_ulong *dst, const target_ulong *src)
881 void cpu_reset(CPUSPARCState *env)
886 env->regwptr = env->regbase + (env->cwp * 16);
887 #if defined(CONFIG_USER_ONLY)
888 env->user_mode_only = 1;
889 #ifdef TARGET_SPARC64
890 env->cleanwin = NWINDOWS - 2;
891 env->cansave = NWINDOWS - 2;
892 env->pstate = PS_RMO | PS_PEF | PS_IE;
893 env->asi = 0x82; // Primary no-fault
899 #ifdef TARGET_SPARC64
900 env->pstate = PS_PRIV;
901 env->hpstate = HS_PRIV;
902 env->pc = 0x1fff0000000ULL;
903 env->tsptr = &env->ts[env->tl];
906 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
907 env->mmuregs[0] |= env->mmu_bm;
909 env->npc = env->pc + 4;
913 static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
915 sparc_def_t def1, *def = &def1;
917 if (cpu_sparc_find_by_name(def, cpu_model) < 0)
920 env->features = def->features;
921 env->cpu_model_str = cpu_model;
922 env->version = def->iu_version;
923 env->fsr = def->fpu_version;
924 #if !defined(TARGET_SPARC64)
925 env->mmu_bm = def->mmu_bm;
926 env->mmu_ctpr_mask = def->mmu_ctpr_mask;
927 env->mmu_cxr_mask = def->mmu_cxr_mask;
928 env->mmu_sfsr_mask = def->mmu_sfsr_mask;
929 env->mmu_trcr_mask = def->mmu_trcr_mask;
930 env->mmuregs[0] |= def->mmu_version;
931 cpu_sparc_set_id(env, 0);
936 static void cpu_sparc_close(CPUSPARCState *env)
941 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
945 env = qemu_mallocz(sizeof(CPUSPARCState));
950 gen_intermediate_code_init(env);
952 if (cpu_sparc_register(env, cpu_model) < 0) {
953 cpu_sparc_close(env);
961 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
963 #if !defined(TARGET_SPARC64)
964 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
968 static const sparc_def_t sparc_defs[] = {
969 #ifdef TARGET_SPARC64
971 .name = "Fujitsu Sparc64",
972 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
973 | (MAXTL << 8) | (NWINDOWS - 1)),
974 .fpu_version = 0x00000000,
976 .features = CPU_DEFAULT_FEATURES,
979 .name = "Fujitsu Sparc64 III",
980 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
981 | (MAXTL << 8) | (NWINDOWS - 1)),
982 .fpu_version = 0x00000000,
984 .features = CPU_DEFAULT_FEATURES,
987 .name = "Fujitsu Sparc64 IV",
988 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
989 | (MAXTL << 8) | (NWINDOWS - 1)),
990 .fpu_version = 0x00000000,
992 .features = CPU_DEFAULT_FEATURES,
995 .name = "Fujitsu Sparc64 V",
996 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
997 | (MAXTL << 8) | (NWINDOWS - 1)),
998 .fpu_version = 0x00000000,
1000 .features = CPU_DEFAULT_FEATURES,
1003 .name = "TI UltraSparc I",
1004 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
1005 | (MAXTL << 8) | (NWINDOWS - 1)),
1006 .fpu_version = 0x00000000,
1008 .features = CPU_DEFAULT_FEATURES,
1011 .name = "TI UltraSparc II",
1012 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
1013 | (MAXTL << 8) | (NWINDOWS - 1)),
1014 .fpu_version = 0x00000000,
1016 .features = CPU_DEFAULT_FEATURES,
1019 .name = "TI UltraSparc IIi",
1020 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
1021 | (MAXTL << 8) | (NWINDOWS - 1)),
1022 .fpu_version = 0x00000000,
1024 .features = CPU_DEFAULT_FEATURES,
1027 .name = "TI UltraSparc IIe",
1028 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
1029 | (MAXTL << 8) | (NWINDOWS - 1)),
1030 .fpu_version = 0x00000000,
1032 .features = CPU_DEFAULT_FEATURES,
1035 .name = "Sun UltraSparc III",
1036 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
1037 | (MAXTL << 8) | (NWINDOWS - 1)),
1038 .fpu_version = 0x00000000,
1040 .features = CPU_DEFAULT_FEATURES,
1043 .name = "Sun UltraSparc III Cu",
1044 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
1045 | (MAXTL << 8) | (NWINDOWS - 1)),
1046 .fpu_version = 0x00000000,
1048 .features = CPU_DEFAULT_FEATURES,
1051 .name = "Sun UltraSparc IIIi",
1052 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
1053 | (MAXTL << 8) | (NWINDOWS - 1)),
1054 .fpu_version = 0x00000000,
1056 .features = CPU_DEFAULT_FEATURES,
1059 .name = "Sun UltraSparc IV",
1060 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
1061 | (MAXTL << 8) | (NWINDOWS - 1)),
1062 .fpu_version = 0x00000000,
1064 .features = CPU_DEFAULT_FEATURES,
1067 .name = "Sun UltraSparc IV+",
1068 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
1069 | (MAXTL << 8) | (NWINDOWS - 1)),
1070 .fpu_version = 0x00000000,
1072 .features = CPU_DEFAULT_FEATURES,
1075 .name = "Sun UltraSparc IIIi+",
1076 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
1077 | (MAXTL << 8) | (NWINDOWS - 1)),
1078 .fpu_version = 0x00000000,
1080 .features = CPU_DEFAULT_FEATURES,
1083 .name = "NEC UltraSparc I",
1084 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
1085 | (MAXTL << 8) | (NWINDOWS - 1)),
1086 .fpu_version = 0x00000000,
1088 .features = CPU_DEFAULT_FEATURES,
1092 .name = "Fujitsu MB86900",
1093 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
1094 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1095 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
1096 .mmu_bm = 0x00004000,
1097 .mmu_ctpr_mask = 0x007ffff0,
1098 .mmu_cxr_mask = 0x0000003f,
1099 .mmu_sfsr_mask = 0xffffffff,
1100 .mmu_trcr_mask = 0xffffffff,
1101 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
1104 .name = "Fujitsu MB86904",
1105 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
1106 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1107 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
1108 .mmu_bm = 0x00004000,
1109 .mmu_ctpr_mask = 0x00ffffc0,
1110 .mmu_cxr_mask = 0x000000ff,
1111 .mmu_sfsr_mask = 0x00016fff,
1112 .mmu_trcr_mask = 0x00ffffff,
1113 .features = CPU_DEFAULT_FEATURES,
1116 .name = "Fujitsu MB86907",
1117 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
1118 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1119 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
1120 .mmu_bm = 0x00004000,
1121 .mmu_ctpr_mask = 0xffffffc0,
1122 .mmu_cxr_mask = 0x000000ff,
1123 .mmu_sfsr_mask = 0x00016fff,
1124 .mmu_trcr_mask = 0xffffffff,
1125 .features = CPU_DEFAULT_FEATURES,
1128 .name = "LSI L64811",
1129 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
1130 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
1131 .mmu_version = 0x10 << 24,
1132 .mmu_bm = 0x00004000,
1133 .mmu_ctpr_mask = 0x007ffff0,
1134 .mmu_cxr_mask = 0x0000003f,
1135 .mmu_sfsr_mask = 0xffffffff,
1136 .mmu_trcr_mask = 0xffffffff,
1137 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1141 .name = "Cypress CY7C601",
1142 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
1143 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1144 .mmu_version = 0x10 << 24,
1145 .mmu_bm = 0x00004000,
1146 .mmu_ctpr_mask = 0x007ffff0,
1147 .mmu_cxr_mask = 0x0000003f,
1148 .mmu_sfsr_mask = 0xffffffff,
1149 .mmu_trcr_mask = 0xffffffff,
1150 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1154 .name = "Cypress CY7C611",
1155 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
1156 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1157 .mmu_version = 0x10 << 24,
1158 .mmu_bm = 0x00004000,
1159 .mmu_ctpr_mask = 0x007ffff0,
1160 .mmu_cxr_mask = 0x0000003f,
1161 .mmu_sfsr_mask = 0xffffffff,
1162 .mmu_trcr_mask = 0xffffffff,
1163 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1167 .name = "TI SuperSparc II",
1168 .iu_version = 0x40000000,
1169 .fpu_version = 0 << 17,
1170 .mmu_version = 0x04000000,
1171 .mmu_bm = 0x00002000,
1172 .mmu_ctpr_mask = 0xffffffc0,
1173 .mmu_cxr_mask = 0x0000ffff,
1174 .mmu_sfsr_mask = 0xffffffff,
1175 .mmu_trcr_mask = 0xffffffff,
1176 .features = CPU_DEFAULT_FEATURES,
1179 .name = "TI MicroSparc I",
1180 .iu_version = 0x41000000,
1181 .fpu_version = 4 << 17,
1182 .mmu_version = 0x41000000,
1183 .mmu_bm = 0x00004000,
1184 .mmu_ctpr_mask = 0x007ffff0,
1185 .mmu_cxr_mask = 0x0000003f,
1186 .mmu_sfsr_mask = 0x00016fff,
1187 .mmu_trcr_mask = 0x0000003f,
1188 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
1189 CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
1193 .name = "TI MicroSparc II",
1194 .iu_version = 0x42000000,
1195 .fpu_version = 4 << 17,
1196 .mmu_version = 0x02000000,
1197 .mmu_bm = 0x00004000,
1198 .mmu_ctpr_mask = 0x00ffffc0,
1199 .mmu_cxr_mask = 0x000000ff,
1200 .mmu_sfsr_mask = 0x00016fff,
1201 .mmu_trcr_mask = 0x00ffffff,
1202 .features = CPU_DEFAULT_FEATURES,
1205 .name = "TI MicroSparc IIep",
1206 .iu_version = 0x42000000,
1207 .fpu_version = 4 << 17,
1208 .mmu_version = 0x04000000,
1209 .mmu_bm = 0x00004000,
1210 .mmu_ctpr_mask = 0x00ffffc0,
1211 .mmu_cxr_mask = 0x000000ff,
1212 .mmu_sfsr_mask = 0x00016bff,
1213 .mmu_trcr_mask = 0x00ffffff,
1214 .features = CPU_DEFAULT_FEATURES,
1217 .name = "TI SuperSparc 51",
1218 .iu_version = 0x43000000,
1219 .fpu_version = 0 << 17,
1220 .mmu_version = 0x04000000,
1221 .mmu_bm = 0x00002000,
1222 .mmu_ctpr_mask = 0xffffffc0,
1223 .mmu_cxr_mask = 0x0000ffff,
1224 .mmu_sfsr_mask = 0xffffffff,
1225 .mmu_trcr_mask = 0xffffffff,
1226 .features = CPU_DEFAULT_FEATURES,
1229 .name = "TI SuperSparc 61",
1230 .iu_version = 0x44000000,
1231 .fpu_version = 0 << 17,
1232 .mmu_version = 0x04000000,
1233 .mmu_bm = 0x00002000,
1234 .mmu_ctpr_mask = 0xffffffc0,
1235 .mmu_cxr_mask = 0x0000ffff,
1236 .mmu_sfsr_mask = 0xffffffff,
1237 .mmu_trcr_mask = 0xffffffff,
1238 .features = CPU_DEFAULT_FEATURES,
1241 .name = "Ross RT625",
1242 .iu_version = 0x1e000000,
1243 .fpu_version = 1 << 17,
1244 .mmu_version = 0x1e000000,
1245 .mmu_bm = 0x00004000,
1246 .mmu_ctpr_mask = 0x007ffff0,
1247 .mmu_cxr_mask = 0x0000003f,
1248 .mmu_sfsr_mask = 0xffffffff,
1249 .mmu_trcr_mask = 0xffffffff,
1250 .features = CPU_DEFAULT_FEATURES,
1253 .name = "Ross RT620",
1254 .iu_version = 0x1f000000,
1255 .fpu_version = 1 << 17,
1256 .mmu_version = 0x1f000000,
1257 .mmu_bm = 0x00004000,
1258 .mmu_ctpr_mask = 0x007ffff0,
1259 .mmu_cxr_mask = 0x0000003f,
1260 .mmu_sfsr_mask = 0xffffffff,
1261 .mmu_trcr_mask = 0xffffffff,
1262 .features = CPU_DEFAULT_FEATURES,
1265 .name = "BIT B5010",
1266 .iu_version = 0x20000000,
1267 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
1268 .mmu_version = 0x20000000,
1269 .mmu_bm = 0x00004000,
1270 .mmu_ctpr_mask = 0x007ffff0,
1271 .mmu_cxr_mask = 0x0000003f,
1272 .mmu_sfsr_mask = 0xffffffff,
1273 .mmu_trcr_mask = 0xffffffff,
1274 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1278 .name = "Matsushita MN10501",
1279 .iu_version = 0x50000000,
1280 .fpu_version = 0 << 17,
1281 .mmu_version = 0x50000000,
1282 .mmu_bm = 0x00004000,
1283 .mmu_ctpr_mask = 0x007ffff0,
1284 .mmu_cxr_mask = 0x0000003f,
1285 .mmu_sfsr_mask = 0xffffffff,
1286 .mmu_trcr_mask = 0xffffffff,
1287 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
1291 .name = "Weitek W8601",
1292 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
1293 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1294 .mmu_version = 0x10 << 24,
1295 .mmu_bm = 0x00004000,
1296 .mmu_ctpr_mask = 0x007ffff0,
1297 .mmu_cxr_mask = 0x0000003f,
1298 .mmu_sfsr_mask = 0xffffffff,
1299 .mmu_trcr_mask = 0xffffffff,
1300 .features = CPU_DEFAULT_FEATURES,
1304 .iu_version = 0xf2000000,
1305 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1306 .mmu_version = 0xf2000000,
1307 .mmu_bm = 0x00004000,
1308 .mmu_ctpr_mask = 0x007ffff0,
1309 .mmu_cxr_mask = 0x0000003f,
1310 .mmu_sfsr_mask = 0xffffffff,
1311 .mmu_trcr_mask = 0xffffffff,
1312 .features = CPU_DEFAULT_FEATURES,
1316 .iu_version = 0xf3000000,
1317 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1318 .mmu_version = 0xf3000000,
1319 .mmu_bm = 0x00004000,
1320 .mmu_ctpr_mask = 0x007ffff0,
1321 .mmu_cxr_mask = 0x0000003f,
1322 .mmu_sfsr_mask = 0xffffffff,
1323 .mmu_trcr_mask = 0xffffffff,
1324 .features = CPU_DEFAULT_FEATURES,
1329 static const char * const feature_name[] = {
1343 static void print_features(FILE *f,
1344 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1345 uint32_t features, const char *prefix)
1349 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1350 if (feature_name[i] && (features & (1 << i))) {
1352 (*cpu_fprintf)(f, "%s", prefix);
1353 (*cpu_fprintf)(f, "%s ", feature_name[i]);
1357 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
1361 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1362 if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
1363 *features |= 1 << i;
1366 fprintf(stderr, "CPU feature %s not found\n", flagname);
1369 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1372 const sparc_def_t *def = NULL;
1373 char *s = strdup(cpu_model);
1374 char *featurestr, *name = strtok(s, ",");
1375 uint32_t plus_features = 0;
1376 uint32_t minus_features = 0;
1377 long long iu_version;
1378 uint32_t fpu_version, mmu_version;
1380 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
1381 if (strcasecmp(name, sparc_defs[i].name) == 0) {
1382 def = &sparc_defs[i];
1387 memcpy(cpu_def, def, sizeof(*def));
1389 featurestr = strtok(NULL, ",");
1390 while (featurestr) {
1393 if (featurestr[0] == '+') {
1394 add_flagname_to_bitmaps(featurestr + 1, &plus_features);
1395 } else if (featurestr[0] == '-') {
1396 add_flagname_to_bitmaps(featurestr + 1, &minus_features);
1397 } else if ((val = strchr(featurestr, '='))) {
1399 if (!strcmp(featurestr, "iu_version")) {
1402 iu_version = strtoll(val, &err, 0);
1403 if (!*val || *err) {
1404 fprintf(stderr, "bad numerical value %s\n", val);
1407 cpu_def->iu_version = iu_version;
1408 #ifdef DEBUG_FEATURES
1409 fprintf(stderr, "iu_version %llx\n", iu_version);
1411 } else if (!strcmp(featurestr, "fpu_version")) {
1414 fpu_version = strtol(val, &err, 0);
1415 if (!*val || *err) {
1416 fprintf(stderr, "bad numerical value %s\n", val);
1419 cpu_def->fpu_version = fpu_version;
1420 #ifdef DEBUG_FEATURES
1421 fprintf(stderr, "fpu_version %llx\n", fpu_version);
1423 } else if (!strcmp(featurestr, "mmu_version")) {
1426 mmu_version = strtol(val, &err, 0);
1427 if (!*val || *err) {
1428 fprintf(stderr, "bad numerical value %s\n", val);
1431 cpu_def->mmu_version = mmu_version;
1432 #ifdef DEBUG_FEATURES
1433 fprintf(stderr, "mmu_version %llx\n", mmu_version);
1436 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1440 fprintf(stderr, "feature string `%s' not in format "
1441 "(+feature|-feature|feature=xyz)\n", featurestr);
1444 featurestr = strtok(NULL, ",");
1446 cpu_def->features |= plus_features;
1447 cpu_def->features &= ~minus_features;
1448 #ifdef DEBUG_FEATURES
1449 print_features(stderr, fprintf, cpu_def->features, NULL);
1459 void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
1463 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
1464 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x ",
1466 sparc_defs[i].iu_version,
1467 sparc_defs[i].fpu_version,
1468 sparc_defs[i].mmu_version);
1469 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
1470 ~sparc_defs[i].features, "-");
1471 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
1472 sparc_defs[i].features, "+");
1473 (*cpu_fprintf)(f, "\n");
1475 (*cpu_fprintf)(f, "CPU feature flags (+/-): ");
1476 print_features(f, cpu_fprintf, -1, NULL);
1477 (*cpu_fprintf)(f, "\n");
1478 (*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version "
1482 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1484 void cpu_dump_state(CPUState *env, FILE *f,
1485 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1490 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
1492 cpu_fprintf(f, "General Registers:\n");
1493 for (i = 0; i < 4; i++)
1494 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1495 cpu_fprintf(f, "\n");
1497 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1498 cpu_fprintf(f, "\nCurrent Register Window:\n");
1499 for (x = 0; x < 3; x++) {
1500 for (i = 0; i < 4; i++)
1501 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1502 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1503 env->regwptr[i + x * 8]);
1504 cpu_fprintf(f, "\n");
1506 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1507 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1508 env->regwptr[i + x * 8]);
1509 cpu_fprintf(f, "\n");
1511 cpu_fprintf(f, "\nFloating Point Registers:\n");
1512 for (i = 0; i < 32; i++) {
1514 cpu_fprintf(f, "%%f%02d:", i);
1515 cpu_fprintf(f, " %016lf", env->fpr[i]);
1517 cpu_fprintf(f, "\n");
1519 #ifdef TARGET_SPARC64
1520 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
1521 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
1522 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
1523 "cleanwin %d cwp %d\n",
1524 env->cansave, env->canrestore, env->otherwin, env->wstate,
1525 env->cleanwin, NWINDOWS - 1 - env->cwp);
1527 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
1528 GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1529 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1530 env->psrs?'S':'-', env->psrps?'P':'-',
1531 env->psret?'E':'-', env->wim);
1533 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
1536 #ifdef TARGET_SPARC64
1537 #if !defined(CONFIG_USER_ONLY)
1538 #include "qemu-common.h"
1540 #include "qemu-timer.h"
1543 void helper_tick_set_count(void *opaque, uint64_t count)
1545 #if !defined(CONFIG_USER_ONLY)
1546 ptimer_set_count(opaque, -count);
1550 uint64_t helper_tick_get_count(void *opaque)
1552 #if !defined(CONFIG_USER_ONLY)
1553 return -ptimer_get_count(opaque);
1559 void helper_tick_set_limit(void *opaque, uint64_t limit)
1561 #if !defined(CONFIG_USER_ONLY)
1562 ptimer_set_limit(opaque, -limit, 0);