2 #include "host-utils.h"
4 #if !defined(CONFIG_USER_ONLY)
5 #include "softmmu_exec.h"
6 #endif /* !defined(CONFIG_USER_ONLY) */
10 //#define DEBUG_UNALIGNED
11 //#define DEBUG_UNASSIGNED
16 #define DPRINTF_MMU(fmt, args...) \
17 do { printf("MMU: " fmt , ##args); } while (0)
19 #define DPRINTF_MMU(fmt, args...) do {} while (0)
23 #define DPRINTF_MXCC(fmt, args...) \
24 do { printf("MXCC: " fmt , ##args); } while (0)
26 #define DPRINTF_MXCC(fmt, args...) do {} while (0)
30 #define DPRINTF_ASI(fmt, args...) \
31 do { printf("ASI: " fmt , ##args); } while (0)
36 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
38 #define AM_CHECK(env1) (1)
43 // Calculates TSB pointer value for fault page size 8k or 64k
44 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
45 uint64_t tag_access_register,
48 uint64_t tsb_base = tsb_register & ~0x1fffULL;
49 int tsb_split = (env->dmmuregs[5] & 0x1000ULL) ? 1 : 0;
50 int tsb_size = env->dmmuregs[5] & 0xf;
52 // discard lower 13 bits which hold tag access context
53 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
56 uint64_t tsb_base_mask = ~0x1fffULL;
57 uint64_t va = tag_access_va;
59 // move va bits to correct position
60 if (page_size == 8*1024) {
62 } else if (page_size == 64*1024) {
67 tsb_base_mask <<= tsb_size;
70 // calculate tsb_base mask and adjust va if split is in use
72 if (page_size == 8*1024) {
73 va &= ~(1ULL << (13 + tsb_size));
74 } else if (page_size == 64*1024) {
75 va |= (1ULL << (13 + tsb_size));
80 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
83 // Calculates tag target register value by reordering bits
84 // in tag access register
85 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
87 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
92 static inline void address_mask(CPUState *env1, target_ulong *addr)
96 *addr &= 0xffffffffULL;
100 static void raise_exception(int tt)
102 env->exception_index = tt;
106 void HELPER(raise_exception)(int tt)
111 static inline void set_cwp(int new_cwp)
113 cpu_set_cwp(env, new_cwp);
116 void helper_check_align(target_ulong addr, uint32_t align)
119 #ifdef DEBUG_UNALIGNED
120 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
121 "\n", addr, env->pc);
123 raise_exception(TT_UNALIGNED);
127 #define F_HELPER(name, p) void helper_f##name##p(void)
129 #define F_BINOP(name) \
130 float32 helper_f ## name ## s (float32 src1, float32 src2) \
132 return float32_ ## name (src1, src2, &env->fp_status); \
136 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
140 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
149 void helper_fsmuld(float32 src1, float32 src2)
151 DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
152 float32_to_float64(src2, &env->fp_status),
156 void helper_fdmulq(void)
158 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
159 float64_to_float128(DT1, &env->fp_status),
163 float32 helper_fnegs(float32 src)
165 return float32_chs(src);
168 #ifdef TARGET_SPARC64
171 DT0 = float64_chs(DT1);
176 QT0 = float128_chs(QT1);
180 /* Integer to float conversion. */
181 float32 helper_fitos(int32_t src)
183 return int32_to_float32(src, &env->fp_status);
186 void helper_fitod(int32_t src)
188 DT0 = int32_to_float64(src, &env->fp_status);
191 void helper_fitoq(int32_t src)
193 QT0 = int32_to_float128(src, &env->fp_status);
196 #ifdef TARGET_SPARC64
197 float32 helper_fxtos(void)
199 return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
204 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
209 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
214 /* floating point conversion */
215 float32 helper_fdtos(void)
217 return float64_to_float32(DT1, &env->fp_status);
220 void helper_fstod(float32 src)
222 DT0 = float32_to_float64(src, &env->fp_status);
225 float32 helper_fqtos(void)
227 return float128_to_float32(QT1, &env->fp_status);
230 void helper_fstoq(float32 src)
232 QT0 = float32_to_float128(src, &env->fp_status);
235 void helper_fqtod(void)
237 DT0 = float128_to_float64(QT1, &env->fp_status);
240 void helper_fdtoq(void)
242 QT0 = float64_to_float128(DT1, &env->fp_status);
245 /* Float to integer conversion. */
246 int32_t helper_fstoi(float32 src)
248 return float32_to_int32_round_to_zero(src, &env->fp_status);
251 int32_t helper_fdtoi(void)
253 return float64_to_int32_round_to_zero(DT1, &env->fp_status);
256 int32_t helper_fqtoi(void)
258 return float128_to_int32_round_to_zero(QT1, &env->fp_status);
261 #ifdef TARGET_SPARC64
262 void helper_fstox(float32 src)
264 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
267 void helper_fdtox(void)
269 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
272 void helper_fqtox(void)
274 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
277 void helper_faligndata(void)
281 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
282 /* on many architectures a shift of 64 does nothing */
283 if ((env->gsr & 7) != 0) {
284 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
286 *((uint64_t *)&DT0) = tmp;
289 #ifdef WORDS_BIGENDIAN
290 #define VIS_B64(n) b[7 - (n)]
291 #define VIS_W64(n) w[3 - (n)]
292 #define VIS_SW64(n) sw[3 - (n)]
293 #define VIS_L64(n) l[1 - (n)]
294 #define VIS_B32(n) b[3 - (n)]
295 #define VIS_W32(n) w[1 - (n)]
297 #define VIS_B64(n) b[n]
298 #define VIS_W64(n) w[n]
299 #define VIS_SW64(n) sw[n]
300 #define VIS_L64(n) l[n]
301 #define VIS_B32(n) b[n]
302 #define VIS_W32(n) w[n]
320 void helper_fpmerge(void)
327 // Reverse calculation order to handle overlap
328 d.VIS_B64(7) = s.VIS_B64(3);
329 d.VIS_B64(6) = d.VIS_B64(3);
330 d.VIS_B64(5) = s.VIS_B64(2);
331 d.VIS_B64(4) = d.VIS_B64(2);
332 d.VIS_B64(3) = s.VIS_B64(1);
333 d.VIS_B64(2) = d.VIS_B64(1);
334 d.VIS_B64(1) = s.VIS_B64(0);
335 //d.VIS_B64(0) = d.VIS_B64(0);
340 void helper_fmul8x16(void)
349 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
350 if ((tmp & 0xff) > 0x7f) \
352 d.VIS_W64(r) = tmp >> 8;
363 void helper_fmul8x16al(void)
372 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
373 if ((tmp & 0xff) > 0x7f) \
375 d.VIS_W64(r) = tmp >> 8;
386 void helper_fmul8x16au(void)
395 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
396 if ((tmp & 0xff) > 0x7f) \
398 d.VIS_W64(r) = tmp >> 8;
409 void helper_fmul8sux16(void)
418 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
419 if ((tmp & 0xff) > 0x7f) \
421 d.VIS_W64(r) = tmp >> 8;
432 void helper_fmul8ulx16(void)
441 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
442 if ((tmp & 0xff) > 0x7f) \
444 d.VIS_W64(r) = tmp >> 8;
455 void helper_fmuld8sux16(void)
464 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
465 if ((tmp & 0xff) > 0x7f) \
469 // Reverse calculation order to handle overlap
477 void helper_fmuld8ulx16(void)
486 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
487 if ((tmp & 0xff) > 0x7f) \
491 // Reverse calculation order to handle overlap
499 void helper_fexpand(void)
504 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
506 d.VIS_W64(0) = s.VIS_B32(0) << 4;
507 d.VIS_W64(1) = s.VIS_B32(1) << 4;
508 d.VIS_W64(2) = s.VIS_B32(2) << 4;
509 d.VIS_W64(3) = s.VIS_B32(3) << 4;
514 #define VIS_HELPER(name, F) \
515 void name##16(void) \
522 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
523 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
524 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
525 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
530 uint32_t name##16s(uint32_t src1, uint32_t src2) \
537 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
538 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
543 void name##32(void) \
550 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
551 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
556 uint32_t name##32s(uint32_t src1, uint32_t src2) \
568 #define FADD(a, b) ((a) + (b))
569 #define FSUB(a, b) ((a) - (b))
570 VIS_HELPER(helper_fpadd, FADD)
571 VIS_HELPER(helper_fpsub, FSUB)
573 #define VIS_CMPHELPER(name, F) \
574 void name##16(void) \
581 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
582 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
583 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
584 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
589 void name##32(void) \
596 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
597 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
602 #define FCMPGT(a, b) ((a) > (b))
603 #define FCMPEQ(a, b) ((a) == (b))
604 #define FCMPLE(a, b) ((a) <= (b))
605 #define FCMPNE(a, b) ((a) != (b))
607 VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
608 VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
609 VIS_CMPHELPER(helper_fcmple, FCMPLE)
610 VIS_CMPHELPER(helper_fcmpne, FCMPNE)
613 void helper_check_ieee_exceptions(void)
617 status = get_float_exception_flags(&env->fp_status);
619 /* Copy IEEE 754 flags into FSR */
620 if (status & float_flag_invalid)
622 if (status & float_flag_overflow)
624 if (status & float_flag_underflow)
626 if (status & float_flag_divbyzero)
628 if (status & float_flag_inexact)
631 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
632 /* Unmasked exception, generate a trap */
633 env->fsr |= FSR_FTT_IEEE_EXCP;
634 raise_exception(TT_FP_EXCP);
636 /* Accumulate exceptions */
637 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
642 void helper_clear_float_exceptions(void)
644 set_float_exception_flags(0, &env->fp_status);
647 float32 helper_fabss(float32 src)
649 return float32_abs(src);
652 #ifdef TARGET_SPARC64
653 void helper_fabsd(void)
655 DT0 = float64_abs(DT1);
658 void helper_fabsq(void)
660 QT0 = float128_abs(QT1);
664 float32 helper_fsqrts(float32 src)
666 return float32_sqrt(src, &env->fp_status);
669 void helper_fsqrtd(void)
671 DT0 = float64_sqrt(DT1, &env->fp_status);
674 void helper_fsqrtq(void)
676 QT0 = float128_sqrt(QT1, &env->fp_status);
679 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
680 void glue(helper_, name) (void) \
682 target_ulong new_fsr; \
684 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
685 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
686 case float_relation_unordered: \
687 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
688 if ((env->fsr & FSR_NVM) || TRAP) { \
689 env->fsr |= new_fsr; \
690 env->fsr |= FSR_NVC; \
691 env->fsr |= FSR_FTT_IEEE_EXCP; \
692 raise_exception(TT_FP_EXCP); \
694 env->fsr |= FSR_NVA; \
697 case float_relation_less: \
698 new_fsr = FSR_FCC0 << FS; \
700 case float_relation_greater: \
701 new_fsr = FSR_FCC1 << FS; \
707 env->fsr |= new_fsr; \
709 #define GEN_FCMPS(name, size, FS, TRAP) \
710 void glue(helper_, name)(float32 src1, float32 src2) \
712 target_ulong new_fsr; \
714 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
715 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
716 case float_relation_unordered: \
717 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
718 if ((env->fsr & FSR_NVM) || TRAP) { \
719 env->fsr |= new_fsr; \
720 env->fsr |= FSR_NVC; \
721 env->fsr |= FSR_FTT_IEEE_EXCP; \
722 raise_exception(TT_FP_EXCP); \
724 env->fsr |= FSR_NVA; \
727 case float_relation_less: \
728 new_fsr = FSR_FCC0 << FS; \
730 case float_relation_greater: \
731 new_fsr = FSR_FCC1 << FS; \
737 env->fsr |= new_fsr; \
740 GEN_FCMPS(fcmps, float32, 0, 0);
741 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
743 GEN_FCMPS(fcmpes, float32, 0, 1);
744 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
746 GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
747 GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
749 #ifdef TARGET_SPARC64
750 GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
751 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
752 GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
754 GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
755 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
756 GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
758 GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
759 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
760 GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
762 GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
763 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
764 GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
766 GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
767 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
768 GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
770 GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
771 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
772 GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
776 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
778 static void dump_mxcc(CPUState *env)
780 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
781 env->mxccdata[0], env->mxccdata[1],
782 env->mxccdata[2], env->mxccdata[3]);
783 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
784 " %016llx %016llx %016llx %016llx\n",
785 env->mxccregs[0], env->mxccregs[1],
786 env->mxccregs[2], env->mxccregs[3],
787 env->mxccregs[4], env->mxccregs[5],
788 env->mxccregs[6], env->mxccregs[7]);
792 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
793 && defined(DEBUG_ASI)
794 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
800 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
801 addr, asi, r1 & 0xff);
804 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
805 addr, asi, r1 & 0xffff);
808 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
809 addr, asi, r1 & 0xffffffff);
812 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
819 #ifndef TARGET_SPARC64
820 #ifndef CONFIG_USER_ONLY
821 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
824 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
825 uint32_t last_addr = addr;
828 helper_check_align(addr, size - 1);
830 case 2: /* SuperSparc MXCC registers */
832 case 0x01c00a00: /* MXCC control register */
834 ret = env->mxccregs[3];
836 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
839 case 0x01c00a04: /* MXCC control register */
841 ret = env->mxccregs[3];
843 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
846 case 0x01c00c00: /* Module reset register */
848 ret = env->mxccregs[5];
849 // should we do something here?
851 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
854 case 0x01c00f00: /* MBus port address register */
856 ret = env->mxccregs[7];
858 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
862 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
866 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
867 "addr = %08x -> ret = %" PRIx64 ","
868 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
873 case 3: /* MMU probe */
877 mmulev = (addr >> 8) & 15;
881 ret = mmu_probe(env, addr, mmulev);
882 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
886 case 4: /* read MMU regs */
888 int reg = (addr >> 8) & 0x1f;
890 ret = env->mmuregs[reg];
891 if (reg == 3) /* Fault status cleared on read */
893 else if (reg == 0x13) /* Fault status read */
894 ret = env->mmuregs[3];
895 else if (reg == 0x14) /* Fault address read */
896 ret = env->mmuregs[4];
897 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
900 case 5: // Turbosparc ITLB Diagnostic
901 case 6: // Turbosparc DTLB Diagnostic
902 case 7: // Turbosparc IOTLB Diagnostic
904 case 9: /* Supervisor code access */
907 ret = ldub_code(addr);
910 ret = lduw_code(addr);
914 ret = ldl_code(addr);
917 ret = ldq_code(addr);
921 case 0xa: /* User data access */
924 ret = ldub_user(addr);
927 ret = lduw_user(addr);
931 ret = ldl_user(addr);
934 ret = ldq_user(addr);
938 case 0xb: /* Supervisor data access */
941 ret = ldub_kernel(addr);
944 ret = lduw_kernel(addr);
948 ret = ldl_kernel(addr);
951 ret = ldq_kernel(addr);
955 case 0xc: /* I-cache tag */
956 case 0xd: /* I-cache data */
957 case 0xe: /* D-cache tag */
958 case 0xf: /* D-cache data */
960 case 0x20: /* MMU passthrough */
963 ret = ldub_phys(addr);
966 ret = lduw_phys(addr);
970 ret = ldl_phys(addr);
973 ret = ldq_phys(addr);
977 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
980 ret = ldub_phys((target_phys_addr_t)addr
981 | ((target_phys_addr_t)(asi & 0xf) << 32));
984 ret = lduw_phys((target_phys_addr_t)addr
985 | ((target_phys_addr_t)(asi & 0xf) << 32));
989 ret = ldl_phys((target_phys_addr_t)addr
990 | ((target_phys_addr_t)(asi & 0xf) << 32));
993 ret = ldq_phys((target_phys_addr_t)addr
994 | ((target_phys_addr_t)(asi & 0xf) << 32));
998 case 0x30: // Turbosparc secondary cache diagnostic
999 case 0x31: // Turbosparc RAM snoop
1000 case 0x32: // Turbosparc page table descriptor diagnostic
1001 case 0x39: /* data cache diagnostic register */
1004 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1006 int reg = (addr >> 8) & 3;
1009 case 0: /* Breakpoint Value (Addr) */
1010 ret = env->mmubpregs[reg];
1012 case 1: /* Breakpoint Mask */
1013 ret = env->mmubpregs[reg];
1015 case 2: /* Breakpoint Control */
1016 ret = env->mmubpregs[reg];
1018 case 3: /* Breakpoint Status */
1019 ret = env->mmubpregs[reg];
1020 env->mmubpregs[reg] = 0ULL;
1023 DPRINTF_MMU("read breakpoint reg[%d] 0x%016llx\n", reg, ret);
1026 case 8: /* User code access, XXX */
1028 do_unassigned_access(addr, 0, 0, asi, size);
1038 ret = (int16_t) ret;
1041 ret = (int32_t) ret;
1048 dump_asi("read ", last_addr, asi, size, ret);
1053 void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
1055 helper_check_align(addr, size - 1);
1057 case 2: /* SuperSparc MXCC registers */
1059 case 0x01c00000: /* MXCC stream data register 0 */
1061 env->mxccdata[0] = val;
1063 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1066 case 0x01c00008: /* MXCC stream data register 1 */
1068 env->mxccdata[1] = val;
1070 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1073 case 0x01c00010: /* MXCC stream data register 2 */
1075 env->mxccdata[2] = val;
1077 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1080 case 0x01c00018: /* MXCC stream data register 3 */
1082 env->mxccdata[3] = val;
1084 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1087 case 0x01c00100: /* MXCC stream source */
1089 env->mxccregs[0] = val;
1091 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1093 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1095 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1097 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1099 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1102 case 0x01c00200: /* MXCC stream destination */
1104 env->mxccregs[1] = val;
1106 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1108 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
1110 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
1112 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
1114 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
1117 case 0x01c00a00: /* MXCC control register */
1119 env->mxccregs[3] = val;
1121 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1124 case 0x01c00a04: /* MXCC control register */
1126 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
1129 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1132 case 0x01c00e00: /* MXCC error register */
1133 // writing a 1 bit clears the error
1135 env->mxccregs[6] &= ~val;
1137 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1140 case 0x01c00f00: /* MBus port address register */
1142 env->mxccregs[7] = val;
1144 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1148 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1152 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
1153 asi, size, addr, val);
1158 case 3: /* MMU flush */
1162 mmulev = (addr >> 8) & 15;
1163 DPRINTF_MMU("mmu flush level %d\n", mmulev);
1165 case 0: // flush page
1166 tlb_flush_page(env, addr & 0xfffff000);
1168 case 1: // flush segment (256k)
1169 case 2: // flush region (16M)
1170 case 3: // flush context (4G)
1171 case 4: // flush entire
1182 case 4: /* write MMU regs */
1184 int reg = (addr >> 8) & 0x1f;
1187 oldreg = env->mmuregs[reg];
1189 case 0: // Control Register
1190 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1192 // Mappings generated during no-fault mode or MMU
1193 // disabled mode are invalid in normal mode
1194 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
1195 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
1198 case 1: // Context Table Pointer Register
1199 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
1201 case 2: // Context Register
1202 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
1203 if (oldreg != env->mmuregs[reg]) {
1204 /* we flush when the MMU context changes because
1205 QEMU has no MMU context support */
1209 case 3: // Synchronous Fault Status Register with Clear
1210 case 4: // Synchronous Fault Address Register
1212 case 0x10: // TLB Replacement Control Register
1213 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
1215 case 0x13: // Synchronous Fault Status Register with Read and Clear
1216 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
1218 case 0x14: // Synchronous Fault Address Register
1219 env->mmuregs[4] = val;
1222 env->mmuregs[reg] = val;
1225 if (oldreg != env->mmuregs[reg]) {
1226 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1227 reg, oldreg, env->mmuregs[reg]);
1234 case 5: // Turbosparc ITLB Diagnostic
1235 case 6: // Turbosparc DTLB Diagnostic
1236 case 7: // Turbosparc IOTLB Diagnostic
1238 case 0xa: /* User data access */
1241 stb_user(addr, val);
1244 stw_user(addr, val);
1248 stl_user(addr, val);
1251 stq_user(addr, val);
1255 case 0xb: /* Supervisor data access */
1258 stb_kernel(addr, val);
1261 stw_kernel(addr, val);
1265 stl_kernel(addr, val);
1268 stq_kernel(addr, val);
1272 case 0xc: /* I-cache tag */
1273 case 0xd: /* I-cache data */
1274 case 0xe: /* D-cache tag */
1275 case 0xf: /* D-cache data */
1276 case 0x10: /* I/D-cache flush page */
1277 case 0x11: /* I/D-cache flush segment */
1278 case 0x12: /* I/D-cache flush region */
1279 case 0x13: /* I/D-cache flush context */
1280 case 0x14: /* I/D-cache flush user */
1282 case 0x17: /* Block copy, sta access */
1288 uint32_t src = val & ~3, dst = addr & ~3, temp;
1290 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1291 temp = ldl_kernel(src);
1292 stl_kernel(dst, temp);
1296 case 0x1f: /* Block fill, stda access */
1299 // fill 32 bytes with val
1301 uint32_t dst = addr & 7;
1303 for (i = 0; i < 32; i += 8, dst += 8)
1304 stq_kernel(dst, val);
1307 case 0x20: /* MMU passthrough */
1311 stb_phys(addr, val);
1314 stw_phys(addr, val);
1318 stl_phys(addr, val);
1321 stq_phys(addr, val);
1326 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1330 stb_phys((target_phys_addr_t)addr
1331 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1334 stw_phys((target_phys_addr_t)addr
1335 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1339 stl_phys((target_phys_addr_t)addr
1340 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1343 stq_phys((target_phys_addr_t)addr
1344 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1349 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1350 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1351 // Turbosparc snoop RAM
1352 case 0x32: // store buffer control or Turbosparc page table
1353 // descriptor diagnostic
1354 case 0x36: /* I-cache flash clear */
1355 case 0x37: /* D-cache flash clear */
1356 case 0x4c: /* breakpoint action */
1358 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1360 int reg = (addr >> 8) & 3;
1363 case 0: /* Breakpoint Value (Addr) */
1364 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1366 case 1: /* Breakpoint Mask */
1367 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1369 case 2: /* Breakpoint Control */
1370 env->mmubpregs[reg] = (val & 0x7fULL);
1372 case 3: /* Breakpoint Status */
1373 env->mmubpregs[reg] = (val & 0xfULL);
1376 DPRINTF_MMU("write breakpoint reg[%d] 0x%016llx\n", reg,
1380 case 8: /* User code access, XXX */
1381 case 9: /* Supervisor code access, XXX */
1383 do_unassigned_access(addr, 1, 0, asi, size);
1387 dump_asi("write", addr, asi, size, val);
1391 #endif /* CONFIG_USER_ONLY */
1392 #else /* TARGET_SPARC64 */
1394 #ifdef CONFIG_USER_ONLY
1395 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1398 #if defined(DEBUG_ASI)
1399 target_ulong last_addr = addr;
1403 raise_exception(TT_PRIV_ACT);
1405 helper_check_align(addr, size - 1);
1406 address_mask(env, &addr);
1409 case 0x82: // Primary no-fault
1410 case 0x8a: // Primary no-fault LE
1411 if (page_check_range(addr, size, PAGE_READ) == -1) {
1413 dump_asi("read ", last_addr, asi, size, ret);
1418 case 0x80: // Primary
1419 case 0x88: // Primary LE
1423 ret = ldub_raw(addr);
1426 ret = lduw_raw(addr);
1429 ret = ldl_raw(addr);
1433 ret = ldq_raw(addr);
1438 case 0x83: // Secondary no-fault
1439 case 0x8b: // Secondary no-fault LE
1440 if (page_check_range(addr, size, PAGE_READ) == -1) {
1442 dump_asi("read ", last_addr, asi, size, ret);
1447 case 0x81: // Secondary
1448 case 0x89: // Secondary LE
1455 /* Convert from little endian */
1457 case 0x88: // Primary LE
1458 case 0x89: // Secondary LE
1459 case 0x8a: // Primary no-fault LE
1460 case 0x8b: // Secondary no-fault LE
1478 /* Convert to signed number */
1485 ret = (int16_t) ret;
1488 ret = (int32_t) ret;
1495 dump_asi("read ", last_addr, asi, size, ret);
1500 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1503 dump_asi("write", addr, asi, size, val);
1506 raise_exception(TT_PRIV_ACT);
1508 helper_check_align(addr, size - 1);
1509 address_mask(env, &addr);
1511 /* Convert to little endian */
1513 case 0x88: // Primary LE
1514 case 0x89: // Secondary LE
1517 addr = bswap16(addr);
1520 addr = bswap32(addr);
1523 addr = bswap64(addr);
1533 case 0x80: // Primary
1534 case 0x88: // Primary LE
1553 case 0x81: // Secondary
1554 case 0x89: // Secondary LE
1558 case 0x82: // Primary no-fault, RO
1559 case 0x83: // Secondary no-fault, RO
1560 case 0x8a: // Primary no-fault LE, RO
1561 case 0x8b: // Secondary no-fault LE, RO
1563 do_unassigned_access(addr, 1, 0, 1, size);
1568 #else /* CONFIG_USER_ONLY */
1570 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1573 #if defined(DEBUG_ASI)
1574 target_ulong last_addr = addr;
1577 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1578 || ((env->def->features & CPU_FEATURE_HYPV)
1579 && asi >= 0x30 && asi < 0x80
1580 && !(env->hpstate & HS_PRIV)))
1581 raise_exception(TT_PRIV_ACT);
1583 helper_check_align(addr, size - 1);
1585 case 0x82: // Primary no-fault
1586 case 0x8a: // Primary no-fault LE
1587 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1589 dump_asi("read ", last_addr, asi, size, ret);
1594 case 0x10: // As if user primary
1595 case 0x18: // As if user primary LE
1596 case 0x80: // Primary
1597 case 0x88: // Primary LE
1598 case 0xe2: // UA2007 Primary block init
1599 case 0xe3: // UA2007 Secondary block init
1600 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1601 if ((env->def->features & CPU_FEATURE_HYPV)
1602 && env->hpstate & HS_PRIV) {
1605 ret = ldub_hypv(addr);
1608 ret = lduw_hypv(addr);
1611 ret = ldl_hypv(addr);
1615 ret = ldq_hypv(addr);
1621 ret = ldub_kernel(addr);
1624 ret = lduw_kernel(addr);
1627 ret = ldl_kernel(addr);
1631 ret = ldq_kernel(addr);
1638 ret = ldub_user(addr);
1641 ret = lduw_user(addr);
1644 ret = ldl_user(addr);
1648 ret = ldq_user(addr);
1653 case 0x14: // Bypass
1654 case 0x15: // Bypass, non-cacheable
1655 case 0x1c: // Bypass LE
1656 case 0x1d: // Bypass, non-cacheable LE
1660 ret = ldub_phys(addr);
1663 ret = lduw_phys(addr);
1666 ret = ldl_phys(addr);
1670 ret = ldq_phys(addr);
1675 case 0x24: // Nucleus quad LDD 128 bit atomic
1676 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1677 // Only ldda allowed
1678 raise_exception(TT_ILL_INSN);
1680 case 0x83: // Secondary no-fault
1681 case 0x8b: // Secondary no-fault LE
1682 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1684 dump_asi("read ", last_addr, asi, size, ret);
1689 case 0x04: // Nucleus
1690 case 0x0c: // Nucleus Little Endian (LE)
1691 case 0x11: // As if user secondary
1692 case 0x19: // As if user secondary LE
1693 case 0x4a: // UPA config
1694 case 0x81: // Secondary
1695 case 0x89: // Secondary LE
1701 case 0x50: // I-MMU regs
1703 int reg = (addr >> 3) & 0xf;
1706 // I-TSB Tag Target register
1707 ret = ultrasparc_tag_target(env->immuregs[6]);
1709 ret = env->immuregs[reg];
1714 case 0x51: // I-MMU 8k TSB pointer
1716 // env->immuregs[5] holds I-MMU TSB register value
1717 // env->immuregs[6] holds I-MMU Tag Access register value
1718 ret = ultrasparc_tsb_pointer(env->immuregs[5], env->immuregs[6],
1722 case 0x52: // I-MMU 64k TSB pointer
1724 // env->immuregs[5] holds I-MMU TSB register value
1725 // env->immuregs[6] holds I-MMU Tag Access register value
1726 ret = ultrasparc_tsb_pointer(env->immuregs[5], env->immuregs[6],
1730 case 0x55: // I-MMU data access
1732 int reg = (addr >> 3) & 0x3f;
1734 ret = env->itlb_tte[reg];
1737 case 0x56: // I-MMU tag read
1739 int reg = (addr >> 3) & 0x3f;
1741 ret = env->itlb_tag[reg];
1744 case 0x58: // D-MMU regs
1746 int reg = (addr >> 3) & 0xf;
1749 // D-TSB Tag Target register
1750 ret = ultrasparc_tag_target(env->dmmuregs[6]);
1752 ret = env->dmmuregs[reg];
1756 case 0x59: // D-MMU 8k TSB pointer
1758 // env->dmmuregs[5] holds D-MMU TSB register value
1759 // env->dmmuregs[6] holds D-MMU Tag Access register value
1760 ret = ultrasparc_tsb_pointer(env->dmmuregs[5], env->dmmuregs[6],
1764 case 0x5a: // D-MMU 64k TSB pointer
1766 // env->dmmuregs[5] holds D-MMU TSB register value
1767 // env->dmmuregs[6] holds D-MMU Tag Access register value
1768 ret = ultrasparc_tsb_pointer(env->dmmuregs[5], env->dmmuregs[6],
1772 case 0x5d: // D-MMU data access
1774 int reg = (addr >> 3) & 0x3f;
1776 ret = env->dtlb_tte[reg];
1779 case 0x5e: // D-MMU tag read
1781 int reg = (addr >> 3) & 0x3f;
1783 ret = env->dtlb_tag[reg];
1786 case 0x46: // D-cache data
1787 case 0x47: // D-cache tag access
1788 case 0x4b: // E-cache error enable
1789 case 0x4c: // E-cache asynchronous fault status
1790 case 0x4d: // E-cache asynchronous fault address
1791 case 0x4e: // E-cache tag data
1792 case 0x66: // I-cache instruction access
1793 case 0x67: // I-cache tag access
1794 case 0x6e: // I-cache predecode
1795 case 0x6f: // I-cache LRU etc.
1796 case 0x76: // E-cache tag
1797 case 0x7e: // E-cache tag
1799 case 0x5b: // D-MMU data pointer
1800 case 0x48: // Interrupt dispatch, RO
1801 case 0x49: // Interrupt data receive
1802 case 0x7f: // Incoming interrupt vector, RO
1805 case 0x54: // I-MMU data in, WO
1806 case 0x57: // I-MMU demap, WO
1807 case 0x5c: // D-MMU data in, WO
1808 case 0x5f: // D-MMU demap, WO
1809 case 0x77: // Interrupt vector, WO
1811 do_unassigned_access(addr, 0, 0, 1, size);
1816 /* Convert from little endian */
1818 case 0x0c: // Nucleus Little Endian (LE)
1819 case 0x18: // As if user primary LE
1820 case 0x19: // As if user secondary LE
1821 case 0x1c: // Bypass LE
1822 case 0x1d: // Bypass, non-cacheable LE
1823 case 0x88: // Primary LE
1824 case 0x89: // Secondary LE
1825 case 0x8a: // Primary no-fault LE
1826 case 0x8b: // Secondary no-fault LE
1844 /* Convert to signed number */
1851 ret = (int16_t) ret;
1854 ret = (int32_t) ret;
1861 dump_asi("read ", last_addr, asi, size, ret);
1866 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1869 dump_asi("write", addr, asi, size, val);
1871 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1872 || ((env->def->features & CPU_FEATURE_HYPV)
1873 && asi >= 0x30 && asi < 0x80
1874 && !(env->hpstate & HS_PRIV)))
1875 raise_exception(TT_PRIV_ACT);
1877 helper_check_align(addr, size - 1);
1878 /* Convert to little endian */
1880 case 0x0c: // Nucleus Little Endian (LE)
1881 case 0x18: // As if user primary LE
1882 case 0x19: // As if user secondary LE
1883 case 0x1c: // Bypass LE
1884 case 0x1d: // Bypass, non-cacheable LE
1885 case 0x88: // Primary LE
1886 case 0x89: // Secondary LE
1889 addr = bswap16(addr);
1892 addr = bswap32(addr);
1895 addr = bswap64(addr);
1905 case 0x10: // As if user primary
1906 case 0x18: // As if user primary LE
1907 case 0x80: // Primary
1908 case 0x88: // Primary LE
1909 case 0xe2: // UA2007 Primary block init
1910 case 0xe3: // UA2007 Secondary block init
1911 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1912 if ((env->def->features & CPU_FEATURE_HYPV)
1913 && env->hpstate & HS_PRIV) {
1916 stb_hypv(addr, val);
1919 stw_hypv(addr, val);
1922 stl_hypv(addr, val);
1926 stq_hypv(addr, val);
1932 stb_kernel(addr, val);
1935 stw_kernel(addr, val);
1938 stl_kernel(addr, val);
1942 stq_kernel(addr, val);
1949 stb_user(addr, val);
1952 stw_user(addr, val);
1955 stl_user(addr, val);
1959 stq_user(addr, val);
1964 case 0x14: // Bypass
1965 case 0x15: // Bypass, non-cacheable
1966 case 0x1c: // Bypass LE
1967 case 0x1d: // Bypass, non-cacheable LE
1971 stb_phys(addr, val);
1974 stw_phys(addr, val);
1977 stl_phys(addr, val);
1981 stq_phys(addr, val);
1986 case 0x24: // Nucleus quad LDD 128 bit atomic
1987 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1988 // Only ldda allowed
1989 raise_exception(TT_ILL_INSN);
1991 case 0x04: // Nucleus
1992 case 0x0c: // Nucleus Little Endian (LE)
1993 case 0x11: // As if user secondary
1994 case 0x19: // As if user secondary LE
1995 case 0x4a: // UPA config
1996 case 0x81: // Secondary
1997 case 0x89: // Secondary LE
2005 env->lsu = val & (DMMU_E | IMMU_E);
2006 // Mappings generated during D/I MMU disabled mode are
2007 // invalid in normal mode
2008 if (oldreg != env->lsu) {
2009 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
2018 case 0x50: // I-MMU regs
2020 int reg = (addr >> 3) & 0xf;
2023 oldreg = env->immuregs[reg];
2028 case 1: // Not in I-MMU
2035 val = 0; // Clear SFSR
2037 case 5: // TSB access
2038 case 6: // Tag access
2042 env->immuregs[reg] = val;
2043 if (oldreg != env->immuregs[reg]) {
2044 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
2045 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
2052 case 0x54: // I-MMU data in
2056 // Try finding an invalid entry
2057 for (i = 0; i < 64; i++) {
2058 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
2059 env->itlb_tag[i] = env->immuregs[6];
2060 env->itlb_tte[i] = val;
2064 // Try finding an unlocked entry
2065 for (i = 0; i < 64; i++) {
2066 if ((env->itlb_tte[i] & 0x40) == 0) {
2067 env->itlb_tag[i] = env->immuregs[6];
2068 env->itlb_tte[i] = val;
2075 case 0x55: // I-MMU data access
2079 unsigned int i = (addr >> 3) & 0x3f;
2081 env->itlb_tag[i] = env->immuregs[6];
2082 env->itlb_tte[i] = val;
2085 case 0x57: // I-MMU demap
2089 for (i = 0; i < 64; i++) {
2090 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
2091 target_ulong mask = 0xffffffffffffe000ULL;
2093 mask <<= 3 * ((env->itlb_tte[i] >> 61) & 3);
2094 if ((val & mask) == (env->itlb_tag[i] & mask)) {
2095 env->itlb_tag[i] = 0;
2096 env->itlb_tte[i] = 0;
2103 case 0x58: // D-MMU regs
2105 int reg = (addr >> 3) & 0xf;
2108 oldreg = env->dmmuregs[reg];
2114 if ((val & 1) == 0) {
2115 val = 0; // Clear SFSR, Fault address
2116 env->dmmuregs[4] = 0;
2118 env->dmmuregs[reg] = val;
2120 case 1: // Primary context
2121 case 2: // Secondary context
2122 case 5: // TSB access
2123 case 6: // Tag access
2124 case 7: // Virtual Watchpoint
2125 case 8: // Physical Watchpoint
2129 env->dmmuregs[reg] = val;
2130 if (oldreg != env->dmmuregs[reg]) {
2131 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
2132 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
2139 case 0x5c: // D-MMU data in
2143 // Try finding an invalid entry
2144 for (i = 0; i < 64; i++) {
2145 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
2146 env->dtlb_tag[i] = env->dmmuregs[6];
2147 env->dtlb_tte[i] = val;
2151 // Try finding an unlocked entry
2152 for (i = 0; i < 64; i++) {
2153 if ((env->dtlb_tte[i] & 0x40) == 0) {
2154 env->dtlb_tag[i] = env->dmmuregs[6];
2155 env->dtlb_tte[i] = val;
2162 case 0x5d: // D-MMU data access
2164 unsigned int i = (addr >> 3) & 0x3f;
2166 env->dtlb_tag[i] = env->dmmuregs[6];
2167 env->dtlb_tte[i] = val;
2170 case 0x5f: // D-MMU demap
2174 for (i = 0; i < 64; i++) {
2175 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
2176 target_ulong mask = 0xffffffffffffe000ULL;
2178 mask <<= 3 * ((env->dtlb_tte[i] >> 61) & 3);
2179 if ((val & mask) == (env->dtlb_tag[i] & mask)) {
2180 env->dtlb_tag[i] = 0;
2181 env->dtlb_tte[i] = 0;
2188 case 0x49: // Interrupt data receive
2191 case 0x46: // D-cache data
2192 case 0x47: // D-cache tag access
2193 case 0x4b: // E-cache error enable
2194 case 0x4c: // E-cache asynchronous fault status
2195 case 0x4d: // E-cache asynchronous fault address
2196 case 0x4e: // E-cache tag data
2197 case 0x66: // I-cache instruction access
2198 case 0x67: // I-cache tag access
2199 case 0x6e: // I-cache predecode
2200 case 0x6f: // I-cache LRU etc.
2201 case 0x76: // E-cache tag
2202 case 0x7e: // E-cache tag
2204 case 0x51: // I-MMU 8k TSB pointer, RO
2205 case 0x52: // I-MMU 64k TSB pointer, RO
2206 case 0x56: // I-MMU tag read, RO
2207 case 0x59: // D-MMU 8k TSB pointer, RO
2208 case 0x5a: // D-MMU 64k TSB pointer, RO
2209 case 0x5b: // D-MMU data pointer, RO
2210 case 0x5e: // D-MMU tag read, RO
2211 case 0x48: // Interrupt dispatch, RO
2212 case 0x7f: // Incoming interrupt vector, RO
2213 case 0x82: // Primary no-fault, RO
2214 case 0x83: // Secondary no-fault, RO
2215 case 0x8a: // Primary no-fault LE, RO
2216 case 0x8b: // Secondary no-fault LE, RO
2218 do_unassigned_access(addr, 1, 0, 1, size);
2222 #endif /* CONFIG_USER_ONLY */
2224 void helper_ldda_asi(target_ulong addr, int asi, int rd)
2226 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2227 || ((env->def->features & CPU_FEATURE_HYPV)
2228 && asi >= 0x30 && asi < 0x80
2229 && !(env->hpstate & HS_PRIV)))
2230 raise_exception(TT_PRIV_ACT);
2233 case 0x24: // Nucleus quad LDD 128 bit atomic
2234 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2235 helper_check_align(addr, 0xf);
2237 env->gregs[1] = ldq_kernel(addr + 8);
2239 bswap64s(&env->gregs[1]);
2240 } else if (rd < 8) {
2241 env->gregs[rd] = ldq_kernel(addr);
2242 env->gregs[rd + 1] = ldq_kernel(addr + 8);
2244 bswap64s(&env->gregs[rd]);
2245 bswap64s(&env->gregs[rd + 1]);
2248 env->regwptr[rd] = ldq_kernel(addr);
2249 env->regwptr[rd + 1] = ldq_kernel(addr + 8);
2251 bswap64s(&env->regwptr[rd]);
2252 bswap64s(&env->regwptr[rd + 1]);
2257 helper_check_align(addr, 0x3);
2259 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
2261 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
2262 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2264 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
2265 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2271 void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
2276 helper_check_align(addr, 3);
2278 case 0xf0: // Block load primary
2279 case 0xf1: // Block load secondary
2280 case 0xf8: // Block load primary LE
2281 case 0xf9: // Block load secondary LE
2283 raise_exception(TT_ILL_INSN);
2286 helper_check_align(addr, 0x3f);
2287 for (i = 0; i < 16; i++) {
2288 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
2298 val = helper_ld_asi(addr, asi, size, 0);
2302 *((uint32_t *)&env->fpr[rd]) = val;
2305 *((int64_t *)&DT0) = val;
2313 void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
2316 target_ulong val = 0;
2318 helper_check_align(addr, 3);
2320 case 0xe0: // UA2007 Block commit store primary (cache flush)
2321 case 0xe1: // UA2007 Block commit store secondary (cache flush)
2322 case 0xf0: // Block store primary
2323 case 0xf1: // Block store secondary
2324 case 0xf8: // Block store primary LE
2325 case 0xf9: // Block store secondary LE
2327 raise_exception(TT_ILL_INSN);
2330 helper_check_align(addr, 0x3f);
2331 for (i = 0; i < 16; i++) {
2332 val = *(uint32_t *)&env->fpr[rd++];
2333 helper_st_asi(addr, val, asi & 0x8f, 4);
2345 val = *((uint32_t *)&env->fpr[rd]);
2348 val = *((int64_t *)&DT0);
2354 helper_st_asi(addr, val, asi, size);
2357 target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2358 target_ulong val2, uint32_t asi)
2362 val2 &= 0xffffffffUL;
2363 ret = helper_ld_asi(addr, asi, 4, 0);
2364 ret &= 0xffffffffUL;
2366 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
2370 target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2371 target_ulong val2, uint32_t asi)
2375 ret = helper_ld_asi(addr, asi, 8, 0);
2377 helper_st_asi(addr, val1, asi, 8);
2380 #endif /* TARGET_SPARC64 */
2382 #ifndef TARGET_SPARC64
2383 void helper_rett(void)
2387 if (env->psret == 1)
2388 raise_exception(TT_ILL_INSN);
2391 cwp = cpu_cwp_inc(env, env->cwp + 1) ;
2392 if (env->wim & (1 << cwp)) {
2393 raise_exception(TT_WIN_UNF);
2396 env->psrs = env->psrps;
2400 target_ulong helper_udiv(target_ulong a, target_ulong b)
2405 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
2409 raise_exception(TT_DIV_ZERO);
2413 if (x0 > 0xffffffff) {
2422 target_ulong helper_sdiv(target_ulong a, target_ulong b)
2427 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
2431 raise_exception(TT_DIV_ZERO);
2435 if ((int32_t) x0 != x0) {
2437 return x0 < 0? 0x80000000: 0x7fffffff;
2444 void helper_stdf(target_ulong addr, int mem_idx)
2446 helper_check_align(addr, 7);
2447 #if !defined(CONFIG_USER_ONLY)
2450 stfq_user(addr, DT0);
2453 stfq_kernel(addr, DT0);
2455 #ifdef TARGET_SPARC64
2457 stfq_hypv(addr, DT0);
2464 address_mask(env, &addr);
2465 stfq_raw(addr, DT0);
2469 void helper_lddf(target_ulong addr, int mem_idx)
2471 helper_check_align(addr, 7);
2472 #if !defined(CONFIG_USER_ONLY)
2475 DT0 = ldfq_user(addr);
2478 DT0 = ldfq_kernel(addr);
2480 #ifdef TARGET_SPARC64
2482 DT0 = ldfq_hypv(addr);
2489 address_mask(env, &addr);
2490 DT0 = ldfq_raw(addr);
2494 void helper_ldqf(target_ulong addr, int mem_idx)
2496 // XXX add 128 bit load
2499 helper_check_align(addr, 7);
2500 #if !defined(CONFIG_USER_ONLY)
2503 u.ll.upper = ldq_user(addr);
2504 u.ll.lower = ldq_user(addr + 8);
2508 u.ll.upper = ldq_kernel(addr);
2509 u.ll.lower = ldq_kernel(addr + 8);
2512 #ifdef TARGET_SPARC64
2514 u.ll.upper = ldq_hypv(addr);
2515 u.ll.lower = ldq_hypv(addr + 8);
2523 address_mask(env, &addr);
2524 u.ll.upper = ldq_raw(addr);
2525 u.ll.lower = ldq_raw((addr + 8) & 0xffffffffULL);
2530 void helper_stqf(target_ulong addr, int mem_idx)
2532 // XXX add 128 bit store
2535 helper_check_align(addr, 7);
2536 #if !defined(CONFIG_USER_ONLY)
2540 stq_user(addr, u.ll.upper);
2541 stq_user(addr + 8, u.ll.lower);
2545 stq_kernel(addr, u.ll.upper);
2546 stq_kernel(addr + 8, u.ll.lower);
2548 #ifdef TARGET_SPARC64
2551 stq_hypv(addr, u.ll.upper);
2552 stq_hypv(addr + 8, u.ll.lower);
2560 address_mask(env, &addr);
2561 stq_raw(addr, u.ll.upper);
2562 stq_raw((addr + 8) & 0xffffffffULL, u.ll.lower);
2566 static inline void set_fsr(void)
2570 switch (env->fsr & FSR_RD_MASK) {
2571 case FSR_RD_NEAREST:
2572 rnd_mode = float_round_nearest_even;
2576 rnd_mode = float_round_to_zero;
2579 rnd_mode = float_round_up;
2582 rnd_mode = float_round_down;
2585 set_float_rounding_mode(rnd_mode, &env->fp_status);
2588 void helper_ldfsr(uint32_t new_fsr)
2590 env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
2594 #ifdef TARGET_SPARC64
2595 void helper_ldxfsr(uint64_t new_fsr)
2597 env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
2602 void helper_debug(void)
2604 env->exception_index = EXCP_DEBUG;
2608 #ifndef TARGET_SPARC64
2609 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2611 void helper_save(void)
2615 cwp = cpu_cwp_dec(env, env->cwp - 1);
2616 if (env->wim & (1 << cwp)) {
2617 raise_exception(TT_WIN_OVF);
2622 void helper_restore(void)
2626 cwp = cpu_cwp_inc(env, env->cwp + 1);
2627 if (env->wim & (1 << cwp)) {
2628 raise_exception(TT_WIN_UNF);
2633 void helper_wrpsr(target_ulong new_psr)
2635 if ((new_psr & PSR_CWP) >= env->nwindows)
2636 raise_exception(TT_ILL_INSN);
2638 PUT_PSR(env, new_psr);
2641 target_ulong helper_rdpsr(void)
2643 return GET_PSR(env);
2647 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2649 void helper_save(void)
2653 cwp = cpu_cwp_dec(env, env->cwp - 1);
2654 if (env->cansave == 0) {
2655 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2656 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2657 ((env->wstate & 0x7) << 2)));
2659 if (env->cleanwin - env->canrestore == 0) {
2660 // XXX Clean windows without trap
2661 raise_exception(TT_CLRWIN);
2670 void helper_restore(void)
2674 cwp = cpu_cwp_inc(env, env->cwp + 1);
2675 if (env->canrestore == 0) {
2676 raise_exception(TT_FILL | (env->otherwin != 0 ?
2677 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2678 ((env->wstate & 0x7) << 2)));
2686 void helper_flushw(void)
2688 if (env->cansave != env->nwindows - 2) {
2689 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2690 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2691 ((env->wstate & 0x7) << 2)));
2695 void helper_saved(void)
2698 if (env->otherwin == 0)
2704 void helper_restored(void)
2707 if (env->cleanwin < env->nwindows - 1)
2709 if (env->otherwin == 0)
2715 target_ulong helper_rdccr(void)
2717 return GET_CCR(env);
2720 void helper_wrccr(target_ulong new_ccr)
2722 PUT_CCR(env, new_ccr);
2725 // CWP handling is reversed in V9, but we still use the V8 register
2727 target_ulong helper_rdcwp(void)
2729 return GET_CWP64(env);
2732 void helper_wrcwp(target_ulong new_cwp)
2734 PUT_CWP64(env, new_cwp);
2737 // This function uses non-native bit order
2738 #define GET_FIELD(X, FROM, TO) \
2739 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2741 // This function uses the order in the manuals, i.e. bit 0 is 2^0
2742 #define GET_FIELD_SP(X, FROM, TO) \
2743 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2745 target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
2747 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
2748 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
2749 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
2750 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
2751 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
2752 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
2753 (((pixel_addr >> 55) & 1) << 4) |
2754 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
2755 GET_FIELD_SP(pixel_addr, 11, 12);
2758 target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
2762 tmp = addr + offset;
2764 env->gsr |= tmp & 7ULL;
2768 target_ulong helper_popc(target_ulong val)
2770 return ctpop64(val);
2773 static inline uint64_t *get_gregset(uint64_t pstate)
2788 static inline void change_pstate(uint64_t new_pstate)
2790 uint64_t pstate_regs, new_pstate_regs;
2791 uint64_t *src, *dst;
2793 pstate_regs = env->pstate & 0xc01;
2794 new_pstate_regs = new_pstate & 0xc01;
2795 if (new_pstate_regs != pstate_regs) {
2796 // Switch global register bank
2797 src = get_gregset(new_pstate_regs);
2798 dst = get_gregset(pstate_regs);
2799 memcpy32(dst, env->gregs);
2800 memcpy32(env->gregs, src);
2802 env->pstate = new_pstate;
2805 void helper_wrpstate(target_ulong new_state)
2807 if (!(env->def->features & CPU_FEATURE_GL))
2808 change_pstate(new_state & 0xf3f);
2811 void helper_done(void)
2813 env->pc = env->tsptr->tpc;
2814 env->npc = env->tsptr->tnpc + 4;
2815 PUT_CCR(env, env->tsptr->tstate >> 32);
2816 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2817 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2818 PUT_CWP64(env, env->tsptr->tstate & 0xff);
2820 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
2823 void helper_retry(void)
2825 env->pc = env->tsptr->tpc;
2826 env->npc = env->tsptr->tnpc;
2827 PUT_CCR(env, env->tsptr->tstate >> 32);
2828 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2829 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2830 PUT_CWP64(env, env->tsptr->tstate & 0xff);
2832 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
2835 void helper_set_softint(uint64_t value)
2837 env->softint |= (uint32_t)value;
2840 void helper_clear_softint(uint64_t value)
2842 env->softint &= (uint32_t)~value;
2845 void helper_write_softint(uint64_t value)
2847 env->softint = (uint32_t)value;
2851 void helper_flush(target_ulong addr)
2854 tb_invalidate_page_range(addr, addr + 8);
2857 #ifdef TARGET_SPARC64
2859 static const char * const excp_names[0x80] = {
2860 [TT_TFAULT] = "Instruction Access Fault",
2861 [TT_TMISS] = "Instruction Access MMU Miss",
2862 [TT_CODE_ACCESS] = "Instruction Access Error",
2863 [TT_ILL_INSN] = "Illegal Instruction",
2864 [TT_PRIV_INSN] = "Privileged Instruction",
2865 [TT_NFPU_INSN] = "FPU Disabled",
2866 [TT_FP_EXCP] = "FPU Exception",
2867 [TT_TOVF] = "Tag Overflow",
2868 [TT_CLRWIN] = "Clean Windows",
2869 [TT_DIV_ZERO] = "Division By Zero",
2870 [TT_DFAULT] = "Data Access Fault",
2871 [TT_DMISS] = "Data Access MMU Miss",
2872 [TT_DATA_ACCESS] = "Data Access Error",
2873 [TT_DPROT] = "Data Protection Error",
2874 [TT_UNALIGNED] = "Unaligned Memory Access",
2875 [TT_PRIV_ACT] = "Privileged Action",
2876 [TT_EXTINT | 0x1] = "External Interrupt 1",
2877 [TT_EXTINT | 0x2] = "External Interrupt 2",
2878 [TT_EXTINT | 0x3] = "External Interrupt 3",
2879 [TT_EXTINT | 0x4] = "External Interrupt 4",
2880 [TT_EXTINT | 0x5] = "External Interrupt 5",
2881 [TT_EXTINT | 0x6] = "External Interrupt 6",
2882 [TT_EXTINT | 0x7] = "External Interrupt 7",
2883 [TT_EXTINT | 0x8] = "External Interrupt 8",
2884 [TT_EXTINT | 0x9] = "External Interrupt 9",
2885 [TT_EXTINT | 0xa] = "External Interrupt 10",
2886 [TT_EXTINT | 0xb] = "External Interrupt 11",
2887 [TT_EXTINT | 0xc] = "External Interrupt 12",
2888 [TT_EXTINT | 0xd] = "External Interrupt 13",
2889 [TT_EXTINT | 0xe] = "External Interrupt 14",
2890 [TT_EXTINT | 0xf] = "External Interrupt 15",
2894 void do_interrupt(CPUState *env)
2896 int intno = env->exception_index;
2899 if (qemu_loglevel_mask(CPU_LOG_INT)) {
2903 if (intno < 0 || intno >= 0x180)
2905 else if (intno >= 0x100)
2906 name = "Trap Instruction";
2907 else if (intno >= 0xc0)
2908 name = "Window Fill";
2909 else if (intno >= 0x80)
2910 name = "Window Spill";
2912 name = excp_names[intno];
2917 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
2918 " SP=%016" PRIx64 "\n",
2921 env->npc, env->regwptr[6]);
2922 log_cpu_state(env, 0);
2929 ptr = (uint8_t *)env->pc;
2930 for(i = 0; i < 16; i++) {
2931 qemu_log(" %02x", ldub(ptr + i));
2939 #if !defined(CONFIG_USER_ONLY)
2940 if (env->tl >= env->maxtl) {
2941 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
2942 " Error state", env->exception_index, env->tl, env->maxtl);
2946 if (env->tl < env->maxtl - 1) {
2949 env->pstate |= PS_RED;
2950 if (env->tl < env->maxtl)
2953 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
2954 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
2955 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
2957 env->tsptr->tpc = env->pc;
2958 env->tsptr->tnpc = env->npc;
2959 env->tsptr->tt = intno;
2960 if (!(env->def->features & CPU_FEATURE_GL)) {
2963 change_pstate(PS_PEF | PS_PRIV | PS_IG);
2970 change_pstate(PS_PEF | PS_PRIV | PS_MG);
2973 change_pstate(PS_PEF | PS_PRIV | PS_AG);
2977 if (intno == TT_CLRWIN)
2978 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
2979 else if ((intno & 0x1c0) == TT_SPILL)
2980 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
2981 else if ((intno & 0x1c0) == TT_FILL)
2982 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
2983 env->tbr &= ~0x7fffULL;
2984 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
2986 env->npc = env->pc + 4;
2987 env->exception_index = 0;
2991 static const char * const excp_names[0x80] = {
2992 [TT_TFAULT] = "Instruction Access Fault",
2993 [TT_ILL_INSN] = "Illegal Instruction",
2994 [TT_PRIV_INSN] = "Privileged Instruction",
2995 [TT_NFPU_INSN] = "FPU Disabled",
2996 [TT_WIN_OVF] = "Window Overflow",
2997 [TT_WIN_UNF] = "Window Underflow",
2998 [TT_UNALIGNED] = "Unaligned Memory Access",
2999 [TT_FP_EXCP] = "FPU Exception",
3000 [TT_DFAULT] = "Data Access Fault",
3001 [TT_TOVF] = "Tag Overflow",
3002 [TT_EXTINT | 0x1] = "External Interrupt 1",
3003 [TT_EXTINT | 0x2] = "External Interrupt 2",
3004 [TT_EXTINT | 0x3] = "External Interrupt 3",
3005 [TT_EXTINT | 0x4] = "External Interrupt 4",
3006 [TT_EXTINT | 0x5] = "External Interrupt 5",
3007 [TT_EXTINT | 0x6] = "External Interrupt 6",
3008 [TT_EXTINT | 0x7] = "External Interrupt 7",
3009 [TT_EXTINT | 0x8] = "External Interrupt 8",
3010 [TT_EXTINT | 0x9] = "External Interrupt 9",
3011 [TT_EXTINT | 0xa] = "External Interrupt 10",
3012 [TT_EXTINT | 0xb] = "External Interrupt 11",
3013 [TT_EXTINT | 0xc] = "External Interrupt 12",
3014 [TT_EXTINT | 0xd] = "External Interrupt 13",
3015 [TT_EXTINT | 0xe] = "External Interrupt 14",
3016 [TT_EXTINT | 0xf] = "External Interrupt 15",
3017 [TT_TOVF] = "Tag Overflow",
3018 [TT_CODE_ACCESS] = "Instruction Access Error",
3019 [TT_DATA_ACCESS] = "Data Access Error",
3020 [TT_DIV_ZERO] = "Division By Zero",
3021 [TT_NCP_INSN] = "Coprocessor Disabled",
3025 void do_interrupt(CPUState *env)
3027 int cwp, intno = env->exception_index;
3030 if (qemu_loglevel_mask(CPU_LOG_INT)) {
3034 if (intno < 0 || intno >= 0x100)
3036 else if (intno >= 0x80)
3037 name = "Trap Instruction";
3039 name = excp_names[intno];
3044 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
3047 env->npc, env->regwptr[6]);
3048 log_cpu_state(env, 0);
3055 ptr = (uint8_t *)env->pc;
3056 for(i = 0; i < 16; i++) {
3057 qemu_log(" %02x", ldub(ptr + i));
3065 #if !defined(CONFIG_USER_ONLY)
3066 if (env->psret == 0) {
3067 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
3068 env->exception_index);
3073 cwp = cpu_cwp_dec(env, env->cwp - 1);
3074 cpu_set_cwp(env, cwp);
3075 env->regwptr[9] = env->pc;
3076 env->regwptr[10] = env->npc;
3077 env->psrps = env->psrs;
3079 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
3081 env->npc = env->pc + 4;
3082 env->exception_index = 0;
3086 #if !defined(CONFIG_USER_ONLY)
3088 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
3091 #define MMUSUFFIX _mmu
3092 #define ALIGNED_ONLY
3095 #include "softmmu_template.h"
3098 #include "softmmu_template.h"
3101 #include "softmmu_template.h"
3104 #include "softmmu_template.h"
3106 /* XXX: make it generic ? */
3107 static void cpu_restore_state2(void *retaddr)
3109 TranslationBlock *tb;
3113 /* now we have a real cpu fault */
3114 pc = (unsigned long)retaddr;
3115 tb = tb_find_pc(pc);
3117 /* the PC is inside the translated code. It means that we have
3118 a virtual CPU fault */
3119 cpu_restore_state(tb, env, pc, (void *)(long)env->cond);
3124 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
3127 #ifdef DEBUG_UNALIGNED
3128 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
3129 "\n", addr, env->pc);
3131 cpu_restore_state2(retaddr);
3132 raise_exception(TT_UNALIGNED);
3135 /* try to fill the TLB and return an exception if error. If retaddr is
3136 NULL, it means that the function was called in C code (i.e. not
3137 from generated code or from helper.c) */
3138 /* XXX: fix it to restore all registers */
3139 void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
3142 CPUState *saved_env;
3144 /* XXX: hack to restore env in all cases, even if not called from
3147 env = cpu_single_env;
3149 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
3151 cpu_restore_state2(retaddr);
3159 #ifndef TARGET_SPARC64
3160 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
3161 int is_asi, int size)
3163 CPUState *saved_env;
3165 /* XXX: hack to restore env in all cases, even if not called from
3168 env = cpu_single_env;
3169 #ifdef DEBUG_UNASSIGNED
3171 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
3172 " asi 0x%02x from " TARGET_FMT_lx "\n",
3173 is_exec ? "exec" : is_write ? "write" : "read", size,
3174 size == 1 ? "" : "s", addr, is_asi, env->pc);
3176 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
3177 " from " TARGET_FMT_lx "\n",
3178 is_exec ? "exec" : is_write ? "write" : "read", size,
3179 size == 1 ? "" : "s", addr, env->pc);
3181 if (env->mmuregs[3]) /* Fault status register */
3182 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
3184 env->mmuregs[3] |= 1 << 16;
3186 env->mmuregs[3] |= 1 << 5;
3188 env->mmuregs[3] |= 1 << 6;
3190 env->mmuregs[3] |= 1 << 7;
3191 env->mmuregs[3] |= (5 << 2) | 2;
3192 env->mmuregs[4] = addr; /* Fault address register */
3193 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
3195 raise_exception(TT_CODE_ACCESS);
3197 raise_exception(TT_DATA_ACCESS);
3202 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
3203 int is_asi, int size)
3205 #ifdef DEBUG_UNASSIGNED
3206 CPUState *saved_env;
3208 /* XXX: hack to restore env in all cases, even if not called from
3211 env = cpu_single_env;
3212 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
3213 "\n", addr, env->pc);
3217 raise_exception(TT_CODE_ACCESS);
3219 raise_exception(TT_DATA_ACCESS);
3223 #ifdef TARGET_SPARC64
3224 void helper_tick_set_count(void *opaque, uint64_t count)
3226 #if !defined(CONFIG_USER_ONLY)
3227 cpu_tick_set_count(opaque, count);
3231 uint64_t helper_tick_get_count(void *opaque)
3233 #if !defined(CONFIG_USER_ONLY)
3234 return cpu_tick_get_count(opaque);
3240 void helper_tick_set_limit(void *opaque, uint64_t limit)
3242 #if !defined(CONFIG_USER_ONLY)
3243 cpu_tick_set_limit(opaque, limit);