6 void raise_exception(int tt)
8 env->exception_index = tt;
12 void check_ieee_exceptions()
14 T0 = get_float_exception_flags(&env->fp_status);
17 /* Copy IEEE 754 flags into FSR */
18 if (T0 & float_flag_invalid)
20 if (T0 & float_flag_overflow)
22 if (T0 & float_flag_underflow)
24 if (T0 & float_flag_divbyzero)
26 if (T0 & float_flag_inexact)
29 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
31 /* Unmasked exception, generate a trap */
32 env->fsr |= FSR_FTT_IEEE_EXCP;
33 raise_exception(TT_FP_EXCP);
37 /* Accumulate exceptions */
38 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
43 #ifdef USE_INT_TO_FLOAT_HELPERS
46 set_float_exception_flags(0, &env->fp_status);
47 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
48 check_ieee_exceptions();
53 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
59 FT0 = float32_abs(FT1);
65 DT0 = float64_abs(DT1);
71 set_float_exception_flags(0, &env->fp_status);
72 FT0 = float32_sqrt(FT1, &env->fp_status);
73 check_ieee_exceptions();
78 set_float_exception_flags(0, &env->fp_status);
79 DT0 = float64_sqrt(DT1, &env->fp_status);
80 check_ieee_exceptions();
83 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
84 void glue(do_, name) (void) \
86 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
87 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
88 case float_relation_unordered: \
89 T0 = (FSR_FCC1 | FSR_FCC0) << FS; \
90 if ((env->fsr & FSR_NVM) || TRAP) { \
92 env->fsr |= FSR_NVC; \
93 env->fsr |= FSR_FTT_IEEE_EXCP; \
94 raise_exception(TT_FP_EXCP); \
96 env->fsr |= FSR_NVA; \
99 case float_relation_less: \
100 T0 = FSR_FCC0 << FS; \
102 case float_relation_greater: \
103 T0 = FSR_FCC1 << FS; \
112 GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
113 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
115 GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
116 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
118 #ifdef TARGET_SPARC64
119 GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
120 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
122 GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
123 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
125 GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
126 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
128 GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
129 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
131 GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
132 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
134 GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
135 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
138 #if defined(CONFIG_USER_ONLY)
139 void helper_ld_asi(int asi, int size, int sign)
143 void helper_st_asi(int asi, int size, int sign)
147 #ifndef TARGET_SPARC64
148 void helper_ld_asi(int asi, int size, int sign)
153 case 3: /* MMU probe */
157 mmulev = (T0 >> 8) & 15;
161 ret = mmu_probe(env, T0, mmulev);
165 printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
169 case 4: /* read MMU regs */
171 int reg = (T0 >> 8) & 0xf;
173 ret = env->mmuregs[reg];
174 if (reg == 3) /* Fault status cleared on read */
175 env->mmuregs[reg] = 0;
177 printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
181 case 0x20 ... 0x2f: /* MMU passthrough */
187 ret = lduw_phys(T0 & ~1);
191 ret = ldl_phys(T0 & ~3);
194 ret = ldl_phys(T0 & ~3);
195 T0 = ldl_phys((T0 + 4) & ~3);
206 void helper_st_asi(int asi, int size, int sign)
209 case 3: /* MMU flush */
213 mmulev = (T0 >> 8) & 15;
215 printf("mmu flush level %d\n", mmulev);
218 case 0: // flush page
219 tlb_flush_page(env, T0 & 0xfffff000);
221 case 1: // flush segment (256k)
222 case 2: // flush region (16M)
223 case 3: // flush context (4G)
224 case 4: // flush entire
235 case 4: /* write MMU regs */
237 int reg = (T0 >> 8) & 0xf;
240 oldreg = env->mmuregs[reg];
243 env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
244 env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
245 // Mappings generated during no-fault mode or MMU
246 // disabled mode are invalid in normal mode
247 if (oldreg != env->mmuregs[reg])
251 env->mmuregs[reg] = T1;
252 if (oldreg != env->mmuregs[reg]) {
253 /* we flush when the MMU context changes because
254 QEMU has no MMU context support */
262 env->mmuregs[reg] = T1;
266 if (oldreg != env->mmuregs[reg]) {
267 printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
273 case 0x17: /* Block copy, sta access */
276 // address (T0) = dst
278 uint32_t src = T1, dst = T0;
283 cpu_physical_memory_read(src, (void *) &temp, 32);
284 cpu_physical_memory_write(dst, (void *) &temp, 32);
287 case 0x1f: /* Block fill, stda access */
290 // address (T0) = dst
296 val = (((uint64_t)T1) << 32) | T2;
299 for (i = 0; i < 32; i += 8, dst += 8) {
300 cpu_physical_memory_write(dst, (void *) &val, 8);
304 case 0x20 ... 0x2f: /* MMU passthrough */
311 stw_phys(T0 & ~1, T1);
315 stl_phys(T0 & ~3, T1);
318 stl_phys(T0 & ~3, T1);
319 stl_phys((T0 + 4) & ~3, T2);
331 void helper_ld_asi(int asi, int size, int sign)
335 if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
336 raise_exception(TT_PRIV_ACT);
340 case 0x15: // Bypass, non-cacheable
347 ret = lduw_phys(T0 & ~1);
350 ret = ldl_phys(T0 & ~3);
354 ret = ldq_phys(T0 & ~7);
359 case 0x04: // Nucleus
360 case 0x0c: // Nucleus Little Endian (LE)
361 case 0x10: // As if user primary
362 case 0x11: // As if user secondary
363 case 0x18: // As if user primary LE
364 case 0x19: // As if user secondary LE
365 case 0x1c: // Bypass LE
366 case 0x1d: // Bypass, non-cacheable LE
367 case 0x24: // Nucleus quad LDD 128 bit atomic
368 case 0x2c: // Nucleus quad LDD 128 bit atomic
369 case 0x4a: // UPA config
370 case 0x82: // Primary no-fault
371 case 0x83: // Secondary no-fault
372 case 0x88: // Primary LE
373 case 0x89: // Secondary LE
374 case 0x8a: // Primary no-fault LE
375 case 0x8b: // Secondary no-fault LE
381 case 0x50: // I-MMU regs
383 int reg = (T0 >> 3) & 0xf;
385 ret = env->immuregs[reg];
388 case 0x51: // I-MMU 8k TSB pointer
389 case 0x52: // I-MMU 64k TSB pointer
390 case 0x55: // I-MMU data access
393 case 0x56: // I-MMU tag read
397 for (i = 0; i < 64; i++) {
398 // Valid, ctx match, vaddr match
399 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
400 env->itlb_tag[i] == T0) {
401 ret = env->itlb_tag[i];
407 case 0x58: // D-MMU regs
409 int reg = (T0 >> 3) & 0xf;
411 ret = env->dmmuregs[reg];
414 case 0x5e: // D-MMU tag read
418 for (i = 0; i < 64; i++) {
419 // Valid, ctx match, vaddr match
420 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
421 env->dtlb_tag[i] == T0) {
422 ret = env->dtlb_tag[i];
428 case 0x59: // D-MMU 8k TSB pointer
429 case 0x5a: // D-MMU 64k TSB pointer
430 case 0x5b: // D-MMU data pointer
431 case 0x5d: // D-MMU data access
432 case 0x48: // Interrupt dispatch, RO
433 case 0x49: // Interrupt data receive
434 case 0x7f: // Incoming interrupt vector, RO
437 case 0x54: // I-MMU data in, WO
438 case 0x57: // I-MMU demap, WO
439 case 0x5c: // D-MMU data in, WO
440 case 0x5f: // D-MMU demap, WO
441 case 0x77: // Interrupt vector, WO
449 void helper_st_asi(int asi, int size, int sign)
451 if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
452 raise_exception(TT_PRIV_ACT);
456 case 0x15: // Bypass, non-cacheable
463 stw_phys(T0 & ~1, T1);
466 stl_phys(T0 & ~3, T1);
470 stq_phys(T0 & ~7, T1);
475 case 0x04: // Nucleus
476 case 0x0c: // Nucleus Little Endian (LE)
477 case 0x10: // As if user primary
478 case 0x11: // As if user secondary
479 case 0x18: // As if user primary LE
480 case 0x19: // As if user secondary LE
481 case 0x1c: // Bypass LE
482 case 0x1d: // Bypass, non-cacheable LE
483 case 0x24: // Nucleus quad LDD 128 bit atomic
484 case 0x2c: // Nucleus quad LDD 128 bit atomic
485 case 0x4a: // UPA config
486 case 0x88: // Primary LE
487 case 0x89: // Secondary LE
495 env->lsu = T1 & (DMMU_E | IMMU_E);
496 // Mappings generated during D/I MMU disabled mode are
497 // invalid in normal mode
498 if (oldreg != env->lsu) {
500 printf("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
507 case 0x50: // I-MMU regs
509 int reg = (T0 >> 3) & 0xf;
512 oldreg = env->immuregs[reg];
517 case 1: // Not in I-MMU
524 T1 = 0; // Clear SFSR
526 case 5: // TSB access
527 case 6: // Tag access
531 env->immuregs[reg] = T1;
533 if (oldreg != env->immuregs[reg]) {
534 printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
540 case 0x54: // I-MMU data in
544 // Try finding an invalid entry
545 for (i = 0; i < 64; i++) {
546 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
547 env->itlb_tag[i] = env->immuregs[6];
548 env->itlb_tte[i] = T1;
552 // Try finding an unlocked entry
553 for (i = 0; i < 64; i++) {
554 if ((env->itlb_tte[i] & 0x40) == 0) {
555 env->itlb_tag[i] = env->immuregs[6];
556 env->itlb_tte[i] = T1;
563 case 0x55: // I-MMU data access
565 unsigned int i = (T0 >> 3) & 0x3f;
567 env->itlb_tag[i] = env->immuregs[6];
568 env->itlb_tte[i] = T1;
571 case 0x57: // I-MMU demap
574 case 0x58: // D-MMU regs
576 int reg = (T0 >> 3) & 0xf;
579 oldreg = env->dmmuregs[reg];
586 T1 = 0; // Clear SFSR, Fault address
587 env->dmmuregs[4] = 0;
589 env->dmmuregs[reg] = T1;
591 case 1: // Primary context
592 case 2: // Secondary context
593 case 5: // TSB access
594 case 6: // Tag access
595 case 7: // Virtual Watchpoint
596 case 8: // Physical Watchpoint
600 env->dmmuregs[reg] = T1;
602 if (oldreg != env->dmmuregs[reg]) {
603 printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
609 case 0x5c: // D-MMU data in
613 // Try finding an invalid entry
614 for (i = 0; i < 64; i++) {
615 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
616 env->dtlb_tag[i] = env->dmmuregs[6];
617 env->dtlb_tte[i] = T1;
621 // Try finding an unlocked entry
622 for (i = 0; i < 64; i++) {
623 if ((env->dtlb_tte[i] & 0x40) == 0) {
624 env->dtlb_tag[i] = env->dmmuregs[6];
625 env->dtlb_tte[i] = T1;
632 case 0x5d: // D-MMU data access
634 unsigned int i = (T0 >> 3) & 0x3f;
636 env->dtlb_tag[i] = env->dmmuregs[6];
637 env->dtlb_tte[i] = T1;
640 case 0x5f: // D-MMU demap
641 case 0x49: // Interrupt data receive
644 case 0x51: // I-MMU 8k TSB pointer, RO
645 case 0x52: // I-MMU 64k TSB pointer, RO
646 case 0x56: // I-MMU tag read, RO
647 case 0x59: // D-MMU 8k TSB pointer, RO
648 case 0x5a: // D-MMU 64k TSB pointer, RO
649 case 0x5b: // D-MMU data pointer, RO
650 case 0x5e: // D-MMU tag read, RO
651 case 0x48: // Interrupt dispatch, RO
652 case 0x7f: // Incoming interrupt vector, RO
653 case 0x82: // Primary no-fault, RO
654 case 0x83: // Secondary no-fault, RO
655 case 0x8a: // Primary no-fault LE, RO
656 case 0x8b: // Secondary no-fault LE, RO
662 #endif /* !CONFIG_USER_ONLY */
664 #ifndef TARGET_SPARC64
670 raise_exception(TT_ILL_INSN);
673 cwp = (env->cwp + 1) & (NWINDOWS - 1);
674 if (env->wim & (1 << cwp)) {
675 raise_exception(TT_WIN_UNF);
678 env->psrs = env->psrps;
682 void helper_ldfsr(void)
685 switch (env->fsr & FSR_RD_MASK) {
687 rnd_mode = float_round_nearest_even;
691 rnd_mode = float_round_to_zero;
694 rnd_mode = float_round_up;
697 rnd_mode = float_round_down;
700 set_float_rounding_mode(rnd_mode, &env->fp_status);
705 env->exception_index = EXCP_DEBUG;
709 #ifndef TARGET_SPARC64
712 if ((T0 & PSR_CWP) >= NWINDOWS)
713 raise_exception(TT_ILL_INSN);
727 T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL);
728 T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL);
729 T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL);
730 T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL);
731 T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL);
732 T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL);
735 static inline uint64_t *get_gregset(uint64_t pstate)
752 uint64_t new_pstate, pstate_regs, new_pstate_regs;
755 new_pstate = T0 & 0xf3f;
756 pstate_regs = env->pstate & 0xc01;
757 new_pstate_regs = new_pstate & 0xc01;
758 if (new_pstate_regs != pstate_regs) {
759 // Switch global register bank
760 src = get_gregset(new_pstate_regs);
761 dst = get_gregset(pstate_regs);
762 memcpy32(dst, env->gregs);
763 memcpy32(env->gregs, src);
765 env->pstate = new_pstate;
771 env->pc = env->tnpc[env->tl];
772 env->npc = env->tnpc[env->tl] + 4;
773 PUT_CCR(env, env->tstate[env->tl] >> 32);
774 env->asi = (env->tstate[env->tl] >> 24) & 0xff;
775 env->pstate = (env->tstate[env->tl] >> 8) & 0xfff;
776 set_cwp(env->tstate[env->tl] & 0xff);
782 env->pc = env->tpc[env->tl];
783 env->npc = env->tnpc[env->tl];
784 PUT_CCR(env, env->tstate[env->tl] >> 32);
785 env->asi = (env->tstate[env->tl] >> 24) & 0xff;
786 env->pstate = (env->tstate[env->tl] >> 8) & 0xfff;
787 set_cwp(env->tstate[env->tl] & 0xff);
791 void set_cwp(int new_cwp)
793 /* put the modified wrap registers at their proper location */
794 if (env->cwp == (NWINDOWS - 1))
795 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
797 /* put the wrap registers at their temporary location */
798 if (new_cwp == (NWINDOWS - 1))
799 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
800 env->regwptr = env->regbase + (new_cwp * 16);
801 REGWPTR = env->regwptr;
804 void cpu_set_cwp(CPUState *env1, int new_cwp)
808 target_ulong *saved_regwptr;
813 saved_regwptr = REGWPTR;
819 REGWPTR = saved_regwptr;
823 #ifdef TARGET_SPARC64
824 void do_interrupt(int intno)
827 if (loglevel & CPU_LOG_INT) {
829 fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
832 env->npc, env->regwptr[6]);
833 cpu_dump_state(env, logfile, fprintf, 0);
839 fprintf(logfile, " code=");
840 ptr = (uint8_t *)env->pc;
841 for(i = 0; i < 16; i++) {
842 fprintf(logfile, " %02x", ldub(ptr + i));
844 fprintf(logfile, "\n");
850 #if !defined(CONFIG_USER_ONLY)
851 if (env->tl == MAXTL) {
852 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
856 env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
857 ((env->pstate & 0xfff) << 8) | (env->cwp & 0xff);
858 env->tpc[env->tl] = env->pc;
859 env->tnpc[env->tl] = env->npc;
860 env->tt[env->tl] = intno;
861 env->pstate = PS_PEF | PS_PRIV | PS_AG;
862 env->tbr &= ~0x7fffULL;
863 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
864 if (env->tl < MAXTL - 1) {
867 env->pstate |= PS_RED;
868 if (env->tl != MAXTL)
872 env->npc = env->pc + 4;
873 env->exception_index = 0;
876 void do_interrupt(int intno)
881 if (loglevel & CPU_LOG_INT) {
883 fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
886 env->npc, env->regwptr[6]);
887 cpu_dump_state(env, logfile, fprintf, 0);
893 fprintf(logfile, " code=");
894 ptr = (uint8_t *)env->pc;
895 for(i = 0; i < 16; i++) {
896 fprintf(logfile, " %02x", ldub(ptr + i));
898 fprintf(logfile, "\n");
904 #if !defined(CONFIG_USER_ONLY)
905 if (env->psret == 0) {
906 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
911 cwp = (env->cwp - 1) & (NWINDOWS - 1);
913 env->regwptr[9] = env->pc;
914 env->regwptr[10] = env->npc;
915 env->psrps = env->psrs;
917 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
919 env->npc = env->pc + 4;
920 env->exception_index = 0;
924 #if !defined(CONFIG_USER_ONLY)
926 #define MMUSUFFIX _mmu
927 #define GETPC() (__builtin_return_address(0))
930 #include "softmmu_template.h"
933 #include "softmmu_template.h"
936 #include "softmmu_template.h"
939 #include "softmmu_template.h"
942 /* try to fill the TLB and return an exception if error. If retaddr is
943 NULL, it means that the function was called in C code (i.e. not
944 from generated code or from helper.c) */
945 /* XXX: fix it to restore all registers */
946 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
948 TranslationBlock *tb;
953 /* XXX: hack to restore env in all cases, even if not called from
956 env = cpu_single_env;
958 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
961 /* now we have a real cpu fault */
962 pc = (unsigned long)retaddr;
965 /* the PC is inside the translated code. It means that we have
966 a virtual CPU fault */
967 cpu_restore_state(tb, env, pc, (void *)T2);