git.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23    TODO-list:
  24
  25    Rest of V9 instructions, VIS instructions
  26    NPC/PC static optimisations (use JUMP_TB when possible)
  27    Optimize synthetic instructions
  28 */
  29
  30 #include <stdarg.h>
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <string.h>
  34 #include <inttypes.h>
  35
  36 #include "cpu.h"
  37 #include "exec-all.h"
  38 #include "disas.h"
  39 #include "helper.h"
  40 #include "tcg-op.h"
  41
  42 #define DEBUG_DISAS
  43
  44 #define DYNAMIC_PC  1 /* dynamic pc value */
  45 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  46                          according to jump_pc[T2] */
  47
  48 /* global register indexes */
  49 static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_dst, cpu_psr;
  50 #ifdef TARGET_SPARC64
  51 static TCGv cpu_xcc;
  52 #endif
  53 /* local register indexes (only used inside old micro ops) */
  54 static TCGv cpu_tmp0;
  55
  56 typedef struct DisasContext {
  57     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  58     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  59     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  60     int is_br;
  61     int mem_idx;
  62     int fpu_enabled;
  63     struct TranslationBlock *tb;
  64 } DisasContext;
  65
  66 typedef struct sparc_def_t sparc_def_t;
  67
  68 struct sparc_def_t {
  69     const unsigned char *name;
  70     target_ulong iu_version;
  71     uint32_t fpu_version;
  72     uint32_t mmu_version;
  73     uint32_t mmu_bm;
  74     uint32_t mmu_ctpr_mask;
  75     uint32_t mmu_cxr_mask;
  76     uint32_t mmu_sfsr_mask;
  77     uint32_t mmu_trcr_mask;
  78 };
  79
  80 static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
  81
  82 extern FILE *logfile;
  83 extern int loglevel;
  84
  85 // This function uses non-native bit order
  86 #define GET_FIELD(X, FROM, TO) \
  87   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  88
  89 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  90 #define GET_FIELD_SP(X, FROM, TO) \
  91     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  92
  93 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  94 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
  95
  96 #ifdef TARGET_SPARC64
  97 #define FFPREG(r) (r)
  98 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
  99 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
 100 #else
 101 #define FFPREG(r) (r)
 102 #define DFPREG(r) (r & 0x1e)
 103 #define QFPREG(r) (r & 0x1c)
 104 #endif
 105
 106 static int sign_extend(int x, int len)
 107 {
 108     len = 32 - len;
 109     return (x << len) >> len;
 110 }
 111
 112 #define IS_IMM (insn & (1<<13))
 113
 114 static void disas_sparc_insn(DisasContext * dc);
 115
 116 #ifdef TARGET_SPARC64
 117 #define GEN32(func, NAME) \
 118 static GenOpFunc * const NAME ## _table [64] = {                              \
 119 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
 120 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
 121 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
 122 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
 123 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
 124 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
 125 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
 126 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
 127 NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0,                   \
 128 NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0,                   \
 129 NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0,                   \
 130 NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0,                   \
 131 };                                                                            \
 132 static inline void func(int n)                                                \
 133 {                                                                             \
 134     NAME ## _table[n]();                                                      \
 135 }
 136 #else
 137 #define GEN32(func, NAME) \
 138 static GenOpFunc *const NAME ## _table [32] = {                               \
 139 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
 140 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
 141 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
 142 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
 143 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
 144 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
 145 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
 146 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
 147 };                                                                            \
 148 static inline void func(int n)                                                \
 149 {                                                                             \
 150     NAME ## _table[n]();                                                      \
 151 }
 152 #endif
 153
 154 /* floating point registers moves */
 155 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
 156 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
 157 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
 158 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
 159
 160 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
 161 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
 162 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
 163 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
 164
 165 #if defined(CONFIG_USER_ONLY)
 166 GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);
 167 GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);
 168 GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);
 169 GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
 170 #endif
 171
 172 /* moves */
 173 #ifdef CONFIG_USER_ONLY
 174 #define supervisor(dc) 0
 175 #ifdef TARGET_SPARC64
 176 #define hypervisor(dc) 0
 177 #endif
 178 #define gen_op_ldst(name)        gen_op_##name##_raw()
 179 #else
 180 #define supervisor(dc) (dc->mem_idx >= 1)
 181 #ifdef TARGET_SPARC64
 182 #define hypervisor(dc) (dc->mem_idx == 2)
 183 #define OP_LD_TABLE(width)                                              \
 184     static GenOpFunc * const gen_op_##width[] = {                       \
 185         &gen_op_##width##_user,                                         \
 186         &gen_op_##width##_kernel,                                       \
 187         &gen_op_##width##_hypv,                                         \
 188     };
 189 #else
 190 #define OP_LD_TABLE(width)                                              \
 191     static GenOpFunc * const gen_op_##width[] = {                       \
 192         &gen_op_##width##_user,                                         \
 193         &gen_op_##width##_kernel,                                       \
 194     };
 195 #endif
 196 #define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
 197 #endif
 198
 199 #ifndef CONFIG_USER_ONLY
 200 #ifdef __i386__
 201 OP_LD_TABLE(std);
 202 #endif /* __i386__ */
 203 OP_LD_TABLE(stf);
 204 OP_LD_TABLE(stdf);
 205 OP_LD_TABLE(ldf);
 206 OP_LD_TABLE(lddf);
 207 #endif
 208
 209 #ifdef TARGET_ABI32
 210 #define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL);
 211 #else
 212 #define ABI32_MASK(addr)
 213 #endif
 214
 215 static inline void gen_movl_simm_T1(int32_t val)
 216 {
 217     tcg_gen_movi_tl(cpu_T[1], val);
 218 }
 219
 220 static inline void gen_movl_reg_TN(int reg, TCGv tn)
 221 {
 222     if (reg == 0)
 223         tcg_gen_movi_tl(tn, 0);
 224     else if (reg < 8)
 225         tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUState, gregs[reg]));
 226     else {
 227         tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 228     }
 229 }
 230
 231 static inline void gen_movl_reg_T0(int reg)
 232 {
 233     gen_movl_reg_TN(reg, cpu_T[0]);
 234 }
 235
 236 static inline void gen_movl_reg_T1(int reg)
 237 {
 238     gen_movl_reg_TN(reg, cpu_T[1]);
 239 }
 240
 241 #ifdef __i386__
 242 static inline void gen_movl_reg_T2(int reg)
 243 {
 244     gen_movl_reg_TN(reg, cpu_T[2]);
 245 }
 246
 247 #endif /* __i386__ */
 248 static inline void gen_movl_TN_reg(int reg, TCGv tn)
 249 {
 250     if (reg == 0)
 251         return;
 252     else if (reg < 8)
 253         tcg_gen_st_tl(tn, cpu_env, offsetof(CPUState, gregs[reg]));
 254     else {
 255         tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 256     }
 257 }
 258
 259 static inline void gen_movl_T0_reg(int reg)
 260 {
 261     gen_movl_TN_reg(reg, cpu_T[0]);
 262 }
 263
 264 static inline void gen_movl_T1_reg(int reg)
 265 {
 266     gen_movl_TN_reg(reg, cpu_T[1]);
 267 }
 268
 269 static inline void gen_op_movl_T0_env(size_t offset)
 270 {
 271     tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
 272 }
 273
 274 static inline void gen_op_movl_env_T0(size_t offset)
 275 {
 276     tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
 277 }
 278
 279 static inline void gen_op_movtl_T0_env(size_t offset)
 280 {
 281     tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);
 282 }
 283
 284 static inline void gen_op_movtl_env_T0(size_t offset)
 285 {
 286     tcg_gen_st_tl(cpu_T[0], cpu_env, offset);
 287 }
 288
 289 static inline void gen_op_add_T1_T0(void)
 290 {
 291     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 292 }
 293
 294 static inline void gen_op_or_T1_T0(void)
 295 {
 296     tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 297 }
 298
 299 static inline void gen_op_xor_T1_T0(void)
 300 {
 301     tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 302 }
 303
 304 static inline void gen_jmp_im(target_ulong pc)
 305 {
 306     tcg_gen_movi_tl(cpu_tmp0, pc);
 307     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, pc));
 308 }
 309
 310 static inline void gen_movl_npc_im(target_ulong npc)
 311 {
 312     tcg_gen_movi_tl(cpu_tmp0, npc);
 313     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, npc));
 314 }
 315
 316 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 317                                target_ulong pc, target_ulong npc)
 318 {
 319     TranslationBlock *tb;
 320
 321     tb = s->tb;
 322     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 323         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 324         /* jump to same page: we can use a direct jump */
 325         tcg_gen_goto_tb(tb_num);
 326         gen_jmp_im(pc);
 327         gen_movl_npc_im(npc);
 328         tcg_gen_exit_tb((long)tb + tb_num);
 329     } else {
 330         /* jump to another page: currently not optimized */
 331         gen_jmp_im(pc);
 332         gen_movl_npc_im(npc);
 333         tcg_gen_exit_tb(0);
 334     }
 335 }
 336
 337 // XXX suboptimal
 338 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
 339 {
 340     tcg_gen_shri_i32(reg, src, 23);
 341     tcg_gen_andi_tl(reg, reg, 0x1);
 342 }
 343
 344 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
 345 {
 346     tcg_gen_shri_i32(reg, src, 22);
 347     tcg_gen_andi_tl(reg, reg, 0x1);
 348 }
 349
 350 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
 351 {
 352     tcg_gen_shri_i32(reg, src, 21);
 353     tcg_gen_andi_tl(reg, reg, 0x1);
 354 }
 355
 356 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
 357 {
 358     tcg_gen_shri_i32(reg, src, 20);
 359     tcg_gen_andi_tl(reg, reg, 0x1);
 360 }
 361
 362 static inline void gen_op_exception(int exception)
 363 {
 364     TCGv r_except;
 365
 366     r_except = tcg_temp_new(TCG_TYPE_I32);
 367     tcg_gen_movi_i32(r_except, exception);
 368     tcg_gen_helper_0_1(raise_exception, r_except);
 369 }
 370
 371 static inline void gen_cc_clear(void)
 372 {
 373     tcg_gen_movi_i32(cpu_psr, 0);
 374 #ifdef TARGET_SPARC64
 375     tcg_gen_movi_i32(cpu_xcc, 0);
 376 #endif
 377 }
 378
 379 /* old op:
 380     if (!T0)
 381         env->psr |= PSR_ZERO;
 382     if ((int32_t) T0 < 0)
 383         env->psr |= PSR_NEG;
 384 */
 385 static inline void gen_cc_NZ(TCGv dst)
 386 {
 387     int l1, l2;
 388     TCGv r_zero;
 389
 390     l1 = gen_new_label();
 391     l2 = gen_new_label();
 392     r_zero = tcg_const_tl(0);
 393     tcg_gen_brcond_i32(TCG_COND_NE, dst, r_zero, l1);
 394     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
 395     gen_set_label(l1);
 396     tcg_gen_brcond_i32(TCG_COND_GE, dst, r_zero, l2);
 397     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
 398     gen_set_label(l2);
 399 #ifdef TARGET_SPARC64
 400     {
 401         int l3, l4;
 402
 403         l3 = gen_new_label();
 404         l4 = gen_new_label();
 405         tcg_gen_brcond_tl(TCG_COND_NE, dst, r_zero, l3);
 406         tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
 407         gen_set_label(l3);
 408         tcg_gen_brcond_tl(TCG_COND_GE, dst, r_zero, l4);
 409         tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
 410         gen_set_label(l4);
 411     }
 412 #endif
 413 }
 414
 415 /* old op:
 416     if (T0 < src1)
 417         env->psr |= PSR_CARRY;
 418 */
 419 static inline void gen_cc_C_add(TCGv dst, TCGv src1)
 420 {
 421     int l1;
 422
 423     l1 = gen_new_label();
 424     tcg_gen_brcond_i32(TCG_COND_GEU, dst, src1, l1);
 425     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 426     gen_set_label(l1);
 427 #ifdef TARGET_SPARC64
 428     {
 429         int l2;
 430
 431         l2 = gen_new_label();
 432         tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2);
 433         tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 434         gen_set_label(l2);
 435     }
 436 #endif
 437 }
 438
 439 /* old op:
 440     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
 441         env->psr |= PSR_OVF;
 442 */
 443 static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2)
 444 {
 445     TCGv r_temp, r_temp2, r_temp3, r_zero;
 446     int l1;
 447
 448     l1 = gen_new_label();
 449
 450     r_temp = tcg_temp_new(TCG_TYPE_TL);
 451     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 452     r_temp3 = tcg_temp_new(TCG_TYPE_TL);
 453     r_zero = tcg_const_tl(0);
 454     tcg_gen_xor_tl(r_temp, src1, src2);
 455     tcg_gen_xori_tl(r_temp, r_temp, -1);
 456     tcg_gen_xor_tl(r_temp2, src1, dst);
 457     tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 458     tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
 459     tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
 460     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 461     gen_set_label(l1);
 462 #ifdef TARGET_SPARC64
 463     {
 464         int l2;
 465
 466         l2 = gen_new_label();
 467         tcg_gen_xor_tl(r_temp, src1, src2);
 468         tcg_gen_xori_tl(r_temp, r_temp, -1);
 469         tcg_gen_xor_tl(r_temp2, src1, dst);
 470         tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 471         tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
 472         tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
 473         tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
 474         gen_set_label(l2);
 475     }
 476 #endif
 477 }
 478
 479 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
 480 {
 481     TCGv r_temp, r_temp2, r_temp3, r_zero;
 482     int l1;
 483
 484     l1 = gen_new_label();
 485
 486     r_temp = tcg_temp_new(TCG_TYPE_TL);
 487     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 488     r_temp3 = tcg_temp_new(TCG_TYPE_TL);
 489     r_zero = tcg_const_tl(0);
 490     tcg_gen_xor_tl(r_temp, src1, src2);
 491     tcg_gen_xori_tl(r_temp, r_temp, -1);
 492     tcg_gen_xor_tl(r_temp2, src1, dst);
 493     tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 494     tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
 495     tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
 496     gen_op_exception(TT_TOVF);
 497     gen_set_label(l1);
 498 #ifdef TARGET_SPARC64
 499     {
 500         int l2;
 501
 502         l2 = gen_new_label();
 503         tcg_gen_xor_tl(r_temp, src1, src2);
 504         tcg_gen_xori_tl(r_temp, r_temp, -1);
 505         tcg_gen_xor_tl(r_temp2, src1, dst);
 506         tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 507         tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
 508         tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
 509         gen_op_exception(TT_TOVF);
 510         gen_set_label(l2);
 511     }
 512 #endif
 513 }
 514
 515 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
 516 {
 517     int l1;
 518     TCGv r_zero, r_temp;
 519
 520     l1 = gen_new_label();
 521     r_zero = tcg_const_tl(0);
 522     r_temp = tcg_temp_new(TCG_TYPE_TL);
 523     tcg_gen_or_tl(r_temp, src1, src2);
 524     tcg_gen_andi_tl(r_temp, r_temp, 0x3);
 525     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1);
 526     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 527     gen_set_label(l1);
 528 }
 529
 530 static inline void gen_tag_tv(TCGv src1, TCGv src2)
 531 {
 532     int l1;
 533     TCGv r_zero, r_temp;
 534
 535     l1 = gen_new_label();
 536     r_zero = tcg_const_tl(0);
 537     r_temp = tcg_temp_new(TCG_TYPE_TL);
 538     tcg_gen_or_tl(r_temp, src1, src2);
 539     tcg_gen_andi_tl(r_temp, r_temp, 0x3);
 540     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1);
 541     gen_op_exception(TT_TOVF);
 542     gen_set_label(l1);
 543 }
 544
 545 static inline void gen_op_add_T1_T0_cc(void)
 546 {
 547     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 548     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 549     gen_cc_clear();
 550     gen_cc_NZ(cpu_T[0]);
 551     gen_cc_C_add(cpu_T[0], cpu_cc_src);
 552     gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
 553 }
 554
 555 static inline void gen_op_addx_T1_T0_cc(void)
 556 {
 557     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 558     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 559     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
 560     gen_cc_clear();
 561     gen_cc_C_add(cpu_T[0], cpu_cc_src);
 562     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 563     gen_cc_C_add(cpu_T[0], cpu_cc_src);
 564     gen_cc_NZ(cpu_T[0]);
 565     gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
 566 }
 567
 568 static inline void gen_op_tadd_T1_T0_cc(void)
 569 {
 570     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 571     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 572     gen_cc_clear();
 573     gen_cc_NZ(cpu_T[0]);
 574     gen_cc_C_add(cpu_T[0], cpu_cc_src);
 575     gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
 576     gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
 577 }
 578
 579 static inline void gen_op_tadd_T1_T0_ccTV(void)
 580 {
 581     gen_tag_tv(cpu_T[0], cpu_T[1]);
 582     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 583     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 584     gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
 585     gen_cc_clear();
 586     gen_cc_NZ(cpu_T[0]);
 587     gen_cc_C_add(cpu_T[0], cpu_cc_src);
 588 }
 589
 590 /* old op:
 591     if (src1 < T1)
 592         env->psr |= PSR_CARRY;
 593 */
 594 static inline void gen_cc_C_sub(TCGv src1, TCGv src2)
 595 {
 596     int l1;
 597
 598     l1 = gen_new_label();
 599     tcg_gen_brcond_i32(TCG_COND_GEU, src1, src2, l1);
 600     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 601     gen_set_label(l1);
 602 #ifdef TARGET_SPARC64
 603     {
 604         int l2;
 605
 606         l2 = gen_new_label();
 607         tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2);
 608         tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 609         gen_set_label(l2);
 610     }
 611 #endif
 612 }
 613
 614 /* old op:
 615     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
 616         env->psr |= PSR_OVF;
 617 */
 618 static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2)
 619 {
 620     TCGv r_temp, r_temp2, r_temp3, r_zero;
 621     int l1;
 622
 623     l1 = gen_new_label();
 624
 625     r_temp = tcg_temp_new(TCG_TYPE_TL);
 626     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 627     r_temp3 = tcg_temp_new(TCG_TYPE_TL);
 628     r_zero = tcg_const_tl(0);
 629     tcg_gen_xor_tl(r_temp, src1, src2);
 630     tcg_gen_xor_tl(r_temp2, src1, dst);
 631     tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 632     tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
 633     tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
 634     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 635     gen_set_label(l1);
 636 #ifdef TARGET_SPARC64
 637     {
 638         int l2;
 639
 640         l2 = gen_new_label();
 641         tcg_gen_xor_tl(r_temp, src1, src2);
 642         tcg_gen_xor_tl(r_temp2, src1, dst);
 643         tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 644         tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
 645         tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
 646         tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
 647         gen_set_label(l2);
 648     }
 649 #endif
 650 }
 651
 652 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
 653 {
 654     TCGv r_temp, r_temp2, r_temp3, r_zero;
 655     int l1;
 656
 657     l1 = gen_new_label();
 658
 659     r_temp = tcg_temp_new(TCG_TYPE_TL);
 660     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 661     r_temp3 = tcg_temp_new(TCG_TYPE_TL);
 662     r_zero = tcg_const_tl(0);
 663     tcg_gen_xor_tl(r_temp, src1, src2);
 664     tcg_gen_xor_tl(r_temp2, src1, dst);
 665     tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 666     tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
 667     tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
 668     gen_op_exception(TT_TOVF);
 669     gen_set_label(l1);
 670 #ifdef TARGET_SPARC64
 671     {
 672         int l2;
 673
 674         l2 = gen_new_label();
 675         tcg_gen_xor_tl(r_temp, src1, src2);
 676         tcg_gen_xor_tl(r_temp2, src1, dst);
 677         tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 678         tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
 679         tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
 680         gen_op_exception(TT_TOVF);
 681         gen_set_label(l2);
 682     }
 683 #endif
 684 }
 685
 686 static inline void gen_op_sub_T1_T0_cc(void)
 687 {
 688     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 689     tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 690     gen_cc_clear();
 691     gen_cc_NZ(cpu_T[0]);
 692     gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
 693     gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
 694 }
 695
 696 static inline void gen_op_subx_T1_T0_cc(void)
 697 {
 698     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 699     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 700     tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
 701     gen_cc_clear();
 702     gen_cc_C_sub(cpu_T[0], cpu_cc_src);
 703     tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 704     gen_cc_C_sub(cpu_T[0], cpu_cc_src);
 705     gen_cc_NZ(cpu_T[0]);
 706     gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
 707 }
 708
 709 static inline void gen_op_tsub_T1_T0_cc(void)
 710 {
 711     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 712     tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 713     gen_cc_clear();
 714     gen_cc_NZ(cpu_T[0]);
 715     gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
 716     gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
 717     gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
 718 }
 719
 720 static inline void gen_op_tsub_T1_T0_ccTV(void)
 721 {
 722     gen_tag_tv(cpu_T[0], cpu_T[1]);
 723     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 724     tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 725     gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
 726     gen_cc_clear();
 727     gen_cc_NZ(cpu_T[0]);
 728     gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
 729 }
 730
 731 static inline void gen_op_div_cc(void)
 732 {
 733     int l1;
 734     TCGv r_zero;
 735
 736     gen_cc_clear();
 737     gen_cc_NZ(cpu_T[0]);
 738     l1 = gen_new_label();
 739     r_zero = tcg_const_tl(0);
 740     tcg_gen_brcond_i32(TCG_COND_EQ, cpu_T[1], r_zero, l1);
 741     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 742     gen_set_label(l1);
 743 }
 744
 745 static inline void gen_op_logic_T0_cc(void)
 746 {
 747     gen_cc_clear();
 748     gen_cc_NZ(cpu_T[0]);
 749 }
 750
 751 // 1
 752 static inline void gen_op_eval_ba(TCGv dst)
 753 {
 754     tcg_gen_movi_tl(dst, 1);
 755 }
 756
 757 // Z
 758 static inline void gen_op_eval_be(TCGv dst, TCGv src)
 759 {
 760     gen_mov_reg_Z(dst, src);
 761 }
 762
 763 // Z | (N ^ V)
 764 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
 765 {
 766     TCGv r_flag;
 767
 768     r_flag = tcg_temp_new(TCG_TYPE_TL);
 769     gen_mov_reg_N(r_flag, src);
 770     gen_mov_reg_V(dst, src);
 771     tcg_gen_xor_tl(dst, dst, r_flag);
 772     gen_mov_reg_Z(r_flag, src);
 773     tcg_gen_or_tl(dst, dst, r_flag);
 774 }
 775
 776 // N ^ V
 777 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
 778 {
 779     TCGv r_V;
 780
 781     r_V = tcg_temp_new(TCG_TYPE_TL);
 782     gen_mov_reg_V(r_V, src);
 783     gen_mov_reg_N(dst, src);
 784     tcg_gen_xor_tl(dst, dst, r_V);
 785 }
 786
 787 // C | Z
 788 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
 789 {
 790     TCGv r_Z;
 791
 792     r_Z = tcg_temp_new(TCG_TYPE_TL);
 793     gen_mov_reg_Z(r_Z, src);
 794     gen_mov_reg_C(dst, src);
 795     tcg_gen_or_tl(dst, dst, r_Z);
 796 }
 797
 798 // C
 799 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
 800 {
 801     gen_mov_reg_C(dst, src);
 802 }
 803
 804 // V
 805 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
 806 {
 807     gen_mov_reg_V(dst, src);
 808 }
 809
 810 // 0
 811 static inline void gen_op_eval_bn(TCGv dst)
 812 {
 813     tcg_gen_movi_tl(dst, 0);
 814 }
 815
 816 // N
 817 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
 818 {
 819     gen_mov_reg_N(dst, src);
 820 }
 821
 822 // !Z
 823 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
 824 {
 825     gen_mov_reg_Z(dst, src);
 826     tcg_gen_xori_tl(dst, dst, 0x1);
 827 }
 828
 829 // !(Z | (N ^ V))
 830 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
 831 {
 832     TCGv r_flag;
 833
 834     r_flag = tcg_temp_new(TCG_TYPE_TL);
 835     gen_mov_reg_N(r_flag, src);
 836     gen_mov_reg_V(dst, src);
 837     tcg_gen_xor_tl(dst, dst, r_flag);
 838     gen_mov_reg_Z(r_flag, src);
 839     tcg_gen_or_tl(dst, dst, r_flag);
 840     tcg_gen_xori_tl(dst, dst, 0x1);
 841 }
 842
 843 // !(N ^ V)
 844 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
 845 {
 846     TCGv r_V;
 847
 848     r_V = tcg_temp_new(TCG_TYPE_TL);
 849     gen_mov_reg_V(r_V, src);
 850     gen_mov_reg_N(dst, src);
 851     tcg_gen_xor_tl(dst, dst, r_V);
 852     tcg_gen_xori_tl(dst, dst, 0x1);
 853 }
 854
 855 // !(C | Z)
 856 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
 857 {
 858     TCGv r_Z;
 859
 860     r_Z = tcg_temp_new(TCG_TYPE_TL);
 861     gen_mov_reg_Z(r_Z, src);
 862     gen_mov_reg_C(dst, src);
 863     tcg_gen_or_tl(dst, dst, r_Z);
 864     tcg_gen_xori_tl(dst, dst, 0x1);
 865 }
 866
 867 // !C
 868 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
 869 {
 870     gen_mov_reg_C(dst, src);
 871     tcg_gen_xori_tl(dst, dst, 0x1);
 872 }
 873
 874 // !N
 875 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
 876 {
 877     gen_mov_reg_N(dst, src);
 878     tcg_gen_xori_tl(dst, dst, 0x1);
 879 }
 880
 881 // !V
 882 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
 883 {
 884     gen_mov_reg_V(dst, src);
 885     tcg_gen_xori_tl(dst, dst, 0x1);
 886 }
 887
 888 /*
 889   FPSR bit field FCC1 | FCC0:
 890    0 =
 891    1 <
 892    2 >
 893    3 unordered
 894 */
 895 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
 896                                     unsigned int fcc_offset)
 897 {
 898     tcg_gen_shri_i32(reg, src, 10 + fcc_offset);
 899     tcg_gen_andi_tl(reg, reg, 0x1);
 900 }
 901
 902 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
 903                                     unsigned int fcc_offset)
 904 {
 905     tcg_gen_shri_i32(reg, src, 11 + fcc_offset);
 906     tcg_gen_andi_tl(reg, reg, 0x1);
 907 }
 908
 909 // !0: FCC0 | FCC1
 910 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
 911                                     unsigned int fcc_offset)
 912 {
 913     TCGv r_fcc1;
 914
 915     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
 916     gen_mov_reg_FCC0(dst, src, fcc_offset);
 917     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
 918     tcg_gen_or_tl(dst, dst, r_fcc1);
 919 }
 920
 921 // 1 or 2: FCC0 ^ FCC1
 922 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
 923                                     unsigned int fcc_offset)
 924 {
 925     TCGv r_fcc1;
 926
 927     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
 928     gen_mov_reg_FCC0(dst, src, fcc_offset);
 929     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
 930     tcg_gen_xor_tl(dst, dst, r_fcc1);
 931 }
 932
 933 // 1 or 3: FCC0
 934 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
 935                                     unsigned int fcc_offset)
 936 {
 937     gen_mov_reg_FCC0(dst, src, fcc_offset);
 938 }
 939
 940 // 1: FCC0 & !FCC1
 941 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
 942                                     unsigned int fcc_offset)
 943 {
 944     TCGv r_fcc1;
 945
 946     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
 947     gen_mov_reg_FCC0(dst, src, fcc_offset);
 948     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
 949     tcg_gen_xori_tl(r_fcc1, r_fcc1, 0x1);
 950     tcg_gen_and_tl(dst, dst, r_fcc1);
 951 }
 952
 953 // 2 or 3: FCC1
 954 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
 955                                     unsigned int fcc_offset)
 956 {
 957     gen_mov_reg_FCC1(dst, src, fcc_offset);
 958 }
 959
 960 // 2: !FCC0 & FCC1
 961 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
 962                                     unsigned int fcc_offset)
 963 {
 964     TCGv r_fcc1;
 965
 966     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
 967     gen_mov_reg_FCC0(dst, src, fcc_offset);
 968     tcg_gen_xori_tl(dst, dst, 0x1);
 969     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
 970     tcg_gen_and_tl(dst, dst, r_fcc1);
 971 }
 972
 973 // 3: FCC0 & FCC1
 974 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
 975                                     unsigned int fcc_offset)
 976 {
 977     TCGv r_fcc1;
 978
 979     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
 980     gen_mov_reg_FCC0(dst, src, fcc_offset);
 981     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
 982     tcg_gen_and_tl(dst, dst, r_fcc1);
 983 }
 984
 985 // 0: !(FCC0 | FCC1)
 986 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
 987                                     unsigned int fcc_offset)
 988 {
 989     TCGv r_fcc1;
 990
 991     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
 992     gen_mov_reg_FCC0(dst, src, fcc_offset);
 993     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
 994     tcg_gen_or_tl(dst, dst, r_fcc1);
 995     tcg_gen_xori_tl(dst, dst, 0x1);
 996 }
 997
 998 // 0 or 3: !(FCC0 ^ FCC1)
 999 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1000                                     unsigned int fcc_offset)
1001 {
1002     TCGv r_fcc1;
1003
1004     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1005     gen_mov_reg_FCC0(dst, src, fcc_offset);
1006     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1007     tcg_gen_xor_tl(dst, dst, r_fcc1);
1008     tcg_gen_xori_tl(dst, dst, 0x1);
1009 }
1010
1011 // 0 or 2: !FCC0
1012 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1013                                     unsigned int fcc_offset)
1014 {
1015     gen_mov_reg_FCC0(dst, src, fcc_offset);
1016     tcg_gen_xori_tl(dst, dst, 0x1);
1017 }
1018
1019 // !1: !(FCC0 & !FCC1)
1020 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1021                                     unsigned int fcc_offset)
1022 {
1023     TCGv r_fcc1;
1024
1025     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1026     gen_mov_reg_FCC0(dst, src, fcc_offset);
1027     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1028     tcg_gen_xori_tl(r_fcc1, r_fcc1, 0x1);
1029     tcg_gen_and_tl(dst, dst, r_fcc1);
1030     tcg_gen_xori_tl(dst, dst, 0x1);
1031 }
1032
1033 // 0 or 1: !FCC1
1034 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1035                                     unsigned int fcc_offset)
1036 {
1037     gen_mov_reg_FCC1(dst, src, fcc_offset);
1038     tcg_gen_xori_tl(dst, dst, 0x1);
1039 }
1040
1041 // !2: !(!FCC0 & FCC1)
1042 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1043                                     unsigned int fcc_offset)
1044 {
1045     TCGv r_fcc1;
1046
1047     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1048     gen_mov_reg_FCC0(dst, src, fcc_offset);
1049     tcg_gen_xori_tl(dst, dst, 0x1);
1050     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1051     tcg_gen_and_tl(dst, dst, r_fcc1);
1052     tcg_gen_xori_tl(dst, dst, 0x1);
1053 }
1054
1055 // !3: !(FCC0 & FCC1)
1056 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1057                                     unsigned int fcc_offset)
1058 {
1059     TCGv r_fcc1;
1060
1061     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1062     gen_mov_reg_FCC0(dst, src, fcc_offset);
1063     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1064     tcg_gen_and_tl(dst, dst, r_fcc1);
1065     tcg_gen_xori_tl(dst, dst, 0x1);
1066 }
1067
1068 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1069                                target_ulong pc2, TCGv r_cond)
1070 {
1071     TCGv r_zero;
1072     int l1;
1073
1074     l1 = gen_new_label();
1075     r_zero = tcg_const_tl(0);
1076
1077     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1);
1078
1079     gen_goto_tb(dc, 0, pc1, pc1 + 4);
1080
1081     gen_set_label(l1);
1082     gen_goto_tb(dc, 1, pc2, pc2 + 4);
1083 }
1084
1085 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1086                                 target_ulong pc2, TCGv r_cond)
1087 {
1088     TCGv r_zero;
1089     int l1;
1090
1091     l1 = gen_new_label();
1092     r_zero = tcg_const_tl(0);
1093
1094     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1);
1095
1096     gen_goto_tb(dc, 0, pc2, pc1);
1097
1098     gen_set_label(l1);
1099     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1100 }
1101
1102 static inline void gen_branch(DisasContext *dc, target_ulong pc,
1103                               target_ulong npc)
1104 {
1105     gen_goto_tb(dc, 0, pc, npc);
1106 }
1107
1108 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1109                                       TCGv r_cond)
1110 {
1111     TCGv r_zero;
1112     int l1, l2;
1113
1114     l1 = gen_new_label();
1115     l2 = gen_new_label();
1116     r_zero = tcg_const_tl(0);
1117
1118     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1);
1119
1120     gen_movl_npc_im(npc1);
1121     gen_op_jmp_label(l2);
1122
1123     gen_set_label(l1);
1124     gen_movl_npc_im(npc2);
1125     gen_set_label(l2);
1126 }
1127
1128 /* call this function before using T2 as it may have been set for a jump */
1129 static inline void flush_T2(DisasContext * dc)
1130 {
1131     if (dc->npc == JUMP_PC) {
1132         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
1133         dc->npc = DYNAMIC_PC;
1134     }
1135 }
1136
1137 static inline void save_npc(DisasContext * dc)
1138 {
1139     if (dc->npc == JUMP_PC) {
1140         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
1141         dc->npc = DYNAMIC_PC;
1142     } else if (dc->npc != DYNAMIC_PC) {
1143         gen_movl_npc_im(dc->npc);
1144     }
1145 }
1146
1147 static inline void save_state(DisasContext * dc)
1148 {
1149     gen_jmp_im(dc->pc);
1150     save_npc(dc);
1151 }
1152
1153 static inline void gen_mov_pc_npc(DisasContext * dc)
1154 {
1155     if (dc->npc == JUMP_PC) {
1156         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
1157         tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1158         tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
1159         dc->pc = DYNAMIC_PC;
1160     } else if (dc->npc == DYNAMIC_PC) {
1161         tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1162         tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
1163         dc->pc = DYNAMIC_PC;
1164     } else {
1165         dc->pc = dc->npc;
1166     }
1167 }
1168
1169 static inline void gen_op_next_insn(void)
1170 {
1171     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1172     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
1173     tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, 4);
1174     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1175 }
1176
1177 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1178 {
1179     TCGv r_src;
1180
1181 #ifdef TARGET_SPARC64
1182     if (cc)
1183         r_src = cpu_xcc;
1184     else
1185         r_src = cpu_psr;
1186 #else
1187     r_src = cpu_psr;
1188 #endif
1189     switch (cond) {
1190     case 0x0:
1191         gen_op_eval_bn(r_dst);
1192         break;
1193     case 0x1:
1194         gen_op_eval_be(r_dst, r_src);
1195         break;
1196     case 0x2:
1197         gen_op_eval_ble(r_dst, r_src);
1198         break;
1199     case 0x3:
1200         gen_op_eval_bl(r_dst, r_src);
1201         break;
1202     case 0x4:
1203         gen_op_eval_bleu(r_dst, r_src);
1204         break;
1205     case 0x5:
1206         gen_op_eval_bcs(r_dst, r_src);
1207         break;
1208     case 0x6:
1209         gen_op_eval_bneg(r_dst, r_src);
1210         break;
1211     case 0x7:
1212         gen_op_eval_bvs(r_dst, r_src);
1213         break;
1214     case 0x8:
1215         gen_op_eval_ba(r_dst);
1216         break;
1217     case 0x9:
1218         gen_op_eval_bne(r_dst, r_src);
1219         break;
1220     case 0xa:
1221         gen_op_eval_bg(r_dst, r_src);
1222         break;
1223     case 0xb:
1224         gen_op_eval_bge(r_dst, r_src);
1225         break;
1226     case 0xc:
1227         gen_op_eval_bgu(r_dst, r_src);
1228         break;
1229     case 0xd:
1230         gen_op_eval_bcc(r_dst, r_src);
1231         break;
1232     case 0xe:
1233         gen_op_eval_bpos(r_dst, r_src);
1234         break;
1235     case 0xf:
1236         gen_op_eval_bvc(r_dst, r_src);
1237         break;
1238     }
1239 }
1240
1241 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1242 {
1243     TCGv r_src;
1244     unsigned int offset;
1245
1246     r_src = tcg_temp_new(TCG_TYPE_TL);
1247     tcg_gen_ld_tl(r_src, cpu_env, offsetof(CPUSPARCState, fsr));
1248
1249     switch (cc) {
1250     default:
1251     case 0x0:
1252         offset = 0;
1253         break;
1254     case 0x1:
1255         offset = 32 - 10;
1256         break;
1257     case 0x2:
1258         offset = 34 - 10;
1259         break;
1260     case 0x3:
1261         offset = 36 - 10;
1262         break;
1263     }
1264
1265     switch (cond) {
1266     case 0x0:
1267         gen_op_eval_bn(r_dst);
1268         break;
1269     case 0x1:
1270         gen_op_eval_fbne(r_dst, r_src, offset);
1271         break;
1272     case 0x2:
1273         gen_op_eval_fblg(r_dst, r_src, offset);
1274         break;
1275     case 0x3:
1276         gen_op_eval_fbul(r_dst, r_src, offset);
1277         break;
1278     case 0x4:
1279         gen_op_eval_fbl(r_dst, r_src, offset);
1280         break;
1281     case 0x5:
1282         gen_op_eval_fbug(r_dst, r_src, offset);
1283         break;
1284     case 0x6:
1285         gen_op_eval_fbg(r_dst, r_src, offset);
1286         break;
1287     case 0x7:
1288         gen_op_eval_fbu(r_dst, r_src, offset);
1289         break;
1290     case 0x8:
1291         gen_op_eval_ba(r_dst);
1292         break;
1293     case 0x9:
1294         gen_op_eval_fbe(r_dst, r_src, offset);
1295         break;
1296     case 0xa:
1297         gen_op_eval_fbue(r_dst, r_src, offset);
1298         break;
1299     case 0xb:
1300         gen_op_eval_fbge(r_dst, r_src, offset);
1301         break;
1302     case 0xc:
1303         gen_op_eval_fbuge(r_dst, r_src, offset);
1304         break;
1305     case 0xd:
1306         gen_op_eval_fble(r_dst, r_src, offset);
1307         break;
1308     case 0xe:
1309         gen_op_eval_fbule(r_dst, r_src, offset);
1310         break;
1311     case 0xf:
1312         gen_op_eval_fbo(r_dst, r_src, offset);
1313         break;
1314     }
1315 }
1316
1317 #ifdef TARGET_SPARC64
1318 // Inverted logic
1319 static const int gen_tcg_cond_reg[8] = {
1320     -1,
1321     TCG_COND_NE,
1322     TCG_COND_GT,
1323     TCG_COND_GE,
1324     -1,
1325     TCG_COND_EQ,
1326     TCG_COND_LE,
1327     TCG_COND_LT,
1328 };
1329
1330 static inline void gen_cond_reg(TCGv r_dst, int cond)
1331 {
1332     TCGv r_zero;
1333     int l1;
1334
1335     l1 = gen_new_label();
1336     r_zero = tcg_const_tl(0);
1337     tcg_gen_mov_tl(r_dst, r_zero);
1338     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
1339     tcg_gen_movi_tl(r_dst, 1);
1340     gen_set_label(l1);
1341 }
1342 #endif
1343
1344 /* XXX: potentially incorrect if dynamic npc */
1345 static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1346 {
1347     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1348     target_ulong target = dc->pc + offset;
1349
1350     if (cond == 0x0) {
1351         /* unconditional not taken */
1352         if (a) {
1353             dc->pc = dc->npc + 4;
1354             dc->npc = dc->pc + 4;
1355         } else {
1356             dc->pc = dc->npc;
1357             dc->npc = dc->pc + 4;
1358         }
1359     } else if (cond == 0x8) {
1360         /* unconditional taken */
1361         if (a) {
1362             dc->pc = target;
1363             dc->npc = dc->pc + 4;
1364         } else {
1365             dc->pc = dc->npc;
1366             dc->npc = target;
1367         }
1368     } else {
1369         flush_T2(dc);
1370         gen_cond(cpu_T[2], cc, cond);
1371         if (a) {
1372             gen_branch_a(dc, target, dc->npc, cpu_T[2]);
1373             dc->is_br = 1;
1374         } else {
1375             dc->pc = dc->npc;
1376             dc->jump_pc[0] = target;
1377             dc->jump_pc[1] = dc->npc + 4;
1378             dc->npc = JUMP_PC;
1379         }
1380     }
1381 }
1382
1383 /* XXX: potentially incorrect if dynamic npc */
1384 static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1385 {
1386     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1387     target_ulong target = dc->pc + offset;
1388
1389     if (cond == 0x0) {
1390         /* unconditional not taken */
1391         if (a) {
1392             dc->pc = dc->npc + 4;
1393             dc->npc = dc->pc + 4;
1394         } else {
1395             dc->pc = dc->npc;
1396             dc->npc = dc->pc + 4;
1397         }
1398     } else if (cond == 0x8) {
1399         /* unconditional taken */
1400         if (a) {
1401             dc->pc = target;
1402             dc->npc = dc->pc + 4;
1403         } else {
1404             dc->pc = dc->npc;
1405             dc->npc = target;
1406         }
1407     } else {
1408         flush_T2(dc);
1409         gen_fcond(cpu_T[2], cc, cond);
1410         if (a) {
1411             gen_branch_a(dc, target, dc->npc, cpu_T[2]);
1412             dc->is_br = 1;
1413         } else {
1414             dc->pc = dc->npc;
1415             dc->jump_pc[0] = target;
1416             dc->jump_pc[1] = dc->npc + 4;
1417             dc->npc = JUMP_PC;
1418         }
1419     }
1420 }
1421
1422 #ifdef TARGET_SPARC64
1423 /* XXX: potentially incorrect if dynamic npc */
1424 static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
1425 {
1426     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1427     target_ulong target = dc->pc + offset;
1428
1429     flush_T2(dc);
1430     gen_cond_reg(cpu_T[2], cond);
1431     if (a) {
1432         gen_branch_a(dc, target, dc->npc, cpu_T[2]);
1433         dc->is_br = 1;
1434     } else {
1435         dc->pc = dc->npc;
1436         dc->jump_pc[0] = target;
1437         dc->jump_pc[1] = dc->npc + 4;
1438         dc->npc = JUMP_PC;
1439     }
1440 }
1441
1442 static GenOpFunc * const gen_fcmps[4] = {
1443     helper_fcmps,
1444     helper_fcmps_fcc1,
1445     helper_fcmps_fcc2,
1446     helper_fcmps_fcc3,
1447 };
1448
1449 static GenOpFunc * const gen_fcmpd[4] = {
1450     helper_fcmpd,
1451     helper_fcmpd_fcc1,
1452     helper_fcmpd_fcc2,
1453     helper_fcmpd_fcc3,
1454 };
1455
1456 #if defined(CONFIG_USER_ONLY)
1457 static GenOpFunc * const gen_fcmpq[4] = {
1458     helper_fcmpq,
1459     helper_fcmpq_fcc1,
1460     helper_fcmpq_fcc2,
1461     helper_fcmpq_fcc3,
1462 };
1463 #endif
1464
1465 static GenOpFunc * const gen_fcmpes[4] = {
1466     helper_fcmpes,
1467     helper_fcmpes_fcc1,
1468     helper_fcmpes_fcc2,
1469     helper_fcmpes_fcc3,
1470 };
1471
1472 static GenOpFunc * const gen_fcmped[4] = {
1473     helper_fcmped,
1474     helper_fcmped_fcc1,
1475     helper_fcmped_fcc2,
1476     helper_fcmped_fcc3,
1477 };
1478
1479 #if defined(CONFIG_USER_ONLY)
1480 static GenOpFunc * const gen_fcmpeq[4] = {
1481     helper_fcmpeq,
1482     helper_fcmpeq_fcc1,
1483     helper_fcmpeq_fcc2,
1484     helper_fcmpeq_fcc3,
1485 };
1486 #endif
1487
1488 static inline void gen_op_fcmps(int fccno)
1489 {
1490     tcg_gen_helper_0_0(gen_fcmps[fccno]);
1491 }
1492
1493 static inline void gen_op_fcmpd(int fccno)
1494 {
1495     tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1496 }
1497
1498 #if defined(CONFIG_USER_ONLY)
1499 static inline void gen_op_fcmpq(int fccno)
1500 {
1501     tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1502 }
1503 #endif
1504
1505 static inline void gen_op_fcmpes(int fccno)
1506 {
1507     tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1508 }
1509
1510 static inline void gen_op_fcmped(int fccno)
1511 {
1512     tcg_gen_helper_0_0(gen_fcmped[fccno]);
1513 }
1514
1515 #if defined(CONFIG_USER_ONLY)
1516 static inline void gen_op_fcmpeq(int fccno)
1517 {
1518     tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1519 }
1520 #endif
1521
1522 #else
1523
1524 static inline void gen_op_fcmps(int fccno)
1525 {
1526     tcg_gen_helper_0_0(helper_fcmps);
1527 }
1528
1529 static inline void gen_op_fcmpd(int fccno)
1530 {
1531     tcg_gen_helper_0_0(helper_fcmpd);
1532 }
1533
1534 #if defined(CONFIG_USER_ONLY)
1535 static inline void gen_op_fcmpq(int fccno)
1536 {
1537     tcg_gen_helper_0_0(helper_fcmpq);
1538 }
1539 #endif
1540
1541 static inline void gen_op_fcmpes(int fccno)
1542 {
1543     tcg_gen_helper_0_0(helper_fcmpes);
1544 }
1545
1546 static inline void gen_op_fcmped(int fccno)
1547 {
1548     tcg_gen_helper_0_0(helper_fcmped);
1549 }
1550
1551 #if defined(CONFIG_USER_ONLY)
1552 static inline void gen_op_fcmpeq(int fccno)
1553 {
1554     tcg_gen_helper_0_0(helper_fcmpeq);
1555 }
1556 #endif
1557
1558 #endif
1559
1560 static inline void gen_op_fpexception_im(int fsr_flags)
1561 {
1562     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
1563     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~FSR_FTT_MASK);
1564     tcg_gen_ori_tl(cpu_tmp0, cpu_tmp0, fsr_flags);
1565     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
1566     gen_op_exception(TT_FP_EXCP);
1567 }
1568
1569 static int gen_trap_ifnofpu(DisasContext * dc)
1570 {
1571 #if !defined(CONFIG_USER_ONLY)
1572     if (!dc->fpu_enabled) {
1573         save_state(dc);
1574         gen_op_exception(TT_NFPU_INSN);
1575         dc->is_br = 1;
1576         return 1;
1577     }
1578 #endif
1579     return 0;
1580 }
1581
1582 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1583 {
1584     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
1585     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1586     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
1587 }
1588
1589 static inline void gen_clear_float_exceptions(void)
1590 {
1591     tcg_gen_helper_0_0(helper_clear_float_exceptions);
1592 }
1593
1594 /* asi moves */
1595 #ifdef TARGET_SPARC64
1596 static inline void gen_ld_asi(int insn, int size, int sign)
1597 {
1598     int asi, offset;
1599     TCGv r_size, r_sign;
1600
1601     r_size = tcg_temp_new(TCG_TYPE_I32);
1602     r_sign = tcg_temp_new(TCG_TYPE_I32);
1603     tcg_gen_movi_i32(r_size, size);
1604     tcg_gen_movi_i32(r_sign, sign);
1605     if (IS_IMM) {
1606         offset = GET_FIELD(insn, 25, 31);
1607         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1608         tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
1609     } else {
1610         asi = GET_FIELD(insn, 19, 26);
1611         tcg_gen_movi_i32(cpu_T[1], asi);
1612     }
1613     tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], cpu_T[1], r_size,
1614                        r_sign);
1615 }
1616
1617 static inline void gen_st_asi(int insn, int size)
1618 {
1619     int asi, offset;
1620     TCGv r_asi, r_size;
1621
1622     r_asi = tcg_temp_new(TCG_TYPE_I32);
1623     r_size = tcg_temp_new(TCG_TYPE_I32);
1624     tcg_gen_movi_i32(r_size, size);
1625     if (IS_IMM) {
1626         offset = GET_FIELD(insn, 25, 31);
1627         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1628         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1629     } else {
1630         asi = GET_FIELD(insn, 19, 26);
1631         tcg_gen_movi_i32(r_asi, asi);
1632     }
1633     tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi, r_size);
1634 }
1635
1636 static inline void gen_ldf_asi(int insn, int size, int rd)
1637 {
1638     int asi, offset;
1639     TCGv r_asi, r_size, r_rd;
1640
1641     r_asi = tcg_temp_new(TCG_TYPE_I32);
1642     r_size = tcg_temp_new(TCG_TYPE_I32);
1643     r_rd = tcg_temp_new(TCG_TYPE_I32);
1644     tcg_gen_movi_i32(r_size, size);
1645     tcg_gen_movi_i32(r_rd, rd);
1646     if (IS_IMM) {
1647         offset = GET_FIELD(insn, 25, 31);
1648         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1649         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1650     } else {
1651         asi = GET_FIELD(insn, 19, 26);
1652         tcg_gen_movi_i32(r_asi, asi);
1653     }
1654     tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, r_size, r_rd);
1655 }
1656
1657 static inline void gen_stf_asi(int insn, int size, int rd)
1658 {
1659     int asi, offset;
1660     TCGv r_asi, r_size, r_rd;
1661
1662     r_asi = tcg_temp_new(TCG_TYPE_I32);
1663     r_size = tcg_temp_new(TCG_TYPE_I32);
1664     r_rd = tcg_temp_new(TCG_TYPE_I32);
1665     tcg_gen_movi_i32(r_size, size);
1666     tcg_gen_movi_i32(r_rd, rd);
1667     if (IS_IMM) {
1668         offset = GET_FIELD(insn, 25, 31);
1669         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1670         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1671     } else {
1672         asi = GET_FIELD(insn, 19, 26);
1673         tcg_gen_movi_i32(r_asi, asi);
1674     }
1675     tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, r_size, r_rd);
1676 }
1677
1678 static inline void gen_swap_asi(int insn)
1679 {
1680     int asi, offset;
1681     TCGv r_size, r_sign, r_temp;
1682
1683     r_size = tcg_temp_new(TCG_TYPE_I32);
1684     r_sign = tcg_temp_new(TCG_TYPE_I32);
1685     r_temp = tcg_temp_new(TCG_TYPE_I32);
1686     tcg_gen_movi_i32(r_size, 4);
1687     tcg_gen_movi_i32(r_sign, 0);
1688     if (IS_IMM) {
1689         offset = GET_FIELD(insn, 25, 31);
1690         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1691         tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
1692     } else {
1693         asi = GET_FIELD(insn, 19, 26);
1694         tcg_gen_movi_i32(cpu_T[1], asi);
1695     }
1696     tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
1697                        r_sign);
1698     tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
1699     tcg_gen_mov_i32(cpu_T[1], r_temp);
1700 }
1701
1702 static inline void gen_ldda_asi(int insn)
1703 {
1704     int asi, offset;
1705     TCGv r_size, r_sign, r_dword;
1706
1707     r_size = tcg_temp_new(TCG_TYPE_I32);
1708     r_sign = tcg_temp_new(TCG_TYPE_I32);
1709     r_dword = tcg_temp_new(TCG_TYPE_I64);
1710     tcg_gen_movi_i32(r_size, 8);
1711     tcg_gen_movi_i32(r_sign, 0);
1712     if (IS_IMM) {
1713         offset = GET_FIELD(insn, 25, 31);
1714         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1715         tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
1716     } else {
1717         asi = GET_FIELD(insn, 19, 26);
1718         tcg_gen_movi_i32(cpu_T[1], asi);
1719     }
1720     tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
1721                        r_sign);
1722     tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1723     tcg_gen_shri_i64(r_dword, r_dword, 32);
1724     tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1725 }
1726
1727 static inline void gen_cas_asi(int insn, int rd)
1728 {
1729     int asi, offset;
1730     TCGv r_val1, r_asi;
1731
1732     r_val1 = tcg_temp_new(TCG_TYPE_I32);
1733     r_asi = tcg_temp_new(TCG_TYPE_I32);
1734     gen_movl_reg_TN(rd, r_val1);
1735     if (IS_IMM) {
1736         offset = GET_FIELD(insn, 25, 31);
1737         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1738         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1739     } else {
1740         asi = GET_FIELD(insn, 19, 26);
1741         tcg_gen_movi_i32(r_asi, asi);
1742     }
1743     tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1744                        r_asi);
1745 }
1746
1747 static inline void gen_casx_asi(int insn, int rd)
1748 {
1749     int asi, offset;
1750     TCGv r_val1, r_asi;
1751
1752     r_val1 = tcg_temp_new(TCG_TYPE_I64);
1753     r_asi = tcg_temp_new(TCG_TYPE_I32);
1754     gen_movl_reg_TN(rd, r_val1);
1755     if (IS_IMM) {
1756         offset = GET_FIELD(insn, 25, 31);
1757         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1758         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1759     } else {
1760         asi = GET_FIELD(insn, 19, 26);
1761         tcg_gen_movi_i32(r_asi, asi);
1762     }
1763     tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1764                        r_asi);
1765 }
1766
1767 #elif !defined(CONFIG_USER_ONLY)
1768
1769 static inline void gen_ld_asi(int insn, int size, int sign)
1770 {
1771     int asi;
1772     TCGv r_size, r_sign, r_dword;
1773
1774     r_size = tcg_temp_new(TCG_TYPE_I32);
1775     r_sign = tcg_temp_new(TCG_TYPE_I32);
1776     r_dword = tcg_temp_new(TCG_TYPE_I64);
1777     tcg_gen_movi_i32(r_size, size);
1778     tcg_gen_movi_i32(r_sign, sign);
1779     asi = GET_FIELD(insn, 19, 26);
1780     tcg_gen_movi_i32(cpu_T[1], asi);
1781     tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
1782                        r_sign);
1783     tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1784 }
1785
1786 static inline void gen_st_asi(int insn, int size)
1787 {
1788     int asi;
1789     TCGv r_dword, r_asi, r_size;
1790
1791     r_dword = tcg_temp_new(TCG_TYPE_I64);
1792     tcg_gen_extu_i32_i64(r_dword, cpu_T[1]);
1793     r_asi = tcg_temp_new(TCG_TYPE_I32);
1794     r_size = tcg_temp_new(TCG_TYPE_I32);
1795     asi = GET_FIELD(insn, 19, 26);
1796     tcg_gen_movi_i32(r_asi, asi);
1797     tcg_gen_movi_i32(r_size, size);
1798     tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
1799 }
1800
1801 static inline void gen_swap_asi(int insn)
1802 {
1803     int asi;
1804     TCGv r_size, r_sign, r_temp;
1805
1806     r_size = tcg_temp_new(TCG_TYPE_I32);
1807     r_sign = tcg_temp_new(TCG_TYPE_I32);
1808     r_temp = tcg_temp_new(TCG_TYPE_I32);
1809     tcg_gen_movi_i32(r_size, 4);
1810     tcg_gen_movi_i32(r_sign, 0);
1811     asi = GET_FIELD(insn, 19, 26);
1812     tcg_gen_movi_i32(cpu_T[1], asi);
1813     tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
1814                        r_sign);
1815     tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
1816     tcg_gen_mov_i32(cpu_T[1], r_temp);
1817 }
1818
1819 static inline void gen_ldda_asi(int insn)
1820 {
1821     int asi;
1822     TCGv r_size, r_sign, r_dword;
1823
1824     r_size = tcg_temp_new(TCG_TYPE_I32);
1825     r_sign = tcg_temp_new(TCG_TYPE_I32);
1826     r_dword = tcg_temp_new(TCG_TYPE_I64);
1827     tcg_gen_movi_i32(r_size, 8);
1828     tcg_gen_movi_i32(r_sign, 0);
1829     asi = GET_FIELD(insn, 19, 26);
1830     tcg_gen_movi_i32(cpu_T[1], asi);
1831     tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
1832                        r_sign);
1833     tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1834     tcg_gen_shri_i64(r_dword, r_dword, 32);
1835     tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1836 }
1837 #endif
1838
1839 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1840 static inline void gen_ldstub_asi(int insn)
1841 {
1842     int asi;
1843     TCGv r_dword, r_asi, r_size;
1844
1845     gen_ld_asi(insn, 1, 0);
1846
1847     r_dword = tcg_temp_new(TCG_TYPE_I64);
1848     r_asi = tcg_temp_new(TCG_TYPE_I32);
1849     r_size = tcg_temp_new(TCG_TYPE_I32);
1850     asi = GET_FIELD(insn, 19, 26);
1851     tcg_gen_movi_i32(r_dword, 0xff);
1852     tcg_gen_movi_i32(r_asi, asi);
1853     tcg_gen_movi_i32(r_size, 1);
1854     tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
1855 }
1856 #endif
1857
1858 /* before an instruction, dc->pc must be static */
1859 static void disas_sparc_insn(DisasContext * dc)
1860 {
1861     unsigned int insn, opc, rs1, rs2, rd;
1862
1863     insn = ldl_code(dc->pc);
1864     opc = GET_FIELD(insn, 0, 1);
1865
1866     rd = GET_FIELD(insn, 2, 6);
1867     switch (opc) {
1868     case 0:                     /* branches/sethi */
1869         {
1870             unsigned int xop = GET_FIELD(insn, 7, 9);
1871             int32_t target;
1872             switch (xop) {
1873 #ifdef TARGET_SPARC64
1874             case 0x1:           /* V9 BPcc */
1875                 {
1876                     int cc;
1877
1878                     target = GET_FIELD_SP(insn, 0, 18);
1879                     target = sign_extend(target, 18);
1880                     target <<= 2;
1881                     cc = GET_FIELD_SP(insn, 20, 21);
1882                     if (cc == 0)
1883                         do_branch(dc, target, insn, 0);
1884                     else if (cc == 2)
1885                         do_branch(dc, target, insn, 1);
1886                     else
1887                         goto illegal_insn;
1888                     goto jmp_insn;
1889                 }
1890             case 0x3:           /* V9 BPr */
1891                 {
1892                     target = GET_FIELD_SP(insn, 0, 13) |
1893                         (GET_FIELD_SP(insn, 20, 21) << 14);
1894                     target = sign_extend(target, 16);
1895                     target <<= 2;
1896                     rs1 = GET_FIELD(insn, 13, 17);
1897                     gen_movl_reg_T0(rs1);
1898                     do_branch_reg(dc, target, insn);
1899                     goto jmp_insn;
1900                 }
1901             case 0x5:           /* V9 FBPcc */
1902                 {
1903                     int cc = GET_FIELD_SP(insn, 20, 21);
1904                     if (gen_trap_ifnofpu(dc))
1905                         goto jmp_insn;
1906                     target = GET_FIELD_SP(insn, 0, 18);
1907                     target = sign_extend(target, 19);
1908                     target <<= 2;
1909                     do_fbranch(dc, target, insn, cc);
1910                     goto jmp_insn;
1911                 }
1912 #else
1913             case 0x7:           /* CBN+x */
1914                 {
1915                     goto ncp_insn;
1916                 }
1917 #endif
1918             case 0x2:           /* BN+x */
1919                 {
1920                     target = GET_FIELD(insn, 10, 31);
1921                     target = sign_extend(target, 22);
1922                     target <<= 2;
1923                     do_branch(dc, target, insn, 0);
1924                     goto jmp_insn;
1925                 }
1926             case 0x6:           /* FBN+x */
1927                 {
1928                     if (gen_trap_ifnofpu(dc))
1929                         goto jmp_insn;
1930                     target = GET_FIELD(insn, 10, 31);
1931                     target = sign_extend(target, 22);
1932                     target <<= 2;
1933                     do_fbranch(dc, target, insn, 0);
1934                     goto jmp_insn;
1935                 }
1936             case 0x4:           /* SETHI */
1937 #define OPTIM
1938 #if defined(OPTIM)
1939                 if (rd) { // nop
1940 #endif
1941                     uint32_t value = GET_FIELD(insn, 10, 31);
1942                     tcg_gen_movi_tl(cpu_T[0], value << 10);
1943                     gen_movl_T0_reg(rd);
1944 #if defined(OPTIM)
1945                 }
1946 #endif
1947                 break;
1948             case 0x0:           /* UNIMPL */
1949             default:
1950                 goto illegal_insn;
1951             }
1952             break;
1953         }
1954         break;
1955     case 1:
1956         /*CALL*/ {
1957             target_long target = GET_FIELDs(insn, 2, 31) << 2;
1958
1959             tcg_gen_movi_tl(cpu_T[0], dc->pc);
1960             gen_movl_T0_reg(15);
1961             target += dc->pc;
1962             gen_mov_pc_npc(dc);
1963             dc->npc = target;
1964         }
1965         goto jmp_insn;
1966     case 2:                     /* FPU & Logical Operations */
1967         {
1968             unsigned int xop = GET_FIELD(insn, 7, 12);
1969             if (xop == 0x3a) {  /* generate trap */
1970                 int cond;
1971
1972                 rs1 = GET_FIELD(insn, 13, 17);
1973                 gen_movl_reg_T0(rs1);
1974                 if (IS_IMM) {
1975                     rs2 = GET_FIELD(insn, 25, 31);
1976                     tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2);
1977                 } else {
1978                     rs2 = GET_FIELD(insn, 27, 31);
1979 #if defined(OPTIM)
1980                     if (rs2 != 0) {
1981 #endif
1982                         gen_movl_reg_T1(rs2);
1983                         gen_op_add_T1_T0();
1984 #if defined(OPTIM)
1985                     }
1986 #endif
1987                 }
1988                 cond = GET_FIELD(insn, 3, 6);
1989                 if (cond == 0x8) {
1990                     save_state(dc);
1991                     tcg_gen_helper_0_1(helper_trap, cpu_T[0]);
1992                 } else if (cond != 0) {
1993 #ifdef TARGET_SPARC64
1994                     /* V9 icc/xcc */
1995                     int cc = GET_FIELD_SP(insn, 11, 12);
1996                     flush_T2(dc);
1997                     save_state(dc);
1998                     if (cc == 0)
1999                         gen_cond(cpu_T[2], 0, cond);
2000                     else if (cc == 2)
2001                         gen_cond(cpu_T[2], 1, cond);
2002                     else
2003                         goto illegal_insn;
2004 #else
2005                     flush_T2(dc);
2006                     save_state(dc);
2007                     gen_cond(cpu_T[2], 0, cond);
2008 #endif
2009                     tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], cpu_T[2]);
2010                 }
2011                 gen_op_next_insn();
2012                 tcg_gen_exit_tb(0);
2013                 dc->is_br = 1;
2014                 goto jmp_insn;
2015             } else if (xop == 0x28) {
2016                 rs1 = GET_FIELD(insn, 13, 17);
2017                 switch(rs1) {
2018                 case 0: /* rdy */
2019 #ifndef TARGET_SPARC64
2020                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2021                                        manual, rdy on the microSPARC
2022                                        II */
2023                 case 0x0f:          /* stbar in the SPARCv8 manual,
2024                                        rdy on the microSPARC II */
2025                 case 0x10 ... 0x1f: /* implementation-dependent in the
2026                                        SPARCv8 manual, rdy on the
2027                                        microSPARC II */
2028 #endif
2029                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
2030                     gen_movl_T0_reg(rd);
2031                     break;
2032 #ifdef TARGET_SPARC64
2033                 case 0x2: /* V9 rdccr */
2034                     gen_op_rdccr();
2035                     gen_movl_T0_reg(rd);
2036                     break;
2037                 case 0x3: /* V9 rdasi */
2038                     gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
2039                     gen_movl_T0_reg(rd);
2040                     break;
2041                 case 0x4: /* V9 rdtick */
2042                     {
2043                         TCGv r_tickptr;
2044
2045                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2046                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2047                                        offsetof(CPUState, tick));
2048                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2049                                            r_tickptr);
2050                         gen_movl_T0_reg(rd);
2051                     }
2052                     break;
2053                 case 0x5: /* V9 rdpc */
2054                     tcg_gen_movi_tl(cpu_T[0], dc->pc);
2055                     gen_movl_T0_reg(rd);
2056                     break;
2057                 case 0x6: /* V9 rdfprs */
2058                     gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
2059                     gen_movl_T0_reg(rd);
2060                     break;
2061                 case 0xf: /* V9 membar */
2062                     break; /* no effect */
2063                 case 0x13: /* Graphics Status */
2064                     if (gen_trap_ifnofpu(dc))
2065                         goto jmp_insn;
2066                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
2067                     gen_movl_T0_reg(rd);
2068                     break;
2069                 case 0x17: /* Tick compare */
2070                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
2071                     gen_movl_T0_reg(rd);
2072                     break;
2073                 case 0x18: /* System tick */
2074                     {
2075                         TCGv r_tickptr;
2076
2077                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2078                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2079                                        offsetof(CPUState, stick));
2080                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2081                                            r_tickptr);
2082                         gen_movl_T0_reg(rd);
2083                     }
2084                     break;
2085                 case 0x19: /* System tick compare */
2086                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
2087                     gen_movl_T0_reg(rd);
2088                     break;
2089                 case 0x10: /* Performance Control */
2090                 case 0x11: /* Performance Instrumentation Counter */
2091                 case 0x12: /* Dispatch Control */
2092                 case 0x14: /* Softint set, WO */
2093                 case 0x15: /* Softint clear, WO */
2094                 case 0x16: /* Softint write */
2095 #endif
2096                 default:
2097                     goto illegal_insn;
2098                 }
2099 #if !defined(CONFIG_USER_ONLY)
2100             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2101 #ifndef TARGET_SPARC64
2102                 if (!supervisor(dc))
2103                     goto priv_insn;
2104                 tcg_gen_helper_1_0(helper_rdpsr, cpu_T[0]);
2105 #else
2106                 if (!hypervisor(dc))
2107                     goto priv_insn;
2108                 rs1 = GET_FIELD(insn, 13, 17);
2109                 switch (rs1) {
2110                 case 0: // hpstate
2111                     // gen_op_rdhpstate();
2112                     break;
2113                 case 1: // htstate
2114                     // gen_op_rdhtstate();
2115                     break;
2116                 case 3: // hintp
2117                     gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
2118                     break;
2119                 case 5: // htba
2120                     gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
2121                     break;
2122                 case 6: // hver
2123                     gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
2124                     break;
2125                 case 31: // hstick_cmpr
2126                     gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2127                     break;
2128                 default:
2129                     goto illegal_insn;
2130                 }
2131 #endif
2132                 gen_movl_T0_reg(rd);
2133                 break;
2134             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2135                 if (!supervisor(dc))
2136                     goto priv_insn;
2137 #ifdef TARGET_SPARC64
2138                 rs1 = GET_FIELD(insn, 13, 17);
2139                 switch (rs1) {
2140                 case 0: // tpc
2141                     {
2142                         TCGv r_tsptr;
2143
2144                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2145                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2146                                        offsetof(CPUState, tsptr));
2147                         tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2148                                       offsetof(trap_state, tpc));
2149                     }
2150                     break;
2151                 case 1: // tnpc
2152                     {
2153                         TCGv r_tsptr;
2154
2155                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2156                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2157                                        offsetof(CPUState, tsptr));
2158                         tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2159                                       offsetof(trap_state, tnpc));
2160                     }
2161                     break;
2162                 case 2: // tstate
2163                     {
2164                         TCGv r_tsptr;
2165
2166                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2167                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2168                                        offsetof(CPUState, tsptr));
2169                         tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2170                                       offsetof(trap_state, tstate));
2171                     }
2172                     break;
2173                 case 3: // tt
2174                     {
2175                         TCGv r_tsptr;
2176
2177                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2178                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2179                                        offsetof(CPUState, tsptr));
2180                         tcg_gen_ld_i32(cpu_T[0], r_tsptr,
2181                                        offsetof(trap_state, tt));
2182                     }
2183                     break;
2184                 case 4: // tick
2185                     {
2186                         TCGv r_tickptr;
2187
2188                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2189                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2190                                        offsetof(CPUState, tick));
2191                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2192                                            r_tickptr);
2193                         gen_movl_T0_reg(rd);
2194                     }
2195                     break;
2196                 case 5: // tba
2197                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
2198                     break;
2199                 case 6: // pstate
2200                     gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate));
2201                     break;
2202                 case 7: // tl
2203                     gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
2204                     break;
2205                 case 8: // pil
2206                     gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
2207                     break;
2208                 case 9: // cwp
2209                     gen_op_rdcwp();
2210                     break;
2211                 case 10: // cansave
2212                     gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
2213                     break;
2214                 case 11: // canrestore
2215                     gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
2216                     break;
2217                 case 12: // cleanwin
2218                     gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
2219                     break;
2220                 case 13: // otherwin
2221                     gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
2222                     break;
2223                 case 14: // wstate
2224                     gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
2225                     break;
2226                 case 16: // UA2005 gl
2227                     gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
2228                     break;
2229                 case 26: // UA2005 strand status
2230                     if (!hypervisor(dc))
2231                         goto priv_insn;
2232                     gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
2233                     break;
2234                 case 31: // ver
2235                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
2236                     break;
2237                 case 15: // fq
2238                 default:
2239                     goto illegal_insn;
2240                 }
2241 #else
2242                 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
2243 #endif
2244                 gen_movl_T0_reg(rd);
2245                 break;
2246             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2247 #ifdef TARGET_SPARC64
2248                 gen_op_flushw();
2249 #else
2250                 if (!supervisor(dc))
2251                     goto priv_insn;
2252                 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
2253                 gen_movl_T0_reg(rd);
2254 #endif
2255                 break;
2256 #endif
2257             } else if (xop == 0x34) {   /* FPU Operations */
2258                 if (gen_trap_ifnofpu(dc))
2259                     goto jmp_insn;
2260                 gen_op_clear_ieee_excp_and_FTT();
2261                 rs1 = GET_FIELD(insn, 13, 17);
2262                 rs2 = GET_FIELD(insn, 27, 31);
2263                 xop = GET_FIELD(insn, 18, 26);
2264                 switch (xop) {
2265                     case 0x1: /* fmovs */
2266                         gen_op_load_fpr_FT0(rs2);
2267                         gen_op_store_FT0_fpr(rd);
2268                         break;
2269                     case 0x5: /* fnegs */
2270                         gen_op_load_fpr_FT1(rs2);
2271                         gen_op_fnegs();
2272                         gen_op_store_FT0_fpr(rd);
2273                         break;
2274                     case 0x9: /* fabss */
2275                         gen_op_load_fpr_FT1(rs2);
2276                         tcg_gen_helper_0_0(helper_fabss);
2277                         gen_op_store_FT0_fpr(rd);
2278                         break;
2279                     case 0x29: /* fsqrts */
2280                         gen_op_load_fpr_FT1(rs2);
2281                         gen_clear_float_exceptions();
2282                         tcg_gen_helper_0_0(helper_fsqrts);
2283                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2284                         gen_op_store_FT0_fpr(rd);
2285                         break;
2286                     case 0x2a: /* fsqrtd */
2287                         gen_op_load_fpr_DT1(DFPREG(rs2));
2288                         gen_clear_float_exceptions();
2289                         tcg_gen_helper_0_0(helper_fsqrtd);
2290                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2291                         gen_op_store_DT0_fpr(DFPREG(rd));
2292                         break;
2293                     case 0x2b: /* fsqrtq */
2294 #if defined(CONFIG_USER_ONLY)
2295                         gen_op_load_fpr_QT1(QFPREG(rs2));
2296                         gen_clear_float_exceptions();
2297                         tcg_gen_helper_0_0(helper_fsqrtq);
2298                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2299                         gen_op_store_QT0_fpr(QFPREG(rd));
2300                         break;
2301 #else
2302                         goto nfpu_insn;
2303 #endif
2304                     case 0x41:
2305                         gen_op_load_fpr_FT0(rs1);
2306                         gen_op_load_fpr_FT1(rs2);
2307                         gen_clear_float_exceptions();
2308                         gen_op_fadds();
2309                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2310                         gen_op_store_FT0_fpr(rd);
2311                         break;
2312                     case 0x42:
2313                         gen_op_load_fpr_DT0(DFPREG(rs1));
2314                         gen_op_load_fpr_DT1(DFPREG(rs2));
2315                         gen_clear_float_exceptions();
2316                         gen_op_faddd();
2317                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2318                         gen_op_store_DT0_fpr(DFPREG(rd));
2319                         break;
2320                     case 0x43: /* faddq */
2321 #if defined(CONFIG_USER_ONLY)
2322                         gen_op_load_fpr_QT0(QFPREG(rs1));
2323                         gen_op_load_fpr_QT1(QFPREG(rs2));
2324                         gen_clear_float_exceptions();
2325                         gen_op_faddq();
2326                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2327                         gen_op_store_QT0_fpr(QFPREG(rd));
2328                         break;
2329 #else
2330                         goto nfpu_insn;
2331 #endif
2332                     case 0x45:
2333                         gen_op_load_fpr_FT0(rs1);
2334                         gen_op_load_fpr_FT1(rs2);
2335                         gen_clear_float_exceptions();
2336                         gen_op_fsubs();
2337                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2338                         gen_op_store_FT0_fpr(rd);
2339                         break;
2340                     case 0x46:
2341                         gen_op_load_fpr_DT0(DFPREG(rs1));
2342                         gen_op_load_fpr_DT1(DFPREG(rs2));
2343                         gen_clear_float_exceptions();
2344                         gen_op_fsubd();
2345                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2346                         gen_op_store_DT0_fpr(DFPREG(rd));
2347                         break;
2348                     case 0x47: /* fsubq */
2349 #if defined(CONFIG_USER_ONLY)
2350                         gen_op_load_fpr_QT0(QFPREG(rs1));
2351                         gen_op_load_fpr_QT1(QFPREG(rs2));
2352                         gen_clear_float_exceptions();
2353                         gen_op_fsubq();
2354                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2355                         gen_op_store_QT0_fpr(QFPREG(rd));
2356                         break;
2357 #else
2358                         goto nfpu_insn;
2359 #endif
2360                     case 0x49:
2361                         gen_op_load_fpr_FT0(rs1);
2362                         gen_op_load_fpr_FT1(rs2);
2363                         gen_clear_float_exceptions();
2364                         gen_op_fmuls();
2365                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2366                         gen_op_store_FT0_fpr(rd);
2367                         break;
2368                     case 0x4a:
2369                         gen_op_load_fpr_DT0(DFPREG(rs1));
2370                         gen_op_load_fpr_DT1(DFPREG(rs2));
2371                         gen_clear_float_exceptions();
2372                         gen_op_fmuld();
2373                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2374                         gen_op_store_DT0_fpr(DFPREG(rd));
2375                         break;
2376                     case 0x4b: /* fmulq */
2377 #if defined(CONFIG_USER_ONLY)
2378                         gen_op_load_fpr_QT0(QFPREG(rs1));
2379                         gen_op_load_fpr_QT1(QFPREG(rs2));
2380                         gen_clear_float_exceptions();
2381                         gen_op_fmulq();
2382                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2383                         gen_op_store_QT0_fpr(QFPREG(rd));
2384                         break;
2385 #else
2386                         goto nfpu_insn;
2387 #endif
2388                     case 0x4d:
2389                         gen_op_load_fpr_FT0(rs1);
2390                         gen_op_load_fpr_FT1(rs2);
2391                         gen_clear_float_exceptions();
2392                         gen_op_fdivs();
2393                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2394                         gen_op_store_FT0_fpr(rd);
2395                         break;
2396                     case 0x4e:
2397                         gen_op_load_fpr_DT0(DFPREG(rs1));
2398                         gen_op_load_fpr_DT1(DFPREG(rs2));
2399                         gen_clear_float_exceptions();
2400                         gen_op_fdivd();
2401                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2402                         gen_op_store_DT0_fpr(DFPREG(rd));
2403                         break;
2404                     case 0x4f: /* fdivq */
2405 #if defined(CONFIG_USER_ONLY)
2406                         gen_op_load_fpr_QT0(QFPREG(rs1));
2407                         gen_op_load_fpr_QT1(QFPREG(rs2));
2408                         gen_clear_float_exceptions();
2409                         gen_op_fdivq();
2410                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2411                         gen_op_store_QT0_fpr(QFPREG(rd));
2412                         break;
2413 #else
2414                         goto nfpu_insn;
2415 #endif
2416                     case 0x69:
2417                         gen_op_load_fpr_FT0(rs1);
2418                         gen_op_load_fpr_FT1(rs2);
2419                         gen_clear_float_exceptions();
2420                         gen_op_fsmuld();
2421                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2422                         gen_op_store_DT0_fpr(DFPREG(rd));
2423                         break;
2424                     case 0x6e: /* fdmulq */
2425 #if defined(CONFIG_USER_ONLY)
2426                         gen_op_load_fpr_DT0(DFPREG(rs1));
2427                         gen_op_load_fpr_DT1(DFPREG(rs2));
2428                         gen_clear_float_exceptions();
2429                         gen_op_fdmulq();
2430                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2431                         gen_op_store_QT0_fpr(QFPREG(rd));
2432                         break;
2433 #else
2434                         goto nfpu_insn;
2435 #endif
2436                     case 0xc4:
2437                         gen_op_load_fpr_FT1(rs2);
2438                         gen_clear_float_exceptions();
2439                         gen_op_fitos();
2440                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2441                         gen_op_store_FT0_fpr(rd);
2442                         break;
2443                     case 0xc6:
2444                         gen_op_load_fpr_DT1(DFPREG(rs2));
2445                         gen_clear_float_exceptions();
2446                         gen_op_fdtos();
2447                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2448                         gen_op_store_FT0_fpr(rd);
2449                         break;
2450                     case 0xc7: /* fqtos */
2451 #if defined(CONFIG_USER_ONLY)
2452                         gen_op_load_fpr_QT1(QFPREG(rs2));
2453                         gen_clear_float_exceptions();
2454                         gen_op_fqtos();
2455                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2456                         gen_op_store_FT0_fpr(rd);
2457                         break;
2458 #else
2459                         goto nfpu_insn;
2460 #endif
2461                     case 0xc8:
2462                         gen_op_load_fpr_FT1(rs2);
2463                         gen_op_fitod();
2464                         gen_op_store_DT0_fpr(DFPREG(rd));
2465                         break;
2466                     case 0xc9:
2467                         gen_op_load_fpr_FT1(rs2);
2468                         gen_op_fstod();
2469                         gen_op_store_DT0_fpr(DFPREG(rd));
2470                         break;
2471                     case 0xcb: /* fqtod */
2472 #if defined(CONFIG_USER_ONLY)
2473                         gen_op_load_fpr_QT1(QFPREG(rs2));
2474                         gen_clear_float_exceptions();
2475                         gen_op_fqtod();
2476                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2477                         gen_op_store_DT0_fpr(DFPREG(rd));
2478                         break;
2479 #else
2480                         goto nfpu_insn;
2481 #endif
2482                     case 0xcc: /* fitoq */
2483 #if defined(CONFIG_USER_ONLY)
2484                         gen_op_load_fpr_FT1(rs2);
2485                         gen_op_fitoq();
2486                         gen_op_store_QT0_fpr(QFPREG(rd));
2487                         break;
2488 #else
2489                         goto nfpu_insn;
2490 #endif
2491                     case 0xcd: /* fstoq */
2492 #if defined(CONFIG_USER_ONLY)
2493                         gen_op_load_fpr_FT1(rs2);
2494                         gen_op_fstoq();
2495                         gen_op_store_QT0_fpr(QFPREG(rd));
2496                         break;
2497 #else
2498                         goto nfpu_insn;
2499 #endif
2500                     case 0xce: /* fdtoq */
2501 #if defined(CONFIG_USER_ONLY)
2502                         gen_op_load_fpr_DT1(DFPREG(rs2));
2503                         gen_op_fdtoq();
2504                         gen_op_store_QT0_fpr(QFPREG(rd));
2505                         break;
2506 #else
2507                         goto nfpu_insn;
2508 #endif
2509                     case 0xd1:
2510                         gen_op_load_fpr_FT1(rs2);
2511                         gen_clear_float_exceptions();
2512                         gen_op_fstoi();
2513                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2514                         gen_op_store_FT0_fpr(rd);
2515                         break;
2516                     case 0xd2:
2517                         gen_op_load_fpr_DT1(DFPREG(rs2));
2518                         gen_clear_float_exceptions();
2519                         gen_op_fdtoi();
2520                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2521                         gen_op_store_FT0_fpr(rd);
2522                         break;
2523                     case 0xd3: /* fqtoi */
2524 #if defined(CONFIG_USER_ONLY)
2525                         gen_op_load_fpr_QT1(QFPREG(rs2));
2526                         gen_clear_float_exceptions();
2527                         gen_op_fqtoi();
2528                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2529                         gen_op_store_FT0_fpr(rd);
2530                         break;
2531 #else
2532                         goto nfpu_insn;
2533 #endif
2534 #ifdef TARGET_SPARC64
2535                     case 0x2: /* V9 fmovd */
2536                         gen_op_load_fpr_DT0(DFPREG(rs2));
2537                         gen_op_store_DT0_fpr(DFPREG(rd));
2538                         break;
2539                     case 0x3: /* V9 fmovq */
2540 #if defined(CONFIG_USER_ONLY)
2541                         gen_op_load_fpr_QT0(QFPREG(rs2));
2542                         gen_op_store_QT0_fpr(QFPREG(rd));
2543                         break;
2544 #else
2545                         goto nfpu_insn;
2546 #endif
2547                     case 0x6: /* V9 fnegd */
2548                         gen_op_load_fpr_DT1(DFPREG(rs2));
2549                         gen_op_fnegd();
2550                         gen_op_store_DT0_fpr(DFPREG(rd));
2551                         break;
2552                     case 0x7: /* V9 fnegq */
2553 #if defined(CONFIG_USER_ONLY)
2554                         gen_op_load_fpr_QT1(QFPREG(rs2));
2555                         gen_op_fnegq();
2556                         gen_op_store_QT0_fpr(QFPREG(rd));
2557                         break;
2558 #else
2559                         goto nfpu_insn;
2560 #endif
2561                     case 0xa: /* V9 fabsd */
2562                         gen_op_load_fpr_DT1(DFPREG(rs2));
2563                         tcg_gen_helper_0_0(helper_fabsd);
2564                         gen_op_store_DT0_fpr(DFPREG(rd));
2565                         break;
2566                     case 0xb: /* V9 fabsq */
2567 #if defined(CONFIG_USER_ONLY)
2568                         gen_op_load_fpr_QT1(QFPREG(rs2));
2569                         tcg_gen_helper_0_0(helper_fabsq);
2570                         gen_op_store_QT0_fpr(QFPREG(rd));
2571                         break;
2572 #else
2573                         goto nfpu_insn;
2574 #endif
2575                     case 0x81: /* V9 fstox */
2576                         gen_op_load_fpr_FT1(rs2);
2577                         gen_clear_float_exceptions();
2578                         gen_op_fstox();
2579                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2580                         gen_op_store_DT0_fpr(DFPREG(rd));
2581                         break;
2582                     case 0x82: /* V9 fdtox */
2583                         gen_op_load_fpr_DT1(DFPREG(rs2));
2584                         gen_clear_float_exceptions();
2585                         gen_op_fdtox();
2586                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2587                         gen_op_store_DT0_fpr(DFPREG(rd));
2588                         break;
2589                     case 0x83: /* V9 fqtox */
2590 #if defined(CONFIG_USER_ONLY)
2591                         gen_op_load_fpr_QT1(QFPREG(rs2));
2592                         gen_clear_float_exceptions();
2593                         gen_op_fqtox();
2594                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2595                         gen_op_store_DT0_fpr(DFPREG(rd));
2596                         break;
2597 #else
2598                         goto nfpu_insn;
2599 #endif
2600                     case 0x84: /* V9 fxtos */
2601                         gen_op_load_fpr_DT1(DFPREG(rs2));
2602                         gen_clear_float_exceptions();
2603                         gen_op_fxtos();
2604                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2605                         gen_op_store_FT0_fpr(rd);
2606                         break;
2607                     case 0x88: /* V9 fxtod */
2608                         gen_op_load_fpr_DT1(DFPREG(rs2));
2609                         gen_clear_float_exceptions();
2610                         gen_op_fxtod();
2611                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2612                         gen_op_store_DT0_fpr(DFPREG(rd));
2613                         break;
2614                     case 0x8c: /* V9 fxtoq */
2615 #if defined(CONFIG_USER_ONLY)
2616                         gen_op_load_fpr_DT1(DFPREG(rs2));
2617                         gen_clear_float_exceptions();
2618                         gen_op_fxtoq();
2619                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2620                         gen_op_store_QT0_fpr(QFPREG(rd));
2621                         break;
2622 #else
2623                         goto nfpu_insn;
2624 #endif
2625 #endif
2626                     default:
2627                         goto illegal_insn;
2628                 }
2629             } else if (xop == 0x35) {   /* FPU Operations */
2630 #ifdef TARGET_SPARC64
2631                 int cond;
2632 #endif
2633                 if (gen_trap_ifnofpu(dc))
2634                     goto jmp_insn;
2635                 gen_op_clear_ieee_excp_and_FTT();
2636                 rs1 = GET_FIELD(insn, 13, 17);
2637                 rs2 = GET_FIELD(insn, 27, 31);
2638                 xop = GET_FIELD(insn, 18, 26);
2639 #ifdef TARGET_SPARC64
2640                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2641                     TCGv r_zero;
2642                     int l1;
2643
2644                     l1 = gen_new_label();
2645                     r_zero = tcg_const_tl(0);
2646                     cond = GET_FIELD_SP(insn, 14, 17);
2647                     rs1 = GET_FIELD(insn, 13, 17);
2648                     gen_movl_reg_T0(rs1);
2649                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
2650                     gen_op_load_fpr_FT0(rs2);
2651                     gen_op_store_FT0_fpr(rd);
2652                     gen_set_label(l1);
2653                     break;
2654                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2655                     TCGv r_zero;
2656                     int l1;
2657
2658                     l1 = gen_new_label();
2659                     r_zero = tcg_const_tl(0);
2660                     cond = GET_FIELD_SP(insn, 14, 17);
2661                     rs1 = GET_FIELD(insn, 13, 17);
2662                     gen_movl_reg_T0(rs1);
2663                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
2664                     gen_op_load_fpr_DT0(DFPREG(rs2));
2665                     gen_op_store_DT0_fpr(DFPREG(rd));
2666                     gen_set_label(l1);
2667                     break;
2668                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2669 #if defined(CONFIG_USER_ONLY)
2670                     TCGv r_zero;
2671                     int l1;
2672
2673                     l1 = gen_new_label();
2674                     r_zero = tcg_const_tl(0);
2675                     cond = GET_FIELD_SP(insn, 14, 17);
2676                     rs1 = GET_FIELD(insn, 13, 17);
2677                     gen_movl_reg_T0(rs1);
2678                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
2679                     gen_op_load_fpr_QT0(QFPREG(rs2));
2680                     gen_op_store_QT0_fpr(QFPREG(rd));
2681                     gen_set_label(l1);
2682                     break;
2683 #else
2684                     goto nfpu_insn;
2685 #endif
2686                 }
2687 #endif
2688                 switch (xop) {
2689 #ifdef TARGET_SPARC64
2690 #define FMOVCC(size_FDQ, fcc)                                           \
2691                     {                                                   \
2692                         TCGv r_zero, r_cond;                            \
2693                         int l1;                                         \
2694                                                                         \
2695                         l1 = gen_new_label();                           \
2696                         r_zero = tcg_const_tl(0);                       \
2697                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2698                         cond = GET_FIELD_SP(insn, 14, 17);              \
2699                         gen_fcond(r_cond, fcc, cond);                   \
2700                         tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); \
2701                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2702                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2703                         gen_set_label(l1);                              \
2704                     }
2705                     case 0x001: /* V9 fmovscc %fcc0 */
2706                         FMOVCC(F, 0);
2707                         break;
2708                     case 0x002: /* V9 fmovdcc %fcc0 */
2709                         FMOVCC(D, 0);
2710                         break;
2711                     case 0x003: /* V9 fmovqcc %fcc0 */
2712 #if defined(CONFIG_USER_ONLY)
2713                         FMOVCC(Q, 0);
2714                         break;
2715 #else
2716                         goto nfpu_insn;
2717 #endif
2718                     case 0x041: /* V9 fmovscc %fcc1 */
2719                         FMOVCC(F, 1);
2720                         break;
2721                     case 0x042: /* V9 fmovdcc %fcc1 */
2722                         FMOVCC(D, 1);
2723                         break;
2724                     case 0x043: /* V9 fmovqcc %fcc1 */
2725 #if defined(CONFIG_USER_ONLY)
2726                         FMOVCC(Q, 1);
2727                         break;
2728 #else
2729                         goto nfpu_insn;
2730 #endif
2731                     case 0x081: /* V9 fmovscc %fcc2 */
2732                         FMOVCC(F, 2);
2733                         break;
2734                     case 0x082: /* V9 fmovdcc %fcc2 */
2735                         FMOVCC(D, 2);
2736                         break;
2737                     case 0x083: /* V9 fmovqcc %fcc2 */
2738 #if defined(CONFIG_USER_ONLY)
2739                         FMOVCC(Q, 2);
2740                         break;
2741 #else
2742                         goto nfpu_insn;
2743 #endif
2744                     case 0x0c1: /* V9 fmovscc %fcc3 */
2745                         FMOVCC(F, 3);
2746                         break;
2747                     case 0x0c2: /* V9 fmovdcc %fcc3 */
2748                         FMOVCC(D, 3);
2749                         break;
2750                     case 0x0c3: /* V9 fmovqcc %fcc3 */
2751 #if defined(CONFIG_USER_ONLY)
2752                         FMOVCC(Q, 3);
2753                         break;
2754 #else
2755                         goto nfpu_insn;
2756 #endif
2757 #undef FMOVCC
2758 #define FMOVCC(size_FDQ, icc)                                           \
2759                     {                                                   \
2760                         TCGv r_zero, r_cond;                            \
2761                         int l1;                                         \
2762                                                                         \
2763                         l1 = gen_new_label();                           \
2764                         r_zero = tcg_const_tl(0);                       \
2765                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2766                         cond = GET_FIELD_SP(insn, 14, 17);              \
2767                         gen_cond(r_cond, icc, cond);                    \
2768                         tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); \
2769                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2770                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2771                         gen_set_label(l1);                              \
2772                     }
2773
2774                     case 0x101: /* V9 fmovscc %icc */
2775                         FMOVCC(F, 0);
2776                         break;
2777                     case 0x102: /* V9 fmovdcc %icc */
2778                         FMOVCC(D, 0);
2779                     case 0x103: /* V9 fmovqcc %icc */
2780 #if defined(CONFIG_USER_ONLY)
2781                         FMOVCC(D, 0);
2782                         break;
2783 #else
2784                         goto nfpu_insn;
2785 #endif
2786                     case 0x181: /* V9 fmovscc %xcc */
2787                         FMOVCC(F, 1);
2788                         break;
2789                     case 0x182: /* V9 fmovdcc %xcc */
2790                         FMOVCC(D, 1);
2791                         break;
2792                     case 0x183: /* V9 fmovqcc %xcc */
2793 #if defined(CONFIG_USER_ONLY)
2794                         FMOVCC(Q, 1);
2795                         break;
2796 #else
2797                         goto nfpu_insn;
2798 #endif
2799 #undef FMOVCC
2800 #endif
2801                     case 0x51: /* fcmps, V9 %fcc */
2802                         gen_op_load_fpr_FT0(rs1);
2803                         gen_op_load_fpr_FT1(rs2);
2804                         gen_op_fcmps(rd & 3);
2805                         break;
2806                     case 0x52: /* fcmpd, V9 %fcc */
2807                         gen_op_load_fpr_DT0(DFPREG(rs1));
2808                         gen_op_load_fpr_DT1(DFPREG(rs2));
2809                         gen_op_fcmpd(rd & 3);
2810                         break;
2811                     case 0x53: /* fcmpq, V9 %fcc */
2812 #if defined(CONFIG_USER_ONLY)
2813                         gen_op_load_fpr_QT0(QFPREG(rs1));
2814                         gen_op_load_fpr_QT1(QFPREG(rs2));
2815                         gen_op_fcmpq(rd & 3);
2816                         break;
2817 #else /* !defined(CONFIG_USER_ONLY) */
2818                         goto nfpu_insn;
2819 #endif
2820                     case 0x55: /* fcmpes, V9 %fcc */
2821                         gen_op_load_fpr_FT0(rs1);
2822                         gen_op_load_fpr_FT1(rs2);
2823                         gen_op_fcmpes(rd & 3);
2824                         break;
2825                     case 0x56: /* fcmped, V9 %fcc */
2826                         gen_op_load_fpr_DT0(DFPREG(rs1));
2827                         gen_op_load_fpr_DT1(DFPREG(rs2));
2828                         gen_op_fcmped(rd & 3);
2829                         break;
2830                     case 0x57: /* fcmpeq, V9 %fcc */
2831 #if defined(CONFIG_USER_ONLY)
2832                         gen_op_load_fpr_QT0(QFPREG(rs1));
2833                         gen_op_load_fpr_QT1(QFPREG(rs2));
2834                         gen_op_fcmpeq(rd & 3);
2835                         break;
2836 #else/* !defined(CONFIG_USER_ONLY) */
2837                         goto nfpu_insn;
2838 #endif
2839                     default:
2840                         goto illegal_insn;
2841                 }
2842 #if defined(OPTIM)
2843             } else if (xop == 0x2) {
2844                 // clr/mov shortcut
2845
2846                 rs1 = GET_FIELD(insn, 13, 17);
2847                 if (rs1 == 0) {
2848                     // or %g0, x, y -> mov T0, x; mov y, T0
2849                     if (IS_IMM) {       /* immediate */
2850                         rs2 = GET_FIELDs(insn, 19, 31);
2851                         tcg_gen_movi_tl(cpu_T[0], (int)rs2);
2852                     } else {            /* register */
2853                         rs2 = GET_FIELD(insn, 27, 31);
2854                         gen_movl_reg_T0(rs2);
2855                     }
2856                 } else {
2857                     gen_movl_reg_T0(rs1);
2858                     if (IS_IMM) {       /* immediate */
2859                         rs2 = GET_FIELDs(insn, 19, 31);
2860                         tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2);
2861                     } else {            /* register */
2862                         // or x, %g0, y -> mov T1, x; mov y, T1
2863                         rs2 = GET_FIELD(insn, 27, 31);
2864                         if (rs2 != 0) {
2865                             gen_movl_reg_T1(rs2);
2866                             gen_op_or_T1_T0();
2867                         }
2868                     }
2869                 }
2870                 gen_movl_T0_reg(rd);
2871 #endif
2872 #ifdef TARGET_SPARC64
2873             } else if (xop == 0x25) { /* sll, V9 sllx */
2874                 rs1 = GET_FIELD(insn, 13, 17);
2875                 gen_movl_reg_T0(rs1);
2876                 if (IS_IMM) {   /* immediate */
2877                     rs2 = GET_FIELDs(insn, 20, 31);
2878                     if (insn & (1 << 12)) {
2879                         tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2880                     } else {
2881                         tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2882                         tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2883                     }
2884                 } else {                /* register */
2885                     rs2 = GET_FIELD(insn, 27, 31);
2886                     gen_movl_reg_T1(rs2);
2887                     if (insn & (1 << 12)) {
2888                         tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2889                         tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2890                     } else {
2891                         tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2892                         tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2893                         tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2894                     }
2895                 }
2896                 gen_movl_T0_reg(rd);
2897             } else if (xop == 0x26) { /* srl, V9 srlx */
2898                 rs1 = GET_FIELD(insn, 13, 17);
2899                 gen_movl_reg_T0(rs1);
2900                 if (IS_IMM) {   /* immediate */
2901                     rs2 = GET_FIELDs(insn, 20, 31);
2902                     if (insn & (1 << 12)) {
2903                         tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2904                     } else {
2905                         tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2906                         tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2907                     }
2908                 } else {                /* register */
2909                     rs2 = GET_FIELD(insn, 27, 31);
2910                     gen_movl_reg_T1(rs2);
2911                     if (insn & (1 << 12)) {
2912                         tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2913                         tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2914                     } else {
2915                         tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2916                         tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2917                         tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2918                     }
2919                 }
2920                 gen_movl_T0_reg(rd);
2921             } else if (xop == 0x27) { /* sra, V9 srax */
2922                 rs1 = GET_FIELD(insn, 13, 17);
2923                 gen_movl_reg_T0(rs1);
2924                 if (IS_IMM) {   /* immediate */
2925                     rs2 = GET_FIELDs(insn, 20, 31);
2926                     if (insn & (1 << 12)) {
2927                         tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2928                     } else {
2929                         tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2930                         tcg_gen_ext_i32_i64(cpu_T[0], cpu_T[0]);
2931                         tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2932                     }
2933                 } else {                /* register */
2934                     rs2 = GET_FIELD(insn, 27, 31);
2935                     gen_movl_reg_T1(rs2);
2936                     if (insn & (1 << 12)) {
2937                         tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2938                         tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2939                     } else {
2940                         tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2941                         tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2942                         tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2943                     }
2944                 }
2945                 gen_movl_T0_reg(rd);
2946 #endif
2947             } else if (xop < 0x36) {
2948                 rs1 = GET_FIELD(insn, 13, 17);
2949                 gen_movl_reg_T0(rs1);
2950                 if (IS_IMM) {   /* immediate */
2951                     rs2 = GET_FIELDs(insn, 19, 31);
2952                     gen_movl_simm_T1(rs2);
2953                 } else {                /* register */
2954                     rs2 = GET_FIELD(insn, 27, 31);
2955                     gen_movl_reg_T1(rs2);
2956                 }
2957                 if (xop < 0x20) {
2958                     switch (xop & ~0x10) {
2959                     case 0x0:
2960                         if (xop & 0x10)
2961                             gen_op_add_T1_T0_cc();
2962                         else
2963                             gen_op_add_T1_T0();
2964                         break;
2965                     case 0x1:
2966                         tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2967                         if (xop & 0x10)
2968                             gen_op_logic_T0_cc();
2969                         break;
2970                     case 0x2:
2971                         tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2972                         if (xop & 0x10)
2973                             gen_op_logic_T0_cc();
2974                         break;
2975                     case 0x3:
2976                         tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2977                         if (xop & 0x10)
2978                             gen_op_logic_T0_cc();
2979                         break;
2980                     case 0x4:
2981                         if (xop & 0x10)
2982                             gen_op_sub_T1_T0_cc();
2983                         else
2984                             tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2985                         break;
2986                     case 0x5:
2987                         tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
2988                         tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2989                         if (xop & 0x10)
2990                             gen_op_logic_T0_cc();
2991                         break;
2992                     case 0x6:
2993                         tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
2994                         tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2995                         if (xop & 0x10)
2996                             gen_op_logic_T0_cc();
2997                         break;
2998                     case 0x7:
2999                         tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3000                         tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3001                         if (xop & 0x10)
3002                             gen_op_logic_T0_cc();
3003                         break;
3004                     case 0x8:
3005                         if (xop & 0x10)
3006                             gen_op_addx_T1_T0_cc();
3007                         else {
3008                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3009                             tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
3010                             tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3011                         }
3012                         break;
3013 #ifdef TARGET_SPARC64
3014                     case 0x9: /* V9 mulx */
3015                         tcg_gen_mul_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
3016                         break;
3017 #endif
3018                     case 0xa:
3019                         gen_op_umul_T1_T0();
3020                         if (xop & 0x10)
3021                             gen_op_logic_T0_cc();
3022                         break;
3023                     case 0xb:
3024                         gen_op_smul_T1_T0();
3025                         if (xop & 0x10)
3026                             gen_op_logic_T0_cc();
3027                         break;
3028                     case 0xc:
3029                         if (xop & 0x10)
3030                             gen_op_subx_T1_T0_cc();
3031                         else {
3032                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3033                             tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
3034                             tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3035                         }
3036                         break;
3037 #ifdef TARGET_SPARC64
3038                     case 0xd: /* V9 udivx */
3039                         gen_op_udivx_T1_T0();
3040                         break;
3041 #endif
3042                     case 0xe:
3043                         gen_op_udiv_T1_T0();
3044                         if (xop & 0x10)
3045                             gen_op_div_cc();
3046                         break;
3047                     case 0xf:
3048                         gen_op_sdiv_T1_T0();
3049                         if (xop & 0x10)
3050                             gen_op_div_cc();
3051                         break;
3052                     default:
3053                         goto illegal_insn;
3054                     }
3055                     gen_movl_T0_reg(rd);
3056                 } else {
3057                     switch (xop) {
3058                     case 0x20: /* taddcc */
3059                         gen_op_tadd_T1_T0_cc();
3060                         gen_movl_T0_reg(rd);
3061                         break;
3062                     case 0x21: /* tsubcc */
3063                         gen_op_tsub_T1_T0_cc();
3064                         gen_movl_T0_reg(rd);
3065                         break;
3066                     case 0x22: /* taddcctv */
3067                         save_state(dc);
3068                         gen_op_tadd_T1_T0_ccTV();
3069                         gen_movl_T0_reg(rd);
3070                         break;
3071                     case 0x23: /* tsubcctv */
3072                         save_state(dc);
3073                         gen_op_tsub_T1_T0_ccTV();
3074                         gen_movl_T0_reg(rd);
3075                         break;
3076                     case 0x24: /* mulscc */
3077                         gen_op_mulscc_T1_T0();
3078                         gen_movl_T0_reg(rd);
3079                         break;
3080 #ifndef TARGET_SPARC64
3081                     case 0x25:  /* sll */
3082                         tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3083                         tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
3084                         gen_movl_T0_reg(rd);
3085                         break;
3086                     case 0x26:  /* srl */
3087                         tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3088                         tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
3089                         gen_movl_T0_reg(rd);
3090                         break;
3091                     case 0x27:  /* sra */
3092                         tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3093                         tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
3094                         gen_movl_T0_reg(rd);
3095                         break;
3096 #endif
3097                     case 0x30:
3098                         {
3099                             switch(rd) {
3100                             case 0: /* wry */
3101                                 gen_op_xor_T1_T0();
3102                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
3103                                 break;
3104 #ifndef TARGET_SPARC64
3105                             case 0x01 ... 0x0f: /* undefined in the
3106                                                    SPARCv8 manual, nop
3107                                                    on the microSPARC
3108                                                    II */
3109                             case 0x10 ... 0x1f: /* implementation-dependent
3110                                                    in the SPARCv8
3111                                                    manual, nop on the
3112                                                    microSPARC II */
3113                                 break;
3114 #else
3115                             case 0x2: /* V9 wrccr */
3116                                 gen_op_xor_T1_T0();
3117                                 gen_op_wrccr();
3118                                 break;
3119                             case 0x3: /* V9 wrasi */
3120                                 gen_op_xor_T1_T0();
3121                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
3122                                 break;
3123                             case 0x6: /* V9 wrfprs */
3124                                 gen_op_xor_T1_T0();
3125                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
3126                                 save_state(dc);
3127                                 gen_op_next_insn();
3128                                 tcg_gen_exit_tb(0);
3129                                 dc->is_br = 1;
3130                                 break;
3131                             case 0xf: /* V9 sir, nop if user */
3132 #if !defined(CONFIG_USER_ONLY)
3133                                 if (supervisor(dc))
3134                                     ; // XXX
3135 #endif
3136                                 break;
3137                             case 0x13: /* Graphics Status */
3138                                 if (gen_trap_ifnofpu(dc))
3139                                     goto jmp_insn;
3140                                 gen_op_xor_T1_T0();
3141                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
3142                                 break;
3143                             case 0x17: /* Tick compare */
3144 #if !defined(CONFIG_USER_ONLY)
3145                                 if (!supervisor(dc))
3146                                     goto illegal_insn;
3147 #endif
3148                                 {
3149                                     TCGv r_tickptr;
3150
3151                                     gen_op_xor_T1_T0();
3152                                     gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3153                                                                  tick_cmpr));
3154                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3155                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3156                                                    offsetof(CPUState, tick));
3157                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3158                                                        r_tickptr, cpu_T[0]);
3159                                 }
3160                                 break;
3161                             case 0x18: /* System tick */
3162 #if !defined(CONFIG_USER_ONLY)
3163                                 if (!supervisor(dc))
3164                                     goto illegal_insn;
3165 #endif
3166                                 {
3167                                     TCGv r_tickptr;
3168
3169                                     gen_op_xor_T1_T0();
3170                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3171                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3172                                                    offsetof(CPUState, stick));
3173                                     tcg_gen_helper_0_2(helper_tick_set_count,
3174                                                        r_tickptr, cpu_T[0]);
3175                                 }
3176                                 break;
3177                             case 0x19: /* System tick compare */
3178 #if !defined(CONFIG_USER_ONLY)
3179                                 if (!supervisor(dc))
3180                                     goto illegal_insn;
3181 #endif
3182                                 {
3183                                     TCGv r_tickptr;
3184
3185                                     gen_op_xor_T1_T0();
3186                                     gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3187                                                                  stick_cmpr));
3188                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3189                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3190                                                    offsetof(CPUState, stick));
3191                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3192                                                        r_tickptr, cpu_T[0]);
3193                                 }
3194                                 break;
3195
3196                             case 0x10: /* Performance Control */
3197                             case 0x11: /* Performance Instrumentation Counter */
3198                             case 0x12: /* Dispatch Control */
3199                             case 0x14: /* Softint set */
3200                             case 0x15: /* Softint clear */
3201                             case 0x16: /* Softint write */
3202 #endif
3203                             default:
3204                                 goto illegal_insn;
3205                             }
3206                         }
3207                         break;
3208 #if !defined(CONFIG_USER_ONLY)
3209                     case 0x31: /* wrpsr, V9 saved, restored */
3210                         {
3211                             if (!supervisor(dc))
3212                                 goto priv_insn;
3213 #ifdef TARGET_SPARC64
3214                             switch (rd) {
3215                             case 0:
3216                                 gen_op_saved();
3217                                 break;
3218                             case 1:
3219                                 gen_op_restored();
3220                                 break;
3221                             case 2: /* UA2005 allclean */
3222                             case 3: /* UA2005 otherw */
3223                             case 4: /* UA2005 normalw */
3224                             case 5: /* UA2005 invalw */
3225                                 // XXX
3226                             default:
3227                                 goto illegal_insn;
3228                             }
3229 #else
3230                             gen_op_xor_T1_T0();
3231                             tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
3232                             save_state(dc);
3233                             gen_op_next_insn();
3234                             tcg_gen_exit_tb(0);
3235                             dc->is_br = 1;
3236 #endif
3237                         }
3238                         break;
3239                     case 0x32: /* wrwim, V9 wrpr */
3240                         {
3241                             if (!supervisor(dc))
3242                                 goto priv_insn;
3243                             gen_op_xor_T1_T0();
3244 #ifdef TARGET_SPARC64
3245                             switch (rd) {
3246                             case 0: // tpc
3247                                 {
3248                                     TCGv r_tsptr;
3249
3250                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3251                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3252                                                    offsetof(CPUState, tsptr));
3253                                     tcg_gen_st_tl(cpu_T[0], r_tsptr,
3254                                                   offsetof(trap_state, tpc));
3255                                 }
3256                                 break;
3257                             case 1: // tnpc
3258                                 {
3259                                     TCGv r_tsptr;
3260
3261                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3262                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3263                                                    offsetof(CPUState, tsptr));
3264                                     tcg_gen_st_tl(cpu_T[0], r_tsptr,
3265                                                   offsetof(trap_state, tnpc));
3266                                 }
3267                                 break;
3268                             case 2: // tstate
3269                                 {
3270                                     TCGv r_tsptr;
3271
3272                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3273                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3274                                                    offsetof(CPUState, tsptr));
3275                                     tcg_gen_st_tl(cpu_T[0], r_tsptr,
3276                                                   offsetof(trap_state, tstate));
3277                                 }
3278                                 break;
3279                             case 3: // tt
3280                                 {
3281                                     TCGv r_tsptr;
3282
3283                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3284                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3285                                                    offsetof(CPUState, tsptr));
3286                                     tcg_gen_st_i32(cpu_T[0], r_tsptr,
3287                                                    offsetof(trap_state, tt));
3288                                 }
3289                                 break;
3290                             case 4: // tick
3291                                 {
3292                                     TCGv r_tickptr;
3293
3294                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3295                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3296                                                    offsetof(CPUState, tick));
3297                                     tcg_gen_helper_0_2(helper_tick_set_count,
3298                                                        r_tickptr, cpu_T[0]);
3299                                 }
3300                                 break;
3301                             case 5: // tba
3302                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3303                                 break;
3304                             case 6: // pstate
3305                                 save_state(dc);
3306                                 tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]);
3307                                 gen_op_next_insn();
3308                                 tcg_gen_exit_tb(0);
3309                                 dc->is_br = 1;
3310                                 break;
3311                             case 7: // tl
3312                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
3313                                 break;
3314                             case 8: // pil
3315                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
3316                                 break;
3317                             case 9: // cwp
3318                                 gen_op_wrcwp();
3319                                 break;
3320                             case 10: // cansave
3321                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
3322                                 break;
3323                             case 11: // canrestore
3324                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
3325                                 break;
3326                             case 12: // cleanwin
3327                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
3328                                 break;
3329                             case 13: // otherwin
3330                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
3331                                 break;
3332                             case 14: // wstate
3333                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
3334                                 break;
3335                             case 16: // UA2005 gl
3336                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
3337                                 break;
3338                             case 26: // UA2005 strand status
3339                                 if (!hypervisor(dc))
3340                                     goto priv_insn;
3341                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
3342                                 break;
3343                             default:
3344                                 goto illegal_insn;
3345                             }
3346 #else
3347                             tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
3348                             gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
3349 #endif
3350                         }
3351                         break;
3352                     case 0x33: /* wrtbr, UA2005 wrhpr */
3353                         {
3354 #ifndef TARGET_SPARC64
3355                             if (!supervisor(dc))
3356                                 goto priv_insn;
3357                             gen_op_xor_T1_T0();
3358                             gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3359 #else
3360                             if (!hypervisor(dc))
3361                                 goto priv_insn;
3362                             gen_op_xor_T1_T0();
3363                             switch (rd) {
3364                             case 0: // hpstate
3365                                 // XXX gen_op_wrhpstate();
3366                                 save_state(dc);
3367                                 gen_op_next_insn();
3368                                 tcg_gen_exit_tb(0);
3369                                 dc->is_br = 1;
3370                                 break;
3371                             case 1: // htstate
3372                                 // XXX gen_op_wrhtstate();
3373                                 break;
3374                             case 3: // hintp
3375                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
3376                                 break;
3377                             case 5: // htba
3378                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
3379                                 break;
3380                             case 31: // hstick_cmpr
3381                                 {
3382                                     TCGv r_tickptr;
3383
3384                                     gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3385                                                                  hstick_cmpr));
3386                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3387                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3388                                                    offsetof(CPUState, hstick));
3389                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3390                                                        r_tickptr, cpu_T[0]);
3391                                 }
3392                                 break;
3393                             case 6: // hver readonly
3394                             default:
3395                                 goto illegal_insn;
3396                             }
3397 #endif
3398                         }
3399                         break;
3400 #endif
3401 #ifdef TARGET_SPARC64
3402                     case 0x2c: /* V9 movcc */
3403                         {
3404                             int cc = GET_FIELD_SP(insn, 11, 12);
3405                             int cond = GET_FIELD_SP(insn, 14, 17);
3406                             TCGv r_zero;
3407                             int l1;
3408
3409                             flush_T2(dc);
3410                             if (insn & (1 << 18)) {
3411                                 if (cc == 0)
3412                                     gen_cond(cpu_T[2], 0, cond);
3413                                 else if (cc == 2)
3414                                     gen_cond(cpu_T[2], 1, cond);
3415                                 else
3416                                     goto illegal_insn;
3417                             } else {
3418                                 gen_fcond(cpu_T[2], cc, cond);
3419                             }
3420
3421                             l1 = gen_new_label();
3422
3423                             r_zero = tcg_const_tl(0);
3424                             tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[2], r_zero, l1);
3425                             if (IS_IMM) {       /* immediate */
3426                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
3427                                 gen_movl_simm_T1(rs2);
3428                             } else {
3429                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3430                                 gen_movl_reg_T1(rs2);
3431                             }
3432                             gen_movl_T1_reg(rd);
3433                             gen_set_label(l1);
3434                             break;
3435                         }
3436                     case 0x2d: /* V9 sdivx */
3437                         gen_op_sdivx_T1_T0();
3438                         gen_movl_T0_reg(rd);
3439                         break;
3440                     case 0x2e: /* V9 popc */
3441                         {
3442                             if (IS_IMM) {       /* immediate */
3443                                 rs2 = GET_FIELD_SPs(insn, 0, 12);
3444                                 gen_movl_simm_T1(rs2);
3445                                 // XXX optimize: popc(constant)
3446                             }
3447                             else {
3448                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3449                                 gen_movl_reg_T1(rs2);
3450                             }
3451                             tcg_gen_helper_1_1(helper_popc, cpu_T[0],
3452                                                cpu_T[1]);
3453                             gen_movl_T0_reg(rd);
3454                         }
3455                     case 0x2f: /* V9 movr */
3456                         {
3457                             int cond = GET_FIELD_SP(insn, 10, 12);
3458                             TCGv r_zero;
3459                             int l1;
3460
3461                             rs1 = GET_FIELD(insn, 13, 17);
3462                             gen_movl_reg_T0(rs1);
3463
3464                             l1 = gen_new_label();
3465
3466                             r_zero = tcg_const_tl(0);
3467                             tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
3468                             if (IS_IMM) {       /* immediate */
3469                                 rs2 = GET_FIELD_SPs(insn, 0, 9);
3470                                 gen_movl_simm_T1(rs2);
3471                             } else {
3472                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3473                                 gen_movl_reg_T1(rs2);
3474                             }
3475                             gen_movl_T1_reg(rd);
3476                             gen_set_label(l1);
3477                             break;
3478                         }
3479 #endif
3480                     default:
3481                         goto illegal_insn;
3482                     }
3483                 }
3484             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3485 #ifdef TARGET_SPARC64
3486                 int opf = GET_FIELD_SP(insn, 5, 13);
3487                 rs1 = GET_FIELD(insn, 13, 17);
3488                 rs2 = GET_FIELD(insn, 27, 31);
3489                 if (gen_trap_ifnofpu(dc))
3490                     goto jmp_insn;
3491
3492                 switch (opf) {
3493                 case 0x000: /* VIS I edge8cc */
3494                 case 0x001: /* VIS II edge8n */
3495                 case 0x002: /* VIS I edge8lcc */
3496                 case 0x003: /* VIS II edge8ln */
3497                 case 0x004: /* VIS I edge16cc */
3498                 case 0x005: /* VIS II edge16n */
3499                 case 0x006: /* VIS I edge16lcc */
3500                 case 0x007: /* VIS II edge16ln */
3501                 case 0x008: /* VIS I edge32cc */
3502                 case 0x009: /* VIS II edge32n */
3503                 case 0x00a: /* VIS I edge32lcc */
3504                 case 0x00b: /* VIS II edge32ln */
3505                     // XXX
3506                     goto illegal_insn;
3507                 case 0x010: /* VIS I array8 */
3508                     gen_movl_reg_T0(rs1);
3509                     gen_movl_reg_T1(rs2);
3510                     gen_op_array8();
3511                     gen_movl_T0_reg(rd);
3512                     break;
3513                 case 0x012: /* VIS I array16 */
3514                     gen_movl_reg_T0(rs1);
3515                     gen_movl_reg_T1(rs2);
3516                     gen_op_array16();
3517                     gen_movl_T0_reg(rd);
3518                     break;
3519                 case 0x014: /* VIS I array32 */
3520                     gen_movl_reg_T0(rs1);
3521                     gen_movl_reg_T1(rs2);
3522                     gen_op_array32();
3523                     gen_movl_T0_reg(rd);
3524                     break;
3525                 case 0x018: /* VIS I alignaddr */
3526                     gen_movl_reg_T0(rs1);
3527                     gen_movl_reg_T1(rs2);
3528                     gen_op_alignaddr();
3529                     gen_movl_T0_reg(rd);
3530                     break;
3531                 case 0x019: /* VIS II bmask */
3532                 case 0x01a: /* VIS I alignaddrl */
3533                     // XXX
3534                     goto illegal_insn;
3535                 case 0x020: /* VIS I fcmple16 */
3536                     gen_op_load_fpr_DT0(DFPREG(rs1));
3537                     gen_op_load_fpr_DT1(DFPREG(rs2));
3538                     gen_op_fcmple16();
3539                     gen_op_store_DT0_fpr(DFPREG(rd));
3540                     break;
3541                 case 0x022: /* VIS I fcmpne16 */
3542                     gen_op_load_fpr_DT0(DFPREG(rs1));
3543                     gen_op_load_fpr_DT1(DFPREG(rs2));
3544                     gen_op_fcmpne16();
3545                     gen_op_store_DT0_fpr(DFPREG(rd));
3546                     break;
3547                 case 0x024: /* VIS I fcmple32 */
3548                     gen_op_load_fpr_DT0(DFPREG(rs1));
3549                     gen_op_load_fpr_DT1(DFPREG(rs2));
3550                     gen_op_fcmple32();
3551                     gen_op_store_DT0_fpr(DFPREG(rd));
3552                     break;
3553                 case 0x026: /* VIS I fcmpne32 */
3554                     gen_op_load_fpr_DT0(DFPREG(rs1));
3555                     gen_op_load_fpr_DT1(DFPREG(rs2));
3556                     gen_op_fcmpne32();
3557                     gen_op_store_DT0_fpr(DFPREG(rd));
3558                     break;
3559                 case 0x028: /* VIS I fcmpgt16 */
3560                     gen_op_load_fpr_DT0(DFPREG(rs1));
3561                     gen_op_load_fpr_DT1(DFPREG(rs2));
3562                     gen_op_fcmpgt16();
3563                     gen_op_store_DT0_fpr(DFPREG(rd));
3564                     break;
3565                 case 0x02a: /* VIS I fcmpeq16 */
3566                     gen_op_load_fpr_DT0(DFPREG(rs1));
3567                     gen_op_load_fpr_DT1(DFPREG(rs2));
3568                     gen_op_fcmpeq16();
3569                     gen_op_store_DT0_fpr(DFPREG(rd));
3570                     break;
3571                 case 0x02c: /* VIS I fcmpgt32 */
3572                     gen_op_load_fpr_DT0(DFPREG(rs1));
3573                     gen_op_load_fpr_DT1(DFPREG(rs2));
3574                     gen_op_fcmpgt32();
3575                     gen_op_store_DT0_fpr(DFPREG(rd));
3576                     break;
3577                 case 0x02e: /* VIS I fcmpeq32 */
3578                     gen_op_load_fpr_DT0(DFPREG(rs1));
3579                     gen_op_load_fpr_DT1(DFPREG(rs2));
3580                     gen_op_fcmpeq32();
3581                     gen_op_store_DT0_fpr(DFPREG(rd));
3582                     break;
3583                 case 0x031: /* VIS I fmul8x16 */
3584                     gen_op_load_fpr_DT0(DFPREG(rs1));
3585                     gen_op_load_fpr_DT1(DFPREG(rs2));
3586                     gen_op_fmul8x16();
3587                     gen_op_store_DT0_fpr(DFPREG(rd));
3588                     break;
3589                 case 0x033: /* VIS I fmul8x16au */
3590                     gen_op_load_fpr_DT0(DFPREG(rs1));
3591                     gen_op_load_fpr_DT1(DFPREG(rs2));
3592                     gen_op_fmul8x16au();
3593                     gen_op_store_DT0_fpr(DFPREG(rd));
3594                     break;
3595                 case 0x035: /* VIS I fmul8x16al */
3596                     gen_op_load_fpr_DT0(DFPREG(rs1));
3597                     gen_op_load_fpr_DT1(DFPREG(rs2));
3598                     gen_op_fmul8x16al();
3599                     gen_op_store_DT0_fpr(DFPREG(rd));
3600                     break;
3601                 case 0x036: /* VIS I fmul8sux16 */
3602                     gen_op_load_fpr_DT0(DFPREG(rs1));
3603                     gen_op_load_fpr_DT1(DFPREG(rs2));
3604                     gen_op_fmul8sux16();
3605                     gen_op_store_DT0_fpr(DFPREG(rd));
3606                     break;
3607                 case 0x037: /* VIS I fmul8ulx16 */
3608                     gen_op_load_fpr_DT0(DFPREG(rs1));
3609                     gen_op_load_fpr_DT1(DFPREG(rs2));
3610                     gen_op_fmul8ulx16();
3611                     gen_op_store_DT0_fpr(DFPREG(rd));
3612                     break;
3613                 case 0x038: /* VIS I fmuld8sux16 */
3614                     gen_op_load_fpr_DT0(DFPREG(rs1));
3615                     gen_op_load_fpr_DT1(DFPREG(rs2));
3616                     gen_op_fmuld8sux16();
3617                     gen_op_store_DT0_fpr(DFPREG(rd));
3618                     break;
3619                 case 0x039: /* VIS I fmuld8ulx16 */
3620                     gen_op_load_fpr_DT0(DFPREG(rs1));
3621                     gen_op_load_fpr_DT1(DFPREG(rs2));
3622                     gen_op_fmuld8ulx16();
3623                     gen_op_store_DT0_fpr(DFPREG(rd));
3624                     break;
3625                 case 0x03a: /* VIS I fpack32 */
3626                 case 0x03b: /* VIS I fpack16 */
3627                 case 0x03d: /* VIS I fpackfix */
3628                 case 0x03e: /* VIS I pdist */
3629                     // XXX
3630                     goto illegal_insn;
3631                 case 0x048: /* VIS I faligndata */
3632                     gen_op_load_fpr_DT0(DFPREG(rs1));
3633                     gen_op_load_fpr_DT1(DFPREG(rs2));
3634                     gen_op_faligndata();
3635                     gen_op_store_DT0_fpr(DFPREG(rd));
3636                     break;
3637                 case 0x04b: /* VIS I fpmerge */
3638                     gen_op_load_fpr_DT0(DFPREG(rs1));
3639                     gen_op_load_fpr_DT1(DFPREG(rs2));
3640                     gen_op_fpmerge();
3641                     gen_op_store_DT0_fpr(DFPREG(rd));
3642                     break;
3643                 case 0x04c: /* VIS II bshuffle */
3644                     // XXX
3645                     goto illegal_insn;
3646                 case 0x04d: /* VIS I fexpand */
3647                     gen_op_load_fpr_DT0(DFPREG(rs1));
3648                     gen_op_load_fpr_DT1(DFPREG(rs2));
3649                     gen_op_fexpand();
3650                     gen_op_store_DT0_fpr(DFPREG(rd));
3651                     break;
3652                 case 0x050: /* VIS I fpadd16 */
3653                     gen_op_load_fpr_DT0(DFPREG(rs1));
3654                     gen_op_load_fpr_DT1(DFPREG(rs2));
3655                     gen_op_fpadd16();
3656                     gen_op_store_DT0_fpr(DFPREG(rd));
3657                     break;
3658                 case 0x051: /* VIS I fpadd16s */
3659                     gen_op_load_fpr_FT0(rs1);
3660                     gen_op_load_fpr_FT1(rs2);
3661                     gen_op_fpadd16s();
3662                     gen_op_store_FT0_fpr(rd);
3663                     break;
3664                 case 0x052: /* VIS I fpadd32 */
3665                     gen_op_load_fpr_DT0(DFPREG(rs1));
3666                     gen_op_load_fpr_DT1(DFPREG(rs2));
3667                     gen_op_fpadd32();
3668                     gen_op_store_DT0_fpr(DFPREG(rd));
3669                     break;
3670                 case 0x053: /* VIS I fpadd32s */
3671                     gen_op_load_fpr_FT0(rs1);
3672                     gen_op_load_fpr_FT1(rs2);
3673                     gen_op_fpadd32s();
3674                     gen_op_store_FT0_fpr(rd);
3675                     break;
3676                 case 0x054: /* VIS I fpsub16 */
3677                     gen_op_load_fpr_DT0(DFPREG(rs1));
3678                     gen_op_load_fpr_DT1(DFPREG(rs2));
3679                     gen_op_fpsub16();
3680                     gen_op_store_DT0_fpr(DFPREG(rd));
3681                     break;
3682                 case 0x055: /* VIS I fpsub16s */
3683                     gen_op_load_fpr_FT0(rs1);
3684                     gen_op_load_fpr_FT1(rs2);
3685                     gen_op_fpsub16s();
3686                     gen_op_store_FT0_fpr(rd);
3687                     break;
3688                 case 0x056: /* VIS I fpsub32 */
3689                     gen_op_load_fpr_DT0(DFPREG(rs1));
3690                     gen_op_load_fpr_DT1(DFPREG(rs2));
3691                     gen_op_fpadd32();
3692                     gen_op_store_DT0_fpr(DFPREG(rd));
3693                     break;
3694                 case 0x057: /* VIS I fpsub32s */
3695                     gen_op_load_fpr_FT0(rs1);
3696                     gen_op_load_fpr_FT1(rs2);
3697                     gen_op_fpsub32s();
3698                     gen_op_store_FT0_fpr(rd);
3699                     break;
3700                 case 0x060: /* VIS I fzero */
3701                     gen_op_movl_DT0_0();
3702                     gen_op_store_DT0_fpr(DFPREG(rd));
3703                     break;
3704                 case 0x061: /* VIS I fzeros */
3705                     gen_op_movl_FT0_0();
3706                     gen_op_store_FT0_fpr(rd);
3707                     break;
3708                 case 0x062: /* VIS I fnor */
3709                     gen_op_load_fpr_DT0(DFPREG(rs1));
3710                     gen_op_load_fpr_DT1(DFPREG(rs2));
3711                     gen_op_fnor();
3712                     gen_op_store_DT0_fpr(DFPREG(rd));
3713                     break;
3714                 case 0x063: /* VIS I fnors */
3715                     gen_op_load_fpr_FT0(rs1);
3716                     gen_op_load_fpr_FT1(rs2);
3717                     gen_op_fnors();
3718                     gen_op_store_FT0_fpr(rd);
3719                     break;
3720                 case 0x064: /* VIS I fandnot2 */
3721                     gen_op_load_fpr_DT1(DFPREG(rs1));
3722                     gen_op_load_fpr_DT0(DFPREG(rs2));
3723                     gen_op_fandnot();
3724                     gen_op_store_DT0_fpr(DFPREG(rd));
3725                     break;
3726                 case 0x065: /* VIS I fandnot2s */
3727                     gen_op_load_fpr_FT1(rs1);
3728                     gen_op_load_fpr_FT0(rs2);
3729                     gen_op_fandnots();
3730                     gen_op_store_FT0_fpr(rd);
3731                     break;
3732                 case 0x066: /* VIS I fnot2 */
3733                     gen_op_load_fpr_DT1(DFPREG(rs2));
3734                     gen_op_fnot();
3735                     gen_op_store_DT0_fpr(DFPREG(rd));
3736                     break;
3737                 case 0x067: /* VIS I fnot2s */
3738                     gen_op_load_fpr_FT1(rs2);
3739                     gen_op_fnot();
3740                     gen_op_store_FT0_fpr(rd);
3741                     break;
3742                 case 0x068: /* VIS I fandnot1 */
3743                     gen_op_load_fpr_DT0(DFPREG(rs1));
3744                     gen_op_load_fpr_DT1(DFPREG(rs2));
3745                     gen_op_fandnot();
3746                     gen_op_store_DT0_fpr(DFPREG(rd));
3747                     break;
3748                 case 0x069: /* VIS I fandnot1s */
3749                     gen_op_load_fpr_FT0(rs1);
3750                     gen_op_load_fpr_FT1(rs2);
3751                     gen_op_fandnots();
3752                     gen_op_store_FT0_fpr(rd);
3753                     break;
3754                 case 0x06a: /* VIS I fnot1 */
3755                     gen_op_load_fpr_DT1(DFPREG(rs1));
3756                     gen_op_fnot();
3757                     gen_op_store_DT0_fpr(DFPREG(rd));
3758                     break;
3759                 case 0x06b: /* VIS I fnot1s */
3760                     gen_op_load_fpr_FT1(rs1);
3761                     gen_op_fnot();
3762                     gen_op_store_FT0_fpr(rd);
3763                     break;
3764                 case 0x06c: /* VIS I fxor */
3765                     gen_op_load_fpr_DT0(DFPREG(rs1));
3766                     gen_op_load_fpr_DT1(DFPREG(rs2));
3767                     gen_op_fxor();
3768                     gen_op_store_DT0_fpr(DFPREG(rd));
3769                     break;
3770                 case 0x06d: /* VIS I fxors */
3771                     gen_op_load_fpr_FT0(rs1);
3772                     gen_op_load_fpr_FT1(rs2);
3773                     gen_op_fxors();
3774                     gen_op_store_FT0_fpr(rd);
3775                     break;
3776                 case 0x06e: /* VIS I fnand */
3777                     gen_op_load_fpr_DT0(DFPREG(rs1));
3778                     gen_op_load_fpr_DT1(DFPREG(rs2));
3779                     gen_op_fnand();
3780                     gen_op_store_DT0_fpr(DFPREG(rd));
3781                     break;
3782                 case 0x06f: /* VIS I fnands */
3783                     gen_op_load_fpr_FT0(rs1);
3784                     gen_op_load_fpr_FT1(rs2);
3785                     gen_op_fnands();
3786                     gen_op_store_FT0_fpr(rd);
3787                     break;
3788                 case 0x070: /* VIS I fand */
3789                     gen_op_load_fpr_DT0(DFPREG(rs1));
3790                     gen_op_load_fpr_DT1(DFPREG(rs2));
3791                     gen_op_fand();
3792                     gen_op_store_DT0_fpr(DFPREG(rd));
3793                     break;
3794                 case 0x071: /* VIS I fands */
3795                     gen_op_load_fpr_FT0(rs1);
3796                     gen_op_load_fpr_FT1(rs2);
3797                     gen_op_fands();
3798                     gen_op_store_FT0_fpr(rd);
3799                     break;
3800                 case 0x072: /* VIS I fxnor */
3801                     gen_op_load_fpr_DT0(DFPREG(rs1));
3802                     gen_op_load_fpr_DT1(DFPREG(rs2));
3803                     gen_op_fxnor();
3804                     gen_op_store_DT0_fpr(DFPREG(rd));
3805                     break;
3806                 case 0x073: /* VIS I fxnors */
3807                     gen_op_load_fpr_FT0(rs1);
3808                     gen_op_load_fpr_FT1(rs2);
3809                     gen_op_fxnors();
3810                     gen_op_store_FT0_fpr(rd);
3811                     break;
3812                 case 0x074: /* VIS I fsrc1 */
3813                     gen_op_load_fpr_DT0(DFPREG(rs1));
3814                     gen_op_store_DT0_fpr(DFPREG(rd));
3815                     break;
3816                 case 0x075: /* VIS I fsrc1s */
3817                     gen_op_load_fpr_FT0(rs1);
3818                     gen_op_store_FT0_fpr(rd);
3819                     break;
3820                 case 0x076: /* VIS I fornot2 */
3821                     gen_op_load_fpr_DT1(DFPREG(rs1));
3822                     gen_op_load_fpr_DT0(DFPREG(rs2));
3823                     gen_op_fornot();
3824                     gen_op_store_DT0_fpr(DFPREG(rd));
3825                     break;
3826                 case 0x077: /* VIS I fornot2s */
3827                     gen_op_load_fpr_FT1(rs1);
3828                     gen_op_load_fpr_FT0(rs2);
3829                     gen_op_fornots();
3830                     gen_op_store_FT0_fpr(rd);
3831                     break;
3832                 case 0x078: /* VIS I fsrc2 */
3833                     gen_op_load_fpr_DT0(DFPREG(rs2));
3834                     gen_op_store_DT0_fpr(DFPREG(rd));
3835                     break;
3836                 case 0x079: /* VIS I fsrc2s */
3837                     gen_op_load_fpr_FT0(rs2);
3838                     gen_op_store_FT0_fpr(rd);
3839                     break;
3840                 case 0x07a: /* VIS I fornot1 */
3841                     gen_op_load_fpr_DT0(DFPREG(rs1));
3842                     gen_op_load_fpr_DT1(DFPREG(rs2));
3843                     gen_op_fornot();
3844                     gen_op_store_DT0_fpr(DFPREG(rd));
3845                     break;
3846                 case 0x07b: /* VIS I fornot1s */
3847                     gen_op_load_fpr_FT0(rs1);
3848                     gen_op_load_fpr_FT1(rs2);
3849                     gen_op_fornots();
3850                     gen_op_store_FT0_fpr(rd);
3851                     break;
3852                 case 0x07c: /* VIS I for */
3853                     gen_op_load_fpr_DT0(DFPREG(rs1));
3854                     gen_op_load_fpr_DT1(DFPREG(rs2));
3855                     gen_op_for();
3856                     gen_op_store_DT0_fpr(DFPREG(rd));
3857                     break;
3858                 case 0x07d: /* VIS I fors */
3859                     gen_op_load_fpr_FT0(rs1);
3860                     gen_op_load_fpr_FT1(rs2);
3861                     gen_op_fors();
3862                     gen_op_store_FT0_fpr(rd);
3863                     break;
3864                 case 0x07e: /* VIS I fone */
3865                     gen_op_movl_DT0_1();
3866                     gen_op_store_DT0_fpr(DFPREG(rd));
3867                     break;
3868                 case 0x07f: /* VIS I fones */
3869                     gen_op_movl_FT0_1();
3870                     gen_op_store_FT0_fpr(rd);
3871                     break;
3872                 case 0x080: /* VIS I shutdown */
3873                 case 0x081: /* VIS II siam */
3874                     // XXX
3875                     goto illegal_insn;
3876                 default:
3877                     goto illegal_insn;
3878                 }
3879 #else
3880                 goto ncp_insn;
3881 #endif
3882             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
3883 #ifdef TARGET_SPARC64
3884                 goto illegal_insn;
3885 #else
3886                 goto ncp_insn;
3887 #endif
3888 #ifdef TARGET_SPARC64
3889             } else if (xop == 0x39) { /* V9 return */
3890                 rs1 = GET_FIELD(insn, 13, 17);
3891                 save_state(dc);
3892                 gen_movl_reg_T0(rs1);
3893                 if (IS_IMM) {   /* immediate */
3894                     rs2 = GET_FIELDs(insn, 19, 31);
3895                     tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
3896                 } else {                /* register */
3897                     rs2 = GET_FIELD(insn, 27, 31);
3898 #if defined(OPTIM)
3899                     if (rs2) {
3900 #endif
3901                         gen_movl_reg_T1(rs2);
3902                         gen_op_add_T1_T0();
3903 #if defined(OPTIM)
3904                     }
3905 #endif
3906                 }
3907                 gen_op_restore();
3908                 gen_mov_pc_npc(dc);
3909                 gen_op_check_align_T0_3();
3910                 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
3911                 dc->npc = DYNAMIC_PC;
3912                 goto jmp_insn;
3913 #endif
3914             } else {
3915                 rs1 = GET_FIELD(insn, 13, 17);
3916                 gen_movl_reg_T0(rs1);
3917                 if (IS_IMM) {   /* immediate */
3918                     rs2 = GET_FIELDs(insn, 19, 31);
3919                     tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
3920                 } else {                /* register */
3921                     rs2 = GET_FIELD(insn, 27, 31);
3922 #if defined(OPTIM)
3923                     if (rs2) {
3924 #endif
3925                         gen_movl_reg_T1(rs2);
3926                         gen_op_add_T1_T0();
3927 #if defined(OPTIM)
3928                     }
3929 #endif
3930                 }
3931                 switch (xop) {
3932                 case 0x38:      /* jmpl */
3933                     {
3934                         if (rd != 0) {
3935                             tcg_gen_movi_tl(cpu_T[1], dc->pc);
3936                             gen_movl_T1_reg(rd);
3937                         }
3938                         gen_mov_pc_npc(dc);
3939                         gen_op_check_align_T0_3();
3940                         tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
3941                         dc->npc = DYNAMIC_PC;
3942                     }
3943                     goto jmp_insn;
3944 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3945                 case 0x39:      /* rett, V9 return */
3946                     {
3947                         if (!supervisor(dc))
3948                             goto priv_insn;
3949                         gen_mov_pc_npc(dc);
3950                         gen_op_check_align_T0_3();
3951                         tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
3952                         dc->npc = DYNAMIC_PC;
3953                         tcg_gen_helper_0_0(helper_rett);
3954                     }
3955                     goto jmp_insn;
3956 #endif
3957                 case 0x3b: /* flush */
3958                     tcg_gen_helper_0_1(helper_flush, cpu_T[0]);
3959                     break;
3960                 case 0x3c:      /* save */
3961                     save_state(dc);
3962                     gen_op_save();
3963                     gen_movl_T0_reg(rd);
3964                     break;
3965                 case 0x3d:      /* restore */
3966                     save_state(dc);
3967                     gen_op_restore();
3968                     gen_movl_T0_reg(rd);
3969                     break;
3970 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
3971                 case 0x3e:      /* V9 done/retry */
3972                     {
3973                         switch (rd) {
3974                         case 0:
3975                             if (!supervisor(dc))
3976                                 goto priv_insn;
3977                             dc->npc = DYNAMIC_PC;
3978                             dc->pc = DYNAMIC_PC;
3979                             tcg_gen_helper_0_0(helper_done);
3980                             goto jmp_insn;
3981                         case 1:
3982                             if (!supervisor(dc))
3983                                 goto priv_insn;
3984                             dc->npc = DYNAMIC_PC;
3985                             dc->pc = DYNAMIC_PC;
3986                             tcg_gen_helper_0_0(helper_retry);
3987                             goto jmp_insn;
3988                         default:
3989                             goto illegal_insn;
3990                         }
3991                     }
3992                     break;
3993 #endif
3994                 default:
3995                     goto illegal_insn;
3996                 }
3997             }
3998             break;
3999         }
4000         break;
4001     case 3:                     /* load/store instructions */
4002         {
4003             unsigned int xop = GET_FIELD(insn, 7, 12);
4004             rs1 = GET_FIELD(insn, 13, 17);
4005             save_state(dc);
4006             gen_movl_reg_T0(rs1);
4007             if (xop == 0x3c || xop == 0x3e)
4008             {
4009                 rs2 = GET_FIELD(insn, 27, 31);
4010                 gen_movl_reg_T1(rs2);
4011             }
4012             else if (IS_IMM) {       /* immediate */
4013                 rs2 = GET_FIELDs(insn, 19, 31);
4014                 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
4015             } else {            /* register */
4016                 rs2 = GET_FIELD(insn, 27, 31);
4017 #if defined(OPTIM)
4018                 if (rs2 != 0) {
4019 #endif
4020                     gen_movl_reg_T1(rs2);
4021                     gen_op_add_T1_T0();
4022 #if defined(OPTIM)
4023                 }
4024 #endif
4025             }
4026             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4027                 (xop > 0x17 && xop <= 0x1d ) ||
4028                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4029                 switch (xop) {
4030                 case 0x0:       /* load unsigned word */
4031                     gen_op_check_align_T0_3();
4032                     ABI32_MASK(cpu_T[0]);
4033                     tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx);
4034                     break;
4035                 case 0x1:       /* load unsigned byte */
4036                     ABI32_MASK(cpu_T[0]);
4037                     tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx);
4038                     break;
4039                 case 0x2:       /* load unsigned halfword */
4040                     gen_op_check_align_T0_1();
4041                     ABI32_MASK(cpu_T[0]);
4042                     tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx);
4043                     break;
4044                 case 0x3:       /* load double word */
4045                     if (rd & 1)
4046                         goto illegal_insn;
4047                     else {
4048                         TCGv r_dword;
4049
4050                         r_dword = tcg_temp_new(TCG_TYPE_I64);
4051                         gen_op_check_align_T0_7();
4052                         ABI32_MASK(cpu_T[0]);
4053                         tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx);
4054                         tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
4055                         gen_movl_T0_reg(rd + 1);
4056                         tcg_gen_shri_i64(r_dword, r_dword, 32);
4057                         tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
4058                     }
4059                     break;
4060                 case 0x9:       /* load signed byte */
4061                     ABI32_MASK(cpu_T[0]);
4062                     tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
4063                     break;
4064                 case 0xa:       /* load signed halfword */
4065                     gen_op_check_align_T0_1();
4066                     ABI32_MASK(cpu_T[0]);
4067                     tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx);
4068                     break;
4069                 case 0xd:       /* ldstub -- XXX: should be atomically */
4070                     tcg_gen_movi_i32(cpu_tmp0, 0xff);
4071                     ABI32_MASK(cpu_T[0]);
4072                     tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
4073                     tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx);
4074                     break;
4075                 case 0x0f:      /* swap register with memory. Also atomically */
4076                     gen_op_check_align_T0_3();
4077                     gen_movl_reg_T1(rd);
4078                     ABI32_MASK(cpu_T[0]);
4079                     tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx);
4080                     tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
4081                     tcg_gen_mov_i32(cpu_T[1], cpu_tmp0);
4082                     break;
4083 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4084                 case 0x10:      /* load word alternate */
4085 #ifndef TARGET_SPARC64
4086                     if (IS_IMM)
4087                         goto illegal_insn;
4088                     if (!supervisor(dc))
4089                         goto priv_insn;
4090 #endif
4091                     gen_op_check_align_T0_3();
4092                     gen_ld_asi(insn, 4, 0);
4093                     break;
4094                 case 0x11:      /* load unsigned byte alternate */
4095 #ifndef TARGET_SPARC64
4096                     if (IS_IMM)
4097                         goto illegal_insn;
4098                     if (!supervisor(dc))
4099                         goto priv_insn;
4100 #endif
4101                     gen_ld_asi(insn, 1, 0);
4102                     break;
4103                 case 0x12:      /* load unsigned halfword alternate */
4104 #ifndef TARGET_SPARC64
4105                     if (IS_IMM)
4106                         goto illegal_insn;
4107                     if (!supervisor(dc))
4108                         goto priv_insn;
4109 #endif
4110                     gen_op_check_align_T0_1();
4111                     gen_ld_asi(insn, 2, 0);
4112                     break;
4113                 case 0x13:      /* load double word alternate */
4114 #ifndef TARGET_SPARC64
4115                     if (IS_IMM)
4116                         goto illegal_insn;
4117                     if (!supervisor(dc))
4118                         goto priv_insn;
4119 #endif
4120                     if (rd & 1)
4121                         goto illegal_insn;
4122                     gen_op_check_align_T0_7();
4123                     gen_ldda_asi(insn);
4124                     gen_movl_T0_reg(rd + 1);
4125                     break;
4126                 case 0x19:      /* load signed byte alternate */
4127 #ifndef TARGET_SPARC64
4128                     if (IS_IMM)
4129                         goto illegal_insn;
4130                     if (!supervisor(dc))
4131                         goto priv_insn;
4132 #endif
4133                     gen_ld_asi(insn, 1, 1);
4134                     break;
4135                 case 0x1a:      /* load signed halfword alternate */
4136 #ifndef TARGET_SPARC64
4137                     if (IS_IMM)
4138                         goto illegal_insn;
4139                     if (!supervisor(dc))
4140                         goto priv_insn;
4141 #endif
4142                     gen_op_check_align_T0_1();
4143                     gen_ld_asi(insn, 2, 1);
4144                     break;
4145                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
4146 #ifndef TARGET_SPARC64
4147                     if (IS_IMM)
4148                         goto illegal_insn;
4149                     if (!supervisor(dc))
4150                         goto priv_insn;
4151 #endif
4152                     gen_ldstub_asi(insn);
4153                     break;
4154                 case 0x1f:      /* swap reg with alt. memory. Also atomically */
4155 #ifndef TARGET_SPARC64
4156                     if (IS_IMM)
4157                         goto illegal_insn;
4158                     if (!supervisor(dc))
4159                         goto priv_insn;
4160 #endif
4161                     gen_op_check_align_T0_3();
4162                     gen_movl_reg_T1(rd);
4163                     gen_swap_asi(insn);
4164                     break;
4165
4166 #ifndef TARGET_SPARC64
4167                 case 0x30: /* ldc */
4168                 case 0x31: /* ldcsr */
4169                 case 0x33: /* lddc */
4170                     goto ncp_insn;
4171 #endif
4172 #endif
4173 #ifdef TARGET_SPARC64
4174                 case 0x08: /* V9 ldsw */
4175                     gen_op_check_align_T0_3();
4176                     ABI32_MASK(cpu_T[0]);
4177                     tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx);
4178                     break;
4179                 case 0x0b: /* V9 ldx */
4180                     gen_op_check_align_T0_7();
4181                     ABI32_MASK(cpu_T[0]);
4182                     tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx);
4183                     break;
4184                 case 0x18: /* V9 ldswa */
4185                     gen_op_check_align_T0_3();
4186                     gen_ld_asi(insn, 4, 1);
4187                     break;
4188                 case 0x1b: /* V9 ldxa */
4189                     gen_op_check_align_T0_7();
4190                     gen_ld_asi(insn, 8, 0);
4191                     break;
4192                 case 0x2d: /* V9 prefetch, no effect */
4193                     goto skip_move;
4194                 case 0x30: /* V9 ldfa */
4195                     gen_op_check_align_T0_3();
4196                     gen_ldf_asi(insn, 4, rd);
4197                     goto skip_move;
4198                 case 0x33: /* V9 lddfa */
4199                     gen_op_check_align_T0_3();
4200                     gen_ldf_asi(insn, 8, DFPREG(rd));
4201                     goto skip_move;
4202                 case 0x3d: /* V9 prefetcha, no effect */
4203                     goto skip_move;
4204                 case 0x32: /* V9 ldqfa */
4205 #if defined(CONFIG_USER_ONLY)
4206                     gen_op_check_align_T0_3();
4207                     gen_ldf_asi(insn, 16, QFPREG(rd));
4208                     goto skip_move;
4209 #else
4210                     goto nfpu_insn;
4211 #endif
4212 #endif
4213                 default:
4214                     goto illegal_insn;
4215                 }
4216                 gen_movl_T1_reg(rd);
4217 #ifdef TARGET_SPARC64
4218             skip_move: ;
4219 #endif
4220             } else if (xop >= 0x20 && xop < 0x24) {
4221                 if (gen_trap_ifnofpu(dc))
4222                     goto jmp_insn;
4223                 switch (xop) {
4224                 case 0x20:      /* load fpreg */
4225                     gen_op_check_align_T0_3();
4226                     gen_op_ldst(ldf);
4227                     gen_op_store_FT0_fpr(rd);
4228                     break;
4229                 case 0x21:      /* load fsr */
4230                     gen_op_check_align_T0_3();
4231                     gen_op_ldst(ldf);
4232                     gen_op_ldfsr();
4233                     tcg_gen_helper_0_0(helper_ldfsr);
4234                     break;
4235                 case 0x22:      /* load quad fpreg */
4236 #if defined(CONFIG_USER_ONLY)
4237                     gen_op_check_align_T0_7();
4238                     gen_op_ldst(ldqf);
4239                     gen_op_store_QT0_fpr(QFPREG(rd));
4240                     break;
4241 #else
4242                     goto nfpu_insn;
4243 #endif
4244                 case 0x23:      /* load double fpreg */
4245                     gen_op_check_align_T0_7();
4246                     gen_op_ldst(lddf);
4247                     gen_op_store_DT0_fpr(DFPREG(rd));
4248                     break;
4249                 default:
4250                     goto illegal_insn;
4251                 }
4252             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4253                        xop == 0xe || xop == 0x1e) {
4254                 gen_movl_reg_T1(rd);
4255                 switch (xop) {
4256                 case 0x4: /* store word */
4257                     gen_op_check_align_T0_3();
4258                     ABI32_MASK(cpu_T[0]);
4259                     tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
4260                     break;
4261                 case 0x5: /* store byte */
4262                     ABI32_MASK(cpu_T[0]);
4263                     tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx);
4264                     break;
4265                 case 0x6: /* store halfword */
4266                     gen_op_check_align_T0_1();
4267                     ABI32_MASK(cpu_T[0]);
4268                     tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx);
4269                     break;
4270                 case 0x7: /* store double word */
4271                     if (rd & 1)
4272                         goto illegal_insn;
4273 #ifndef __i386__
4274                     else {
4275                         TCGv r_dword, r_low;
4276
4277                         gen_op_check_align_T0_7();
4278                         r_dword = tcg_temp_new(TCG_TYPE_I64);
4279                         r_low = tcg_temp_new(TCG_TYPE_I32);
4280                         gen_movl_reg_TN(rd + 1, r_low);
4281                         tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
4282                                            r_low);
4283                         tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx);
4284                     }
4285 #else /* __i386__ */
4286                     gen_op_check_align_T0_7();
4287                     flush_T2(dc);
4288                     gen_movl_reg_T2(rd + 1);
4289                     gen_op_ldst(std);
4290 #endif /* __i386__ */
4291                     break;
4292 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4293                 case 0x14: /* store word alternate */
4294 #ifndef TARGET_SPARC64
4295                     if (IS_IMM)
4296                         goto illegal_insn;
4297                     if (!supervisor(dc))
4298                         goto priv_insn;
4299 #endif
4300                     gen_op_check_align_T0_3();
4301                     gen_st_asi(insn, 4);
4302                     break;
4303                 case 0x15: /* store byte alternate */
4304 #ifndef TARGET_SPARC64
4305                     if (IS_IMM)
4306                         goto illegal_insn;
4307                     if (!supervisor(dc))
4308                         goto priv_insn;
4309 #endif
4310                     gen_st_asi(insn, 1);
4311                     break;
4312                 case 0x16: /* store halfword alternate */
4313 #ifndef TARGET_SPARC64
4314                     if (IS_IMM)
4315                         goto illegal_insn;
4316                     if (!supervisor(dc))
4317                         goto priv_insn;
4318 #endif
4319                     gen_op_check_align_T0_1();
4320                     gen_st_asi(insn, 2);
4321                     break;
4322                 case 0x17: /* store double word alternate */
4323 #ifndef TARGET_SPARC64
4324                     if (IS_IMM)
4325                         goto illegal_insn;
4326                     if (!supervisor(dc))
4327                         goto priv_insn;
4328 #endif
4329                     if (rd & 1)
4330                         goto illegal_insn;
4331                     else {
4332                         int asi;
4333                         TCGv r_dword, r_temp, r_size;
4334
4335                         gen_op_check_align_T0_7();
4336                         r_dword = tcg_temp_new(TCG_TYPE_I64);
4337                         r_temp = tcg_temp_new(TCG_TYPE_I32);
4338                         r_size = tcg_temp_new(TCG_TYPE_I32);
4339                         gen_movl_reg_TN(rd + 1, r_temp);
4340                         tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
4341                                            r_temp);
4342 #ifdef TARGET_SPARC64
4343                         if (IS_IMM) {
4344                             int offset;
4345
4346                             offset = GET_FIELD(insn, 25, 31);
4347                             tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
4348                             tcg_gen_ld_i32(r_dword, cpu_env, offsetof(CPUSPARCState, asi));
4349                         } else {
4350 #endif
4351                             asi = GET_FIELD(insn, 19, 26);
4352                             tcg_gen_movi_i32(r_temp, asi);
4353 #ifdef TARGET_SPARC64
4354                         }
4355 #endif
4356                         tcg_gen_movi_i32(r_size, 8);
4357                         tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_temp, r_size);
4358                     }
4359                     break;
4360 #endif
4361 #ifdef TARGET_SPARC64
4362                 case 0x0e: /* V9 stx */
4363                     gen_op_check_align_T0_7();
4364                     ABI32_MASK(cpu_T[0]);
4365                     tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx);
4366                     break;
4367                 case 0x1e: /* V9 stxa */
4368                     gen_op_check_align_T0_7();
4369                     gen_st_asi(insn, 8);
4370                     break;
4371 #endif
4372                 default:
4373                     goto illegal_insn;
4374                 }
4375             } else if (xop > 0x23 && xop < 0x28) {
4376                 if (gen_trap_ifnofpu(dc))
4377                     goto jmp_insn;
4378                 switch (xop) {
4379                 case 0x24:
4380                     gen_op_check_align_T0_3();
4381                     gen_op_load_fpr_FT0(rd);
4382                     gen_op_ldst(stf);
4383                     break;
4384                 case 0x25: /* stfsr, V9 stxfsr */
4385 #ifdef CONFIG_USER_ONLY
4386                     gen_op_check_align_T0_3();
4387 #endif
4388                     gen_op_stfsr();
4389                     gen_op_ldst(stf);
4390                     break;
4391                 case 0x26:
4392 #ifdef TARGET_SPARC64
4393 #if defined(CONFIG_USER_ONLY)
4394                     /* V9 stqf, store quad fpreg */
4395                     gen_op_check_align_T0_7();
4396                     gen_op_load_fpr_QT0(QFPREG(rd));
4397                     gen_op_ldst(stqf);
4398                     break;
4399 #else
4400                     goto nfpu_insn;
4401 #endif
4402 #else /* !TARGET_SPARC64 */
4403                     /* stdfq, store floating point queue */
4404 #if defined(CONFIG_USER_ONLY)
4405                     goto illegal_insn;
4406 #else
4407                     if (!supervisor(dc))
4408                         goto priv_insn;
4409                     if (gen_trap_ifnofpu(dc))
4410                         goto jmp_insn;
4411                     goto nfq_insn;
4412 #endif
4413 #endif
4414                 case 0x27:
4415                     gen_op_check_align_T0_7();
4416                     gen_op_load_fpr_DT0(DFPREG(rd));
4417                     gen_op_ldst(stdf);
4418                     break;
4419                 default:
4420                     goto illegal_insn;
4421                 }
4422             } else if (xop > 0x33 && xop < 0x3f) {
4423                 switch (xop) {
4424 #ifdef TARGET_SPARC64
4425                 case 0x34: /* V9 stfa */
4426                     gen_op_check_align_T0_3();
4427                     gen_op_load_fpr_FT0(rd);
4428                     gen_stf_asi(insn, 4, rd);
4429                     break;
4430                 case 0x36: /* V9 stqfa */
4431 #if defined(CONFIG_USER_ONLY)
4432                     gen_op_check_align_T0_7();
4433                     gen_op_load_fpr_QT0(QFPREG(rd));
4434                     gen_stf_asi(insn, 16, QFPREG(rd));
4435                     break;
4436 #else
4437                     goto nfpu_insn;
4438 #endif
4439                 case 0x37: /* V9 stdfa */
4440                     gen_op_check_align_T0_3();
4441                     gen_op_load_fpr_DT0(DFPREG(rd));
4442                     gen_stf_asi(insn, 8, DFPREG(rd));
4443                     break;
4444                 case 0x3c: /* V9 casa */
4445                     gen_op_check_align_T0_3();
4446                     gen_cas_asi(insn, rd);
4447                     gen_movl_T1_reg(rd);
4448                     break;
4449                 case 0x3e: /* V9 casxa */
4450                     gen_op_check_align_T0_7();
4451                     gen_casx_asi(insn, rd);
4452                     gen_movl_T1_reg(rd);
4453                     break;
4454 #else
4455                 case 0x34: /* stc */
4456                 case 0x35: /* stcsr */
4457                 case 0x36: /* stdcq */
4458                 case 0x37: /* stdc */
4459                     goto ncp_insn;
4460 #endif
4461                 default:
4462                     goto illegal_insn;
4463                 }
4464             }
4465             else
4466                 goto illegal_insn;
4467         }
4468         break;
4469     }
4470     /* default case for non jump instructions */
4471     if (dc->npc == DYNAMIC_PC) {
4472         dc->pc = DYNAMIC_PC;
4473         gen_op_next_insn();
4474     } else if (dc->npc == JUMP_PC) {
4475         /* we can do a static jump */
4476         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
4477         dc->is_br = 1;
4478     } else {
4479         dc->pc = dc->npc;
4480         dc->npc = dc->npc + 4;
4481     }
4482  jmp_insn:
4483     return;
4484  illegal_insn:
4485     save_state(dc);
4486     gen_op_exception(TT_ILL_INSN);
4487     dc->is_br = 1;
4488     return;
4489 #if !defined(CONFIG_USER_ONLY)
4490  priv_insn:
4491     save_state(dc);
4492     gen_op_exception(TT_PRIV_INSN);
4493     dc->is_br = 1;
4494     return;
4495  nfpu_insn:
4496     save_state(dc);
4497     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4498     dc->is_br = 1;
4499     return;
4500 #ifndef TARGET_SPARC64
4501  nfq_insn:
4502     save_state(dc);
4503     gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4504     dc->is_br = 1;
4505     return;
4506 #endif
4507 #endif
4508 #ifndef TARGET_SPARC64
4509  ncp_insn:
4510     save_state(dc);
4511     gen_op_exception(TT_NCP_INSN);
4512     dc->is_br = 1;
4513     return;
4514 #endif
4515 }
4516
4517 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
4518 {
4519 }
4520
4521 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4522                                                  int spc, CPUSPARCState *env)
4523 {
4524     target_ulong pc_start, last_pc;
4525     uint16_t *gen_opc_end;
4526     DisasContext dc1, *dc = &dc1;
4527     int j, lj = -1;
4528
4529     memset(dc, 0, sizeof(DisasContext));
4530     dc->tb = tb;
4531     pc_start = tb->pc;
4532     dc->pc = pc_start;
4533     last_pc = dc->pc;
4534     dc->npc = (target_ulong) tb->cs_base;
4535     dc->mem_idx = cpu_mmu_index(env);
4536     dc->fpu_enabled = cpu_fpu_enabled(env);
4537     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4538
4539     cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4540
4541     do {
4542         if (env->nb_breakpoints > 0) {
4543             for(j = 0; j < env->nb_breakpoints; j++) {
4544                 if (env->breakpoints[j] == dc->pc) {
4545                     if (dc->pc != pc_start)
4546                         save_state(dc);
4547                     tcg_gen_helper_0_0(helper_debug);
4548                     tcg_gen_exit_tb(0);
4549                     dc->is_br = 1;
4550                     goto exit_gen_loop;
4551                 }
4552             }
4553         }
4554         if (spc) {
4555             if (loglevel > 0)
4556                 fprintf(logfile, "Search PC...\n");
4557             j = gen_opc_ptr - gen_opc_buf;
4558             if (lj < j) {
4559                 lj++;
4560                 while (lj < j)
4561                     gen_opc_instr_start[lj++] = 0;
4562                 gen_opc_pc[lj] = dc->pc;
4563                 gen_opc_npc[lj] = dc->npc;
4564                 gen_opc_instr_start[lj] = 1;
4565             }
4566         }
4567         last_pc = dc->pc;
4568         disas_sparc_insn(dc);
4569
4570         if (dc->is_br)
4571             break;
4572         /* if the next PC is different, we abort now */
4573         if (dc->pc != (last_pc + 4))
4574             break;
4575         /* if we reach a page boundary, we stop generation so that the
4576            PC of a TT_TFAULT exception is always in the right page */
4577         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4578             break;
4579         /* if single step mode, we generate only one instruction and
4580            generate an exception */
4581         if (env->singlestep_enabled) {
4582             gen_jmp_im(dc->pc);
4583             tcg_gen_exit_tb(0);
4584             break;
4585         }
4586     } while ((gen_opc_ptr < gen_opc_end) &&
4587              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4588
4589  exit_gen_loop:
4590     if (!dc->is_br) {
4591         if (dc->pc != DYNAMIC_PC &&
4592             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4593             /* static PC and NPC: we can use direct chaining */
4594             gen_branch(dc, dc->pc, dc->npc);
4595         } else {
4596             if (dc->pc != DYNAMIC_PC)
4597                 gen_jmp_im(dc->pc);
4598             save_npc(dc);
4599             tcg_gen_exit_tb(0);
4600         }
4601     }
4602     *gen_opc_ptr = INDEX_op_end;
4603     if (spc) {
4604         j = gen_opc_ptr - gen_opc_buf;
4605         lj++;
4606         while (lj <= j)
4607             gen_opc_instr_start[lj++] = 0;
4608 #if 0
4609         if (loglevel > 0) {
4610             page_dump(logfile);
4611         }
4612 #endif
4613         gen_opc_jump_pc[0] = dc->jump_pc[0];
4614         gen_opc_jump_pc[1] = dc->jump_pc[1];
4615     } else {
4616         tb->size = last_pc + 4 - pc_start;
4617     }
4618 #ifdef DEBUG_DISAS
4619     if (loglevel & CPU_LOG_TB_IN_ASM) {
4620         fprintf(logfile, "--------------\n");
4621         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4622         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4623         fprintf(logfile, "\n");
4624     }
4625 #endif
4626     return 0;
4627 }
4628
4629 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4630 {
4631     return gen_intermediate_code_internal(tb, 0, env);
4632 }
4633
4634 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4635 {
4636     return gen_intermediate_code_internal(tb, 1, env);
4637 }
4638
4639 void cpu_reset(CPUSPARCState *env)
4640 {
4641     tlb_flush(env, 1);
4642     env->cwp = 0;
4643     env->wim = 1;
4644     env->regwptr = env->regbase + (env->cwp * 16);
4645 #if defined(CONFIG_USER_ONLY)
4646     env->user_mode_only = 1;
4647 #ifdef TARGET_SPARC64
4648     env->cleanwin = NWINDOWS - 2;
4649     env->cansave = NWINDOWS - 2;
4650     env->pstate = PS_RMO | PS_PEF | PS_IE;
4651     env->asi = 0x82; // Primary no-fault
4652 #endif
4653 #else
4654     env->psret = 0;
4655     env->psrs = 1;
4656     env->psrps = 1;
4657 #ifdef TARGET_SPARC64
4658     env->pstate = PS_PRIV;
4659     env->hpstate = HS_PRIV;
4660     env->pc = 0x1fff0000000ULL;
4661     env->tsptr = &env->ts[env->tl];
4662 #else
4663     env->pc = 0;
4664     env->mmuregs[0] &= ~(MMU_E | MMU_NF);
4665     env->mmuregs[0] |= env->mmu_bm;
4666 #endif
4667     env->npc = env->pc + 4;
4668 #endif
4669 }
4670
4671 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
4672 {
4673     CPUSPARCState *env;
4674     const sparc_def_t *def;
4675     static int inited;
4676
4677     def = cpu_sparc_find_by_name(cpu_model);
4678     if (!def)
4679         return NULL;
4680
4681     env = qemu_mallocz(sizeof(CPUSPARCState));
4682     if (!env)
4683         return NULL;
4684     cpu_exec_init(env);
4685     env->cpu_model_str = cpu_model;
4686     env->version = def->iu_version;
4687     env->fsr = def->fpu_version;
4688 #if !defined(TARGET_SPARC64)
4689     env->mmu_bm = def->mmu_bm;
4690     env->mmu_ctpr_mask = def->mmu_ctpr_mask;
4691     env->mmu_cxr_mask = def->mmu_cxr_mask;
4692     env->mmu_sfsr_mask = def->mmu_sfsr_mask;
4693     env->mmu_trcr_mask = def->mmu_trcr_mask;
4694     env->mmuregs[0] |= def->mmu_version;
4695     cpu_sparc_set_id(env, 0);
4696 #endif
4697
4698     /* init various static tables */
4699     if (!inited) {
4700         inited = 1;
4701
4702         tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
4703         cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4704         cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4705                                          offsetof(CPUState, regwptr),
4706                                          "regwptr");
4707         //#if TARGET_LONG_BITS > HOST_LONG_BITS
4708 #ifdef TARGET_SPARC64
4709         cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4710                                       TCG_AREG0, offsetof(CPUState, t0), "T0");
4711         cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4712                                       TCG_AREG0, offsetof(CPUState, t1), "T1");
4713         cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4714                                       TCG_AREG0, offsetof(CPUState, t2), "T2");
4715         cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4716                                      TCG_AREG0, offsetof(CPUState, xcc),
4717                                      "xcc");
4718 #else
4719         cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4720         cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4721         cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4722 #endif
4723         cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4724                                         TCG_AREG0, offsetof(CPUState, cc_src),
4725                                         "cc_src");
4726         cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4727                                         TCG_AREG0, offsetof(CPUState, cc_dst),
4728                                         "cc_dst");
4729         cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4730                                      TCG_AREG0, offsetof(CPUState, psr),
4731                                      "psr");
4732     }
4733
4734     cpu_reset(env);
4735
4736     return env;
4737 }
4738
4739 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
4740 {
4741 #if !defined(TARGET_SPARC64)
4742     env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
4743 #endif
4744 }
4745
4746 static const sparc_def_t sparc_defs[] = {
4747 #ifdef TARGET_SPARC64
4748     {
4749         .name = "Fujitsu Sparc64",
4750         .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
4751                        | (MAXTL << 8) | (NWINDOWS - 1)),
4752         .fpu_version = 0x00000000,
4753         .mmu_version = 0,
4754     },
4755     {
4756         .name = "Fujitsu Sparc64 III",
4757         .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
4758                        | (MAXTL << 8) | (NWINDOWS - 1)),
4759         .fpu_version = 0x00000000,
4760         .mmu_version = 0,
4761     },
4762     {
4763         .name = "Fujitsu Sparc64 IV",
4764         .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
4765                        | (MAXTL << 8) | (NWINDOWS - 1)),
4766         .fpu_version = 0x00000000,
4767         .mmu_version = 0,
4768     },
4769     {
4770         .name = "Fujitsu Sparc64 V",
4771         .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
4772                        | (MAXTL << 8) | (NWINDOWS - 1)),
4773         .fpu_version = 0x00000000,
4774         .mmu_version = 0,
4775     },
4776     {
4777         .name = "TI UltraSparc I",
4778         .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
4779                        | (MAXTL << 8) | (NWINDOWS - 1)),
4780         .fpu_version = 0x00000000,
4781         .mmu_version = 0,
4782     },
4783     {
4784         .name = "TI UltraSparc II",
4785         .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
4786                        | (MAXTL << 8) | (NWINDOWS - 1)),
4787         .fpu_version = 0x00000000,
4788         .mmu_version = 0,
4789     },
4790     {
4791         .name = "TI UltraSparc IIi",
4792         .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
4793                        | (MAXTL << 8) | (NWINDOWS - 1)),
4794         .fpu_version = 0x00000000,
4795         .mmu_version = 0,
4796     },
4797     {
4798         .name = "TI UltraSparc IIe",
4799         .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
4800                        | (MAXTL << 8) | (NWINDOWS - 1)),
4801         .fpu_version = 0x00000000,
4802         .mmu_version = 0,
4803     },
4804     {
4805         .name = "Sun UltraSparc III",
4806         .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
4807                        | (MAXTL << 8) | (NWINDOWS - 1)),
4808         .fpu_version = 0x00000000,
4809         .mmu_version = 0,
4810     },
4811     {
4812         .name = "Sun UltraSparc III Cu",
4813         .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
4814                        | (MAXTL << 8) | (NWINDOWS - 1)),
4815         .fpu_version = 0x00000000,
4816         .mmu_version = 0,
4817     },
4818     {
4819         .name = "Sun UltraSparc IIIi",
4820         .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
4821                        | (MAXTL << 8) | (NWINDOWS - 1)),
4822         .fpu_version = 0x00000000,
4823         .mmu_version = 0,
4824     },
4825     {
4826         .name = "Sun UltraSparc IV",
4827         .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
4828                        | (MAXTL << 8) | (NWINDOWS - 1)),
4829         .fpu_version = 0x00000000,
4830         .mmu_version = 0,
4831     },
4832     {
4833         .name = "Sun UltraSparc IV+",
4834         .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
4835                        | (MAXTL << 8) | (NWINDOWS - 1)),
4836         .fpu_version = 0x00000000,
4837         .mmu_version = 0,
4838     },
4839     {
4840         .name = "Sun UltraSparc IIIi+",
4841         .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
4842                        | (MAXTL << 8) | (NWINDOWS - 1)),
4843         .fpu_version = 0x00000000,
4844         .mmu_version = 0,
4845     },
4846     {
4847         .name = "NEC UltraSparc I",
4848         .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
4849                        | (MAXTL << 8) | (NWINDOWS - 1)),
4850         .fpu_version = 0x00000000,
4851         .mmu_version = 0,
4852     },
4853 #else
4854     {
4855         .name = "Fujitsu MB86900",
4856         .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
4857         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4858         .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
4859         .mmu_bm = 0x00004000,
4860         .mmu_ctpr_mask = 0x007ffff0,
4861         .mmu_cxr_mask = 0x0000003f,
4862         .mmu_sfsr_mask = 0xffffffff,
4863         .mmu_trcr_mask = 0xffffffff,
4864     },
4865     {
4866         .name = "Fujitsu MB86904",
4867         .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
4868         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4869         .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
4870         .mmu_bm = 0x00004000,
4871         .mmu_ctpr_mask = 0x00ffffc0,
4872         .mmu_cxr_mask = 0x000000ff,
4873         .mmu_sfsr_mask = 0x00016fff,
4874         .mmu_trcr_mask = 0x00ffffff,
4875     },
4876     {
4877         .name = "Fujitsu MB86907",
4878         .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
4879         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4880         .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
4881         .mmu_bm = 0x00004000,
4882         .mmu_ctpr_mask = 0xffffffc0,
4883         .mmu_cxr_mask = 0x000000ff,
4884         .mmu_sfsr_mask = 0x00016fff,
4885         .mmu_trcr_mask = 0xffffffff,
4886     },
4887     {
4888         .name = "LSI L64811",
4889         .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
4890         .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
4891         .mmu_version = 0x10 << 24,
4892         .mmu_bm = 0x00004000,
4893         .mmu_ctpr_mask = 0x007ffff0,
4894         .mmu_cxr_mask = 0x0000003f,
4895         .mmu_sfsr_mask = 0xffffffff,
4896         .mmu_trcr_mask = 0xffffffff,
4897     },
4898     {
4899         .name = "Cypress CY7C601",
4900         .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
4901         .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4902         .mmu_version = 0x10 << 24,
4903         .mmu_bm = 0x00004000,
4904         .mmu_ctpr_mask = 0x007ffff0,
4905         .mmu_cxr_mask = 0x0000003f,
4906         .mmu_sfsr_mask = 0xffffffff,
4907         .mmu_trcr_mask = 0xffffffff,
4908     },
4909     {
4910         .name = "Cypress CY7C611",
4911         .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
4912         .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4913         .mmu_version = 0x10 << 24,
4914         .mmu_bm = 0x00004000,
4915         .mmu_ctpr_mask = 0x007ffff0,
4916         .mmu_cxr_mask = 0x0000003f,
4917         .mmu_sfsr_mask = 0xffffffff,
4918         .mmu_trcr_mask = 0xffffffff,
4919     },
4920     {
4921         .name = "TI SuperSparc II",
4922         .iu_version = 0x40000000,
4923         .fpu_version = 0 << 17,
4924         .mmu_version = 0x04000000,
4925         .mmu_bm = 0x00002000,
4926         .mmu_ctpr_mask = 0xffffffc0,
4927         .mmu_cxr_mask = 0x0000ffff,
4928         .mmu_sfsr_mask = 0xffffffff,
4929         .mmu_trcr_mask = 0xffffffff,
4930     },
4931     {
4932         .name = "TI MicroSparc I",
4933         .iu_version = 0x41000000,
4934         .fpu_version = 4 << 17,
4935         .mmu_version = 0x41000000,
4936         .mmu_bm = 0x00004000,
4937         .mmu_ctpr_mask = 0x007ffff0,
4938         .mmu_cxr_mask = 0x0000003f,
4939         .mmu_sfsr_mask = 0x00016fff,
4940         .mmu_trcr_mask = 0x0000003f,
4941     },
4942     {
4943         .name = "TI MicroSparc II",
4944         .iu_version = 0x42000000,
4945         .fpu_version = 4 << 17,
4946         .mmu_version = 0x02000000,
4947         .mmu_bm = 0x00004000,
4948         .mmu_ctpr_mask = 0x00ffffc0,
4949         .mmu_cxr_mask = 0x000000ff,
4950         .mmu_sfsr_mask = 0x00016fff,
4951         .mmu_trcr_mask = 0x00ffffff,
4952     },
4953     {
4954         .name = "TI MicroSparc IIep",
4955         .iu_version = 0x42000000,
4956         .fpu_version = 4 << 17,
4957         .mmu_version = 0x04000000,
4958         .mmu_bm = 0x00004000,
4959         .mmu_ctpr_mask = 0x00ffffc0,
4960         .mmu_cxr_mask = 0x000000ff,
4961         .mmu_sfsr_mask = 0x00016bff,
4962         .mmu_trcr_mask = 0x00ffffff,
4963     },
4964     {
4965         .name = "TI SuperSparc 51",
4966         .iu_version = 0x43000000,
4967         .fpu_version = 0 << 17,
4968         .mmu_version = 0x04000000,
4969         .mmu_bm = 0x00002000,
4970         .mmu_ctpr_mask = 0xffffffc0,
4971         .mmu_cxr_mask = 0x0000ffff,
4972         .mmu_sfsr_mask = 0xffffffff,
4973         .mmu_trcr_mask = 0xffffffff,
4974     },
4975     {
4976         .name = "TI SuperSparc 61",
4977         .iu_version = 0x44000000,
4978         .fpu_version = 0 << 17,
4979         .mmu_version = 0x04000000,
4980         .mmu_bm = 0x00002000,
4981         .mmu_ctpr_mask = 0xffffffc0,
4982         .mmu_cxr_mask = 0x0000ffff,
4983         .mmu_sfsr_mask = 0xffffffff,
4984         .mmu_trcr_mask = 0xffffffff,
4985     },
4986     {
4987         .name = "Ross RT625",
4988         .iu_version = 0x1e000000,
4989         .fpu_version = 1 << 17,
4990         .mmu_version = 0x1e000000,
4991         .mmu_bm = 0x00004000,
4992         .mmu_ctpr_mask = 0x007ffff0,
4993         .mmu_cxr_mask = 0x0000003f,
4994         .mmu_sfsr_mask = 0xffffffff,
4995         .mmu_trcr_mask = 0xffffffff,
4996     },
4997     {
4998         .name = "Ross RT620",
4999         .iu_version = 0x1f000000,
5000         .fpu_version = 1 << 17,
5001         .mmu_version = 0x1f000000,
5002         .mmu_bm = 0x00004000,
5003         .mmu_ctpr_mask = 0x007ffff0,
5004         .mmu_cxr_mask = 0x0000003f,
5005         .mmu_sfsr_mask = 0xffffffff,
5006         .mmu_trcr_mask = 0xffffffff,
5007     },
5008     {
5009         .name = "BIT B5010",
5010         .iu_version = 0x20000000,
5011         .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
5012         .mmu_version = 0x20000000,
5013         .mmu_bm = 0x00004000,
5014         .mmu_ctpr_mask = 0x007ffff0,
5015         .mmu_cxr_mask = 0x0000003f,
5016         .mmu_sfsr_mask = 0xffffffff,
5017         .mmu_trcr_mask = 0xffffffff,
5018     },
5019     {
5020         .name = "Matsushita MN10501",
5021         .iu_version = 0x50000000,
5022         .fpu_version = 0 << 17,
5023         .mmu_version = 0x50000000,
5024         .mmu_bm = 0x00004000,
5025         .mmu_ctpr_mask = 0x007ffff0,
5026         .mmu_cxr_mask = 0x0000003f,
5027         .mmu_sfsr_mask = 0xffffffff,
5028         .mmu_trcr_mask = 0xffffffff,
5029     },
5030     {
5031         .name = "Weitek W8601",
5032         .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
5033         .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
5034         .mmu_version = 0x10 << 24,
5035         .mmu_bm = 0x00004000,
5036         .mmu_ctpr_mask = 0x007ffff0,
5037         .mmu_cxr_mask = 0x0000003f,
5038         .mmu_sfsr_mask = 0xffffffff,
5039         .mmu_trcr_mask = 0xffffffff,
5040     },
5041     {
5042         .name = "LEON2",
5043         .iu_version = 0xf2000000,
5044         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
5045         .mmu_version = 0xf2000000,
5046         .mmu_bm = 0x00004000,
5047         .mmu_ctpr_mask = 0x007ffff0,
5048         .mmu_cxr_mask = 0x0000003f,
5049         .mmu_sfsr_mask = 0xffffffff,
5050         .mmu_trcr_mask = 0xffffffff,
5051     },
5052     {
5053         .name = "LEON3",
5054         .iu_version = 0xf3000000,
5055         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
5056         .mmu_version = 0xf3000000,
5057         .mmu_bm = 0x00004000,
5058         .mmu_ctpr_mask = 0x007ffff0,
5059         .mmu_cxr_mask = 0x0000003f,
5060         .mmu_sfsr_mask = 0xffffffff,
5061         .mmu_trcr_mask = 0xffffffff,
5062     },
5063 #endif
5064 };
5065
5066 static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name)
5067 {
5068     unsigned int i;
5069
5070     for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
5071         if (strcasecmp(name, sparc_defs[i].name) == 0) {
5072             return &sparc_defs[i];
5073         }
5074     }
5075     return NULL;
5076 }
5077
5078 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
5079 {
5080     unsigned int i;
5081
5082     for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
5083         (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
5084                        sparc_defs[i].name,
5085                        sparc_defs[i].iu_version,
5086                        sparc_defs[i].fpu_version,
5087                        sparc_defs[i].mmu_version);
5088     }
5089 }
5090
5091 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
5092
5093 void cpu_dump_state(CPUState *env, FILE *f,
5094                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
5095                     int flags)
5096 {
5097     int i, x;
5098
5099     cpu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
5100     cpu_fprintf(f, "General Registers:\n");
5101     for (i = 0; i < 4; i++)
5102         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
5103     cpu_fprintf(f, "\n");
5104     for (; i < 8; i++)
5105         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
5106     cpu_fprintf(f, "\nCurrent Register Window:\n");
5107     for (x = 0; x < 3; x++) {
5108         for (i = 0; i < 4; i++)
5109             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
5110                     (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
5111                     env->regwptr[i + x * 8]);
5112         cpu_fprintf(f, "\n");
5113         for (; i < 8; i++)
5114             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
5115                     (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
5116                     env->regwptr[i + x * 8]);
5117         cpu_fprintf(f, "\n");
5118     }
5119     cpu_fprintf(f, "\nFloating Point Registers:\n");
5120     for (i = 0; i < 32; i++) {
5121         if ((i & 3) == 0)
5122             cpu_fprintf(f, "%%f%02d:", i);
5123         cpu_fprintf(f, " %016lf", env->fpr[i]);
5124         if ((i & 3) == 3)
5125             cpu_fprintf(f, "\n");
5126     }
5127 #ifdef TARGET_SPARC64
5128     cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
5129                 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
5130     cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
5131                 env->cansave, env->canrestore, env->otherwin, env->wstate,
5132                 env->cleanwin, NWINDOWS - 1 - env->cwp);
5133 #else
5134     cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
5135             GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
5136             GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
5137             env->psrs?'S':'-', env->psrps?'P':'-',
5138             env->psret?'E':'-', env->wim);
5139 #endif
5140     cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
5141 }
5142
5143 #if defined(CONFIG_USER_ONLY)
5144 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
5145 {
5146     return addr;
5147 }
5148
5149 #else
5150 extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
5151                                  int *access_index, target_ulong address, int rw,
5152                                  int mmu_idx);
5153
5154 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
5155 {
5156     target_phys_addr_t phys_addr;
5157     int prot, access_index;
5158
5159     if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
5160                              MMU_KERNEL_IDX) != 0)
5161         if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
5162                                  0, MMU_KERNEL_IDX) != 0)
5163             return -1;
5164     if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
5165         return -1;
5166     return phys_addr;
5167 }
5168 #endif
5169
5170 void helper_flush(target_ulong addr)
5171 {
5172     addr &= ~7;
5173     tb_invalidate_page_range(addr, addr + 8);
5174 }