git.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <stdarg.h>
  23 #include <stdlib.h>
  24 #include <stdio.h>
  25 #include <string.h>
  26 #include <inttypes.h>
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30 #include "disas.h"
  31 #include "helper.h"
  32 #include "tcg-op.h"
  33
  34 #define DEBUG_DISAS
  35
  36 #define DYNAMIC_PC  1 /* dynamic pc value */
  37 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  38                          according to jump_pc[T2] */
  39
  40 /* global register indexes */
  41 static TCGv cpu_env, cpu_regwptr;
  42 static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
  43 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
  44 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
  45 #ifdef TARGET_SPARC64
  46 static TCGv cpu_xcc;
  47 #endif
  48 /* local register indexes (only used inside old micro ops) */
  49 static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
  50
  51 #include "gen-icount.h"
  52
  53 typedef struct DisasContext {
  54     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  55     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  56     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  57     int is_br;
  58     int mem_idx;
  59     int fpu_enabled;
  60     int address_mask_32bit;
  61     struct TranslationBlock *tb;
  62     uint32_t features;
  63 } DisasContext;
  64
  65 // This function uses non-native bit order
  66 #define GET_FIELD(X, FROM, TO) \
  67   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  68
  69 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  70 #define GET_FIELD_SP(X, FROM, TO) \
  71     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  72
  73 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  74 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
  75
  76 #ifdef TARGET_SPARC64
  77 #define FFPREG(r) (r)
  78 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
  79 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
  80 #else
  81 #define FFPREG(r) (r)
  82 #define DFPREG(r) (r & 0x1e)
  83 #define QFPREG(r) (r & 0x1c)
  84 #endif
  85
  86 static int sign_extend(int x, int len)
  87 {
  88     len = 32 - len;
  89     return (x << len) >> len;
  90 }
  91
  92 #define IS_IMM (insn & (1<<13))
  93
  94 /* floating point registers moves */
  95 static void gen_op_load_fpr_FT0(unsigned int src)
  96 {
  97     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  98     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
  99 }
 100
 101 static void gen_op_load_fpr_FT1(unsigned int src)
 102 {
 103     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 104     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
 105 }
 106
 107 static void gen_op_store_FT0_fpr(unsigned int dst)
 108 {
 109     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
 110     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 111 }
 112
 113 static void gen_op_load_fpr_DT0(unsigned int src)
 114 {
 115     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 116     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 117                    offsetof(CPU_DoubleU, l.upper));
 118     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 119     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 120                    offsetof(CPU_DoubleU, l.lower));
 121 }
 122
 123 static void gen_op_load_fpr_DT1(unsigned int src)
 124 {
 125     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 126     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
 127                    offsetof(CPU_DoubleU, l.upper));
 128     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 129     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
 130                    offsetof(CPU_DoubleU, l.lower));
 131 }
 132
 133 static void gen_op_store_DT0_fpr(unsigned int dst)
 134 {
 135     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 136                    offsetof(CPU_DoubleU, l.upper));
 137     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 138     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 139                    offsetof(CPU_DoubleU, l.lower));
 140     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 141 }
 142
 143 static void gen_op_load_fpr_QT0(unsigned int src)
 144 {
 145     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 146     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 147                    offsetof(CPU_QuadU, l.upmost));
 148     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 149     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 150                    offsetof(CPU_QuadU, l.upper));
 151     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 152     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 153                    offsetof(CPU_QuadU, l.lower));
 154     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 155     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 156                    offsetof(CPU_QuadU, l.lowest));
 157 }
 158
 159 static void gen_op_load_fpr_QT1(unsigned int src)
 160 {
 161     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 162     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 163                    offsetof(CPU_QuadU, l.upmost));
 164     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 165     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 166                    offsetof(CPU_QuadU, l.upper));
 167     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 168     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 169                    offsetof(CPU_QuadU, l.lower));
 170     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 171     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 172                    offsetof(CPU_QuadU, l.lowest));
 173 }
 174
 175 static void gen_op_store_QT0_fpr(unsigned int dst)
 176 {
 177     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 178                    offsetof(CPU_QuadU, l.upmost));
 179     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 180     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 181                    offsetof(CPU_QuadU, l.upper));
 182     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 183     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 184                    offsetof(CPU_QuadU, l.lower));
 185     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
 186     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 187                    offsetof(CPU_QuadU, l.lowest));
 188     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
 189 }
 190
 191 /* moves */
 192 #ifdef CONFIG_USER_ONLY
 193 #define supervisor(dc) 0
 194 #ifdef TARGET_SPARC64
 195 #define hypervisor(dc) 0
 196 #endif
 197 #else
 198 #define supervisor(dc) (dc->mem_idx >= 1)
 199 #ifdef TARGET_SPARC64
 200 #define hypervisor(dc) (dc->mem_idx == 2)
 201 #else
 202 #endif
 203 #endif
 204
 205 #ifdef TARGET_SPARC64
 206 #ifndef TARGET_ABI32
 207 #define AM_CHECK(dc) ((dc)->address_mask_32bit)
 208 #else
 209 #define AM_CHECK(dc) (1)
 210 #endif
 211 #endif
 212
 213 static inline void gen_address_mask(DisasContext *dc, TCGv addr)
 214 {
 215 #ifdef TARGET_SPARC64
 216     if (AM_CHECK(dc))
 217         tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
 218 #endif
 219 }
 220
 221 static inline void gen_movl_reg_TN(int reg, TCGv tn)
 222 {
 223     if (reg == 0)
 224         tcg_gen_movi_tl(tn, 0);
 225     else if (reg < 8)
 226         tcg_gen_mov_tl(tn, cpu_gregs[reg]);
 227     else {
 228         tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 229     }
 230 }
 231
 232 static inline void gen_movl_TN_reg(int reg, TCGv tn)
 233 {
 234     if (reg == 0)
 235         return;
 236     else if (reg < 8)
 237         tcg_gen_mov_tl(cpu_gregs[reg], tn);
 238     else {
 239         tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 240     }
 241 }
 242
 243 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 244                                target_ulong pc, target_ulong npc)
 245 {
 246     TranslationBlock *tb;
 247
 248     tb = s->tb;
 249     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 250         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 251         /* jump to same page: we can use a direct jump */
 252         tcg_gen_goto_tb(tb_num);
 253         tcg_gen_movi_tl(cpu_pc, pc);
 254         tcg_gen_movi_tl(cpu_npc, npc);
 255         tcg_gen_exit_tb((long)tb + tb_num);
 256     } else {
 257         /* jump to another page: currently not optimized */
 258         tcg_gen_movi_tl(cpu_pc, pc);
 259         tcg_gen_movi_tl(cpu_npc, npc);
 260         tcg_gen_exit_tb(0);
 261     }
 262 }
 263
 264 // XXX suboptimal
 265 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
 266 {
 267     tcg_gen_extu_i32_tl(reg, src);
 268     tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
 269     tcg_gen_andi_tl(reg, reg, 0x1);
 270 }
 271
 272 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
 273 {
 274     tcg_gen_extu_i32_tl(reg, src);
 275     tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
 276     tcg_gen_andi_tl(reg, reg, 0x1);
 277 }
 278
 279 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
 280 {
 281     tcg_gen_extu_i32_tl(reg, src);
 282     tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
 283     tcg_gen_andi_tl(reg, reg, 0x1);
 284 }
 285
 286 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
 287 {
 288     tcg_gen_extu_i32_tl(reg, src);
 289     tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
 290     tcg_gen_andi_tl(reg, reg, 0x1);
 291 }
 292
 293 static inline void gen_cc_clear_icc(void)
 294 {
 295     tcg_gen_movi_i32(cpu_psr, 0);
 296 }
 297
 298 #ifdef TARGET_SPARC64
 299 static inline void gen_cc_clear_xcc(void)
 300 {
 301     tcg_gen_movi_i32(cpu_xcc, 0);
 302 }
 303 #endif
 304
 305 /* old op:
 306     if (!T0)
 307         env->psr |= PSR_ZERO;
 308     if ((int32_t) T0 < 0)
 309         env->psr |= PSR_NEG;
 310 */
 311 static inline void gen_cc_NZ_icc(TCGv dst)
 312 {
 313     TCGv r_temp;
 314     int l1, l2;
 315
 316     l1 = gen_new_label();
 317     l2 = gen_new_label();
 318     r_temp = tcg_temp_new(TCG_TYPE_TL);
 319     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 320     tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
 321     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
 322     gen_set_label(l1);
 323     tcg_gen_ext_i32_tl(r_temp, dst);
 324     tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
 325     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
 326     gen_set_label(l2);
 327     tcg_temp_free(r_temp);
 328 }
 329
 330 #ifdef TARGET_SPARC64
 331 static inline void gen_cc_NZ_xcc(TCGv dst)
 332 {
 333     int l1, l2;
 334
 335     l1 = gen_new_label();
 336     l2 = gen_new_label();
 337     tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
 338     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
 339     gen_set_label(l1);
 340     tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
 341     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
 342     gen_set_label(l2);
 343 }
 344 #endif
 345
 346 /* old op:
 347     if (T0 < src1)
 348         env->psr |= PSR_CARRY;
 349 */
 350 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
 351 {
 352     TCGv r_temp;
 353     int l1;
 354
 355     l1 = gen_new_label();
 356     r_temp = tcg_temp_new(TCG_TYPE_TL);
 357     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 358     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 359     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 360     gen_set_label(l1);
 361     tcg_temp_free(r_temp);
 362 }
 363
 364 #ifdef TARGET_SPARC64
 365 static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
 366 {
 367     int l1;
 368
 369     l1 = gen_new_label();
 370     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 371     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 372     gen_set_label(l1);
 373 }
 374 #endif
 375
 376 /* old op:
 377     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
 378         env->psr |= PSR_OVF;
 379 */
 380 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
 381 {
 382     TCGv r_temp;
 383
 384     r_temp = tcg_temp_new(TCG_TYPE_TL);
 385     tcg_gen_xor_tl(r_temp, src1, src2);
 386     tcg_gen_xori_tl(r_temp, r_temp, -1);
 387     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 388     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 389     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 390     tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
 391     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 392     tcg_temp_free(r_temp);
 393     tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
 394 }
 395
 396 #ifdef TARGET_SPARC64
 397 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
 398 {
 399     TCGv r_temp;
 400
 401     r_temp = tcg_temp_new(TCG_TYPE_TL);
 402     tcg_gen_xor_tl(r_temp, src1, src2);
 403     tcg_gen_xori_tl(r_temp, r_temp, -1);
 404     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 405     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 406     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 407     tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
 408     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 409     tcg_temp_free(r_temp);
 410     tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
 411 }
 412 #endif
 413
 414 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
 415 {
 416     TCGv r_temp, r_const;
 417     int l1;
 418
 419     l1 = gen_new_label();
 420
 421     r_temp = tcg_temp_new(TCG_TYPE_TL);
 422     tcg_gen_xor_tl(r_temp, src1, src2);
 423     tcg_gen_xori_tl(r_temp, r_temp, -1);
 424     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 425     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 426     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 427     tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
 428     r_const = tcg_const_i32(TT_TOVF);
 429     tcg_gen_helper_0_1(raise_exception, r_const);
 430     tcg_temp_free(r_const);
 431     gen_set_label(l1);
 432     tcg_temp_free(r_temp);
 433 }
 434
 435 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
 436 {
 437     int l1;
 438
 439     l1 = gen_new_label();
 440     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 441     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 442     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
 443     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 444     gen_set_label(l1);
 445 }
 446
 447 static inline void gen_tag_tv(TCGv src1, TCGv src2)
 448 {
 449     int l1;
 450     TCGv r_const;
 451
 452     l1 = gen_new_label();
 453     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 454     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 455     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
 456     r_const = tcg_const_i32(TT_TOVF);
 457     tcg_gen_helper_0_1(raise_exception, r_const);
 458     tcg_temp_free(r_const);
 459     gen_set_label(l1);
 460 }
 461
 462 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
 463 {
 464     tcg_gen_mov_tl(cpu_cc_src, src1);
 465     tcg_gen_mov_tl(cpu_cc_src2, src2);
 466     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 467     gen_cc_clear_icc();
 468     gen_cc_NZ_icc(cpu_cc_dst);
 469     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 470     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 471 #ifdef TARGET_SPARC64
 472     gen_cc_clear_xcc();
 473     gen_cc_NZ_xcc(cpu_cc_dst);
 474     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 475     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 476 #endif
 477     tcg_gen_mov_tl(dst, cpu_cc_dst);
 478 }
 479
 480 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
 481 {
 482     tcg_gen_mov_tl(cpu_cc_src, src1);
 483     tcg_gen_mov_tl(cpu_cc_src2, src2);
 484     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 485     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
 486     gen_cc_clear_icc();
 487     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 488 #ifdef TARGET_SPARC64
 489     gen_cc_clear_xcc();
 490     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 491 #endif
 492     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
 493     gen_cc_NZ_icc(cpu_cc_dst);
 494     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 495     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 496 #ifdef TARGET_SPARC64
 497     gen_cc_NZ_xcc(cpu_cc_dst);
 498     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 499     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 500 #endif
 501     tcg_gen_mov_tl(dst, cpu_cc_dst);
 502 }
 503
 504 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
 505 {
 506     tcg_gen_mov_tl(cpu_cc_src, src1);
 507     tcg_gen_mov_tl(cpu_cc_src2, src2);
 508     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 509     gen_cc_clear_icc();
 510     gen_cc_NZ_icc(cpu_cc_dst);
 511     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 512     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 513     gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
 514 #ifdef TARGET_SPARC64
 515     gen_cc_clear_xcc();
 516     gen_cc_NZ_xcc(cpu_cc_dst);
 517     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 518     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 519 #endif
 520     tcg_gen_mov_tl(dst, cpu_cc_dst);
 521 }
 522
 523 static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
 524 {
 525     tcg_gen_mov_tl(cpu_cc_src, src1);
 526     tcg_gen_mov_tl(cpu_cc_src2, src2);
 527     gen_tag_tv(cpu_cc_src, cpu_cc_src2);
 528     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 529     gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 530     gen_cc_clear_icc();
 531     gen_cc_NZ_icc(cpu_cc_dst);
 532     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 533 #ifdef TARGET_SPARC64
 534     gen_cc_clear_xcc();
 535     gen_cc_NZ_xcc(cpu_cc_dst);
 536     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 537     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 538 #endif
 539     tcg_gen_mov_tl(dst, cpu_cc_dst);
 540 }
 541
 542 /* old op:
 543     if (src1 < T1)
 544         env->psr |= PSR_CARRY;
 545 */
 546 static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
 547 {
 548     TCGv r_temp1, r_temp2;
 549     int l1;
 550
 551     l1 = gen_new_label();
 552     r_temp1 = tcg_temp_new(TCG_TYPE_TL);
 553     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 554     tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
 555     tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
 556     tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
 557     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 558     gen_set_label(l1);
 559     tcg_temp_free(r_temp1);
 560     tcg_temp_free(r_temp2);
 561 }
 562
 563 #ifdef TARGET_SPARC64
 564 static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
 565 {
 566     int l1;
 567
 568     l1 = gen_new_label();
 569     tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
 570     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 571     gen_set_label(l1);
 572 }
 573 #endif
 574
 575 /* old op:
 576     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
 577         env->psr |= PSR_OVF;
 578 */
 579 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
 580 {
 581     TCGv r_temp;
 582
 583     r_temp = tcg_temp_new(TCG_TYPE_TL);
 584     tcg_gen_xor_tl(r_temp, src1, src2);
 585     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 586     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 587     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 588     tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
 589     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 590     tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
 591     tcg_temp_free(r_temp);
 592 }
 593
 594 #ifdef TARGET_SPARC64
 595 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
 596 {
 597     TCGv r_temp;
 598
 599     r_temp = tcg_temp_new(TCG_TYPE_TL);
 600     tcg_gen_xor_tl(r_temp, src1, src2);
 601     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 602     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 603     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 604     tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
 605     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 606     tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
 607     tcg_temp_free(r_temp);
 608 }
 609 #endif
 610
 611 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
 612 {
 613     TCGv r_temp, r_const;
 614     int l1;
 615
 616     l1 = gen_new_label();
 617
 618     r_temp = tcg_temp_new(TCG_TYPE_TL);
 619     tcg_gen_xor_tl(r_temp, src1, src2);
 620     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 621     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 622     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 623     tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
 624     r_const = tcg_const_i32(TT_TOVF);
 625     tcg_gen_helper_0_1(raise_exception, r_const);
 626     tcg_temp_free(r_const);
 627     gen_set_label(l1);
 628     tcg_temp_free(r_temp);
 629 }
 630
 631 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
 632 {
 633     tcg_gen_mov_tl(cpu_cc_src, src1);
 634     tcg_gen_mov_tl(cpu_cc_src2, src2);
 635     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 636     gen_cc_clear_icc();
 637     gen_cc_NZ_icc(cpu_cc_dst);
 638     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 639     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 640 #ifdef TARGET_SPARC64
 641     gen_cc_clear_xcc();
 642     gen_cc_NZ_xcc(cpu_cc_dst);
 643     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 644     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 645 #endif
 646     tcg_gen_mov_tl(dst, cpu_cc_dst);
 647 }
 648
 649 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
 650 {
 651     tcg_gen_mov_tl(cpu_cc_src, src1);
 652     tcg_gen_mov_tl(cpu_cc_src2, src2);
 653     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 654     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
 655     gen_cc_clear_icc();
 656     gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
 657 #ifdef TARGET_SPARC64
 658     gen_cc_clear_xcc();
 659     gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
 660 #endif
 661     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
 662     gen_cc_NZ_icc(cpu_cc_dst);
 663     gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
 664     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 665 #ifdef TARGET_SPARC64
 666     gen_cc_NZ_xcc(cpu_cc_dst);
 667     gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
 668     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 669 #endif
 670     tcg_gen_mov_tl(dst, cpu_cc_dst);
 671 }
 672
 673 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
 674 {
 675     tcg_gen_mov_tl(cpu_cc_src, src1);
 676     tcg_gen_mov_tl(cpu_cc_src2, src2);
 677     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 678     gen_cc_clear_icc();
 679     gen_cc_NZ_icc(cpu_cc_dst);
 680     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 681     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 682     gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
 683 #ifdef TARGET_SPARC64
 684     gen_cc_clear_xcc();
 685     gen_cc_NZ_xcc(cpu_cc_dst);
 686     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 687     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 688 #endif
 689     tcg_gen_mov_tl(dst, cpu_cc_dst);
 690 }
 691
 692 static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
 693 {
 694     tcg_gen_mov_tl(cpu_cc_src, src1);
 695     tcg_gen_mov_tl(cpu_cc_src2, src2);
 696     gen_tag_tv(cpu_cc_src, cpu_cc_src2);
 697     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 698     gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 699     gen_cc_clear_icc();
 700     gen_cc_NZ_icc(cpu_cc_dst);
 701     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 702 #ifdef TARGET_SPARC64
 703     gen_cc_clear_xcc();
 704     gen_cc_NZ_xcc(cpu_cc_dst);
 705     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 706     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 707 #endif
 708     tcg_gen_mov_tl(dst, cpu_cc_dst);
 709 }
 710
 711 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
 712 {
 713     TCGv r_temp, r_temp2;
 714     int l1;
 715
 716     l1 = gen_new_label();
 717     r_temp = tcg_temp_new(TCG_TYPE_TL);
 718     r_temp2 = tcg_temp_new(TCG_TYPE_I32);
 719
 720     /* old op:
 721     if (!(env->y & 1))
 722         T1 = 0;
 723     */
 724     tcg_gen_mov_tl(cpu_cc_src, src1);
 725     tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 726     tcg_gen_trunc_tl_i32(r_temp2, r_temp);
 727     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 728     tcg_gen_mov_tl(cpu_cc_src2, src2);
 729     tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
 730     tcg_gen_movi_tl(cpu_cc_src2, 0);
 731     gen_set_label(l1);
 732
 733     // b2 = T0 & 1;
 734     // env->y = (b2 << 31) | (env->y >> 1);
 735     tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
 736     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 737     tcg_gen_shli_i32(r_temp2, r_temp2, 31);
 738     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 739     tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
 740     tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
 741     tcg_temp_free(r_temp2);
 742     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 743
 744     // b1 = N ^ V;
 745     gen_mov_reg_N(cpu_tmp0, cpu_psr);
 746     gen_mov_reg_V(r_temp, cpu_psr);
 747     tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
 748     tcg_temp_free(r_temp);
 749
 750     // T0 = (b1 << 31) | (T0 >> 1);
 751     // src1 = T0;
 752     tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
 753     tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
 754     tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
 755
 756     /* do addition and update flags */
 757     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 758
 759     gen_cc_clear_icc();
 760     gen_cc_NZ_icc(cpu_cc_dst);
 761     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 762     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 763     tcg_gen_mov_tl(dst, cpu_cc_dst);
 764 }
 765
 766 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
 767 {
 768     TCGv r_temp, r_temp2;
 769
 770     r_temp = tcg_temp_new(TCG_TYPE_I64);
 771     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 772
 773     tcg_gen_extu_tl_i64(r_temp, src2);
 774     tcg_gen_extu_tl_i64(r_temp2, src1);
 775     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 776
 777     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 778     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 779     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 780     tcg_temp_free(r_temp);
 781 #ifdef TARGET_SPARC64
 782     tcg_gen_mov_i64(dst, r_temp2);
 783 #else
 784     tcg_gen_trunc_i64_tl(dst, r_temp2);
 785 #endif
 786     tcg_temp_free(r_temp2);
 787 }
 788
 789 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
 790 {
 791     TCGv r_temp, r_temp2;
 792
 793     r_temp = tcg_temp_new(TCG_TYPE_I64);
 794     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 795
 796     tcg_gen_ext_tl_i64(r_temp, src2);
 797     tcg_gen_ext_tl_i64(r_temp2, src1);
 798     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 799
 800     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 801     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 802     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 803     tcg_temp_free(r_temp);
 804 #ifdef TARGET_SPARC64
 805     tcg_gen_mov_i64(dst, r_temp2);
 806 #else
 807     tcg_gen_trunc_i64_tl(dst, r_temp2);
 808 #endif
 809     tcg_temp_free(r_temp2);
 810 }
 811
 812 #ifdef TARGET_SPARC64
 813 static inline void gen_trap_ifdivzero_tl(TCGv divisor)
 814 {
 815     TCGv r_const;
 816     int l1;
 817
 818     l1 = gen_new_label();
 819     tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
 820     r_const = tcg_const_i32(TT_DIV_ZERO);
 821     tcg_gen_helper_0_1(raise_exception, r_const);
 822     tcg_temp_free(r_const);
 823     gen_set_label(l1);
 824 }
 825
 826 static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
 827 {
 828     int l1, l2;
 829
 830     l1 = gen_new_label();
 831     l2 = gen_new_label();
 832     tcg_gen_mov_tl(cpu_cc_src, src1);
 833     tcg_gen_mov_tl(cpu_cc_src2, src2);
 834     gen_trap_ifdivzero_tl(cpu_cc_src2);
 835     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
 836     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
 837     tcg_gen_movi_i64(dst, INT64_MIN);
 838     tcg_gen_br(l2);
 839     gen_set_label(l1);
 840     tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
 841     gen_set_label(l2);
 842 }
 843 #endif
 844
 845 static inline void gen_op_div_cc(TCGv dst)
 846 {
 847     int l1;
 848
 849     tcg_gen_mov_tl(cpu_cc_dst, dst);
 850     gen_cc_clear_icc();
 851     gen_cc_NZ_icc(cpu_cc_dst);
 852     l1 = gen_new_label();
 853     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
 854     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 855     gen_set_label(l1);
 856 }
 857
 858 static inline void gen_op_logic_cc(TCGv dst)
 859 {
 860     tcg_gen_mov_tl(cpu_cc_dst, dst);
 861
 862     gen_cc_clear_icc();
 863     gen_cc_NZ_icc(cpu_cc_dst);
 864 #ifdef TARGET_SPARC64
 865     gen_cc_clear_xcc();
 866     gen_cc_NZ_xcc(cpu_cc_dst);
 867 #endif
 868 }
 869
 870 // 1
 871 static inline void gen_op_eval_ba(TCGv dst)
 872 {
 873     tcg_gen_movi_tl(dst, 1);
 874 }
 875
 876 // Z
 877 static inline void gen_op_eval_be(TCGv dst, TCGv src)
 878 {
 879     gen_mov_reg_Z(dst, src);
 880 }
 881
 882 // Z | (N ^ V)
 883 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
 884 {
 885     gen_mov_reg_N(cpu_tmp0, src);
 886     gen_mov_reg_V(dst, src);
 887     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 888     gen_mov_reg_Z(cpu_tmp0, src);
 889     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 890 }
 891
 892 // N ^ V
 893 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
 894 {
 895     gen_mov_reg_V(cpu_tmp0, src);
 896     gen_mov_reg_N(dst, src);
 897     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 898 }
 899
 900 // C | Z
 901 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
 902 {
 903     gen_mov_reg_Z(cpu_tmp0, src);
 904     gen_mov_reg_C(dst, src);
 905     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 906 }
 907
 908 // C
 909 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
 910 {
 911     gen_mov_reg_C(dst, src);
 912 }
 913
 914 // V
 915 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
 916 {
 917     gen_mov_reg_V(dst, src);
 918 }
 919
 920 // 0
 921 static inline void gen_op_eval_bn(TCGv dst)
 922 {
 923     tcg_gen_movi_tl(dst, 0);
 924 }
 925
 926 // N
 927 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
 928 {
 929     gen_mov_reg_N(dst, src);
 930 }
 931
 932 // !Z
 933 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
 934 {
 935     gen_mov_reg_Z(dst, src);
 936     tcg_gen_xori_tl(dst, dst, 0x1);
 937 }
 938
 939 // !(Z | (N ^ V))
 940 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
 941 {
 942     gen_mov_reg_N(cpu_tmp0, src);
 943     gen_mov_reg_V(dst, src);
 944     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 945     gen_mov_reg_Z(cpu_tmp0, src);
 946     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 947     tcg_gen_xori_tl(dst, dst, 0x1);
 948 }
 949
 950 // !(N ^ V)
 951 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
 952 {
 953     gen_mov_reg_V(cpu_tmp0, src);
 954     gen_mov_reg_N(dst, src);
 955     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 956     tcg_gen_xori_tl(dst, dst, 0x1);
 957 }
 958
 959 // !(C | Z)
 960 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
 961 {
 962     gen_mov_reg_Z(cpu_tmp0, src);
 963     gen_mov_reg_C(dst, src);
 964     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 965     tcg_gen_xori_tl(dst, dst, 0x1);
 966 }
 967
 968 // !C
 969 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
 970 {
 971     gen_mov_reg_C(dst, src);
 972     tcg_gen_xori_tl(dst, dst, 0x1);
 973 }
 974
 975 // !N
 976 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
 977 {
 978     gen_mov_reg_N(dst, src);
 979     tcg_gen_xori_tl(dst, dst, 0x1);
 980 }
 981
 982 // !V
 983 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
 984 {
 985     gen_mov_reg_V(dst, src);
 986     tcg_gen_xori_tl(dst, dst, 0x1);
 987 }
 988
 989 /*
 990   FPSR bit field FCC1 | FCC0:
 991    0 =
 992    1 <
 993    2 >
 994    3 unordered
 995 */
 996 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
 997                                     unsigned int fcc_offset)
 998 {
 999     tcg_gen_extu_i32_tl(reg, src);
1000     tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
1001     tcg_gen_andi_tl(reg, reg, 0x1);
1002 }
1003
1004 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
1005                                     unsigned int fcc_offset)
1006 {
1007     tcg_gen_extu_i32_tl(reg, src);
1008     tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
1009     tcg_gen_andi_tl(reg, reg, 0x1);
1010 }
1011
1012 // !0: FCC0 | FCC1
1013 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1014                                     unsigned int fcc_offset)
1015 {
1016     gen_mov_reg_FCC0(dst, src, fcc_offset);
1017     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1018     tcg_gen_or_tl(dst, dst, cpu_tmp0);
1019 }
1020
1021 // 1 or 2: FCC0 ^ FCC1
1022 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1023                                     unsigned int fcc_offset)
1024 {
1025     gen_mov_reg_FCC0(dst, src, fcc_offset);
1026     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1027     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1028 }
1029
1030 // 1 or 3: FCC0
1031 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1032                                     unsigned int fcc_offset)
1033 {
1034     gen_mov_reg_FCC0(dst, src, fcc_offset);
1035 }
1036
1037 // 1: FCC0 & !FCC1
1038 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1039                                     unsigned int fcc_offset)
1040 {
1041     gen_mov_reg_FCC0(dst, src, fcc_offset);
1042     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1043     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1044     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1045 }
1046
1047 // 2 or 3: FCC1
1048 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1049                                     unsigned int fcc_offset)
1050 {
1051     gen_mov_reg_FCC1(dst, src, fcc_offset);
1052 }
1053
1054 // 2: !FCC0 & FCC1
1055 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1056                                     unsigned int fcc_offset)
1057 {
1058     gen_mov_reg_FCC0(dst, src, fcc_offset);
1059     tcg_gen_xori_tl(dst, dst, 0x1);
1060     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1061     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1062 }
1063
1064 // 3: FCC0 & FCC1
1065 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1066                                     unsigned int fcc_offset)
1067 {
1068     gen_mov_reg_FCC0(dst, src, fcc_offset);
1069     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1070     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1071 }
1072
1073 // 0: !(FCC0 | FCC1)
1074 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1075                                     unsigned int fcc_offset)
1076 {
1077     gen_mov_reg_FCC0(dst, src, fcc_offset);
1078     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1079     tcg_gen_or_tl(dst, dst, cpu_tmp0);
1080     tcg_gen_xori_tl(dst, dst, 0x1);
1081 }
1082
1083 // 0 or 3: !(FCC0 ^ FCC1)
1084 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1085                                     unsigned int fcc_offset)
1086 {
1087     gen_mov_reg_FCC0(dst, src, fcc_offset);
1088     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1089     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1090     tcg_gen_xori_tl(dst, dst, 0x1);
1091 }
1092
1093 // 0 or 2: !FCC0
1094 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1095                                     unsigned int fcc_offset)
1096 {
1097     gen_mov_reg_FCC0(dst, src, fcc_offset);
1098     tcg_gen_xori_tl(dst, dst, 0x1);
1099 }
1100
1101 // !1: !(FCC0 & !FCC1)
1102 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1103                                     unsigned int fcc_offset)
1104 {
1105     gen_mov_reg_FCC0(dst, src, fcc_offset);
1106     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1107     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1108     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1109     tcg_gen_xori_tl(dst, dst, 0x1);
1110 }
1111
1112 // 0 or 1: !FCC1
1113 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1114                                     unsigned int fcc_offset)
1115 {
1116     gen_mov_reg_FCC1(dst, src, fcc_offset);
1117     tcg_gen_xori_tl(dst, dst, 0x1);
1118 }
1119
1120 // !2: !(!FCC0 & FCC1)
1121 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1122                                     unsigned int fcc_offset)
1123 {
1124     gen_mov_reg_FCC0(dst, src, fcc_offset);
1125     tcg_gen_xori_tl(dst, dst, 0x1);
1126     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1127     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1128     tcg_gen_xori_tl(dst, dst, 0x1);
1129 }
1130
1131 // !3: !(FCC0 & FCC1)
1132 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1133                                     unsigned int fcc_offset)
1134 {
1135     gen_mov_reg_FCC0(dst, src, fcc_offset);
1136     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1137     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1138     tcg_gen_xori_tl(dst, dst, 0x1);
1139 }
1140
1141 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1142                                target_ulong pc2, TCGv r_cond)
1143 {
1144     int l1;
1145
1146     l1 = gen_new_label();
1147
1148     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1149
1150     gen_goto_tb(dc, 0, pc1, pc1 + 4);
1151
1152     gen_set_label(l1);
1153     gen_goto_tb(dc, 1, pc2, pc2 + 4);
1154 }
1155
1156 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1157                                 target_ulong pc2, TCGv r_cond)
1158 {
1159     int l1;
1160
1161     l1 = gen_new_label();
1162
1163     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1164
1165     gen_goto_tb(dc, 0, pc2, pc1);
1166
1167     gen_set_label(l1);
1168     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1169 }
1170
1171 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1172                                       TCGv r_cond)
1173 {
1174     int l1, l2;
1175
1176     l1 = gen_new_label();
1177     l2 = gen_new_label();
1178
1179     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1180
1181     tcg_gen_movi_tl(cpu_npc, npc1);
1182     tcg_gen_br(l2);
1183
1184     gen_set_label(l1);
1185     tcg_gen_movi_tl(cpu_npc, npc2);
1186     gen_set_label(l2);
1187 }
1188
1189 /* call this function before using the condition register as it may
1190    have been set for a jump */
1191 static inline void flush_cond(DisasContext *dc, TCGv cond)
1192 {
1193     if (dc->npc == JUMP_PC) {
1194         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1195         dc->npc = DYNAMIC_PC;
1196     }
1197 }
1198
1199 static inline void save_npc(DisasContext *dc, TCGv cond)
1200 {
1201     if (dc->npc == JUMP_PC) {
1202         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1203         dc->npc = DYNAMIC_PC;
1204     } else if (dc->npc != DYNAMIC_PC) {
1205         tcg_gen_movi_tl(cpu_npc, dc->npc);
1206     }
1207 }
1208
1209 static inline void save_state(DisasContext *dc, TCGv cond)
1210 {
1211     tcg_gen_movi_tl(cpu_pc, dc->pc);
1212     save_npc(dc, cond);
1213 }
1214
1215 static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1216 {
1217     if (dc->npc == JUMP_PC) {
1218         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1219         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1220         dc->pc = DYNAMIC_PC;
1221     } else if (dc->npc == DYNAMIC_PC) {
1222         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1223         dc->pc = DYNAMIC_PC;
1224     } else {
1225         dc->pc = dc->npc;
1226     }
1227 }
1228
1229 static inline void gen_op_next_insn(void)
1230 {
1231     tcg_gen_mov_tl(cpu_pc, cpu_npc);
1232     tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1233 }
1234
1235 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1236 {
1237     TCGv r_src;
1238
1239 #ifdef TARGET_SPARC64
1240     if (cc)
1241         r_src = cpu_xcc;
1242     else
1243         r_src = cpu_psr;
1244 #else
1245     r_src = cpu_psr;
1246 #endif
1247     switch (cond) {
1248     case 0x0:
1249         gen_op_eval_bn(r_dst);
1250         break;
1251     case 0x1:
1252         gen_op_eval_be(r_dst, r_src);
1253         break;
1254     case 0x2:
1255         gen_op_eval_ble(r_dst, r_src);
1256         break;
1257     case 0x3:
1258         gen_op_eval_bl(r_dst, r_src);
1259         break;
1260     case 0x4:
1261         gen_op_eval_bleu(r_dst, r_src);
1262         break;
1263     case 0x5:
1264         gen_op_eval_bcs(r_dst, r_src);
1265         break;
1266     case 0x6:
1267         gen_op_eval_bneg(r_dst, r_src);
1268         break;
1269     case 0x7:
1270         gen_op_eval_bvs(r_dst, r_src);
1271         break;
1272     case 0x8:
1273         gen_op_eval_ba(r_dst);
1274         break;
1275     case 0x9:
1276         gen_op_eval_bne(r_dst, r_src);
1277         break;
1278     case 0xa:
1279         gen_op_eval_bg(r_dst, r_src);
1280         break;
1281     case 0xb:
1282         gen_op_eval_bge(r_dst, r_src);
1283         break;
1284     case 0xc:
1285         gen_op_eval_bgu(r_dst, r_src);
1286         break;
1287     case 0xd:
1288         gen_op_eval_bcc(r_dst, r_src);
1289         break;
1290     case 0xe:
1291         gen_op_eval_bpos(r_dst, r_src);
1292         break;
1293     case 0xf:
1294         gen_op_eval_bvc(r_dst, r_src);
1295         break;
1296     }
1297 }
1298
1299 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1300 {
1301     unsigned int offset;
1302
1303     switch (cc) {
1304     default:
1305     case 0x0:
1306         offset = 0;
1307         break;
1308     case 0x1:
1309         offset = 32 - 10;
1310         break;
1311     case 0x2:
1312         offset = 34 - 10;
1313         break;
1314     case 0x3:
1315         offset = 36 - 10;
1316         break;
1317     }
1318
1319     switch (cond) {
1320     case 0x0:
1321         gen_op_eval_bn(r_dst);
1322         break;
1323     case 0x1:
1324         gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1325         break;
1326     case 0x2:
1327         gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1328         break;
1329     case 0x3:
1330         gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1331         break;
1332     case 0x4:
1333         gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1334         break;
1335     case 0x5:
1336         gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1337         break;
1338     case 0x6:
1339         gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1340         break;
1341     case 0x7:
1342         gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1343         break;
1344     case 0x8:
1345         gen_op_eval_ba(r_dst);
1346         break;
1347     case 0x9:
1348         gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1349         break;
1350     case 0xa:
1351         gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1352         break;
1353     case 0xb:
1354         gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1355         break;
1356     case 0xc:
1357         gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1358         break;
1359     case 0xd:
1360         gen_op_eval_fble(r_dst, cpu_fsr, offset);
1361         break;
1362     case 0xe:
1363         gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1364         break;
1365     case 0xf:
1366         gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1367         break;
1368     }
1369 }
1370
1371 #ifdef TARGET_SPARC64
1372 // Inverted logic
1373 static const int gen_tcg_cond_reg[8] = {
1374     -1,
1375     TCG_COND_NE,
1376     TCG_COND_GT,
1377     TCG_COND_GE,
1378     -1,
1379     TCG_COND_EQ,
1380     TCG_COND_LE,
1381     TCG_COND_LT,
1382 };
1383
1384 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1385 {
1386     int l1;
1387
1388     l1 = gen_new_label();
1389     tcg_gen_movi_tl(r_dst, 0);
1390     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1391     tcg_gen_movi_tl(r_dst, 1);
1392     gen_set_label(l1);
1393 }
1394 #endif
1395
1396 /* XXX: potentially incorrect if dynamic npc */
1397 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1398                       TCGv r_cond)
1399 {
1400     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1401     target_ulong target = dc->pc + offset;
1402
1403     if (cond == 0x0) {
1404         /* unconditional not taken */
1405         if (a) {
1406             dc->pc = dc->npc + 4;
1407             dc->npc = dc->pc + 4;
1408         } else {
1409             dc->pc = dc->npc;
1410             dc->npc = dc->pc + 4;
1411         }
1412     } else if (cond == 0x8) {
1413         /* unconditional taken */
1414         if (a) {
1415             dc->pc = target;
1416             dc->npc = dc->pc + 4;
1417         } else {
1418             dc->pc = dc->npc;
1419             dc->npc = target;
1420         }
1421     } else {
1422         flush_cond(dc, r_cond);
1423         gen_cond(r_cond, cc, cond);
1424         if (a) {
1425             gen_branch_a(dc, target, dc->npc, r_cond);
1426             dc->is_br = 1;
1427         } else {
1428             dc->pc = dc->npc;
1429             dc->jump_pc[0] = target;
1430             dc->jump_pc[1] = dc->npc + 4;
1431             dc->npc = JUMP_PC;
1432         }
1433     }
1434 }
1435
1436 /* XXX: potentially incorrect if dynamic npc */
1437 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1438                       TCGv r_cond)
1439 {
1440     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1441     target_ulong target = dc->pc + offset;
1442
1443     if (cond == 0x0) {
1444         /* unconditional not taken */
1445         if (a) {
1446             dc->pc = dc->npc + 4;
1447             dc->npc = dc->pc + 4;
1448         } else {
1449             dc->pc = dc->npc;
1450             dc->npc = dc->pc + 4;
1451         }
1452     } else if (cond == 0x8) {
1453         /* unconditional taken */
1454         if (a) {
1455             dc->pc = target;
1456             dc->npc = dc->pc + 4;
1457         } else {
1458             dc->pc = dc->npc;
1459             dc->npc = target;
1460         }
1461     } else {
1462         flush_cond(dc, r_cond);
1463         gen_fcond(r_cond, cc, cond);
1464         if (a) {
1465             gen_branch_a(dc, target, dc->npc, r_cond);
1466             dc->is_br = 1;
1467         } else {
1468             dc->pc = dc->npc;
1469             dc->jump_pc[0] = target;
1470             dc->jump_pc[1] = dc->npc + 4;
1471             dc->npc = JUMP_PC;
1472         }
1473     }
1474 }
1475
1476 #ifdef TARGET_SPARC64
1477 /* XXX: potentially incorrect if dynamic npc */
1478 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1479                           TCGv r_cond, TCGv r_reg)
1480 {
1481     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1482     target_ulong target = dc->pc + offset;
1483
1484     flush_cond(dc, r_cond);
1485     gen_cond_reg(r_cond, cond, r_reg);
1486     if (a) {
1487         gen_branch_a(dc, target, dc->npc, r_cond);
1488         dc->is_br = 1;
1489     } else {
1490         dc->pc = dc->npc;
1491         dc->jump_pc[0] = target;
1492         dc->jump_pc[1] = dc->npc + 4;
1493         dc->npc = JUMP_PC;
1494     }
1495 }
1496
1497 static GenOpFunc * const gen_fcmps[4] = {
1498     helper_fcmps,
1499     helper_fcmps_fcc1,
1500     helper_fcmps_fcc2,
1501     helper_fcmps_fcc3,
1502 };
1503
1504 static GenOpFunc * const gen_fcmpd[4] = {
1505     helper_fcmpd,
1506     helper_fcmpd_fcc1,
1507     helper_fcmpd_fcc2,
1508     helper_fcmpd_fcc3,
1509 };
1510
1511 static GenOpFunc * const gen_fcmpq[4] = {
1512     helper_fcmpq,
1513     helper_fcmpq_fcc1,
1514     helper_fcmpq_fcc2,
1515     helper_fcmpq_fcc3,
1516 };
1517
1518 static GenOpFunc * const gen_fcmpes[4] = {
1519     helper_fcmpes,
1520     helper_fcmpes_fcc1,
1521     helper_fcmpes_fcc2,
1522     helper_fcmpes_fcc3,
1523 };
1524
1525 static GenOpFunc * const gen_fcmped[4] = {
1526     helper_fcmped,
1527     helper_fcmped_fcc1,
1528     helper_fcmped_fcc2,
1529     helper_fcmped_fcc3,
1530 };
1531
1532 static GenOpFunc * const gen_fcmpeq[4] = {
1533     helper_fcmpeq,
1534     helper_fcmpeq_fcc1,
1535     helper_fcmpeq_fcc2,
1536     helper_fcmpeq_fcc3,
1537 };
1538
1539 static inline void gen_op_fcmps(int fccno)
1540 {
1541     tcg_gen_helper_0_0(gen_fcmps[fccno]);
1542 }
1543
1544 static inline void gen_op_fcmpd(int fccno)
1545 {
1546     tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1547 }
1548
1549 static inline void gen_op_fcmpq(int fccno)
1550 {
1551     tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1552 }
1553
1554 static inline void gen_op_fcmpes(int fccno)
1555 {
1556     tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1557 }
1558
1559 static inline void gen_op_fcmped(int fccno)
1560 {
1561     tcg_gen_helper_0_0(gen_fcmped[fccno]);
1562 }
1563
1564 static inline void gen_op_fcmpeq(int fccno)
1565 {
1566     tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1567 }
1568
1569 #else
1570
1571 static inline void gen_op_fcmps(int fccno)
1572 {
1573     tcg_gen_helper_0_0(helper_fcmps);
1574 }
1575
1576 static inline void gen_op_fcmpd(int fccno)
1577 {
1578     tcg_gen_helper_0_0(helper_fcmpd);
1579 }
1580
1581 static inline void gen_op_fcmpq(int fccno)
1582 {
1583     tcg_gen_helper_0_0(helper_fcmpq);
1584 }
1585
1586 static inline void gen_op_fcmpes(int fccno)
1587 {
1588     tcg_gen_helper_0_0(helper_fcmpes);
1589 }
1590
1591 static inline void gen_op_fcmped(int fccno)
1592 {
1593     tcg_gen_helper_0_0(helper_fcmped);
1594 }
1595
1596 static inline void gen_op_fcmpeq(int fccno)
1597 {
1598     tcg_gen_helper_0_0(helper_fcmpeq);
1599 }
1600 #endif
1601
1602 static inline void gen_op_fpexception_im(int fsr_flags)
1603 {
1604     TCGv r_const;
1605
1606     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1607     tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1608     r_const = tcg_const_i32(TT_FP_EXCP);
1609     tcg_gen_helper_0_1(raise_exception, r_const);
1610     tcg_temp_free(r_const);
1611 }
1612
1613 static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1614 {
1615 #if !defined(CONFIG_USER_ONLY)
1616     if (!dc->fpu_enabled) {
1617         TCGv r_const;
1618
1619         save_state(dc, r_cond);
1620         r_const = tcg_const_i32(TT_NFPU_INSN);
1621         tcg_gen_helper_0_1(raise_exception, r_const);
1622         tcg_temp_free(r_const);
1623         dc->is_br = 1;
1624         return 1;
1625     }
1626 #endif
1627     return 0;
1628 }
1629
1630 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1631 {
1632     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1633 }
1634
1635 static inline void gen_clear_float_exceptions(void)
1636 {
1637     tcg_gen_helper_0_0(helper_clear_float_exceptions);
1638 }
1639
1640 /* asi moves */
1641 #ifdef TARGET_SPARC64
1642 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1643 {
1644     int asi, offset;
1645     TCGv r_asi;
1646
1647     if (IS_IMM) {
1648         r_asi = tcg_temp_new(TCG_TYPE_I32);
1649         offset = GET_FIELD(insn, 25, 31);
1650         tcg_gen_addi_tl(r_addr, r_addr, offset);
1651         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1652     } else {
1653         asi = GET_FIELD(insn, 19, 26);
1654         r_asi = tcg_const_i32(asi);
1655     }
1656     return r_asi;
1657 }
1658
1659 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1660                               int sign)
1661 {
1662     TCGv r_asi, r_size, r_sign;
1663
1664     r_asi = gen_get_asi(insn, addr);
1665     r_size = tcg_const_i32(size);
1666     r_sign = tcg_const_i32(sign);
1667     tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1668     tcg_temp_free(r_sign);
1669     tcg_temp_free(r_size);
1670     tcg_temp_free(r_asi);
1671 }
1672
1673 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1674 {
1675     TCGv r_asi, r_size;
1676
1677     r_asi = gen_get_asi(insn, addr);
1678     r_size = tcg_const_i32(size);
1679     tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1680     tcg_temp_free(r_size);
1681     tcg_temp_free(r_asi);
1682 }
1683
1684 static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1685 {
1686     TCGv r_asi, r_size, r_rd;
1687
1688     r_asi = gen_get_asi(insn, addr);
1689     r_size = tcg_const_i32(size);
1690     r_rd = tcg_const_i32(rd);
1691     tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1692     tcg_temp_free(r_rd);
1693     tcg_temp_free(r_size);
1694     tcg_temp_free(r_asi);
1695 }
1696
1697 static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1698 {
1699     TCGv r_asi, r_size, r_rd;
1700
1701     r_asi = gen_get_asi(insn, addr);
1702     r_size = tcg_const_i32(size);
1703     r_rd = tcg_const_i32(rd);
1704     tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1705     tcg_temp_free(r_rd);
1706     tcg_temp_free(r_size);
1707     tcg_temp_free(r_asi);
1708 }
1709
1710 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1711 {
1712     TCGv r_asi, r_size, r_sign;
1713
1714     r_asi = gen_get_asi(insn, addr);
1715     r_size = tcg_const_i32(4);
1716     r_sign = tcg_const_i32(0);
1717     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1718     tcg_temp_free(r_sign);
1719     tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1720     tcg_temp_free(r_size);
1721     tcg_temp_free(r_asi);
1722     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1723 }
1724
1725 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1726 {
1727     TCGv r_asi, r_size, r_sign;
1728
1729     r_asi = gen_get_asi(insn, addr);
1730     r_size = tcg_const_i32(8);
1731     r_sign = tcg_const_i32(0);
1732     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1733     tcg_temp_free(r_sign);
1734     tcg_temp_free(r_size);
1735     tcg_temp_free(r_asi);
1736     tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1737     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1738     tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1739 }
1740
1741 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1742 {
1743     TCGv r_temp, r_asi, r_size;
1744
1745     r_temp = tcg_temp_new(TCG_TYPE_TL);
1746     gen_movl_reg_TN(rd + 1, r_temp);
1747     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1748                        r_temp);
1749     tcg_temp_free(r_temp);
1750     r_asi = gen_get_asi(insn, addr);
1751     r_size = tcg_const_i32(8);
1752     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1753     tcg_temp_free(r_size);
1754     tcg_temp_free(r_asi);
1755 }
1756
1757 static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1758                                int rd)
1759 {
1760     TCGv r_val1, r_asi;
1761
1762     r_val1 = tcg_temp_new(TCG_TYPE_TL);
1763     gen_movl_reg_TN(rd, r_val1);
1764     r_asi = gen_get_asi(insn, addr);
1765     tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1766     tcg_temp_free(r_asi);
1767     tcg_temp_free(r_val1);
1768 }
1769
1770 static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1771                                 int rd)
1772 {
1773     TCGv r_asi;
1774
1775     gen_movl_reg_TN(rd, cpu_tmp64);
1776     r_asi = gen_get_asi(insn, addr);
1777     tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1778     tcg_temp_free(r_asi);
1779 }
1780
1781 #elif !defined(CONFIG_USER_ONLY)
1782
1783 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1784                               int sign)
1785 {
1786     TCGv r_asi, r_size, r_sign;
1787
1788     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1789     r_size = tcg_const_i32(size);
1790     r_sign = tcg_const_i32(sign);
1791     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1792     tcg_temp_free(r_sign);
1793     tcg_temp_free(r_size);
1794     tcg_temp_free(r_asi);
1795     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1796 }
1797
1798 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1799 {
1800     TCGv r_asi, r_size;
1801
1802     tcg_gen_extu_tl_i64(cpu_tmp64, src);
1803     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1804     r_size = tcg_const_i32(size);
1805     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1806     tcg_temp_free(r_size);
1807     tcg_temp_free(r_asi);
1808 }
1809
1810 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1811 {
1812     TCGv r_asi, r_size, r_sign;
1813
1814     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1815     r_size = tcg_const_i32(4);
1816     r_sign = tcg_const_i32(0);
1817     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1818     tcg_temp_free(r_sign);
1819     tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1820     tcg_temp_free(r_size);
1821     tcg_temp_free(r_asi);
1822     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1823 }
1824
1825 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1826 {
1827     TCGv r_asi, r_size, r_sign;
1828
1829     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1830     r_size = tcg_const_i32(8);
1831     r_sign = tcg_const_i32(0);
1832     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1833     tcg_temp_free(r_sign);
1834     tcg_temp_free(r_size);
1835     tcg_temp_free(r_asi);
1836     tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1837     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1838     tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1839 }
1840
1841 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1842 {
1843     TCGv r_temp, r_asi, r_size;
1844
1845     r_temp = tcg_temp_new(TCG_TYPE_TL);
1846     gen_movl_reg_TN(rd + 1, r_temp);
1847     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1848     tcg_temp_free(r_temp);
1849     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1850     r_size = tcg_const_i32(8);
1851     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1852     tcg_temp_free(r_size);
1853     tcg_temp_free(r_asi);
1854 }
1855 #endif
1856
1857 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1858 static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1859 {
1860     TCGv r_val, r_asi, r_size;
1861
1862     gen_ld_asi(dst, addr, insn, 1, 0);
1863
1864     r_val = tcg_const_i64(0xffULL);
1865     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1866     r_size = tcg_const_i32(1);
1867     tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1868     tcg_temp_free(r_size);
1869     tcg_temp_free(r_asi);
1870     tcg_temp_free(r_val);
1871 }
1872 #endif
1873
1874 static inline TCGv get_src1(unsigned int insn, TCGv def)
1875 {
1876     TCGv r_rs1 = def;
1877     unsigned int rs1;
1878
1879     rs1 = GET_FIELD(insn, 13, 17);
1880     if (rs1 == 0)
1881         r_rs1 = tcg_const_tl(0); // XXX how to free?
1882     else if (rs1 < 8)
1883         r_rs1 = cpu_gregs[rs1];
1884     else
1885         tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1886     return r_rs1;
1887 }
1888
1889 static inline TCGv get_src2(unsigned int insn, TCGv def)
1890 {
1891     TCGv r_rs2 = def;
1892     unsigned int rs2;
1893
1894     if (IS_IMM) { /* immediate */
1895         rs2 = GET_FIELDs(insn, 19, 31);
1896         r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1897     } else { /* register */
1898         rs2 = GET_FIELD(insn, 27, 31);
1899         if (rs2 == 0)
1900             r_rs2 = tcg_const_tl(0); // XXX how to free?
1901         else if (rs2 < 8)
1902             r_rs2 = cpu_gregs[rs2];
1903         else
1904             tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1905     }
1906     return r_rs2;
1907 }
1908
1909 #define CHECK_IU_FEATURE(dc, FEATURE)                      \
1910     if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1911         goto illegal_insn;
1912 #define CHECK_FPU_FEATURE(dc, FEATURE)                     \
1913     if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1914         goto nfpu_insn;
1915
1916 /* before an instruction, dc->pc must be static */
1917 static void disas_sparc_insn(DisasContext * dc)
1918 {
1919     unsigned int insn, opc, rs1, rs2, rd;
1920
1921     if (unlikely(loglevel & CPU_LOG_TB_OP))
1922         tcg_gen_debug_insn_start(dc->pc);
1923     insn = ldl_code(dc->pc);
1924     opc = GET_FIELD(insn, 0, 1);
1925
1926     rd = GET_FIELD(insn, 2, 6);
1927
1928     cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1929     cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
1930
1931     switch (opc) {
1932     case 0:                     /* branches/sethi */
1933         {
1934             unsigned int xop = GET_FIELD(insn, 7, 9);
1935             int32_t target;
1936             switch (xop) {
1937 #ifdef TARGET_SPARC64
1938             case 0x1:           /* V9 BPcc */
1939                 {
1940                     int cc;
1941
1942                     target = GET_FIELD_SP(insn, 0, 18);
1943                     target = sign_extend(target, 18);
1944                     target <<= 2;
1945                     cc = GET_FIELD_SP(insn, 20, 21);
1946                     if (cc == 0)
1947                         do_branch(dc, target, insn, 0, cpu_cond);
1948                     else if (cc == 2)
1949                         do_branch(dc, target, insn, 1, cpu_cond);
1950                     else
1951                         goto illegal_insn;
1952                     goto jmp_insn;
1953                 }
1954             case 0x3:           /* V9 BPr */
1955                 {
1956                     target = GET_FIELD_SP(insn, 0, 13) |
1957                         (GET_FIELD_SP(insn, 20, 21) << 14);
1958                     target = sign_extend(target, 16);
1959                     target <<= 2;
1960                     cpu_src1 = get_src1(insn, cpu_src1);
1961                     do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1962                     goto jmp_insn;
1963                 }
1964             case 0x5:           /* V9 FBPcc */
1965                 {
1966                     int cc = GET_FIELD_SP(insn, 20, 21);
1967                     if (gen_trap_ifnofpu(dc, cpu_cond))
1968                         goto jmp_insn;
1969                     target = GET_FIELD_SP(insn, 0, 18);
1970                     target = sign_extend(target, 19);
1971                     target <<= 2;
1972                     do_fbranch(dc, target, insn, cc, cpu_cond);
1973                     goto jmp_insn;
1974                 }
1975 #else
1976             case 0x7:           /* CBN+x */
1977                 {
1978                     goto ncp_insn;
1979                 }
1980 #endif
1981             case 0x2:           /* BN+x */
1982                 {
1983                     target = GET_FIELD(insn, 10, 31);
1984                     target = sign_extend(target, 22);
1985                     target <<= 2;
1986                     do_branch(dc, target, insn, 0, cpu_cond);
1987                     goto jmp_insn;
1988                 }
1989             case 0x6:           /* FBN+x */
1990                 {
1991                     if (gen_trap_ifnofpu(dc, cpu_cond))
1992                         goto jmp_insn;
1993                     target = GET_FIELD(insn, 10, 31);
1994                     target = sign_extend(target, 22);
1995                     target <<= 2;
1996                     do_fbranch(dc, target, insn, 0, cpu_cond);
1997                     goto jmp_insn;
1998                 }
1999             case 0x4:           /* SETHI */
2000                 if (rd) { // nop
2001                     uint32_t value = GET_FIELD(insn, 10, 31);
2002                     TCGv r_const;
2003
2004                     r_const = tcg_const_tl(value << 10);
2005                     gen_movl_TN_reg(rd, r_const);
2006                     tcg_temp_free(r_const);
2007                 }
2008                 break;
2009             case 0x0:           /* UNIMPL */
2010             default:
2011                 goto illegal_insn;
2012             }
2013             break;
2014         }
2015         break;
2016     case 1:
2017         /*CALL*/ {
2018             target_long target = GET_FIELDs(insn, 2, 31) << 2;
2019             TCGv r_const;
2020
2021             r_const = tcg_const_tl(dc->pc);
2022             gen_movl_TN_reg(15, r_const);
2023             tcg_temp_free(r_const);
2024             target += dc->pc;
2025             gen_mov_pc_npc(dc, cpu_cond);
2026             dc->npc = target;
2027         }
2028         goto jmp_insn;
2029     case 2:                     /* FPU & Logical Operations */
2030         {
2031             unsigned int xop = GET_FIELD(insn, 7, 12);
2032             if (xop == 0x3a) {  /* generate trap */
2033                 int cond;
2034
2035                 cpu_src1 = get_src1(insn, cpu_src1);
2036                 if (IS_IMM) {
2037                     rs2 = GET_FIELD(insn, 25, 31);
2038                     tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2039                 } else {
2040                     rs2 = GET_FIELD(insn, 27, 31);
2041                     if (rs2 != 0) {
2042                         gen_movl_reg_TN(rs2, cpu_src2);
2043                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2044                     } else
2045                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
2046                 }
2047                 cond = GET_FIELD(insn, 3, 6);
2048                 if (cond == 0x8) {
2049                     save_state(dc, cpu_cond);
2050                     tcg_gen_helper_0_1(helper_trap, cpu_dst);
2051                 } else if (cond != 0) {
2052                     TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2053 #ifdef TARGET_SPARC64
2054                     /* V9 icc/xcc */
2055                     int cc = GET_FIELD_SP(insn, 11, 12);
2056
2057                     save_state(dc, cpu_cond);
2058                     if (cc == 0)
2059                         gen_cond(r_cond, 0, cond);
2060                     else if (cc == 2)
2061                         gen_cond(r_cond, 1, cond);
2062                     else
2063                         goto illegal_insn;
2064 #else
2065                     save_state(dc, cpu_cond);
2066                     gen_cond(r_cond, 0, cond);
2067 #endif
2068                     tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2069                     tcg_temp_free(r_cond);
2070                 }
2071                 gen_op_next_insn();
2072                 tcg_gen_exit_tb(0);
2073                 dc->is_br = 1;
2074                 goto jmp_insn;
2075             } else if (xop == 0x28) {
2076                 rs1 = GET_FIELD(insn, 13, 17);
2077                 switch(rs1) {
2078                 case 0: /* rdy */
2079 #ifndef TARGET_SPARC64
2080                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2081                                        manual, rdy on the microSPARC
2082                                        II */
2083                 case 0x0f:          /* stbar in the SPARCv8 manual,
2084                                        rdy on the microSPARC II */
2085                 case 0x10 ... 0x1f: /* implementation-dependent in the
2086                                        SPARCv8 manual, rdy on the
2087                                        microSPARC II */
2088 #endif
2089                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2090                                   offsetof(CPUSPARCState, y));
2091                     gen_movl_TN_reg(rd, cpu_tmp0);
2092                     break;
2093 #ifdef TARGET_SPARC64
2094                 case 0x2: /* V9 rdccr */
2095                     tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2096                     gen_movl_TN_reg(rd, cpu_dst);
2097                     break;
2098                 case 0x3: /* V9 rdasi */
2099                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2100                                    offsetof(CPUSPARCState, asi));
2101                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2102                     gen_movl_TN_reg(rd, cpu_dst);
2103                     break;
2104                 case 0x4: /* V9 rdtick */
2105                     {
2106                         TCGv r_tickptr;
2107
2108                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2109                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2110                                        offsetof(CPUState, tick));
2111                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2112                                            r_tickptr);
2113                         tcg_temp_free(r_tickptr);
2114                         gen_movl_TN_reg(rd, cpu_dst);
2115                     }
2116                     break;
2117                 case 0x5: /* V9 rdpc */
2118                     {
2119                         TCGv r_const;
2120
2121                         r_const = tcg_const_tl(dc->pc);
2122                         gen_movl_TN_reg(rd, r_const);
2123                         tcg_temp_free(r_const);
2124                     }
2125                     break;
2126                 case 0x6: /* V9 rdfprs */
2127                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2128                                    offsetof(CPUSPARCState, fprs));
2129                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2130                     gen_movl_TN_reg(rd, cpu_dst);
2131                     break;
2132                 case 0xf: /* V9 membar */
2133                     break; /* no effect */
2134                 case 0x13: /* Graphics Status */
2135                     if (gen_trap_ifnofpu(dc, cpu_cond))
2136                         goto jmp_insn;
2137                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2138                                   offsetof(CPUSPARCState, gsr));
2139                     gen_movl_TN_reg(rd, cpu_tmp0);
2140                     break;
2141                 case 0x17: /* Tick compare */
2142                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2143                                   offsetof(CPUSPARCState, tick_cmpr));
2144                     gen_movl_TN_reg(rd, cpu_tmp0);
2145                     break;
2146                 case 0x18: /* System tick */
2147                     {
2148                         TCGv r_tickptr;
2149
2150                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2151                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2152                                        offsetof(CPUState, stick));
2153                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2154                                            r_tickptr);
2155                         tcg_temp_free(r_tickptr);
2156                         gen_movl_TN_reg(rd, cpu_dst);
2157                     }
2158                     break;
2159                 case 0x19: /* System tick compare */
2160                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2161                                   offsetof(CPUSPARCState, stick_cmpr));
2162                     gen_movl_TN_reg(rd, cpu_tmp0);
2163                     break;
2164                 case 0x10: /* Performance Control */
2165                 case 0x11: /* Performance Instrumentation Counter */
2166                 case 0x12: /* Dispatch Control */
2167                 case 0x14: /* Softint set, WO */
2168                 case 0x15: /* Softint clear, WO */
2169                 case 0x16: /* Softint write */
2170 #endif
2171                 default:
2172                     goto illegal_insn;
2173                 }
2174 #if !defined(CONFIG_USER_ONLY)
2175             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2176 #ifndef TARGET_SPARC64
2177                 if (!supervisor(dc))
2178                     goto priv_insn;
2179                 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2180 #else
2181                 if (!hypervisor(dc))
2182                     goto priv_insn;
2183                 rs1 = GET_FIELD(insn, 13, 17);
2184                 switch (rs1) {
2185                 case 0: // hpstate
2186                     // gen_op_rdhpstate();
2187                     break;
2188                 case 1: // htstate
2189                     // gen_op_rdhtstate();
2190                     break;
2191                 case 3: // hintp
2192                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2193                                    offsetof(CPUSPARCState, hintp));
2194                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2195                     break;
2196                 case 5: // htba
2197                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2198                                    offsetof(CPUSPARCState, htba));
2199                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2200                     break;
2201                 case 6: // hver
2202                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2203                                    offsetof(CPUSPARCState, hver));
2204                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2205                     break;
2206                 case 31: // hstick_cmpr
2207                     tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2208                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
2209                                    offsetof(CPUSPARCState, hstick_cmpr));
2210                     break;
2211                 default:
2212                     goto illegal_insn;
2213                 }
2214 #endif
2215                 gen_movl_TN_reg(rd, cpu_dst);
2216                 break;
2217             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2218                 if (!supervisor(dc))
2219                     goto priv_insn;
2220 #ifdef TARGET_SPARC64
2221                 rs1 = GET_FIELD(insn, 13, 17);
2222                 switch (rs1) {
2223                 case 0: // tpc
2224                     {
2225                         TCGv r_tsptr;
2226
2227                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2228                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2229                                        offsetof(CPUState, tsptr));
2230                         tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2231                                       offsetof(trap_state, tpc));
2232                         tcg_temp_free(r_tsptr);
2233                     }
2234                     break;
2235                 case 1: // tnpc
2236                     {
2237                         TCGv r_tsptr;
2238
2239                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2240                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2241                                        offsetof(CPUState, tsptr));
2242                         tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2243                                       offsetof(trap_state, tnpc));
2244                         tcg_temp_free(r_tsptr);
2245                     }
2246                     break;
2247                 case 2: // tstate
2248                     {
2249                         TCGv r_tsptr;
2250
2251                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2252                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2253                                        offsetof(CPUState, tsptr));
2254                         tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2255                                       offsetof(trap_state, tstate));
2256                         tcg_temp_free(r_tsptr);
2257                     }
2258                     break;
2259                 case 3: // tt
2260                     {
2261                         TCGv r_tsptr;
2262
2263                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2264                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2265                                        offsetof(CPUState, tsptr));
2266                         tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
2267                                        offsetof(trap_state, tt));
2268                         tcg_temp_free(r_tsptr);
2269                     }
2270                     break;
2271                 case 4: // tick
2272                     {
2273                         TCGv r_tickptr;
2274
2275                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2276                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2277                                        offsetof(CPUState, tick));
2278                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
2279                                            r_tickptr);
2280                         gen_movl_TN_reg(rd, cpu_tmp0);
2281                         tcg_temp_free(r_tickptr);
2282                     }
2283                     break;
2284                 case 5: // tba
2285                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2286                                   offsetof(CPUSPARCState, tbr));
2287                     break;
2288                 case 6: // pstate
2289                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2290                                    offsetof(CPUSPARCState, pstate));
2291                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2292                     break;
2293                 case 7: // tl
2294                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2295                                    offsetof(CPUSPARCState, tl));
2296                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2297                     break;
2298                 case 8: // pil
2299                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2300                                    offsetof(CPUSPARCState, psrpil));
2301                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2302                     break;
2303                 case 9: // cwp
2304                     tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
2305                     break;
2306                 case 10: // cansave
2307                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2308                                    offsetof(CPUSPARCState, cansave));
2309                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2310                     break;
2311                 case 11: // canrestore
2312                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2313                                    offsetof(CPUSPARCState, canrestore));
2314                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2315                     break;
2316                 case 12: // cleanwin
2317                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2318                                    offsetof(CPUSPARCState, cleanwin));
2319                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2320                     break;
2321                 case 13: // otherwin
2322                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2323                                    offsetof(CPUSPARCState, otherwin));
2324                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2325                     break;
2326                 case 14: // wstate
2327                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2328                                    offsetof(CPUSPARCState, wstate));
2329                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2330                     break;
2331                 case 16: // UA2005 gl
2332                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2333                                    offsetof(CPUSPARCState, gl));
2334                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2335                     break;
2336                 case 26: // UA2005 strand status
2337                     if (!hypervisor(dc))
2338                         goto priv_insn;
2339                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2340                                    offsetof(CPUSPARCState, ssr));
2341                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2342                     break;
2343                 case 31: // ver
2344                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2345                                   offsetof(CPUSPARCState, version));
2346                     break;
2347                 case 15: // fq
2348                 default:
2349                     goto illegal_insn;
2350                 }
2351 #else
2352                 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2353                                offsetof(CPUSPARCState, wim));
2354                 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2355 #endif
2356                 gen_movl_TN_reg(rd, cpu_tmp0);
2357                 break;
2358             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2359 #ifdef TARGET_SPARC64
2360                 save_state(dc, cpu_cond);
2361                 tcg_gen_helper_0_0(helper_flushw);
2362 #else
2363                 if (!supervisor(dc))
2364                     goto priv_insn;
2365                 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr));
2366                 gen_movl_TN_reg(rd, cpu_tmp0);
2367 #endif
2368                 break;
2369 #endif
2370             } else if (xop == 0x34) {   /* FPU Operations */
2371                 if (gen_trap_ifnofpu(dc, cpu_cond))
2372                     goto jmp_insn;
2373                 gen_op_clear_ieee_excp_and_FTT();
2374                 rs1 = GET_FIELD(insn, 13, 17);
2375                 rs2 = GET_FIELD(insn, 27, 31);
2376                 xop = GET_FIELD(insn, 18, 26);
2377                 switch (xop) {
2378                     case 0x1: /* fmovs */
2379                         gen_op_load_fpr_FT0(rs2);
2380                         gen_op_store_FT0_fpr(rd);
2381                         break;
2382                     case 0x5: /* fnegs */
2383                         gen_op_load_fpr_FT1(rs2);
2384                         tcg_gen_helper_0_0(helper_fnegs);
2385                         gen_op_store_FT0_fpr(rd);
2386                         break;
2387                     case 0x9: /* fabss */
2388                         gen_op_load_fpr_FT1(rs2);
2389                         tcg_gen_helper_0_0(helper_fabss);
2390                         gen_op_store_FT0_fpr(rd);
2391                         break;
2392                     case 0x29: /* fsqrts */
2393                         CHECK_FPU_FEATURE(dc, FSQRT);
2394                         gen_op_load_fpr_FT1(rs2);
2395                         gen_clear_float_exceptions();
2396                         tcg_gen_helper_0_0(helper_fsqrts);
2397                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2398                         gen_op_store_FT0_fpr(rd);
2399                         break;
2400                     case 0x2a: /* fsqrtd */
2401                         CHECK_FPU_FEATURE(dc, FSQRT);
2402                         gen_op_load_fpr_DT1(DFPREG(rs2));
2403                         gen_clear_float_exceptions();
2404                         tcg_gen_helper_0_0(helper_fsqrtd);
2405                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2406                         gen_op_store_DT0_fpr(DFPREG(rd));
2407                         break;
2408                     case 0x2b: /* fsqrtq */
2409                         CHECK_FPU_FEATURE(dc, FLOAT128);
2410                         gen_op_load_fpr_QT1(QFPREG(rs2));
2411                         gen_clear_float_exceptions();
2412                         tcg_gen_helper_0_0(helper_fsqrtq);
2413                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2414                         gen_op_store_QT0_fpr(QFPREG(rd));
2415                         break;
2416                     case 0x41:
2417                         gen_op_load_fpr_FT0(rs1);
2418                         gen_op_load_fpr_FT1(rs2);
2419                         gen_clear_float_exceptions();
2420                         tcg_gen_helper_0_0(helper_fadds);
2421                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2422                         gen_op_store_FT0_fpr(rd);
2423                         break;
2424                     case 0x42:
2425                         gen_op_load_fpr_DT0(DFPREG(rs1));
2426                         gen_op_load_fpr_DT1(DFPREG(rs2));
2427                         gen_clear_float_exceptions();
2428                         tcg_gen_helper_0_0(helper_faddd);
2429                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2430                         gen_op_store_DT0_fpr(DFPREG(rd));
2431                         break;
2432                     case 0x43: /* faddq */
2433                         CHECK_FPU_FEATURE(dc, FLOAT128);
2434                         gen_op_load_fpr_QT0(QFPREG(rs1));
2435                         gen_op_load_fpr_QT1(QFPREG(rs2));
2436                         gen_clear_float_exceptions();
2437                         tcg_gen_helper_0_0(helper_faddq);
2438                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2439                         gen_op_store_QT0_fpr(QFPREG(rd));
2440                         break;
2441                     case 0x45:
2442                         gen_op_load_fpr_FT0(rs1);
2443                         gen_op_load_fpr_FT1(rs2);
2444                         gen_clear_float_exceptions();
2445                         tcg_gen_helper_0_0(helper_fsubs);
2446                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2447                         gen_op_store_FT0_fpr(rd);
2448                         break;
2449                     case 0x46:
2450                         gen_op_load_fpr_DT0(DFPREG(rs1));
2451                         gen_op_load_fpr_DT1(DFPREG(rs2));
2452                         gen_clear_float_exceptions();
2453                         tcg_gen_helper_0_0(helper_fsubd);
2454                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2455                         gen_op_store_DT0_fpr(DFPREG(rd));
2456                         break;
2457                     case 0x47: /* fsubq */
2458                         CHECK_FPU_FEATURE(dc, FLOAT128);
2459                         gen_op_load_fpr_QT0(QFPREG(rs1));
2460                         gen_op_load_fpr_QT1(QFPREG(rs2));
2461                         gen_clear_float_exceptions();
2462                         tcg_gen_helper_0_0(helper_fsubq);
2463                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2464                         gen_op_store_QT0_fpr(QFPREG(rd));
2465                         break;
2466                     case 0x49: /* fmuls */
2467                         CHECK_FPU_FEATURE(dc, FMUL);
2468                         gen_op_load_fpr_FT0(rs1);
2469                         gen_op_load_fpr_FT1(rs2);
2470                         gen_clear_float_exceptions();
2471                         tcg_gen_helper_0_0(helper_fmuls);
2472                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2473                         gen_op_store_FT0_fpr(rd);
2474                         break;
2475                     case 0x4a: /* fmuld */
2476                         CHECK_FPU_FEATURE(dc, FMUL);
2477                         gen_op_load_fpr_DT0(DFPREG(rs1));
2478                         gen_op_load_fpr_DT1(DFPREG(rs2));
2479                         gen_clear_float_exceptions();
2480                         tcg_gen_helper_0_0(helper_fmuld);
2481                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2482                         gen_op_store_DT0_fpr(DFPREG(rd));
2483                         break;
2484                     case 0x4b: /* fmulq */
2485                         CHECK_FPU_FEATURE(dc, FLOAT128);
2486                         CHECK_FPU_FEATURE(dc, FMUL);
2487                         gen_op_load_fpr_QT0(QFPREG(rs1));
2488                         gen_op_load_fpr_QT1(QFPREG(rs2));
2489                         gen_clear_float_exceptions();
2490                         tcg_gen_helper_0_0(helper_fmulq);
2491                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2492                         gen_op_store_QT0_fpr(QFPREG(rd));
2493                         break;
2494                     case 0x4d:
2495                         gen_op_load_fpr_FT0(rs1);
2496                         gen_op_load_fpr_FT1(rs2);
2497                         gen_clear_float_exceptions();
2498                         tcg_gen_helper_0_0(helper_fdivs);
2499                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2500                         gen_op_store_FT0_fpr(rd);
2501                         break;
2502                     case 0x4e:
2503                         gen_op_load_fpr_DT0(DFPREG(rs1));
2504                         gen_op_load_fpr_DT1(DFPREG(rs2));
2505                         gen_clear_float_exceptions();
2506                         tcg_gen_helper_0_0(helper_fdivd);
2507                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2508                         gen_op_store_DT0_fpr(DFPREG(rd));
2509                         break;
2510                     case 0x4f: /* fdivq */
2511                         CHECK_FPU_FEATURE(dc, FLOAT128);
2512                         gen_op_load_fpr_QT0(QFPREG(rs1));
2513                         gen_op_load_fpr_QT1(QFPREG(rs2));
2514                         gen_clear_float_exceptions();
2515                         tcg_gen_helper_0_0(helper_fdivq);
2516                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2517                         gen_op_store_QT0_fpr(QFPREG(rd));
2518                         break;
2519                     case 0x69:
2520                         CHECK_FPU_FEATURE(dc, FSMULD);
2521                         gen_op_load_fpr_FT0(rs1);
2522                         gen_op_load_fpr_FT1(rs2);
2523                         gen_clear_float_exceptions();
2524                         tcg_gen_helper_0_0(helper_fsmuld);
2525                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2526                         gen_op_store_DT0_fpr(DFPREG(rd));
2527                         break;
2528                     case 0x6e: /* fdmulq */
2529                         CHECK_FPU_FEATURE(dc, FLOAT128);
2530                         gen_op_load_fpr_DT0(DFPREG(rs1));
2531                         gen_op_load_fpr_DT1(DFPREG(rs2));
2532                         gen_clear_float_exceptions();
2533                         tcg_gen_helper_0_0(helper_fdmulq);
2534                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2535                         gen_op_store_QT0_fpr(QFPREG(rd));
2536                         break;
2537                     case 0xc4:
2538                         gen_op_load_fpr_FT1(rs2);
2539                         gen_clear_float_exceptions();
2540                         tcg_gen_helper_0_0(helper_fitos);
2541                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2542                         gen_op_store_FT0_fpr(rd);
2543                         break;
2544                     case 0xc6:
2545                         gen_op_load_fpr_DT1(DFPREG(rs2));
2546                         gen_clear_float_exceptions();
2547                         tcg_gen_helper_0_0(helper_fdtos);
2548                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2549                         gen_op_store_FT0_fpr(rd);
2550                         break;
2551                     case 0xc7: /* fqtos */
2552                         CHECK_FPU_FEATURE(dc, FLOAT128);
2553                         gen_op_load_fpr_QT1(QFPREG(rs2));
2554                         gen_clear_float_exceptions();
2555                         tcg_gen_helper_0_0(helper_fqtos);
2556                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2557                         gen_op_store_FT0_fpr(rd);
2558                         break;
2559                     case 0xc8:
2560                         gen_op_load_fpr_FT1(rs2);
2561                         tcg_gen_helper_0_0(helper_fitod);
2562                         gen_op_store_DT0_fpr(DFPREG(rd));
2563                         break;
2564                     case 0xc9:
2565                         gen_op_load_fpr_FT1(rs2);
2566                         tcg_gen_helper_0_0(helper_fstod);
2567                         gen_op_store_DT0_fpr(DFPREG(rd));
2568                         break;
2569                     case 0xcb: /* fqtod */
2570                         CHECK_FPU_FEATURE(dc, FLOAT128);
2571                         gen_op_load_fpr_QT1(QFPREG(rs2));
2572                         gen_clear_float_exceptions();
2573                         tcg_gen_helper_0_0(helper_fqtod);
2574                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2575                         gen_op_store_DT0_fpr(DFPREG(rd));
2576                         break;
2577                     case 0xcc: /* fitoq */
2578                         CHECK_FPU_FEATURE(dc, FLOAT128);
2579                         gen_op_load_fpr_FT1(rs2);
2580                         tcg_gen_helper_0_0(helper_fitoq);
2581                         gen_op_store_QT0_fpr(QFPREG(rd));
2582                         break;
2583                     case 0xcd: /* fstoq */
2584                         CHECK_FPU_FEATURE(dc, FLOAT128);
2585                         gen_op_load_fpr_FT1(rs2);
2586                         tcg_gen_helper_0_0(helper_fstoq);
2587                         gen_op_store_QT0_fpr(QFPREG(rd));
2588                         break;
2589                     case 0xce: /* fdtoq */
2590                         CHECK_FPU_FEATURE(dc, FLOAT128);
2591                         gen_op_load_fpr_DT1(DFPREG(rs2));
2592                         tcg_gen_helper_0_0(helper_fdtoq);
2593                         gen_op_store_QT0_fpr(QFPREG(rd));
2594                         break;
2595                     case 0xd1:
2596                         gen_op_load_fpr_FT1(rs2);
2597                         gen_clear_float_exceptions();
2598                         tcg_gen_helper_0_0(helper_fstoi);
2599                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2600                         gen_op_store_FT0_fpr(rd);
2601                         break;
2602                     case 0xd2:
2603                         gen_op_load_fpr_DT1(DFPREG(rs2));
2604                         gen_clear_float_exceptions();
2605                         tcg_gen_helper_0_0(helper_fdtoi);
2606                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2607                         gen_op_store_FT0_fpr(rd);
2608                         break;
2609                     case 0xd3: /* fqtoi */
2610                         CHECK_FPU_FEATURE(dc, FLOAT128);
2611                         gen_op_load_fpr_QT1(QFPREG(rs2));
2612                         gen_clear_float_exceptions();
2613                         tcg_gen_helper_0_0(helper_fqtoi);
2614                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2615                         gen_op_store_FT0_fpr(rd);
2616                         break;
2617 #ifdef TARGET_SPARC64
2618                     case 0x2: /* V9 fmovd */
2619                         gen_op_load_fpr_DT0(DFPREG(rs2));
2620                         gen_op_store_DT0_fpr(DFPREG(rd));
2621                         break;
2622                     case 0x3: /* V9 fmovq */
2623                         CHECK_FPU_FEATURE(dc, FLOAT128);
2624                         gen_op_load_fpr_QT0(QFPREG(rs2));
2625                         gen_op_store_QT0_fpr(QFPREG(rd));
2626                         break;
2627                     case 0x6: /* V9 fnegd */
2628                         gen_op_load_fpr_DT1(DFPREG(rs2));
2629                         tcg_gen_helper_0_0(helper_fnegd);
2630                         gen_op_store_DT0_fpr(DFPREG(rd));
2631                         break;
2632                     case 0x7: /* V9 fnegq */
2633                         CHECK_FPU_FEATURE(dc, FLOAT128);
2634                         gen_op_load_fpr_QT1(QFPREG(rs2));
2635                         tcg_gen_helper_0_0(helper_fnegq);
2636                         gen_op_store_QT0_fpr(QFPREG(rd));
2637                         break;
2638                     case 0xa: /* V9 fabsd */
2639                         gen_op_load_fpr_DT1(DFPREG(rs2));
2640                         tcg_gen_helper_0_0(helper_fabsd);
2641                         gen_op_store_DT0_fpr(DFPREG(rd));
2642                         break;
2643                     case 0xb: /* V9 fabsq */
2644                         CHECK_FPU_FEATURE(dc, FLOAT128);
2645                         gen_op_load_fpr_QT1(QFPREG(rs2));
2646                         tcg_gen_helper_0_0(helper_fabsq);
2647                         gen_op_store_QT0_fpr(QFPREG(rd));
2648                         break;
2649                     case 0x81: /* V9 fstox */
2650                         gen_op_load_fpr_FT1(rs2);
2651                         gen_clear_float_exceptions();
2652                         tcg_gen_helper_0_0(helper_fstox);
2653                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2654                         gen_op_store_DT0_fpr(DFPREG(rd));
2655                         break;
2656                     case 0x82: /* V9 fdtox */
2657                         gen_op_load_fpr_DT1(DFPREG(rs2));
2658                         gen_clear_float_exceptions();
2659                         tcg_gen_helper_0_0(helper_fdtox);
2660                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2661                         gen_op_store_DT0_fpr(DFPREG(rd));
2662                         break;
2663                     case 0x83: /* V9 fqtox */
2664                         CHECK_FPU_FEATURE(dc, FLOAT128);
2665                         gen_op_load_fpr_QT1(QFPREG(rs2));
2666                         gen_clear_float_exceptions();
2667                         tcg_gen_helper_0_0(helper_fqtox);
2668                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2669                         gen_op_store_DT0_fpr(DFPREG(rd));
2670                         break;
2671                     case 0x84: /* V9 fxtos */
2672                         gen_op_load_fpr_DT1(DFPREG(rs2));
2673                         gen_clear_float_exceptions();
2674                         tcg_gen_helper_0_0(helper_fxtos);
2675                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2676                         gen_op_store_FT0_fpr(rd);
2677                         break;
2678                     case 0x88: /* V9 fxtod */
2679                         gen_op_load_fpr_DT1(DFPREG(rs2));
2680                         gen_clear_float_exceptions();
2681                         tcg_gen_helper_0_0(helper_fxtod);
2682                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2683                         gen_op_store_DT0_fpr(DFPREG(rd));
2684                         break;
2685                     case 0x8c: /* V9 fxtoq */
2686                         CHECK_FPU_FEATURE(dc, FLOAT128);
2687                         gen_op_load_fpr_DT1(DFPREG(rs2));
2688                         gen_clear_float_exceptions();
2689                         tcg_gen_helper_0_0(helper_fxtoq);
2690                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2691                         gen_op_store_QT0_fpr(QFPREG(rd));
2692                         break;
2693 #endif
2694                     default:
2695                         goto illegal_insn;
2696                 }
2697             } else if (xop == 0x35) {   /* FPU Operations */
2698 #ifdef TARGET_SPARC64
2699                 int cond;
2700 #endif
2701                 if (gen_trap_ifnofpu(dc, cpu_cond))
2702                     goto jmp_insn;
2703                 gen_op_clear_ieee_excp_and_FTT();
2704                 rs1 = GET_FIELD(insn, 13, 17);
2705                 rs2 = GET_FIELD(insn, 27, 31);
2706                 xop = GET_FIELD(insn, 18, 26);
2707 #ifdef TARGET_SPARC64
2708                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2709                     int l1;
2710
2711                     l1 = gen_new_label();
2712                     cond = GET_FIELD_SP(insn, 14, 17);
2713                     cpu_src1 = get_src1(insn, cpu_src1);
2714                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2715                                        0, l1);
2716                     gen_op_load_fpr_FT0(rs2);
2717                     gen_op_store_FT0_fpr(rd);
2718                     gen_set_label(l1);
2719                     break;
2720                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2721                     int l1;
2722
2723                     l1 = gen_new_label();
2724                     cond = GET_FIELD_SP(insn, 14, 17);
2725                     cpu_src1 = get_src1(insn, cpu_src1);
2726                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2727                                        0, l1);
2728                     gen_op_load_fpr_DT0(DFPREG(rs2));
2729                     gen_op_store_DT0_fpr(DFPREG(rd));
2730                     gen_set_label(l1);
2731                     break;
2732                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2733                     int l1;
2734
2735                     CHECK_FPU_FEATURE(dc, FLOAT128);
2736                     l1 = gen_new_label();
2737                     cond = GET_FIELD_SP(insn, 14, 17);
2738                     cpu_src1 = get_src1(insn, cpu_src1);
2739                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2740                                        0, l1);
2741                     gen_op_load_fpr_QT0(QFPREG(rs2));
2742                     gen_op_store_QT0_fpr(QFPREG(rd));
2743                     gen_set_label(l1);
2744                     break;
2745                 }
2746 #endif
2747                 switch (xop) {
2748 #ifdef TARGET_SPARC64
2749 #define FMOVCC(size_FDQ, fcc)                                           \
2750                     {                                                   \
2751                         TCGv r_cond;                                    \
2752                         int l1;                                         \
2753                                                                         \
2754                         l1 = gen_new_label();                           \
2755                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2756                         cond = GET_FIELD_SP(insn, 14, 17);              \
2757                         gen_fcond(r_cond, fcc, cond);                   \
2758                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2759                                            0, l1);                      \
2760                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2761                             (glue(size_FDQ, FPREG(rs2)));               \
2762                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2763                             (glue(size_FDQ, FPREG(rd)));                \
2764                         gen_set_label(l1);                              \
2765                         tcg_temp_free(r_cond);                          \
2766                     }
2767                     case 0x001: /* V9 fmovscc %fcc0 */
2768                         FMOVCC(F, 0);
2769                         break;
2770                     case 0x002: /* V9 fmovdcc %fcc0 */
2771                         FMOVCC(D, 0);
2772                         break;
2773                     case 0x003: /* V9 fmovqcc %fcc0 */
2774                         CHECK_FPU_FEATURE(dc, FLOAT128);
2775                         FMOVCC(Q, 0);
2776                         break;
2777                     case 0x041: /* V9 fmovscc %fcc1 */
2778                         FMOVCC(F, 1);
2779                         break;
2780                     case 0x042: /* V9 fmovdcc %fcc1 */
2781                         FMOVCC(D, 1);
2782                         break;
2783                     case 0x043: /* V9 fmovqcc %fcc1 */
2784                         CHECK_FPU_FEATURE(dc, FLOAT128);
2785                         FMOVCC(Q, 1);
2786                         break;
2787                     case 0x081: /* V9 fmovscc %fcc2 */
2788                         FMOVCC(F, 2);
2789                         break;
2790                     case 0x082: /* V9 fmovdcc %fcc2 */
2791                         FMOVCC(D, 2);
2792                         break;
2793                     case 0x083: /* V9 fmovqcc %fcc2 */
2794                         CHECK_FPU_FEATURE(dc, FLOAT128);
2795                         FMOVCC(Q, 2);
2796                         break;
2797                     case 0x0c1: /* V9 fmovscc %fcc3 */
2798                         FMOVCC(F, 3);
2799                         break;
2800                     case 0x0c2: /* V9 fmovdcc %fcc3 */
2801                         FMOVCC(D, 3);
2802                         break;
2803                     case 0x0c3: /* V9 fmovqcc %fcc3 */
2804                         CHECK_FPU_FEATURE(dc, FLOAT128);
2805                         FMOVCC(Q, 3);
2806                         break;
2807 #undef FMOVCC
2808 #define FMOVCC(size_FDQ, icc)                                           \
2809                     {                                                   \
2810                         TCGv r_cond;                                    \
2811                         int l1;                                         \
2812                                                                         \
2813                         l1 = gen_new_label();                           \
2814                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2815                         cond = GET_FIELD_SP(insn, 14, 17);              \
2816                         gen_cond(r_cond, icc, cond);                    \
2817                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2818                                            0, l1);                      \
2819                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2820                             (glue(size_FDQ, FPREG(rs2)));               \
2821                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2822                             (glue(size_FDQ, FPREG(rd)));                \
2823                         gen_set_label(l1);                              \
2824                         tcg_temp_free(r_cond);                          \
2825                     }
2826
2827                     case 0x101: /* V9 fmovscc %icc */
2828                         FMOVCC(F, 0);
2829                         break;
2830                     case 0x102: /* V9 fmovdcc %icc */
2831                         FMOVCC(D, 0);
2832                     case 0x103: /* V9 fmovqcc %icc */
2833                         CHECK_FPU_FEATURE(dc, FLOAT128);
2834                         FMOVCC(Q, 0);
2835                         break;
2836                     case 0x181: /* V9 fmovscc %xcc */
2837                         FMOVCC(F, 1);
2838                         break;
2839                     case 0x182: /* V9 fmovdcc %xcc */
2840                         FMOVCC(D, 1);
2841                         break;
2842                     case 0x183: /* V9 fmovqcc %xcc */
2843                         CHECK_FPU_FEATURE(dc, FLOAT128);
2844                         FMOVCC(Q, 1);
2845                         break;
2846 #undef FMOVCC
2847 #endif
2848                     case 0x51: /* fcmps, V9 %fcc */
2849                         gen_op_load_fpr_FT0(rs1);
2850                         gen_op_load_fpr_FT1(rs2);
2851                         gen_op_fcmps(rd & 3);
2852                         break;
2853                     case 0x52: /* fcmpd, V9 %fcc */
2854                         gen_op_load_fpr_DT0(DFPREG(rs1));
2855                         gen_op_load_fpr_DT1(DFPREG(rs2));
2856                         gen_op_fcmpd(rd & 3);
2857                         break;
2858                     case 0x53: /* fcmpq, V9 %fcc */
2859                         CHECK_FPU_FEATURE(dc, FLOAT128);
2860                         gen_op_load_fpr_QT0(QFPREG(rs1));
2861                         gen_op_load_fpr_QT1(QFPREG(rs2));
2862                         gen_op_fcmpq(rd & 3);
2863                         break;
2864                     case 0x55: /* fcmpes, V9 %fcc */
2865                         gen_op_load_fpr_FT0(rs1);
2866                         gen_op_load_fpr_FT1(rs2);
2867                         gen_op_fcmpes(rd & 3);
2868                         break;
2869                     case 0x56: /* fcmped, V9 %fcc */
2870                         gen_op_load_fpr_DT0(DFPREG(rs1));
2871                         gen_op_load_fpr_DT1(DFPREG(rs2));
2872                         gen_op_fcmped(rd & 3);
2873                         break;
2874                     case 0x57: /* fcmpeq, V9 %fcc */
2875                         CHECK_FPU_FEATURE(dc, FLOAT128);
2876                         gen_op_load_fpr_QT0(QFPREG(rs1));
2877                         gen_op_load_fpr_QT1(QFPREG(rs2));
2878                         gen_op_fcmpeq(rd & 3);
2879                         break;
2880                     default:
2881                         goto illegal_insn;
2882                 }
2883             } else if (xop == 0x2) {
2884                 // clr/mov shortcut
2885
2886                 rs1 = GET_FIELD(insn, 13, 17);
2887                 if (rs1 == 0) {
2888                     // or %g0, x, y -> mov T0, x; mov y, T0
2889                     if (IS_IMM) {       /* immediate */
2890                         TCGv r_const;
2891
2892                         rs2 = GET_FIELDs(insn, 19, 31);
2893                         r_const = tcg_const_tl((int)rs2);
2894                         gen_movl_TN_reg(rd, r_const);
2895                         tcg_temp_free(r_const);
2896                     } else {            /* register */
2897                         rs2 = GET_FIELD(insn, 27, 31);
2898                         gen_movl_reg_TN(rs2, cpu_dst);
2899                         gen_movl_TN_reg(rd, cpu_dst);
2900                     }
2901                 } else {
2902                     cpu_src1 = get_src1(insn, cpu_src1);
2903                     if (IS_IMM) {       /* immediate */
2904                         rs2 = GET_FIELDs(insn, 19, 31);
2905                         tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2906                         gen_movl_TN_reg(rd, cpu_dst);
2907                     } else {            /* register */
2908                         // or x, %g0, y -> mov T1, x; mov y, T1
2909                         rs2 = GET_FIELD(insn, 27, 31);
2910                         if (rs2 != 0) {
2911                             gen_movl_reg_TN(rs2, cpu_src2);
2912                             tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2913                             gen_movl_TN_reg(rd, cpu_dst);
2914                         } else
2915                             gen_movl_TN_reg(rd, cpu_src1);
2916                     }
2917                 }
2918 #ifdef TARGET_SPARC64
2919             } else if (xop == 0x25) { /* sll, V9 sllx */
2920                 cpu_src1 = get_src1(insn, cpu_src1);
2921                 if (IS_IMM) {   /* immediate */
2922                     rs2 = GET_FIELDs(insn, 20, 31);
2923                     if (insn & (1 << 12)) {
2924                         tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2925                     } else {
2926                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2927                         tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2928                     }
2929                 } else {                /* register */
2930                     rs2 = GET_FIELD(insn, 27, 31);
2931                     gen_movl_reg_TN(rs2, cpu_src2);
2932                     if (insn & (1 << 12)) {
2933                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2934                         tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2935                     } else {
2936                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2937                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2938                         tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2939                     }
2940                 }
2941                 gen_movl_TN_reg(rd, cpu_dst);
2942             } else if (xop == 0x26) { /* srl, V9 srlx */
2943                 cpu_src1 = get_src1(insn, cpu_src1);
2944                 if (IS_IMM) {   /* immediate */
2945                     rs2 = GET_FIELDs(insn, 20, 31);
2946                     if (insn & (1 << 12)) {
2947                         tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2948                     } else {
2949                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2950                         tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2951                     }
2952                 } else {                /* register */
2953                     rs2 = GET_FIELD(insn, 27, 31);
2954                     gen_movl_reg_TN(rs2, cpu_src2);
2955                     if (insn & (1 << 12)) {
2956                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2957                         tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2958                     } else {
2959                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2960                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2961                         tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2962                     }
2963                 }
2964                 gen_movl_TN_reg(rd, cpu_dst);
2965             } else if (xop == 0x27) { /* sra, V9 srax */
2966                 cpu_src1 = get_src1(insn, cpu_src1);
2967                 if (IS_IMM) {   /* immediate */
2968                     rs2 = GET_FIELDs(insn, 20, 31);
2969                     if (insn & (1 << 12)) {
2970                         tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2971                     } else {
2972                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2973                         tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2974                         tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2975                     }
2976                 } else {                /* register */
2977                     rs2 = GET_FIELD(insn, 27, 31);
2978                     gen_movl_reg_TN(rs2, cpu_src2);
2979                     if (insn & (1 << 12)) {
2980                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2981                         tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2982                     } else {
2983                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2984                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2985                         tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2986                     }
2987                 }
2988                 gen_movl_TN_reg(rd, cpu_dst);
2989 #endif
2990             } else if (xop < 0x36) {
2991                 cpu_src1 = get_src1(insn, cpu_src1);
2992                 cpu_src2 = get_src2(insn, cpu_src2);
2993                 if (xop < 0x20) {
2994                     switch (xop & ~0x10) {
2995                     case 0x0:
2996                         if (xop & 0x10)
2997                             gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2998                         else
2999                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3000                         break;
3001                     case 0x1:
3002                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
3003                         if (xop & 0x10)
3004                             gen_op_logic_cc(cpu_dst);
3005                         break;
3006                     case 0x2:
3007                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3008                         if (xop & 0x10)
3009                             gen_op_logic_cc(cpu_dst);
3010                         break;
3011                     case 0x3:
3012                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3013                         if (xop & 0x10)
3014                             gen_op_logic_cc(cpu_dst);
3015                         break;
3016                     case 0x4:
3017                         if (xop & 0x10)
3018                             gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3019                         else
3020                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3021                         break;
3022                     case 0x5:
3023                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3024                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3025                         if (xop & 0x10)
3026                             gen_op_logic_cc(cpu_dst);
3027                         break;
3028                     case 0x6:
3029                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3030                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3031                         if (xop & 0x10)
3032                             gen_op_logic_cc(cpu_dst);
3033                         break;
3034                     case 0x7:
3035                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3036                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3037                         if (xop & 0x10)
3038                             gen_op_logic_cc(cpu_dst);
3039                         break;
3040                     case 0x8:
3041                         if (xop & 0x10)
3042                             gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3043                         else {
3044                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3045                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3046                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3047                         }
3048                         break;
3049 #ifdef TARGET_SPARC64
3050                     case 0x9: /* V9 mulx */
3051                         tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3052                         break;
3053 #endif
3054                     case 0xa:
3055                         CHECK_IU_FEATURE(dc, MUL);
3056                         gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3057                         if (xop & 0x10)
3058                             gen_op_logic_cc(cpu_dst);
3059                         break;
3060                     case 0xb:
3061                         CHECK_IU_FEATURE(dc, MUL);
3062                         gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3063                         if (xop & 0x10)
3064                             gen_op_logic_cc(cpu_dst);
3065                         break;
3066                     case 0xc:
3067                         if (xop & 0x10)
3068                             gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3069                         else {
3070                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3071                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3072                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3073                         }
3074                         break;
3075 #ifdef TARGET_SPARC64
3076                     case 0xd: /* V9 udivx */
3077                         tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3078                         tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3079                         gen_trap_ifdivzero_tl(cpu_cc_src2);
3080                         tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3081                         break;
3082 #endif
3083                     case 0xe:
3084                         CHECK_IU_FEATURE(dc, DIV);
3085                         tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3086                                            cpu_src2);
3087                         if (xop & 0x10)
3088                             gen_op_div_cc(cpu_dst);
3089                         break;
3090                     case 0xf:
3091                         CHECK_IU_FEATURE(dc, DIV);
3092                         tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3093                                            cpu_src2);
3094                         if (xop & 0x10)
3095                             gen_op_div_cc(cpu_dst);
3096                         break;
3097                     default:
3098                         goto illegal_insn;
3099                     }
3100                     gen_movl_TN_reg(rd, cpu_dst);
3101                 } else {
3102                     switch (xop) {
3103                     case 0x20: /* taddcc */
3104                         gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3105                         gen_movl_TN_reg(rd, cpu_dst);
3106                         break;
3107                     case 0x21: /* tsubcc */
3108                         gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3109                         gen_movl_TN_reg(rd, cpu_dst);
3110                         break;
3111                     case 0x22: /* taddcctv */
3112                         save_state(dc, cpu_cond);
3113                         gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3114                         gen_movl_TN_reg(rd, cpu_dst);
3115                         break;
3116                     case 0x23: /* tsubcctv */
3117                         save_state(dc, cpu_cond);
3118                         gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3119                         gen_movl_TN_reg(rd, cpu_dst);
3120                         break;
3121                     case 0x24: /* mulscc */
3122                         gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3123                         gen_movl_TN_reg(rd, cpu_dst);
3124                         break;
3125 #ifndef TARGET_SPARC64
3126                     case 0x25:  /* sll */
3127                         if (IS_IMM) { /* immediate */
3128                             rs2 = GET_FIELDs(insn, 20, 31);
3129                             tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3130                         } else { /* register */
3131                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3132                             tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3133                         }
3134                         gen_movl_TN_reg(rd, cpu_dst);
3135                         break;
3136                     case 0x26:  /* srl */
3137                         if (IS_IMM) { /* immediate */
3138                             rs2 = GET_FIELDs(insn, 20, 31);
3139                             tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3140                         } else { /* register */
3141                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3142                             tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3143                         }
3144                         gen_movl_TN_reg(rd, cpu_dst);
3145                         break;
3146                     case 0x27:  /* sra */
3147                         if (IS_IMM) { /* immediate */
3148                             rs2 = GET_FIELDs(insn, 20, 31);
3149                             tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3150                         } else { /* register */
3151                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3152                             tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3153                         }
3154                         gen_movl_TN_reg(rd, cpu_dst);
3155                         break;
3156 #endif
3157                     case 0x30:
3158                         {
3159                             switch(rd) {
3160                             case 0: /* wry */
3161                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3162                                 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3163                                               offsetof(CPUSPARCState, y));
3164                                 break;
3165 #ifndef TARGET_SPARC64
3166                             case 0x01 ... 0x0f: /* undefined in the
3167                                                    SPARCv8 manual, nop
3168                                                    on the microSPARC
3169                                                    II */
3170                             case 0x10 ... 0x1f: /* implementation-dependent
3171                                                    in the SPARCv8
3172                                                    manual, nop on the
3173                                                    microSPARC II */
3174                                 break;
3175 #else
3176                             case 0x2: /* V9 wrccr */
3177                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3178                                 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3179                                 break;
3180                             case 0x3: /* V9 wrasi */
3181                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3182                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3183                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3184                                                offsetof(CPUSPARCState, asi));
3185                                 break;
3186                             case 0x6: /* V9 wrfprs */
3187                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3188                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3189                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3190                                                offsetof(CPUSPARCState, fprs));
3191                                 save_state(dc, cpu_cond);
3192                                 gen_op_next_insn();
3193                                 tcg_gen_exit_tb(0);
3194                                 dc->is_br = 1;
3195                                 break;
3196                             case 0xf: /* V9 sir, nop if user */
3197 #if !defined(CONFIG_USER_ONLY)
3198                                 if (supervisor(dc))
3199                                     ; // XXX
3200 #endif
3201                                 break;
3202                             case 0x13: /* Graphics Status */
3203                                 if (gen_trap_ifnofpu(dc, cpu_cond))
3204                                     goto jmp_insn;
3205                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3206                                 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3207                                               offsetof(CPUSPARCState, gsr));
3208                                 break;
3209                             case 0x17: /* Tick compare */
3210 #if !defined(CONFIG_USER_ONLY)
3211                                 if (!supervisor(dc))
3212                                     goto illegal_insn;
3213 #endif
3214                                 {
3215                                     TCGv r_tickptr;
3216
3217                                     tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3218                                                    cpu_src2);
3219                                     tcg_gen_st_tl(cpu_tmp0, cpu_env,
3220                                                   offsetof(CPUSPARCState,
3221                                                            tick_cmpr));
3222                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3223                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3224                                                    offsetof(CPUState, tick));
3225                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3226                                                        r_tickptr, cpu_tmp0);
3227                                     tcg_temp_free(r_tickptr);
3228                                 }
3229                                 break;
3230                             case 0x18: /* System tick */
3231 #if !defined(CONFIG_USER_ONLY)
3232                                 if (!supervisor(dc))
3233                                     goto illegal_insn;
3234 #endif
3235                                 {
3236                                     TCGv r_tickptr;
3237
3238                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3239                                                    cpu_src2);
3240                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3241                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3242                                                    offsetof(CPUState, stick));
3243                                     tcg_gen_helper_0_2(helper_tick_set_count,
3244                                                        r_tickptr, cpu_dst);
3245                                     tcg_temp_free(r_tickptr);
3246                                 }
3247                                 break;
3248                             case 0x19: /* System tick compare */
3249 #if !defined(CONFIG_USER_ONLY)
3250                                 if (!supervisor(dc))
3251                                     goto illegal_insn;
3252 #endif
3253                                 {
3254                                     TCGv r_tickptr;
3255
3256                                     tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3257                                                    cpu_src2);
3258                                     tcg_gen_st_tl(cpu_tmp0, cpu_env,
3259                                                   offsetof(CPUSPARCState,
3260                                                            stick_cmpr));
3261                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3262                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3263                                                    offsetof(CPUState, stick));
3264                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3265                                                        r_tickptr, cpu_tmp0);
3266                                     tcg_temp_free(r_tickptr);
3267                                 }
3268                                 break;
3269
3270                             case 0x10: /* Performance Control */
3271                             case 0x11: /* Performance Instrumentation
3272                                           Counter */
3273                             case 0x12: /* Dispatch Control */
3274                             case 0x14: /* Softint set */
3275                             case 0x15: /* Softint clear */
3276                             case 0x16: /* Softint write */
3277 #endif
3278                             default:
3279                                 goto illegal_insn;
3280                             }
3281                         }
3282                         break;
3283 #if !defined(CONFIG_USER_ONLY)
3284                     case 0x31: /* wrpsr, V9 saved, restored */
3285                         {
3286                             if (!supervisor(dc))
3287                                 goto priv_insn;
3288 #ifdef TARGET_SPARC64
3289                             switch (rd) {
3290                             case 0:
3291                                 tcg_gen_helper_0_0(helper_saved);
3292                                 break;
3293                             case 1:
3294                                 tcg_gen_helper_0_0(helper_restored);
3295                                 break;
3296                             case 2: /* UA2005 allclean */
3297                             case 3: /* UA2005 otherw */
3298                             case 4: /* UA2005 normalw */
3299                             case 5: /* UA2005 invalw */
3300                                 // XXX
3301                             default:
3302                                 goto illegal_insn;
3303                             }
3304 #else
3305                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3306                             tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3307                             save_state(dc, cpu_cond);
3308                             gen_op_next_insn();
3309                             tcg_gen_exit_tb(0);
3310                             dc->is_br = 1;
3311 #endif
3312                         }
3313                         break;
3314                     case 0x32: /* wrwim, V9 wrpr */
3315                         {
3316                             if (!supervisor(dc))
3317                                 goto priv_insn;
3318                             tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3319 #ifdef TARGET_SPARC64
3320                             switch (rd) {
3321                             case 0: // tpc
3322                                 {
3323                                     TCGv r_tsptr;
3324
3325                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3326                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3327                                                    offsetof(CPUState, tsptr));
3328                                     tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3329                                                   offsetof(trap_state, tpc));
3330                                     tcg_temp_free(r_tsptr);
3331                                 }
3332                                 break;
3333                             case 1: // tnpc
3334                                 {
3335                                     TCGv r_tsptr;
3336
3337                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3338                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3339                                                    offsetof(CPUState, tsptr));
3340                                     tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3341                                                   offsetof(trap_state, tnpc));
3342                                     tcg_temp_free(r_tsptr);
3343                                 }
3344                                 break;
3345                             case 2: // tstate
3346                                 {
3347                                     TCGv r_tsptr;
3348
3349                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3350                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3351                                                    offsetof(CPUState, tsptr));
3352                                     tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3353                                                   offsetof(trap_state,
3354                                                            tstate));
3355                                     tcg_temp_free(r_tsptr);
3356                                 }
3357                                 break;
3358                             case 3: // tt
3359                                 {
3360                                     TCGv r_tsptr;
3361
3362                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3363                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3364                                                    offsetof(CPUState, tsptr));
3365                                     tcg_gen_st_i32(cpu_tmp0, r_tsptr,
3366                                                    offsetof(trap_state, tt));
3367                                     tcg_temp_free(r_tsptr);
3368                                 }
3369                                 break;
3370                             case 4: // tick
3371                                 {
3372                                     TCGv r_tickptr;
3373
3374                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3375                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3376                                                    offsetof(CPUState, tick));
3377                                     tcg_gen_helper_0_2(helper_tick_set_count,
3378                                                        r_tickptr, cpu_tmp0);
3379                                     tcg_temp_free(r_tickptr);
3380                                 }
3381                                 break;
3382                             case 5: // tba
3383                                 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3384                                               offsetof(CPUSPARCState, tbr));
3385                                 break;
3386                             case 6: // pstate
3387                                 save_state(dc, cpu_cond);
3388                                 tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
3389                                 gen_op_next_insn();
3390                                 tcg_gen_exit_tb(0);
3391                                 dc->is_br = 1;
3392                                 break;
3393                             case 7: // tl
3394                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3395                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3396                                                offsetof(CPUSPARCState, tl));
3397                                 break;
3398                             case 8: // pil
3399                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3400                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3401                                                offsetof(CPUSPARCState,
3402                                                         psrpil));
3403                                 break;
3404                             case 9: // cwp
3405                                 tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
3406                                 break;
3407                             case 10: // cansave
3408                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3409                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3410                                                offsetof(CPUSPARCState,
3411                                                         cansave));
3412                                 break;
3413                             case 11: // canrestore
3414                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3415                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3416                                                offsetof(CPUSPARCState,
3417                                                         canrestore));
3418                                 break;
3419                             case 12: // cleanwin
3420                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3421                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3422                                                offsetof(CPUSPARCState,
3423                                                         cleanwin));
3424                                 break;
3425                             case 13: // otherwin
3426                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3427                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3428                                                offsetof(CPUSPARCState,
3429                                                         otherwin));
3430                                 break;
3431                             case 14: // wstate
3432                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3433                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3434                                                offsetof(CPUSPARCState,
3435                                                         wstate));
3436                                 break;
3437                             case 16: // UA2005 gl
3438                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3439                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3440                                                offsetof(CPUSPARCState, gl));
3441                                 break;
3442                             case 26: // UA2005 strand status
3443                                 if (!hypervisor(dc))
3444                                     goto priv_insn;
3445                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3446                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3447                                                offsetof(CPUSPARCState, ssr));
3448                                 break;
3449                             default:
3450                                 goto illegal_insn;
3451                             }
3452 #else
3453                             tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3454                             tcg_gen_st_i32(cpu_tmp32, cpu_env,
3455                                            offsetof(CPUSPARCState, wim));
3456 #endif
3457                         }
3458                         break;
3459                     case 0x33: /* wrtbr, UA2005 wrhpr */
3460                         {
3461 #ifndef TARGET_SPARC64
3462                             if (!supervisor(dc))
3463                                 goto priv_insn;
3464                             tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3465                             tcg_gen_st_tl(cpu_tmp0, cpu_env,
3466                                           offsetof(CPUSPARCState, tbr));
3467 #else
3468                             if (!hypervisor(dc))
3469                                 goto priv_insn;
3470                             tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3471                             switch (rd) {
3472                             case 0: // hpstate
3473                                 // XXX gen_op_wrhpstate();
3474                                 save_state(dc, cpu_cond);
3475                                 gen_op_next_insn();
3476                                 tcg_gen_exit_tb(0);
3477                                 dc->is_br = 1;
3478                                 break;
3479                             case 1: // htstate
3480                                 // XXX gen_op_wrhtstate();
3481                                 break;
3482                             case 3: // hintp
3483                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3484                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3485                                                offsetof(CPUSPARCState, hintp));
3486                                 break;
3487                             case 5: // htba
3488                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3489                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3490                                                offsetof(CPUSPARCState, htba));
3491                                 break;
3492                             case 31: // hstick_cmpr
3493                                 {
3494                                     TCGv r_tickptr;
3495
3496                                     tcg_gen_st_tl(cpu_tmp0, cpu_env,
3497                                                   offsetof(CPUSPARCState,
3498                                                            hstick_cmpr));
3499                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3500                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3501                                                    offsetof(CPUState, hstick));
3502                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3503                                                        r_tickptr, cpu_tmp0);
3504                                     tcg_temp_free(r_tickptr);
3505                                 }
3506                                 break;
3507                             case 6: // hver readonly
3508                             default:
3509                                 goto illegal_insn;
3510                             }
3511 #endif
3512                         }
3513                         break;
3514 #endif
3515 #ifdef TARGET_SPARC64
3516                     case 0x2c: /* V9 movcc */
3517                         {
3518                             int cc = GET_FIELD_SP(insn, 11, 12);
3519                             int cond = GET_FIELD_SP(insn, 14, 17);
3520                             TCGv r_cond;
3521                             int l1;
3522
3523                             r_cond = tcg_temp_new(TCG_TYPE_TL);
3524                             if (insn & (1 << 18)) {
3525                                 if (cc == 0)
3526                                     gen_cond(r_cond, 0, cond);
3527                                 else if (cc == 2)
3528                                     gen_cond(r_cond, 1, cond);
3529                                 else
3530                                     goto illegal_insn;
3531                             } else {
3532                                 gen_fcond(r_cond, cc, cond);
3533                             }
3534
3535                             l1 = gen_new_label();
3536
3537                             tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3538                             if (IS_IMM) {       /* immediate */
3539                                 TCGv r_const;
3540
3541                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
3542                                 r_const = tcg_const_tl((int)rs2);
3543                                 gen_movl_TN_reg(rd, r_const);
3544                                 tcg_temp_free(r_const);
3545                             } else {
3546                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3547                                 gen_movl_reg_TN(rs2, cpu_tmp0);
3548                                 gen_movl_TN_reg(rd, cpu_tmp0);
3549                             }
3550                             gen_set_label(l1);
3551                             tcg_temp_free(r_cond);
3552                             break;
3553                         }
3554                     case 0x2d: /* V9 sdivx */
3555                         gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3556                         gen_movl_TN_reg(rd, cpu_dst);
3557                         break;
3558                     case 0x2e: /* V9 popc */
3559                         {
3560                             cpu_src2 = get_src2(insn, cpu_src2);
3561                             tcg_gen_helper_1_1(helper_popc, cpu_dst,
3562                                                cpu_src2);
3563                             gen_movl_TN_reg(rd, cpu_dst);
3564                         }
3565                     case 0x2f: /* V9 movr */
3566                         {
3567                             int cond = GET_FIELD_SP(insn, 10, 12);
3568                             int l1;
3569
3570                             cpu_src1 = get_src1(insn, cpu_src1);
3571
3572                             l1 = gen_new_label();
3573
3574                             tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3575                                               cpu_src1, 0, l1);
3576                             if (IS_IMM) {       /* immediate */
3577                                 TCGv r_const;
3578
3579                                 rs2 = GET_FIELD_SPs(insn, 0, 9);
3580                                 r_const = tcg_const_tl((int)rs2);
3581                                 gen_movl_TN_reg(rd, r_const);
3582                                 tcg_temp_free(r_const);
3583                             } else {
3584                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3585                                 gen_movl_reg_TN(rs2, cpu_tmp0);
3586                                 gen_movl_TN_reg(rd, cpu_tmp0);
3587                             }
3588                             gen_set_label(l1);
3589                             break;
3590                         }
3591 #endif
3592                     default:
3593                         goto illegal_insn;
3594                     }
3595                 }
3596             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3597 #ifdef TARGET_SPARC64
3598                 int opf = GET_FIELD_SP(insn, 5, 13);
3599                 rs1 = GET_FIELD(insn, 13, 17);
3600                 rs2 = GET_FIELD(insn, 27, 31);
3601                 if (gen_trap_ifnofpu(dc, cpu_cond))
3602                     goto jmp_insn;
3603
3604                 switch (opf) {
3605                 case 0x000: /* VIS I edge8cc */
3606                 case 0x001: /* VIS II edge8n */
3607                 case 0x002: /* VIS I edge8lcc */
3608                 case 0x003: /* VIS II edge8ln */
3609                 case 0x004: /* VIS I edge16cc */
3610                 case 0x005: /* VIS II edge16n */
3611                 case 0x006: /* VIS I edge16lcc */
3612                 case 0x007: /* VIS II edge16ln */
3613                 case 0x008: /* VIS I edge32cc */
3614                 case 0x009: /* VIS II edge32n */
3615                 case 0x00a: /* VIS I edge32lcc */
3616                 case 0x00b: /* VIS II edge32ln */
3617                     // XXX
3618                     goto illegal_insn;
3619                 case 0x010: /* VIS I array8 */
3620                     CHECK_FPU_FEATURE(dc, VIS1);
3621                     cpu_src1 = get_src1(insn, cpu_src1);
3622                     gen_movl_reg_TN(rs2, cpu_src2);
3623                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3624                                        cpu_src2);
3625                     gen_movl_TN_reg(rd, cpu_dst);
3626                     break;
3627                 case 0x012: /* VIS I array16 */
3628                     CHECK_FPU_FEATURE(dc, VIS1);
3629                     cpu_src1 = get_src1(insn, cpu_src1);
3630                     gen_movl_reg_TN(rs2, cpu_src2);
3631                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3632                                        cpu_src2);
3633                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3634                     gen_movl_TN_reg(rd, cpu_dst);
3635                     break;
3636                 case 0x014: /* VIS I array32 */
3637                     CHECK_FPU_FEATURE(dc, VIS1);
3638                     cpu_src1 = get_src1(insn, cpu_src1);
3639                     gen_movl_reg_TN(rs2, cpu_src2);
3640                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3641                                        cpu_src2);
3642                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3643                     gen_movl_TN_reg(rd, cpu_dst);
3644                     break;
3645                 case 0x018: /* VIS I alignaddr */
3646                     CHECK_FPU_FEATURE(dc, VIS1);
3647                     cpu_src1 = get_src1(insn, cpu_src1);
3648                     gen_movl_reg_TN(rs2, cpu_src2);
3649                     tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3650                                        cpu_src2);
3651                     gen_movl_TN_reg(rd, cpu_dst);
3652                     break;
3653                 case 0x019: /* VIS II bmask */
3654                 case 0x01a: /* VIS I alignaddrl */
3655                     // XXX
3656                     goto illegal_insn;
3657                 case 0x020: /* VIS I fcmple16 */
3658                     CHECK_FPU_FEATURE(dc, VIS1);
3659                     gen_op_load_fpr_DT0(DFPREG(rs1));
3660                     gen_op_load_fpr_DT1(DFPREG(rs2));
3661                     tcg_gen_helper_0_0(helper_fcmple16);
3662                     gen_op_store_DT0_fpr(DFPREG(rd));
3663                     break;
3664                 case 0x022: /* VIS I fcmpne16 */
3665                     CHECK_FPU_FEATURE(dc, VIS1);
3666                     gen_op_load_fpr_DT0(DFPREG(rs1));
3667                     gen_op_load_fpr_DT1(DFPREG(rs2));
3668                     tcg_gen_helper_0_0(helper_fcmpne16);
3669                     gen_op_store_DT0_fpr(DFPREG(rd));
3670                     break;
3671                 case 0x024: /* VIS I fcmple32 */
3672                     CHECK_FPU_FEATURE(dc, VIS1);
3673                     gen_op_load_fpr_DT0(DFPREG(rs1));
3674                     gen_op_load_fpr_DT1(DFPREG(rs2));
3675                     tcg_gen_helper_0_0(helper_fcmple32);
3676                     gen_op_store_DT0_fpr(DFPREG(rd));
3677                     break;
3678                 case 0x026: /* VIS I fcmpne32 */
3679                     CHECK_FPU_FEATURE(dc, VIS1);
3680                     gen_op_load_fpr_DT0(DFPREG(rs1));
3681                     gen_op_load_fpr_DT1(DFPREG(rs2));
3682                     tcg_gen_helper_0_0(helper_fcmpne32);
3683                     gen_op_store_DT0_fpr(DFPREG(rd));
3684                     break;
3685                 case 0x028: /* VIS I fcmpgt16 */
3686                     CHECK_FPU_FEATURE(dc, VIS1);
3687                     gen_op_load_fpr_DT0(DFPREG(rs1));
3688                     gen_op_load_fpr_DT1(DFPREG(rs2));
3689                     tcg_gen_helper_0_0(helper_fcmpgt16);
3690                     gen_op_store_DT0_fpr(DFPREG(rd));
3691                     break;
3692                 case 0x02a: /* VIS I fcmpeq16 */
3693                     CHECK_FPU_FEATURE(dc, VIS1);
3694                     gen_op_load_fpr_DT0(DFPREG(rs1));
3695                     gen_op_load_fpr_DT1(DFPREG(rs2));
3696                     tcg_gen_helper_0_0(helper_fcmpeq16);
3697                     gen_op_store_DT0_fpr(DFPREG(rd));
3698                     break;
3699                 case 0x02c: /* VIS I fcmpgt32 */
3700                     CHECK_FPU_FEATURE(dc, VIS1);
3701                     gen_op_load_fpr_DT0(DFPREG(rs1));
3702                     gen_op_load_fpr_DT1(DFPREG(rs2));
3703                     tcg_gen_helper_0_0(helper_fcmpgt32);
3704                     gen_op_store_DT0_fpr(DFPREG(rd));
3705                     break;
3706                 case 0x02e: /* VIS I fcmpeq32 */
3707                     CHECK_FPU_FEATURE(dc, VIS1);
3708                     gen_op_load_fpr_DT0(DFPREG(rs1));
3709                     gen_op_load_fpr_DT1(DFPREG(rs2));
3710                     tcg_gen_helper_0_0(helper_fcmpeq32);
3711                     gen_op_store_DT0_fpr(DFPREG(rd));
3712                     break;
3713                 case 0x031: /* VIS I fmul8x16 */
3714                     CHECK_FPU_FEATURE(dc, VIS1);
3715                     gen_op_load_fpr_DT0(DFPREG(rs1));
3716                     gen_op_load_fpr_DT1(DFPREG(rs2));
3717                     tcg_gen_helper_0_0(helper_fmul8x16);
3718                     gen_op_store_DT0_fpr(DFPREG(rd));
3719                     break;
3720                 case 0x033: /* VIS I fmul8x16au */
3721                     CHECK_FPU_FEATURE(dc, VIS1);
3722                     gen_op_load_fpr_DT0(DFPREG(rs1));
3723                     gen_op_load_fpr_DT1(DFPREG(rs2));
3724                     tcg_gen_helper_0_0(helper_fmul8x16au);
3725                     gen_op_store_DT0_fpr(DFPREG(rd));
3726                     break;
3727                 case 0x035: /* VIS I fmul8x16al */
3728                     CHECK_FPU_FEATURE(dc, VIS1);
3729                     gen_op_load_fpr_DT0(DFPREG(rs1));
3730                     gen_op_load_fpr_DT1(DFPREG(rs2));
3731                     tcg_gen_helper_0_0(helper_fmul8x16al);
3732                     gen_op_store_DT0_fpr(DFPREG(rd));
3733                     break;
3734                 case 0x036: /* VIS I fmul8sux16 */
3735                     CHECK_FPU_FEATURE(dc, VIS1);
3736                     gen_op_load_fpr_DT0(DFPREG(rs1));
3737                     gen_op_load_fpr_DT1(DFPREG(rs2));
3738                     tcg_gen_helper_0_0(helper_fmul8sux16);
3739                     gen_op_store_DT0_fpr(DFPREG(rd));
3740                     break;
3741                 case 0x037: /* VIS I fmul8ulx16 */
3742                     CHECK_FPU_FEATURE(dc, VIS1);
3743                     gen_op_load_fpr_DT0(DFPREG(rs1));
3744                     gen_op_load_fpr_DT1(DFPREG(rs2));
3745                     tcg_gen_helper_0_0(helper_fmul8ulx16);
3746                     gen_op_store_DT0_fpr(DFPREG(rd));
3747                     break;
3748                 case 0x038: /* VIS I fmuld8sux16 */
3749                     CHECK_FPU_FEATURE(dc, VIS1);
3750                     gen_op_load_fpr_DT0(DFPREG(rs1));
3751                     gen_op_load_fpr_DT1(DFPREG(rs2));
3752                     tcg_gen_helper_0_0(helper_fmuld8sux16);
3753                     gen_op_store_DT0_fpr(DFPREG(rd));
3754                     break;
3755                 case 0x039: /* VIS I fmuld8ulx16 */
3756                     CHECK_FPU_FEATURE(dc, VIS1);
3757                     gen_op_load_fpr_DT0(DFPREG(rs1));
3758                     gen_op_load_fpr_DT1(DFPREG(rs2));
3759                     tcg_gen_helper_0_0(helper_fmuld8ulx16);
3760                     gen_op_store_DT0_fpr(DFPREG(rd));
3761                     break;
3762                 case 0x03a: /* VIS I fpack32 */
3763                 case 0x03b: /* VIS I fpack16 */
3764                 case 0x03d: /* VIS I fpackfix */
3765                 case 0x03e: /* VIS I pdist */
3766                     // XXX
3767                     goto illegal_insn;
3768                 case 0x048: /* VIS I faligndata */
3769                     CHECK_FPU_FEATURE(dc, VIS1);
3770                     gen_op_load_fpr_DT0(DFPREG(rs1));
3771                     gen_op_load_fpr_DT1(DFPREG(rs2));
3772                     tcg_gen_helper_0_0(helper_faligndata);
3773                     gen_op_store_DT0_fpr(DFPREG(rd));
3774                     break;
3775                 case 0x04b: /* VIS I fpmerge */
3776                     CHECK_FPU_FEATURE(dc, VIS1);
3777                     gen_op_load_fpr_DT0(DFPREG(rs1));
3778                     gen_op_load_fpr_DT1(DFPREG(rs2));
3779                     tcg_gen_helper_0_0(helper_fpmerge);
3780                     gen_op_store_DT0_fpr(DFPREG(rd));
3781                     break;
3782                 case 0x04c: /* VIS II bshuffle */
3783                     // XXX
3784                     goto illegal_insn;
3785                 case 0x04d: /* VIS I fexpand */
3786                     CHECK_FPU_FEATURE(dc, VIS1);
3787                     gen_op_load_fpr_DT0(DFPREG(rs1));
3788                     gen_op_load_fpr_DT1(DFPREG(rs2));
3789                     tcg_gen_helper_0_0(helper_fexpand);
3790                     gen_op_store_DT0_fpr(DFPREG(rd));
3791                     break;
3792                 case 0x050: /* VIS I fpadd16 */
3793                     CHECK_FPU_FEATURE(dc, VIS1);
3794                     gen_op_load_fpr_DT0(DFPREG(rs1));
3795                     gen_op_load_fpr_DT1(DFPREG(rs2));
3796                     tcg_gen_helper_0_0(helper_fpadd16);
3797                     gen_op_store_DT0_fpr(DFPREG(rd));
3798                     break;
3799                 case 0x051: /* VIS I fpadd16s */
3800                     CHECK_FPU_FEATURE(dc, VIS1);
3801                     gen_op_load_fpr_FT0(rs1);
3802                     gen_op_load_fpr_FT1(rs2);
3803                     tcg_gen_helper_0_0(helper_fpadd16s);
3804                     gen_op_store_FT0_fpr(rd);
3805                     break;
3806                 case 0x052: /* VIS I fpadd32 */
3807                     CHECK_FPU_FEATURE(dc, VIS1);
3808                     gen_op_load_fpr_DT0(DFPREG(rs1));
3809                     gen_op_load_fpr_DT1(DFPREG(rs2));
3810                     tcg_gen_helper_0_0(helper_fpadd32);
3811                     gen_op_store_DT0_fpr(DFPREG(rd));
3812                     break;
3813                 case 0x053: /* VIS I fpadd32s */
3814                     CHECK_FPU_FEATURE(dc, VIS1);
3815                     gen_op_load_fpr_FT0(rs1);
3816                     gen_op_load_fpr_FT1(rs2);
3817                     tcg_gen_helper_0_0(helper_fpadd32s);
3818                     gen_op_store_FT0_fpr(rd);
3819                     break;
3820                 case 0x054: /* VIS I fpsub16 */
3821                     CHECK_FPU_FEATURE(dc, VIS1);
3822                     gen_op_load_fpr_DT0(DFPREG(rs1));
3823                     gen_op_load_fpr_DT1(DFPREG(rs2));
3824                     tcg_gen_helper_0_0(helper_fpsub16);
3825                     gen_op_store_DT0_fpr(DFPREG(rd));
3826                     break;
3827                 case 0x055: /* VIS I fpsub16s */
3828                     CHECK_FPU_FEATURE(dc, VIS1);
3829                     gen_op_load_fpr_FT0(rs1);
3830                     gen_op_load_fpr_FT1(rs2);
3831                     tcg_gen_helper_0_0(helper_fpsub16s);
3832                     gen_op_store_FT0_fpr(rd);
3833                     break;
3834                 case 0x056: /* VIS I fpsub32 */
3835                     CHECK_FPU_FEATURE(dc, VIS1);
3836                     gen_op_load_fpr_DT0(DFPREG(rs1));
3837                     gen_op_load_fpr_DT1(DFPREG(rs2));
3838                     tcg_gen_helper_0_0(helper_fpadd32);
3839                     gen_op_store_DT0_fpr(DFPREG(rd));
3840                     break;
3841                 case 0x057: /* VIS I fpsub32s */
3842                     CHECK_FPU_FEATURE(dc, VIS1);
3843                     gen_op_load_fpr_FT0(rs1);
3844                     gen_op_load_fpr_FT1(rs2);
3845                     tcg_gen_helper_0_0(helper_fpsub32s);
3846                     gen_op_store_FT0_fpr(rd);
3847                     break;
3848                 case 0x060: /* VIS I fzero */
3849                     CHECK_FPU_FEATURE(dc, VIS1);
3850                     tcg_gen_helper_0_0(helper_movl_DT0_0);
3851                     gen_op_store_DT0_fpr(DFPREG(rd));
3852                     break;
3853                 case 0x061: /* VIS I fzeros */
3854                     CHECK_FPU_FEATURE(dc, VIS1);
3855                     tcg_gen_helper_0_0(helper_movl_FT0_0);
3856                     gen_op_store_FT0_fpr(rd);
3857                     break;
3858                 case 0x062: /* VIS I fnor */
3859                     CHECK_FPU_FEATURE(dc, VIS1);
3860                     gen_op_load_fpr_DT0(DFPREG(rs1));
3861                     gen_op_load_fpr_DT1(DFPREG(rs2));
3862                     tcg_gen_helper_0_0(helper_fnor);
3863                     gen_op_store_DT0_fpr(DFPREG(rd));
3864                     break;
3865                 case 0x063: /* VIS I fnors */
3866                     CHECK_FPU_FEATURE(dc, VIS1);
3867                     gen_op_load_fpr_FT0(rs1);
3868                     gen_op_load_fpr_FT1(rs2);
3869                     tcg_gen_helper_0_0(helper_fnors);
3870                     gen_op_store_FT0_fpr(rd);
3871                     break;
3872                 case 0x064: /* VIS I fandnot2 */
3873                     CHECK_FPU_FEATURE(dc, VIS1);
3874                     gen_op_load_fpr_DT1(DFPREG(rs1));
3875                     gen_op_load_fpr_DT0(DFPREG(rs2));
3876                     tcg_gen_helper_0_0(helper_fandnot);
3877                     gen_op_store_DT0_fpr(DFPREG(rd));
3878                     break;
3879                 case 0x065: /* VIS I fandnot2s */
3880                     CHECK_FPU_FEATURE(dc, VIS1);
3881                     gen_op_load_fpr_FT1(rs1);
3882                     gen_op_load_fpr_FT0(rs2);
3883                     tcg_gen_helper_0_0(helper_fandnots);
3884                     gen_op_store_FT0_fpr(rd);
3885                     break;
3886                 case 0x066: /* VIS I fnot2 */
3887                     CHECK_FPU_FEATURE(dc, VIS1);
3888                     gen_op_load_fpr_DT1(DFPREG(rs2));
3889                     tcg_gen_helper_0_0(helper_fnot);
3890                     gen_op_store_DT0_fpr(DFPREG(rd));
3891                     break;
3892                 case 0x067: /* VIS I fnot2s */
3893                     CHECK_FPU_FEATURE(dc, VIS1);
3894                     gen_op_load_fpr_FT1(rs2);
3895                     tcg_gen_helper_0_0(helper_fnot);
3896                     gen_op_store_FT0_fpr(rd);
3897                     break;
3898                 case 0x068: /* VIS I fandnot1 */
3899                     CHECK_FPU_FEATURE(dc, VIS1);
3900                     gen_op_load_fpr_DT0(DFPREG(rs1));
3901                     gen_op_load_fpr_DT1(DFPREG(rs2));
3902                     tcg_gen_helper_0_0(helper_fandnot);
3903                     gen_op_store_DT0_fpr(DFPREG(rd));
3904                     break;
3905                 case 0x069: /* VIS I fandnot1s */
3906                     CHECK_FPU_FEATURE(dc, VIS1);
3907                     gen_op_load_fpr_FT0(rs1);
3908                     gen_op_load_fpr_FT1(rs2);
3909                     tcg_gen_helper_0_0(helper_fandnots);
3910                     gen_op_store_FT0_fpr(rd);
3911                     break;
3912                 case 0x06a: /* VIS I fnot1 */
3913                     CHECK_FPU_FEATURE(dc, VIS1);
3914                     gen_op_load_fpr_DT1(DFPREG(rs1));
3915                     tcg_gen_helper_0_0(helper_fnot);
3916                     gen_op_store_DT0_fpr(DFPREG(rd));
3917                     break;
3918                 case 0x06b: /* VIS I fnot1s */
3919                     CHECK_FPU_FEATURE(dc, VIS1);
3920                     gen_op_load_fpr_FT1(rs1);
3921                     tcg_gen_helper_0_0(helper_fnot);
3922                     gen_op_store_FT0_fpr(rd);
3923                     break;
3924                 case 0x06c: /* VIS I fxor */
3925                     CHECK_FPU_FEATURE(dc, VIS1);
3926                     gen_op_load_fpr_DT0(DFPREG(rs1));
3927                     gen_op_load_fpr_DT1(DFPREG(rs2));
3928                     tcg_gen_helper_0_0(helper_fxor);
3929                     gen_op_store_DT0_fpr(DFPREG(rd));
3930                     break;
3931                 case 0x06d: /* VIS I fxors */
3932                     CHECK_FPU_FEATURE(dc, VIS1);
3933                     gen_op_load_fpr_FT0(rs1);
3934                     gen_op_load_fpr_FT1(rs2);
3935                     tcg_gen_helper_0_0(helper_fxors);
3936                     gen_op_store_FT0_fpr(rd);
3937                     break;
3938                 case 0x06e: /* VIS I fnand */
3939                     CHECK_FPU_FEATURE(dc, VIS1);
3940                     gen_op_load_fpr_DT0(DFPREG(rs1));
3941                     gen_op_load_fpr_DT1(DFPREG(rs2));
3942                     tcg_gen_helper_0_0(helper_fnand);
3943                     gen_op_store_DT0_fpr(DFPREG(rd));
3944                     break;
3945                 case 0x06f: /* VIS I fnands */
3946                     CHECK_FPU_FEATURE(dc, VIS1);
3947                     gen_op_load_fpr_FT0(rs1);
3948                     gen_op_load_fpr_FT1(rs2);
3949                     tcg_gen_helper_0_0(helper_fnands);
3950                     gen_op_store_FT0_fpr(rd);
3951                     break;
3952                 case 0x070: /* VIS I fand */
3953                     CHECK_FPU_FEATURE(dc, VIS1);
3954                     gen_op_load_fpr_DT0(DFPREG(rs1));
3955                     gen_op_load_fpr_DT1(DFPREG(rs2));
3956                     tcg_gen_helper_0_0(helper_fand);
3957                     gen_op_store_DT0_fpr(DFPREG(rd));
3958                     break;
3959                 case 0x071: /* VIS I fands */
3960                     CHECK_FPU_FEATURE(dc, VIS1);
3961                     gen_op_load_fpr_FT0(rs1);
3962                     gen_op_load_fpr_FT1(rs2);
3963                     tcg_gen_helper_0_0(helper_fands);
3964                     gen_op_store_FT0_fpr(rd);
3965                     break;
3966                 case 0x072: /* VIS I fxnor */
3967                     CHECK_FPU_FEATURE(dc, VIS1);
3968                     gen_op_load_fpr_DT0(DFPREG(rs1));
3969                     gen_op_load_fpr_DT1(DFPREG(rs2));
3970                     tcg_gen_helper_0_0(helper_fxnor);
3971                     gen_op_store_DT0_fpr(DFPREG(rd));
3972                     break;
3973                 case 0x073: /* VIS I fxnors */
3974                     CHECK_FPU_FEATURE(dc, VIS1);
3975                     gen_op_load_fpr_FT0(rs1);
3976                     gen_op_load_fpr_FT1(rs2);
3977                     tcg_gen_helper_0_0(helper_fxnors);
3978                     gen_op_store_FT0_fpr(rd);
3979                     break;
3980                 case 0x074: /* VIS I fsrc1 */
3981                     CHECK_FPU_FEATURE(dc, VIS1);
3982                     gen_op_load_fpr_DT0(DFPREG(rs1));
3983                     gen_op_store_DT0_fpr(DFPREG(rd));
3984                     break;
3985                 case 0x075: /* VIS I fsrc1s */
3986                     CHECK_FPU_FEATURE(dc, VIS1);
3987                     gen_op_load_fpr_FT0(rs1);
3988                     gen_op_store_FT0_fpr(rd);
3989                     break;
3990                 case 0x076: /* VIS I fornot2 */
3991                     CHECK_FPU_FEATURE(dc, VIS1);
3992                     gen_op_load_fpr_DT1(DFPREG(rs1));
3993                     gen_op_load_fpr_DT0(DFPREG(rs2));
3994                     tcg_gen_helper_0_0(helper_fornot);
3995                     gen_op_store_DT0_fpr(DFPREG(rd));
3996                     break;
3997                 case 0x077: /* VIS I fornot2s */
3998                     CHECK_FPU_FEATURE(dc, VIS1);
3999                     gen_op_load_fpr_FT1(rs1);
4000                     gen_op_load_fpr_FT0(rs2);
4001                     tcg_gen_helper_0_0(helper_fornots);
4002                     gen_op_store_FT0_fpr(rd);
4003                     break;
4004                 case 0x078: /* VIS I fsrc2 */
4005                     CHECK_FPU_FEATURE(dc, VIS1);
4006                     gen_op_load_fpr_DT0(DFPREG(rs2));
4007                     gen_op_store_DT0_fpr(DFPREG(rd));
4008                     break;
4009                 case 0x079: /* VIS I fsrc2s */
4010                     CHECK_FPU_FEATURE(dc, VIS1);
4011                     gen_op_load_fpr_FT0(rs2);
4012                     gen_op_store_FT0_fpr(rd);
4013                     break;
4014                 case 0x07a: /* VIS I fornot1 */
4015                     CHECK_FPU_FEATURE(dc, VIS1);
4016                     gen_op_load_fpr_DT0(DFPREG(rs1));
4017                     gen_op_load_fpr_DT1(DFPREG(rs2));
4018                     tcg_gen_helper_0_0(helper_fornot);
4019                     gen_op_store_DT0_fpr(DFPREG(rd));
4020                     break;
4021                 case 0x07b: /* VIS I fornot1s */
4022                     CHECK_FPU_FEATURE(dc, VIS1);
4023                     gen_op_load_fpr_FT0(rs1);
4024                     gen_op_load_fpr_FT1(rs2);
4025                     tcg_gen_helper_0_0(helper_fornots);
4026                     gen_op_store_FT0_fpr(rd);
4027                     break;
4028                 case 0x07c: /* VIS I for */
4029                     CHECK_FPU_FEATURE(dc, VIS1);
4030                     gen_op_load_fpr_DT0(DFPREG(rs1));
4031                     gen_op_load_fpr_DT1(DFPREG(rs2));
4032                     tcg_gen_helper_0_0(helper_for);
4033                     gen_op_store_DT0_fpr(DFPREG(rd));
4034                     break;
4035                 case 0x07d: /* VIS I fors */
4036                     CHECK_FPU_FEATURE(dc, VIS1);
4037                     gen_op_load_fpr_FT0(rs1);
4038                     gen_op_load_fpr_FT1(rs2);
4039                     tcg_gen_helper_0_0(helper_fors);
4040                     gen_op_store_FT0_fpr(rd);
4041                     break;
4042                 case 0x07e: /* VIS I fone */
4043                     CHECK_FPU_FEATURE(dc, VIS1);
4044                     tcg_gen_helper_0_0(helper_movl_DT0_1);
4045                     gen_op_store_DT0_fpr(DFPREG(rd));
4046                     break;
4047                 case 0x07f: /* VIS I fones */
4048                     CHECK_FPU_FEATURE(dc, VIS1);
4049                     tcg_gen_helper_0_0(helper_movl_FT0_1);
4050                     gen_op_store_FT0_fpr(rd);
4051                     break;
4052                 case 0x080: /* VIS I shutdown */
4053                 case 0x081: /* VIS II siam */
4054                     // XXX
4055                     goto illegal_insn;
4056                 default:
4057                     goto illegal_insn;
4058                 }
4059 #else
4060                 goto ncp_insn;
4061 #endif
4062             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4063 #ifdef TARGET_SPARC64
4064                 goto illegal_insn;
4065 #else
4066                 goto ncp_insn;
4067 #endif
4068 #ifdef TARGET_SPARC64
4069             } else if (xop == 0x39) { /* V9 return */
4070                 TCGv r_const;
4071
4072                 save_state(dc, cpu_cond);
4073                 cpu_src1 = get_src1(insn, cpu_src1);
4074                 if (IS_IMM) {   /* immediate */
4075                     rs2 = GET_FIELDs(insn, 19, 31);
4076                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4077                 } else {                /* register */
4078                     rs2 = GET_FIELD(insn, 27, 31);
4079                     if (rs2) {
4080                         gen_movl_reg_TN(rs2, cpu_src2);
4081                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4082                     } else
4083                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
4084                 }
4085                 tcg_gen_helper_0_0(helper_restore);
4086                 gen_mov_pc_npc(dc, cpu_cond);
4087                 r_const = tcg_const_i32(3);
4088                 tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4089                 tcg_temp_free(r_const);
4090                 tcg_gen_mov_tl(cpu_npc, cpu_dst);
4091                 dc->npc = DYNAMIC_PC;
4092                 goto jmp_insn;
4093 #endif
4094             } else {
4095                 cpu_src1 = get_src1(insn, cpu_src1);
4096                 if (IS_IMM) {   /* immediate */
4097                     rs2 = GET_FIELDs(insn, 19, 31);
4098                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4099                 } else {                /* register */
4100                     rs2 = GET_FIELD(insn, 27, 31);
4101                     if (rs2) {
4102                         gen_movl_reg_TN(rs2, cpu_src2);
4103                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4104                     } else
4105                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
4106                 }
4107                 switch (xop) {
4108                 case 0x38:      /* jmpl */
4109                     {
4110                         TCGv r_const;
4111
4112                         r_const = tcg_const_tl(dc->pc);
4113                         gen_movl_TN_reg(rd, r_const);
4114                         tcg_temp_free(r_const);
4115                         gen_mov_pc_npc(dc, cpu_cond);
4116                         r_const = tcg_const_i32(3);
4117                         tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4118                                            r_const);
4119                         tcg_temp_free(r_const);
4120                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
4121                         dc->npc = DYNAMIC_PC;
4122                     }
4123                     goto jmp_insn;
4124 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4125                 case 0x39:      /* rett, V9 return */
4126                     {
4127                         TCGv r_const;
4128
4129                         if (!supervisor(dc))
4130                             goto priv_insn;
4131                         gen_mov_pc_npc(dc, cpu_cond);
4132                         r_const = tcg_const_i32(3);
4133                         tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4134                                            r_const);
4135                         tcg_temp_free(r_const);
4136                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
4137                         dc->npc = DYNAMIC_PC;
4138                         tcg_gen_helper_0_0(helper_rett);
4139                     }
4140                     goto jmp_insn;
4141 #endif
4142                 case 0x3b: /* flush */
4143                     if (!((dc)->features & CPU_FEATURE_FLUSH))
4144                         goto unimp_flush;
4145                     tcg_gen_helper_0_1(helper_flush, cpu_dst);
4146                     break;
4147                 case 0x3c:      /* save */
4148                     save_state(dc, cpu_cond);
4149                     tcg_gen_helper_0_0(helper_save);
4150                     gen_movl_TN_reg(rd, cpu_dst);
4151                     break;
4152                 case 0x3d:      /* restore */
4153                     save_state(dc, cpu_cond);
4154                     tcg_gen_helper_0_0(helper_restore);
4155                     gen_movl_TN_reg(rd, cpu_dst);
4156                     break;
4157 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4158                 case 0x3e:      /* V9 done/retry */
4159                     {
4160                         switch (rd) {
4161                         case 0:
4162                             if (!supervisor(dc))
4163                                 goto priv_insn;
4164                             dc->npc = DYNAMIC_PC;
4165                             dc->pc = DYNAMIC_PC;
4166                             tcg_gen_helper_0_0(helper_done);
4167                             goto jmp_insn;
4168                         case 1:
4169                             if (!supervisor(dc))
4170                                 goto priv_insn;
4171                             dc->npc = DYNAMIC_PC;
4172                             dc->pc = DYNAMIC_PC;
4173                             tcg_gen_helper_0_0(helper_retry);
4174                             goto jmp_insn;
4175                         default:
4176                             goto illegal_insn;
4177                         }
4178                     }
4179                     break;
4180 #endif
4181                 default:
4182                     goto illegal_insn;
4183                 }
4184             }
4185             break;
4186         }
4187         break;
4188     case 3:                     /* load/store instructions */
4189         {
4190             unsigned int xop = GET_FIELD(insn, 7, 12);
4191
4192             cpu_src1 = get_src1(insn, cpu_src1);
4193             if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
4194                 rs2 = GET_FIELD(insn, 27, 31);
4195                 gen_movl_reg_TN(rs2, cpu_src2);
4196                 tcg_gen_mov_tl(cpu_addr, cpu_src1);
4197             } else if (IS_IMM) {     /* immediate */
4198                 rs2 = GET_FIELDs(insn, 19, 31);
4199                 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4200             } else {            /* register */
4201                 rs2 = GET_FIELD(insn, 27, 31);
4202                 if (rs2 != 0) {
4203                     gen_movl_reg_TN(rs2, cpu_src2);
4204                     tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4205                 } else
4206                     tcg_gen_mov_tl(cpu_addr, cpu_src1);
4207             }
4208             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4209                 (xop > 0x17 && xop <= 0x1d ) ||
4210                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4211                 switch (xop) {
4212                 case 0x0:       /* load unsigned word */
4213                     gen_address_mask(dc, cpu_addr);
4214                     tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4215                     break;
4216                 case 0x1:       /* load unsigned byte */
4217                     gen_address_mask(dc, cpu_addr);
4218                     tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4219                     break;
4220                 case 0x2:       /* load unsigned halfword */
4221                     gen_address_mask(dc, cpu_addr);
4222                     tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4223                     break;
4224                 case 0x3:       /* load double word */
4225                     if (rd & 1)
4226                         goto illegal_insn;
4227                     else {
4228                         TCGv r_const;
4229
4230                         save_state(dc, cpu_cond);
4231                         r_const = tcg_const_i32(7);
4232                         tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4233                                            r_const); // XXX remove
4234                         tcg_temp_free(r_const);
4235                         gen_address_mask(dc, cpu_addr);
4236                         tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4237                         tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4238                         tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4239                         gen_movl_TN_reg(rd + 1, cpu_tmp0);
4240                         tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4241                         tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4242                         tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4243                     }
4244                     break;
4245                 case 0x9:       /* load signed byte */
4246                     gen_address_mask(dc, cpu_addr);
4247                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4248                     break;
4249                 case 0xa:       /* load signed halfword */
4250                     gen_address_mask(dc, cpu_addr);
4251                     tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4252                     break;
4253                 case 0xd:       /* ldstub -- XXX: should be atomically */
4254                     {
4255                         TCGv r_const;
4256
4257                         gen_address_mask(dc, cpu_addr);
4258                         tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4259                         r_const = tcg_const_tl(0xff);
4260                         tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4261                         tcg_temp_free(r_const);
4262                     }
4263                     break;
4264                 case 0x0f:      /* swap register with memory. Also
4265                                    atomically */
4266                     CHECK_IU_FEATURE(dc, SWAP);
4267                     gen_movl_reg_TN(rd, cpu_val);
4268                     gen_address_mask(dc, cpu_addr);
4269                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4270                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4271                     tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4272                     break;
4273 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4274                 case 0x10:      /* load word alternate */
4275 #ifndef TARGET_SPARC64
4276                     if (IS_IMM)
4277                         goto illegal_insn;
4278                     if (!supervisor(dc))
4279                         goto priv_insn;
4280 #endif
4281                     save_state(dc, cpu_cond);
4282                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4283                     break;
4284                 case 0x11:      /* load unsigned byte alternate */
4285 #ifndef TARGET_SPARC64
4286                     if (IS_IMM)
4287                         goto illegal_insn;
4288                     if (!supervisor(dc))
4289                         goto priv_insn;
4290 #endif
4291                     save_state(dc, cpu_cond);
4292                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4293                     break;
4294                 case 0x12:      /* load unsigned halfword alternate */
4295 #ifndef TARGET_SPARC64
4296                     if (IS_IMM)
4297                         goto illegal_insn;
4298                     if (!supervisor(dc))
4299                         goto priv_insn;
4300 #endif
4301                     save_state(dc, cpu_cond);
4302                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4303                     break;
4304                 case 0x13:      /* load double word alternate */
4305 #ifndef TARGET_SPARC64
4306                     if (IS_IMM)
4307                         goto illegal_insn;
4308                     if (!supervisor(dc))
4309                         goto priv_insn;
4310 #endif
4311                     if (rd & 1)
4312                         goto illegal_insn;
4313                     save_state(dc, cpu_cond);
4314                     gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4315                     gen_movl_TN_reg(rd + 1, cpu_tmp0);
4316                     break;
4317                 case 0x19:      /* load signed byte alternate */
4318 #ifndef TARGET_SPARC64
4319                     if (IS_IMM)
4320                         goto illegal_insn;
4321                     if (!supervisor(dc))
4322                         goto priv_insn;
4323 #endif
4324                     save_state(dc, cpu_cond);
4325                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4326                     break;
4327                 case 0x1a:      /* load signed halfword alternate */
4328 #ifndef TARGET_SPARC64
4329                     if (IS_IMM)
4330                         goto illegal_insn;
4331                     if (!supervisor(dc))
4332                         goto priv_insn;
4333 #endif
4334                     save_state(dc, cpu_cond);
4335                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4336                     break;
4337                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
4338 #ifndef TARGET_SPARC64
4339                     if (IS_IMM)
4340                         goto illegal_insn;
4341                     if (!supervisor(dc))
4342                         goto priv_insn;
4343 #endif
4344                     save_state(dc, cpu_cond);
4345                     gen_ldstub_asi(cpu_val, cpu_addr, insn);
4346                     break;
4347                 case 0x1f:      /* swap reg with alt. memory. Also
4348                                    atomically */
4349                     CHECK_IU_FEATURE(dc, SWAP);
4350 #ifndef TARGET_SPARC64
4351                     if (IS_IMM)
4352                         goto illegal_insn;
4353                     if (!supervisor(dc))
4354                         goto priv_insn;
4355 #endif
4356                     save_state(dc, cpu_cond);
4357                     gen_movl_reg_TN(rd, cpu_val);
4358                     gen_swap_asi(cpu_val, cpu_addr, insn);
4359                     break;
4360
4361 #ifndef TARGET_SPARC64
4362                 case 0x30: /* ldc */
4363                 case 0x31: /* ldcsr */
4364                 case 0x33: /* lddc */
4365                     goto ncp_insn;
4366 #endif
4367 #endif
4368 #ifdef TARGET_SPARC64
4369                 case 0x08: /* V9 ldsw */
4370                     gen_address_mask(dc, cpu_addr);
4371                     tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4372                     break;
4373                 case 0x0b: /* V9 ldx */
4374                     gen_address_mask(dc, cpu_addr);
4375                     tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4376                     break;
4377                 case 0x18: /* V9 ldswa */
4378                     save_state(dc, cpu_cond);
4379                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4380                     break;
4381                 case 0x1b: /* V9 ldxa */
4382                     save_state(dc, cpu_cond);
4383                     gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4384                     break;
4385                 case 0x2d: /* V9 prefetch, no effect */
4386                     goto skip_move;
4387                 case 0x30: /* V9 ldfa */
4388                     save_state(dc, cpu_cond);
4389                     gen_ldf_asi(cpu_addr, insn, 4, rd);
4390                     goto skip_move;
4391                 case 0x33: /* V9 lddfa */
4392                     save_state(dc, cpu_cond);
4393                     gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4394                     goto skip_move;
4395                 case 0x3d: /* V9 prefetcha, no effect */
4396                     goto skip_move;
4397                 case 0x32: /* V9 ldqfa */
4398                     CHECK_FPU_FEATURE(dc, FLOAT128);
4399                     save_state(dc, cpu_cond);
4400                     gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4401                     goto skip_move;
4402 #endif
4403                 default:
4404                     goto illegal_insn;
4405                 }
4406                 gen_movl_TN_reg(rd, cpu_val);
4407 #ifdef TARGET_SPARC64
4408             skip_move: ;
4409 #endif
4410             } else if (xop >= 0x20 && xop < 0x24) {
4411                 if (gen_trap_ifnofpu(dc, cpu_cond))
4412                     goto jmp_insn;
4413                 save_state(dc, cpu_cond);
4414                 switch (xop) {
4415                 case 0x20:      /* load fpreg */
4416                     gen_address_mask(dc, cpu_addr);
4417                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4418                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4419                                    offsetof(CPUState, fpr[rd]));
4420                     break;
4421                 case 0x21:      /* load fsr */
4422                     gen_address_mask(dc, cpu_addr);
4423                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4424                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4425                                    offsetof(CPUState, ft0));
4426                     tcg_gen_helper_0_0(helper_ldfsr);
4427                     break;
4428                 case 0x22:      /* load quad fpreg */
4429                     {
4430                         TCGv r_const;
4431
4432                         CHECK_FPU_FEATURE(dc, FLOAT128);
4433                         r_const = tcg_const_i32(dc->mem_idx);
4434                         tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4435                         tcg_temp_free(r_const);
4436                         gen_op_store_QT0_fpr(QFPREG(rd));
4437                     }
4438                     break;
4439                 case 0x23:      /* load double fpreg */
4440                     {
4441                         TCGv r_const;
4442
4443                         r_const = tcg_const_i32(dc->mem_idx);
4444                         tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4445                         tcg_temp_free(r_const);
4446                         gen_op_store_DT0_fpr(DFPREG(rd));
4447                     }
4448                     break;
4449                 default:
4450                     goto illegal_insn;
4451                 }
4452             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4453                        xop == 0xe || xop == 0x1e) {
4454                 gen_movl_reg_TN(rd, cpu_val);
4455                 switch (xop) {
4456                 case 0x4: /* store word */
4457                     gen_address_mask(dc, cpu_addr);
4458                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4459                     break;
4460                 case 0x5: /* store byte */
4461                     gen_address_mask(dc, cpu_addr);
4462                     tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4463                     break;
4464                 case 0x6: /* store halfword */
4465                     gen_address_mask(dc, cpu_addr);
4466                     tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4467                     break;
4468                 case 0x7: /* store double word */
4469                     if (rd & 1)
4470                         goto illegal_insn;
4471                     else {
4472                         TCGv r_low, r_const;
4473
4474                         save_state(dc, cpu_cond);
4475                         gen_address_mask(dc, cpu_addr);
4476                         r_const = tcg_const_i32(7);
4477                         tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4478                                            r_const); // XXX remove
4479                         tcg_temp_free(r_const);
4480                         r_low = tcg_temp_new(TCG_TYPE_TL);
4481                         gen_movl_reg_TN(rd + 1, r_low);
4482                         tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4483                                            r_low);
4484                         tcg_temp_free(r_low);
4485                         tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4486                     }
4487                     break;
4488 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4489                 case 0x14: /* store word alternate */
4490 #ifndef TARGET_SPARC64
4491                     if (IS_IMM)
4492                         goto illegal_insn;
4493                     if (!supervisor(dc))
4494                         goto priv_insn;
4495 #endif
4496                     save_state(dc, cpu_cond);
4497                     gen_st_asi(cpu_val, cpu_addr, insn, 4);
4498                     break;
4499                 case 0x15: /* store byte alternate */
4500 #ifndef TARGET_SPARC64
4501                     if (IS_IMM)
4502                         goto illegal_insn;
4503                     if (!supervisor(dc))
4504                         goto priv_insn;
4505 #endif
4506                     save_state(dc, cpu_cond);
4507                     gen_st_asi(cpu_val, cpu_addr, insn, 1);
4508                     break;
4509                 case 0x16: /* store halfword alternate */
4510 #ifndef TARGET_SPARC64
4511                     if (IS_IMM)
4512                         goto illegal_insn;
4513                     if (!supervisor(dc))
4514                         goto priv_insn;
4515 #endif
4516                     save_state(dc, cpu_cond);
4517                     gen_st_asi(cpu_val, cpu_addr, insn, 2);
4518                     break;
4519                 case 0x17: /* store double word alternate */
4520 #ifndef TARGET_SPARC64
4521                     if (IS_IMM)
4522                         goto illegal_insn;
4523                     if (!supervisor(dc))
4524                         goto priv_insn;
4525 #endif
4526                     if (rd & 1)
4527                         goto illegal_insn;
4528                     else {
4529                         save_state(dc, cpu_cond);
4530                         gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4531                     }
4532                     break;
4533 #endif
4534 #ifdef TARGET_SPARC64
4535                 case 0x0e: /* V9 stx */
4536                     gen_address_mask(dc, cpu_addr);
4537                     tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4538                     break;
4539                 case 0x1e: /* V9 stxa */
4540                     save_state(dc, cpu_cond);
4541                     gen_st_asi(cpu_val, cpu_addr, insn, 8);
4542                     break;
4543 #endif
4544                 default:
4545                     goto illegal_insn;
4546                 }
4547             } else if (xop > 0x23 && xop < 0x28) {
4548                 if (gen_trap_ifnofpu(dc, cpu_cond))
4549                     goto jmp_insn;
4550                 save_state(dc, cpu_cond);
4551                 switch (xop) {
4552                 case 0x24: /* store fpreg */
4553                     gen_address_mask(dc, cpu_addr);
4554                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4555                                    offsetof(CPUState, fpr[rd]));
4556                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4557                     break;
4558                 case 0x25: /* stfsr, V9 stxfsr */
4559                     gen_address_mask(dc, cpu_addr);
4560                     tcg_gen_helper_0_0(helper_stfsr);
4561                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4562                                    offsetof(CPUState, ft0));
4563                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4564                     break;
4565                 case 0x26:
4566 #ifdef TARGET_SPARC64
4567                     /* V9 stqf, store quad fpreg */
4568                     {
4569                         TCGv r_const;
4570
4571                         CHECK_FPU_FEATURE(dc, FLOAT128);
4572                         gen_op_load_fpr_QT0(QFPREG(rd));
4573                         r_const = tcg_const_i32(dc->mem_idx);
4574                         tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4575                         tcg_temp_free(r_const);
4576                     }
4577                     break;
4578 #else /* !TARGET_SPARC64 */
4579                     /* stdfq, store floating point queue */
4580 #if defined(CONFIG_USER_ONLY)
4581                     goto illegal_insn;
4582 #else
4583                     if (!supervisor(dc))
4584                         goto priv_insn;
4585                     if (gen_trap_ifnofpu(dc, cpu_cond))
4586                         goto jmp_insn;
4587                     goto nfq_insn;
4588 #endif
4589 #endif
4590                 case 0x27: /* store double fpreg */
4591                     {
4592                         TCGv r_const;
4593
4594                         gen_op_load_fpr_DT0(DFPREG(rd));
4595                         r_const = tcg_const_i32(dc->mem_idx);
4596                         tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4597                         tcg_temp_free(r_const);
4598                     }
4599                     break;
4600                 default:
4601                     goto illegal_insn;
4602                 }
4603             } else if (xop > 0x33 && xop < 0x3f) {
4604                 save_state(dc, cpu_cond);
4605                 switch (xop) {
4606 #ifdef TARGET_SPARC64
4607                 case 0x34: /* V9 stfa */
4608                     gen_op_load_fpr_FT0(rd);
4609                     gen_stf_asi(cpu_addr, insn, 4, rd);
4610                     break;
4611                 case 0x36: /* V9 stqfa */
4612                     {
4613                         TCGv r_const;
4614
4615                         CHECK_FPU_FEATURE(dc, FLOAT128);
4616                         r_const = tcg_const_i32(7);
4617                         tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4618                                            r_const);
4619                         tcg_temp_free(r_const);
4620                         gen_op_load_fpr_QT0(QFPREG(rd));
4621                         gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4622                     }
4623                     break;
4624                 case 0x37: /* V9 stdfa */
4625                     gen_op_load_fpr_DT0(DFPREG(rd));
4626                     gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4627                     break;
4628                 case 0x3c: /* V9 casa */
4629                     gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4630                     gen_movl_TN_reg(rd, cpu_val);
4631                     break;
4632                 case 0x3e: /* V9 casxa */
4633                     gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4634                     gen_movl_TN_reg(rd, cpu_val);
4635                     break;
4636 #else
4637                 case 0x34: /* stc */
4638                 case 0x35: /* stcsr */
4639                 case 0x36: /* stdcq */
4640                 case 0x37: /* stdc */
4641                     goto ncp_insn;
4642 #endif
4643                 default:
4644                     goto illegal_insn;
4645                 }
4646             }
4647             else
4648                 goto illegal_insn;
4649         }
4650         break;
4651     }
4652     /* default case for non jump instructions */
4653     if (dc->npc == DYNAMIC_PC) {
4654         dc->pc = DYNAMIC_PC;
4655         gen_op_next_insn();
4656     } else if (dc->npc == JUMP_PC) {
4657         /* we can do a static jump */
4658         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4659         dc->is_br = 1;
4660     } else {
4661         dc->pc = dc->npc;
4662         dc->npc = dc->npc + 4;
4663     }
4664  jmp_insn:
4665     return;
4666  illegal_insn:
4667     {
4668         TCGv r_const;
4669
4670         save_state(dc, cpu_cond);
4671         r_const = tcg_const_i32(TT_ILL_INSN);
4672         tcg_gen_helper_0_1(raise_exception, r_const);
4673         tcg_temp_free(r_const);
4674         dc->is_br = 1;
4675     }
4676     return;
4677  unimp_flush:
4678     {
4679         TCGv r_const;
4680
4681         save_state(dc, cpu_cond);
4682         r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4683         tcg_gen_helper_0_1(raise_exception, r_const);
4684         tcg_temp_free(r_const);
4685         dc->is_br = 1;
4686     }
4687     return;
4688 #if !defined(CONFIG_USER_ONLY)
4689  priv_insn:
4690     {
4691         TCGv r_const;
4692
4693         save_state(dc, cpu_cond);
4694         r_const = tcg_const_i32(TT_PRIV_INSN);
4695         tcg_gen_helper_0_1(raise_exception, r_const);
4696         tcg_temp_free(r_const);
4697         dc->is_br = 1;
4698     }
4699     return;
4700 #endif
4701  nfpu_insn:
4702     save_state(dc, cpu_cond);
4703     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4704     dc->is_br = 1;
4705     return;
4706 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4707  nfq_insn:
4708     save_state(dc, cpu_cond);
4709     gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4710     dc->is_br = 1;
4711     return;
4712 #endif
4713 #ifndef TARGET_SPARC64
4714  ncp_insn:
4715     {
4716         TCGv r_const;
4717
4718         save_state(dc, cpu_cond);
4719         r_const = tcg_const_i32(TT_NCP_INSN);
4720         tcg_gen_helper_0_1(raise_exception, r_const);
4721         tcg_temp_free(r_const);
4722         dc->is_br = 1;
4723     }
4724     return;
4725 #endif
4726 }
4727
4728 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4729                                                  int spc, CPUSPARCState *env)
4730 {
4731     target_ulong pc_start, last_pc;
4732     uint16_t *gen_opc_end;
4733     DisasContext dc1, *dc = &dc1;
4734     int j, lj = -1;
4735     int num_insns;
4736     int max_insns;
4737
4738     memset(dc, 0, sizeof(DisasContext));
4739     dc->tb = tb;
4740     pc_start = tb->pc;
4741     dc->pc = pc_start;
4742     last_pc = dc->pc;
4743     dc->npc = (target_ulong) tb->cs_base;
4744     dc->mem_idx = cpu_mmu_index(env);
4745     dc->features = env->features;
4746     if ((dc->features & CPU_FEATURE_FLOAT)) {
4747         dc->fpu_enabled = cpu_fpu_enabled(env);
4748 #if defined(CONFIG_USER_ONLY)
4749         dc->features |= CPU_FEATURE_FLOAT128;
4750 #endif
4751     } else
4752         dc->fpu_enabled = 0;
4753 #ifdef TARGET_SPARC64
4754     dc->address_mask_32bit = env->pstate & PS_AM;
4755 #endif
4756     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4757
4758     cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4759     cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4760     cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4761
4762     cpu_dst = tcg_temp_local_new(TCG_TYPE_TL);
4763
4764     // loads and stores
4765     cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
4766     cpu_addr = tcg_temp_local_new(TCG_TYPE_TL);
4767
4768     num_insns = 0;
4769     max_insns = tb->cflags & CF_COUNT_MASK;
4770     if (max_insns == 0)
4771         max_insns = CF_COUNT_MASK;
4772     gen_icount_start();
4773     do {
4774         if (env->nb_breakpoints > 0) {
4775             for(j = 0; j < env->nb_breakpoints; j++) {
4776                 if (env->breakpoints[j] == dc->pc) {
4777                     if (dc->pc != pc_start)
4778                         save_state(dc, cpu_cond);
4779                     tcg_gen_helper_0_0(helper_debug);
4780                     tcg_gen_exit_tb(0);
4781                     dc->is_br = 1;
4782                     goto exit_gen_loop;
4783                 }
4784             }
4785         }
4786         if (spc) {
4787             if (loglevel > 0)
4788                 fprintf(logfile, "Search PC...\n");
4789             j = gen_opc_ptr - gen_opc_buf;
4790             if (lj < j) {
4791                 lj++;
4792                 while (lj < j)
4793                     gen_opc_instr_start[lj++] = 0;
4794                 gen_opc_pc[lj] = dc->pc;
4795                 gen_opc_npc[lj] = dc->npc;
4796                 gen_opc_instr_start[lj] = 1;
4797                 gen_opc_icount[lj] = num_insns;
4798             }
4799         }
4800         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
4801             gen_io_start();
4802         last_pc = dc->pc;
4803         disas_sparc_insn(dc);
4804         num_insns++;
4805
4806         if (dc->is_br)
4807             break;
4808         /* if the next PC is different, we abort now */
4809         if (dc->pc != (last_pc + 4))
4810             break;
4811         /* if we reach a page boundary, we stop generation so that the
4812            PC of a TT_TFAULT exception is always in the right page */
4813         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4814             break;
4815         /* if single step mode, we generate only one instruction and
4816            generate an exception */
4817         if (env->singlestep_enabled) {
4818             tcg_gen_movi_tl(cpu_pc, dc->pc);
4819             tcg_gen_exit_tb(0);
4820             break;
4821         }
4822     } while ((gen_opc_ptr < gen_opc_end) &&
4823              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
4824              num_insns < max_insns);
4825
4826  exit_gen_loop:
4827     tcg_temp_free(cpu_addr);
4828     tcg_temp_free(cpu_val);
4829     tcg_temp_free(cpu_dst);
4830     tcg_temp_free(cpu_tmp64);
4831     tcg_temp_free(cpu_tmp32);
4832     tcg_temp_free(cpu_tmp0);
4833     if (tb->cflags & CF_LAST_IO)
4834         gen_io_end();
4835     if (!dc->is_br) {
4836         if (dc->pc != DYNAMIC_PC &&
4837             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4838             /* static PC and NPC: we can use direct chaining */
4839             gen_goto_tb(dc, 0, dc->pc, dc->npc);
4840         } else {
4841             if (dc->pc != DYNAMIC_PC)
4842                 tcg_gen_movi_tl(cpu_pc, dc->pc);
4843             save_npc(dc, cpu_cond);
4844             tcg_gen_exit_tb(0);
4845         }
4846     }
4847     gen_icount_end(tb, num_insns);
4848     *gen_opc_ptr = INDEX_op_end;
4849     if (spc) {
4850         j = gen_opc_ptr - gen_opc_buf;
4851         lj++;
4852         while (lj <= j)
4853             gen_opc_instr_start[lj++] = 0;
4854 #if 0
4855         if (loglevel > 0) {
4856             page_dump(logfile);
4857         }
4858 #endif
4859         gen_opc_jump_pc[0] = dc->jump_pc[0];
4860         gen_opc_jump_pc[1] = dc->jump_pc[1];
4861     } else {
4862         tb->size = last_pc + 4 - pc_start;
4863         tb->icount = num_insns;
4864     }
4865 #ifdef DEBUG_DISAS
4866     if (loglevel & CPU_LOG_TB_IN_ASM) {
4867         fprintf(logfile, "--------------\n");
4868         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4869         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4870         fprintf(logfile, "\n");
4871     }
4872 #endif
4873     return 0;
4874 }
4875
4876 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4877 {
4878     return gen_intermediate_code_internal(tb, 0, env);
4879 }
4880
4881 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4882 {
4883     return gen_intermediate_code_internal(tb, 1, env);
4884 }
4885
4886 void gen_intermediate_code_init(CPUSPARCState *env)
4887 {
4888     unsigned int i;
4889     static int inited;
4890     static const char * const gregnames[8] = {
4891         NULL, // g0 not used
4892         "g1",
4893         "g2",
4894         "g3",
4895         "g4",
4896         "g5",
4897         "g6",
4898         "g7",
4899     };
4900
4901     /* init various static tables */
4902     if (!inited) {
4903         inited = 1;
4904
4905         cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4906         cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4907                                          offsetof(CPUState, regwptr),
4908                                          "regwptr");
4909 #ifdef TARGET_SPARC64
4910         cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4911                                      TCG_AREG0, offsetof(CPUState, xcc),
4912                                      "xcc");
4913 #endif
4914         cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4915                                       TCG_AREG0, offsetof(CPUState, cond),
4916                                       "cond");
4917         cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4918                                         TCG_AREG0, offsetof(CPUState, cc_src),
4919                                         "cc_src");
4920         cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4921                                          offsetof(CPUState, cc_src2),
4922                                          "cc_src2");
4923         cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4924                                         TCG_AREG0, offsetof(CPUState, cc_dst),
4925                                         "cc_dst");
4926         cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4927                                      TCG_AREG0, offsetof(CPUState, psr),
4928                                      "psr");
4929         cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4930                                      TCG_AREG0, offsetof(CPUState, fsr),
4931                                      "fsr");
4932         cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4933                                     TCG_AREG0, offsetof(CPUState, pc),
4934                                     "pc");
4935         cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4936                                     TCG_AREG0, offsetof(CPUState, npc),
4937                                     "npc");
4938         for (i = 1; i < 8; i++)
4939             cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4940                                               offsetof(CPUState, gregs[i]),
4941                                               gregnames[i]);
4942         /* register helpers */
4943
4944 #undef DEF_HELPER
4945 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4946 #include "helper.h"
4947     }
4948 }
4949
4950 void gen_pc_load(CPUState *env, TranslationBlock *tb,
4951                 unsigned long searched_pc, int pc_pos, void *puc)
4952 {
4953     target_ulong npc;
4954     env->pc = gen_opc_pc[pc_pos];
4955     npc = gen_opc_npc[pc_pos];
4956     if (npc == 1) {
4957         /* dynamic NPC: already stored */
4958     } else if (npc == 2) {
4959         target_ulong t2 = (target_ulong)(unsigned long)puc;
4960         /* jump PC: use T2 and the jump targets of the translation */
4961         if (t2)
4962             env->npc = gen_opc_jump_pc[0];
4963         else
4964             env->npc = gen_opc_jump_pc[1];
4965     } else {
4966         env->npc = npc;
4967     }
4968 }