git.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <stdarg.h>
  23 #include <stdlib.h>
  24 #include <stdio.h>
  25 #include <string.h>
  26 #include <inttypes.h>
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30 #include "disas.h"
  31 #include "helper.h"
  32 #include "tcg-op.h"
  33
  34 #define DEBUG_DISAS
  35
  36 #define DYNAMIC_PC  1 /* dynamic pc value */
  37 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  38                          according to jump_pc[T2] */
  39
  40 /* global register indexes */
  41 static TCGv cpu_env, cpu_T[2], cpu_regwptr;
  42 static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
  43 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
  44 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
  45 #ifdef TARGET_SPARC64
  46 static TCGv cpu_xcc;
  47 #endif
  48 /* local register indexes (only used inside old micro ops) */
  49 static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
  50
  51 typedef struct DisasContext {
  52     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  53     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  54     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  55     int is_br;
  56     int mem_idx;
  57     int fpu_enabled;
  58     struct TranslationBlock *tb;
  59     uint32_t features;
  60 } DisasContext;
  61
  62 // This function uses non-native bit order
  63 #define GET_FIELD(X, FROM, TO) \
  64   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  65
  66 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  67 #define GET_FIELD_SP(X, FROM, TO) \
  68     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  69
  70 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  71 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
  72
  73 #ifdef TARGET_SPARC64
  74 #define FFPREG(r) (r)
  75 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
  76 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
  77 #else
  78 #define FFPREG(r) (r)
  79 #define DFPREG(r) (r & 0x1e)
  80 #define QFPREG(r) (r & 0x1c)
  81 #endif
  82
  83 static int sign_extend(int x, int len)
  84 {
  85     len = 32 - len;
  86     return (x << len) >> len;
  87 }
  88
  89 #define IS_IMM (insn & (1<<13))
  90
  91 /* floating point registers moves */
  92 static void gen_op_load_fpr_FT0(unsigned int src)
  93 {
  94     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  95     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
  96 }
  97
  98 static void gen_op_load_fpr_FT1(unsigned int src)
  99 {
 100     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 101     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
 102 }
 103
 104 static void gen_op_store_FT0_fpr(unsigned int dst)
 105 {
 106     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
 107     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 108 }
 109
 110 static void gen_op_load_fpr_DT0(unsigned int src)
 111 {
 112     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 113     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 114                    offsetof(CPU_DoubleU, l.upper));
 115     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 116     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 117                    offsetof(CPU_DoubleU, l.lower));
 118 }
 119
 120 static void gen_op_load_fpr_DT1(unsigned int src)
 121 {
 122     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 123     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
 124                    offsetof(CPU_DoubleU, l.upper));
 125     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 126     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
 127                    offsetof(CPU_DoubleU, l.lower));
 128 }
 129
 130 static void gen_op_store_DT0_fpr(unsigned int dst)
 131 {
 132     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 133                    offsetof(CPU_DoubleU, l.upper));
 134     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 135     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 136                    offsetof(CPU_DoubleU, l.lower));
 137     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 138 }
 139
 140 static void gen_op_load_fpr_QT0(unsigned int src)
 141 {
 142     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 143     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 144                    offsetof(CPU_QuadU, l.upmost));
 145     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 146     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 147                    offsetof(CPU_QuadU, l.upper));
 148     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 149     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 150                    offsetof(CPU_QuadU, l.lower));
 151     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 152     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 153                    offsetof(CPU_QuadU, l.lowest));
 154 }
 155
 156 static void gen_op_load_fpr_QT1(unsigned int src)
 157 {
 158     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 159     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 160                    offsetof(CPU_QuadU, l.upmost));
 161     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 162     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 163                    offsetof(CPU_QuadU, l.upper));
 164     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 165     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 166                    offsetof(CPU_QuadU, l.lower));
 167     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 168     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 169                    offsetof(CPU_QuadU, l.lowest));
 170 }
 171
 172 static void gen_op_store_QT0_fpr(unsigned int dst)
 173 {
 174     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 175                    offsetof(CPU_QuadU, l.upmost));
 176     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 177     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 178                    offsetof(CPU_QuadU, l.upper));
 179     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 180     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 181                    offsetof(CPU_QuadU, l.lower));
 182     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
 183     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 184                    offsetof(CPU_QuadU, l.lowest));
 185     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
 186 }
 187
 188 /* moves */
 189 #ifdef CONFIG_USER_ONLY
 190 #define supervisor(dc) 0
 191 #ifdef TARGET_SPARC64
 192 #define hypervisor(dc) 0
 193 #endif
 194 #else
 195 #define supervisor(dc) (dc->mem_idx >= 1)
 196 #ifdef TARGET_SPARC64
 197 #define hypervisor(dc) (dc->mem_idx == 2)
 198 #else
 199 #endif
 200 #endif
 201
 202 #ifdef TARGET_ABI32
 203 #define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
 204 #else
 205 #define ABI32_MASK(addr)
 206 #endif
 207
 208 static inline void gen_movl_reg_TN(int reg, TCGv tn)
 209 {
 210     if (reg == 0)
 211         tcg_gen_movi_tl(tn, 0);
 212     else if (reg < 8)
 213         tcg_gen_mov_tl(tn, cpu_gregs[reg]);
 214     else {
 215         tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 216     }
 217 }
 218
 219 static inline void gen_movl_TN_reg(int reg, TCGv tn)
 220 {
 221     if (reg == 0)
 222         return;
 223     else if (reg < 8)
 224         tcg_gen_mov_tl(cpu_gregs[reg], tn);
 225     else {
 226         tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 227     }
 228 }
 229
 230 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 231                                target_ulong pc, target_ulong npc)
 232 {
 233     TranslationBlock *tb;
 234
 235     tb = s->tb;
 236     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 237         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 238         /* jump to same page: we can use a direct jump */
 239         tcg_gen_goto_tb(tb_num);
 240         tcg_gen_movi_tl(cpu_pc, pc);
 241         tcg_gen_movi_tl(cpu_npc, npc);
 242         tcg_gen_exit_tb((long)tb + tb_num);
 243     } else {
 244         /* jump to another page: currently not optimized */
 245         tcg_gen_movi_tl(cpu_pc, pc);
 246         tcg_gen_movi_tl(cpu_npc, npc);
 247         tcg_gen_exit_tb(0);
 248     }
 249 }
 250
 251 // XXX suboptimal
 252 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
 253 {
 254     tcg_gen_extu_i32_tl(reg, src);
 255     tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
 256     tcg_gen_andi_tl(reg, reg, 0x1);
 257 }
 258
 259 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
 260 {
 261     tcg_gen_extu_i32_tl(reg, src);
 262     tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
 263     tcg_gen_andi_tl(reg, reg, 0x1);
 264 }
 265
 266 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
 267 {
 268     tcg_gen_extu_i32_tl(reg, src);
 269     tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
 270     tcg_gen_andi_tl(reg, reg, 0x1);
 271 }
 272
 273 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
 274 {
 275     tcg_gen_extu_i32_tl(reg, src);
 276     tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
 277     tcg_gen_andi_tl(reg, reg, 0x1);
 278 }
 279
 280 static inline void gen_cc_clear_icc(void)
 281 {
 282     tcg_gen_movi_i32(cpu_psr, 0);
 283 }
 284
 285 #ifdef TARGET_SPARC64
 286 static inline void gen_cc_clear_xcc(void)
 287 {
 288     tcg_gen_movi_i32(cpu_xcc, 0);
 289 }
 290 #endif
 291
 292 /* old op:
 293     if (!T0)
 294         env->psr |= PSR_ZERO;
 295     if ((int32_t) T0 < 0)
 296         env->psr |= PSR_NEG;
 297 */
 298 static inline void gen_cc_NZ_icc(TCGv dst)
 299 {
 300     TCGv r_temp;
 301     int l1, l2;
 302
 303     l1 = gen_new_label();
 304     l2 = gen_new_label();
 305     r_temp = tcg_temp_new(TCG_TYPE_TL);
 306     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 307     tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
 308     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
 309     gen_set_label(l1);
 310     tcg_gen_ext_i32_tl(r_temp, dst);
 311     tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
 312     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
 313     gen_set_label(l2);
 314     tcg_temp_free(r_temp);
 315 }
 316
 317 #ifdef TARGET_SPARC64
 318 static inline void gen_cc_NZ_xcc(TCGv dst)
 319 {
 320     int l1, l2;
 321
 322     l1 = gen_new_label();
 323     l2 = gen_new_label();
 324     tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
 325     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
 326     gen_set_label(l1);
 327     tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
 328     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
 329     gen_set_label(l2);
 330 }
 331 #endif
 332
 333 /* old op:
 334     if (T0 < src1)
 335         env->psr |= PSR_CARRY;
 336 */
 337 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
 338 {
 339     TCGv r_temp;
 340     int l1;
 341
 342     l1 = gen_new_label();
 343     r_temp = tcg_temp_new(TCG_TYPE_TL);
 344     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 345     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 346     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 347     gen_set_label(l1);
 348     tcg_temp_free(r_temp);
 349 }
 350
 351 #ifdef TARGET_SPARC64
 352 static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
 353 {
 354     int l1;
 355
 356     l1 = gen_new_label();
 357     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 358     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 359     gen_set_label(l1);
 360 }
 361 #endif
 362
 363 /* old op:
 364     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
 365         env->psr |= PSR_OVF;
 366 */
 367 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
 368 {
 369     TCGv r_temp;
 370
 371     r_temp = tcg_temp_new(TCG_TYPE_TL);
 372     tcg_gen_xor_tl(r_temp, src1, src2);
 373     tcg_gen_xori_tl(r_temp, r_temp, -1);
 374     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 375     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 376     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 377     tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
 378     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 379     tcg_temp_free(r_temp);
 380     tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
 381 }
 382
 383 #ifdef TARGET_SPARC64
 384 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
 385 {
 386     TCGv r_temp;
 387
 388     r_temp = tcg_temp_new(TCG_TYPE_TL);
 389     tcg_gen_xor_tl(r_temp, src1, src2);
 390     tcg_gen_xori_tl(r_temp, r_temp, -1);
 391     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 392     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 393     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 394     tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
 395     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 396     tcg_temp_free(r_temp);
 397     tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
 398 }
 399 #endif
 400
 401 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
 402 {
 403     TCGv r_temp, r_const;
 404     int l1;
 405
 406     l1 = gen_new_label();
 407
 408     r_temp = tcg_temp_new(TCG_TYPE_TL);
 409     tcg_gen_xor_tl(r_temp, src1, src2);
 410     tcg_gen_xori_tl(r_temp, r_temp, -1);
 411     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 412     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 413     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 414     tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
 415     r_const = tcg_const_i32(TT_TOVF);
 416     tcg_gen_helper_0_1(raise_exception, r_const);
 417     tcg_temp_free(r_const);
 418     gen_set_label(l1);
 419     tcg_temp_free(r_temp);
 420 }
 421
 422 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
 423 {
 424     int l1;
 425
 426     l1 = gen_new_label();
 427     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 428     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 429     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
 430     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 431     gen_set_label(l1);
 432 }
 433
 434 static inline void gen_tag_tv(TCGv src1, TCGv src2)
 435 {
 436     int l1;
 437     TCGv r_const;
 438
 439     l1 = gen_new_label();
 440     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 441     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 442     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
 443     r_const = tcg_const_i32(TT_TOVF);
 444     tcg_gen_helper_0_1(raise_exception, r_const);
 445     tcg_temp_free(r_const);
 446     gen_set_label(l1);
 447 }
 448
 449 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
 450 {
 451     tcg_gen_mov_tl(cpu_cc_src, src1);
 452     tcg_gen_mov_tl(cpu_cc_src2, src2);
 453     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 454     gen_cc_clear_icc();
 455     gen_cc_NZ_icc(cpu_cc_dst);
 456     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 457     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 458 #ifdef TARGET_SPARC64
 459     gen_cc_clear_xcc();
 460     gen_cc_NZ_xcc(cpu_cc_dst);
 461     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 462     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 463 #endif
 464     tcg_gen_mov_tl(dst, cpu_cc_dst);
 465 }
 466
 467 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
 468 {
 469     tcg_gen_mov_tl(cpu_cc_src, src1);
 470     tcg_gen_mov_tl(cpu_cc_src2, src2);
 471     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 472     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
 473     gen_cc_clear_icc();
 474     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 475 #ifdef TARGET_SPARC64
 476     gen_cc_clear_xcc();
 477     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 478 #endif
 479     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
 480     gen_cc_NZ_icc(cpu_cc_dst);
 481     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 482     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 483 #ifdef TARGET_SPARC64
 484     gen_cc_NZ_xcc(cpu_cc_dst);
 485     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 486     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 487 #endif
 488     tcg_gen_mov_tl(dst, cpu_cc_dst);
 489 }
 490
 491 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
 492 {
 493     tcg_gen_mov_tl(cpu_cc_src, src1);
 494     tcg_gen_mov_tl(cpu_cc_src2, src2);
 495     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 496     gen_cc_clear_icc();
 497     gen_cc_NZ_icc(cpu_cc_dst);
 498     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 499     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 500     gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
 501 #ifdef TARGET_SPARC64
 502     gen_cc_clear_xcc();
 503     gen_cc_NZ_xcc(cpu_cc_dst);
 504     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 505     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 506 #endif
 507     tcg_gen_mov_tl(dst, cpu_cc_dst);
 508 }
 509
 510 static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
 511 {
 512     tcg_gen_mov_tl(cpu_cc_src, src1);
 513     tcg_gen_mov_tl(cpu_cc_src2, src2);
 514     gen_tag_tv(cpu_cc_src, cpu_cc_src2);
 515     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 516     gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 517     gen_cc_clear_icc();
 518     gen_cc_NZ_icc(cpu_cc_dst);
 519     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 520 #ifdef TARGET_SPARC64
 521     gen_cc_clear_xcc();
 522     gen_cc_NZ_xcc(cpu_cc_dst);
 523     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 524     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 525 #endif
 526     tcg_gen_mov_tl(dst, cpu_cc_dst);
 527 }
 528
 529 /* old op:
 530     if (src1 < T1)
 531         env->psr |= PSR_CARRY;
 532 */
 533 static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
 534 {
 535     TCGv r_temp1, r_temp2;
 536     int l1;
 537
 538     l1 = gen_new_label();
 539     r_temp1 = tcg_temp_new(TCG_TYPE_TL);
 540     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 541     tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
 542     tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
 543     tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
 544     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 545     gen_set_label(l1);
 546     tcg_temp_free(r_temp1);
 547     tcg_temp_free(r_temp2);
 548 }
 549
 550 #ifdef TARGET_SPARC64
 551 static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
 552 {
 553     int l1;
 554
 555     l1 = gen_new_label();
 556     tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
 557     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 558     gen_set_label(l1);
 559 }
 560 #endif
 561
 562 /* old op:
 563     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
 564         env->psr |= PSR_OVF;
 565 */
 566 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
 567 {
 568     TCGv r_temp;
 569
 570     r_temp = tcg_temp_new(TCG_TYPE_TL);
 571     tcg_gen_xor_tl(r_temp, src1, src2);
 572     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 573     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 574     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 575     tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
 576     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 577     tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
 578     tcg_temp_free(r_temp);
 579 }
 580
 581 #ifdef TARGET_SPARC64
 582 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
 583 {
 584     TCGv r_temp;
 585
 586     r_temp = tcg_temp_new(TCG_TYPE_TL);
 587     tcg_gen_xor_tl(r_temp, src1, src2);
 588     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 589     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 590     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 591     tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
 592     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 593     tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
 594     tcg_temp_free(r_temp);
 595 }
 596 #endif
 597
 598 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
 599 {
 600     TCGv r_temp, r_const;
 601     int l1;
 602
 603     l1 = gen_new_label();
 604
 605     r_temp = tcg_temp_new(TCG_TYPE_TL);
 606     tcg_gen_xor_tl(r_temp, src1, src2);
 607     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 608     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 609     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 610     tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
 611     r_const = tcg_const_i32(TT_TOVF);
 612     tcg_gen_helper_0_1(raise_exception, r_const);
 613     tcg_temp_free(r_const);
 614     gen_set_label(l1);
 615     tcg_temp_free(r_temp);
 616 }
 617
 618 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
 619 {
 620     tcg_gen_mov_tl(cpu_cc_src, src1);
 621     tcg_gen_mov_tl(cpu_cc_src2, src2);
 622     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 623     gen_cc_clear_icc();
 624     gen_cc_NZ_icc(cpu_cc_dst);
 625     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 626     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 627 #ifdef TARGET_SPARC64
 628     gen_cc_clear_xcc();
 629     gen_cc_NZ_xcc(cpu_cc_dst);
 630     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 631     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 632 #endif
 633     tcg_gen_mov_tl(dst, cpu_cc_dst);
 634 }
 635
 636 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
 637 {
 638     tcg_gen_mov_tl(cpu_cc_src, src1);
 639     tcg_gen_mov_tl(cpu_cc_src2, src2);
 640     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 641     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
 642     gen_cc_clear_icc();
 643     gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
 644 #ifdef TARGET_SPARC64
 645     gen_cc_clear_xcc();
 646     gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
 647 #endif
 648     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
 649     gen_cc_NZ_icc(cpu_cc_dst);
 650     gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
 651     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 652 #ifdef TARGET_SPARC64
 653     gen_cc_NZ_xcc(cpu_cc_dst);
 654     gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
 655     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 656 #endif
 657     tcg_gen_mov_tl(dst, cpu_cc_dst);
 658 }
 659
 660 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
 661 {
 662     tcg_gen_mov_tl(cpu_cc_src, src1);
 663     tcg_gen_mov_tl(cpu_cc_src2, src2);
 664     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 665     gen_cc_clear_icc();
 666     gen_cc_NZ_icc(cpu_cc_dst);
 667     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 668     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 669     gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
 670 #ifdef TARGET_SPARC64
 671     gen_cc_clear_xcc();
 672     gen_cc_NZ_xcc(cpu_cc_dst);
 673     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 674     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 675 #endif
 676     tcg_gen_mov_tl(dst, cpu_cc_dst);
 677 }
 678
 679 static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
 680 {
 681     tcg_gen_mov_tl(cpu_cc_src, src1);
 682     tcg_gen_mov_tl(cpu_cc_src2, src2);
 683     gen_tag_tv(cpu_cc_src, cpu_cc_src2);
 684     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 685     gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 686     gen_cc_clear_icc();
 687     gen_cc_NZ_icc(cpu_cc_dst);
 688     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 689 #ifdef TARGET_SPARC64
 690     gen_cc_clear_xcc();
 691     gen_cc_NZ_xcc(cpu_cc_dst);
 692     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 693     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 694 #endif
 695     tcg_gen_mov_tl(dst, cpu_cc_dst);
 696 }
 697
 698 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
 699 {
 700     TCGv r_temp, r_temp2;
 701     int l1;
 702
 703     l1 = gen_new_label();
 704     r_temp = tcg_temp_new(TCG_TYPE_TL);
 705     r_temp2 = tcg_temp_new(TCG_TYPE_I32);
 706
 707     /* old op:
 708     if (!(env->y & 1))
 709         T1 = 0;
 710     */
 711     tcg_gen_mov_tl(cpu_cc_src, src1);
 712     tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 713     tcg_gen_trunc_tl_i32(r_temp2, r_temp);
 714     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 715     tcg_gen_mov_tl(cpu_cc_src2, src2);
 716     tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
 717     tcg_gen_movi_tl(cpu_cc_src2, 0);
 718     gen_set_label(l1);
 719
 720     // b2 = T0 & 1;
 721     // env->y = (b2 << 31) | (env->y >> 1);
 722     tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
 723     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 724     tcg_gen_shli_i32(r_temp2, r_temp2, 31);
 725     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 726     tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
 727     tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
 728     tcg_temp_free(r_temp2);
 729     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 730
 731     // b1 = N ^ V;
 732     gen_mov_reg_N(cpu_tmp0, cpu_psr);
 733     gen_mov_reg_V(r_temp, cpu_psr);
 734     tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
 735     tcg_temp_free(r_temp);
 736
 737     // T0 = (b1 << 31) | (T0 >> 1);
 738     // src1 = T0;
 739     tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
 740     tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
 741     tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
 742
 743     /* do addition and update flags */
 744     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 745
 746     gen_cc_clear_icc();
 747     gen_cc_NZ_icc(cpu_cc_dst);
 748     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 749     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 750     tcg_gen_mov_tl(dst, cpu_cc_dst);
 751 }
 752
 753 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
 754 {
 755     TCGv r_temp, r_temp2;
 756
 757     r_temp = tcg_temp_new(TCG_TYPE_I64);
 758     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 759
 760     tcg_gen_extu_tl_i64(r_temp, src2);
 761     tcg_gen_extu_tl_i64(r_temp2, src1);
 762     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 763
 764     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 765     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 766     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 767     tcg_temp_free(r_temp);
 768 #ifdef TARGET_SPARC64
 769     tcg_gen_mov_i64(dst, r_temp2);
 770 #else
 771     tcg_gen_trunc_i64_tl(dst, r_temp2);
 772 #endif
 773     tcg_temp_free(r_temp2);
 774 }
 775
 776 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
 777 {
 778     TCGv r_temp, r_temp2;
 779
 780     r_temp = tcg_temp_new(TCG_TYPE_I64);
 781     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 782
 783     tcg_gen_ext_tl_i64(r_temp, src2);
 784     tcg_gen_ext_tl_i64(r_temp2, src1);
 785     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 786
 787     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 788     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 789     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 790     tcg_temp_free(r_temp);
 791 #ifdef TARGET_SPARC64
 792     tcg_gen_mov_i64(dst, r_temp2);
 793 #else
 794     tcg_gen_trunc_i64_tl(dst, r_temp2);
 795 #endif
 796     tcg_temp_free(r_temp2);
 797 }
 798
 799 #ifdef TARGET_SPARC64
 800 static inline void gen_trap_ifdivzero_tl(TCGv divisor)
 801 {
 802     TCGv r_const;
 803     int l1;
 804
 805     l1 = gen_new_label();
 806     tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
 807     r_const = tcg_const_i32(TT_DIV_ZERO);
 808     tcg_gen_helper_0_1(raise_exception, r_const);
 809     tcg_temp_free(r_const);
 810     gen_set_label(l1);
 811 }
 812
 813 static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
 814 {
 815     int l1, l2;
 816
 817     l1 = gen_new_label();
 818     l2 = gen_new_label();
 819     tcg_gen_mov_tl(cpu_cc_src, src1);
 820     tcg_gen_mov_tl(cpu_cc_src2, src2);
 821     gen_trap_ifdivzero_tl(cpu_cc_src2);
 822     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
 823     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
 824     tcg_gen_movi_i64(dst, INT64_MIN);
 825     tcg_gen_br(l2);
 826     gen_set_label(l1);
 827     tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
 828     gen_set_label(l2);
 829 }
 830 #endif
 831
 832 static inline void gen_op_div_cc(TCGv dst)
 833 {
 834     int l1;
 835
 836     tcg_gen_mov_tl(cpu_cc_dst, dst);
 837     gen_cc_clear_icc();
 838     gen_cc_NZ_icc(cpu_cc_dst);
 839     l1 = gen_new_label();
 840     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
 841     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 842     gen_set_label(l1);
 843 }
 844
 845 static inline void gen_op_logic_cc(TCGv dst)
 846 {
 847     tcg_gen_mov_tl(cpu_cc_dst, dst);
 848
 849     gen_cc_clear_icc();
 850     gen_cc_NZ_icc(cpu_cc_dst);
 851 #ifdef TARGET_SPARC64
 852     gen_cc_clear_xcc();
 853     gen_cc_NZ_xcc(cpu_cc_dst);
 854 #endif
 855 }
 856
 857 // 1
 858 static inline void gen_op_eval_ba(TCGv dst)
 859 {
 860     tcg_gen_movi_tl(dst, 1);
 861 }
 862
 863 // Z
 864 static inline void gen_op_eval_be(TCGv dst, TCGv src)
 865 {
 866     gen_mov_reg_Z(dst, src);
 867 }
 868
 869 // Z | (N ^ V)
 870 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
 871 {
 872     gen_mov_reg_N(cpu_tmp0, src);
 873     gen_mov_reg_V(dst, src);
 874     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 875     gen_mov_reg_Z(cpu_tmp0, src);
 876     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 877 }
 878
 879 // N ^ V
 880 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
 881 {
 882     gen_mov_reg_V(cpu_tmp0, src);
 883     gen_mov_reg_N(dst, src);
 884     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 885 }
 886
 887 // C | Z
 888 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
 889 {
 890     gen_mov_reg_Z(cpu_tmp0, src);
 891     gen_mov_reg_C(dst, src);
 892     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 893 }
 894
 895 // C
 896 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
 897 {
 898     gen_mov_reg_C(dst, src);
 899 }
 900
 901 // V
 902 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
 903 {
 904     gen_mov_reg_V(dst, src);
 905 }
 906
 907 // 0
 908 static inline void gen_op_eval_bn(TCGv dst)
 909 {
 910     tcg_gen_movi_tl(dst, 0);
 911 }
 912
 913 // N
 914 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
 915 {
 916     gen_mov_reg_N(dst, src);
 917 }
 918
 919 // !Z
 920 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
 921 {
 922     gen_mov_reg_Z(dst, src);
 923     tcg_gen_xori_tl(dst, dst, 0x1);
 924 }
 925
 926 // !(Z | (N ^ V))
 927 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
 928 {
 929     gen_mov_reg_N(cpu_tmp0, src);
 930     gen_mov_reg_V(dst, src);
 931     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 932     gen_mov_reg_Z(cpu_tmp0, src);
 933     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 934     tcg_gen_xori_tl(dst, dst, 0x1);
 935 }
 936
 937 // !(N ^ V)
 938 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
 939 {
 940     gen_mov_reg_V(cpu_tmp0, src);
 941     gen_mov_reg_N(dst, src);
 942     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 943     tcg_gen_xori_tl(dst, dst, 0x1);
 944 }
 945
 946 // !(C | Z)
 947 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
 948 {
 949     gen_mov_reg_Z(cpu_tmp0, src);
 950     gen_mov_reg_C(dst, src);
 951     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 952     tcg_gen_xori_tl(dst, dst, 0x1);
 953 }
 954
 955 // !C
 956 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
 957 {
 958     gen_mov_reg_C(dst, src);
 959     tcg_gen_xori_tl(dst, dst, 0x1);
 960 }
 961
 962 // !N
 963 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
 964 {
 965     gen_mov_reg_N(dst, src);
 966     tcg_gen_xori_tl(dst, dst, 0x1);
 967 }
 968
 969 // !V
 970 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
 971 {
 972     gen_mov_reg_V(dst, src);
 973     tcg_gen_xori_tl(dst, dst, 0x1);
 974 }
 975
 976 /*
 977   FPSR bit field FCC1 | FCC0:
 978    0 =
 979    1 <
 980    2 >
 981    3 unordered
 982 */
 983 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
 984                                     unsigned int fcc_offset)
 985 {
 986     tcg_gen_extu_i32_tl(reg, src);
 987     tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
 988     tcg_gen_andi_tl(reg, reg, 0x1);
 989 }
 990
 991 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
 992                                     unsigned int fcc_offset)
 993 {
 994     tcg_gen_extu_i32_tl(reg, src);
 995     tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
 996     tcg_gen_andi_tl(reg, reg, 0x1);
 997 }
 998
 999 // !0: FCC0 | FCC1
1000 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1001                                     unsigned int fcc_offset)
1002 {
1003     gen_mov_reg_FCC0(dst, src, fcc_offset);
1004     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1005     tcg_gen_or_tl(dst, dst, cpu_tmp0);
1006 }
1007
1008 // 1 or 2: FCC0 ^ FCC1
1009 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1010                                     unsigned int fcc_offset)
1011 {
1012     gen_mov_reg_FCC0(dst, src, fcc_offset);
1013     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1014     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1015 }
1016
1017 // 1 or 3: FCC0
1018 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1019                                     unsigned int fcc_offset)
1020 {
1021     gen_mov_reg_FCC0(dst, src, fcc_offset);
1022 }
1023
1024 // 1: FCC0 & !FCC1
1025 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1026                                     unsigned int fcc_offset)
1027 {
1028     gen_mov_reg_FCC0(dst, src, fcc_offset);
1029     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1030     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1031     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1032 }
1033
1034 // 2 or 3: FCC1
1035 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1036                                     unsigned int fcc_offset)
1037 {
1038     gen_mov_reg_FCC1(dst, src, fcc_offset);
1039 }
1040
1041 // 2: !FCC0 & FCC1
1042 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1043                                     unsigned int fcc_offset)
1044 {
1045     gen_mov_reg_FCC0(dst, src, fcc_offset);
1046     tcg_gen_xori_tl(dst, dst, 0x1);
1047     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1048     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1049 }
1050
1051 // 3: FCC0 & FCC1
1052 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1053                                     unsigned int fcc_offset)
1054 {
1055     gen_mov_reg_FCC0(dst, src, fcc_offset);
1056     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1057     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1058 }
1059
1060 // 0: !(FCC0 | FCC1)
1061 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1062                                     unsigned int fcc_offset)
1063 {
1064     gen_mov_reg_FCC0(dst, src, fcc_offset);
1065     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1066     tcg_gen_or_tl(dst, dst, cpu_tmp0);
1067     tcg_gen_xori_tl(dst, dst, 0x1);
1068 }
1069
1070 // 0 or 3: !(FCC0 ^ FCC1)
1071 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1072                                     unsigned int fcc_offset)
1073 {
1074     gen_mov_reg_FCC0(dst, src, fcc_offset);
1075     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1076     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1077     tcg_gen_xori_tl(dst, dst, 0x1);
1078 }
1079
1080 // 0 or 2: !FCC0
1081 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1082                                     unsigned int fcc_offset)
1083 {
1084     gen_mov_reg_FCC0(dst, src, fcc_offset);
1085     tcg_gen_xori_tl(dst, dst, 0x1);
1086 }
1087
1088 // !1: !(FCC0 & !FCC1)
1089 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1090                                     unsigned int fcc_offset)
1091 {
1092     gen_mov_reg_FCC0(dst, src, fcc_offset);
1093     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1094     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1095     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1096     tcg_gen_xori_tl(dst, dst, 0x1);
1097 }
1098
1099 // 0 or 1: !FCC1
1100 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1101                                     unsigned int fcc_offset)
1102 {
1103     gen_mov_reg_FCC1(dst, src, fcc_offset);
1104     tcg_gen_xori_tl(dst, dst, 0x1);
1105 }
1106
1107 // !2: !(!FCC0 & FCC1)
1108 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1109                                     unsigned int fcc_offset)
1110 {
1111     gen_mov_reg_FCC0(dst, src, fcc_offset);
1112     tcg_gen_xori_tl(dst, dst, 0x1);
1113     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1114     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1115     tcg_gen_xori_tl(dst, dst, 0x1);
1116 }
1117
1118 // !3: !(FCC0 & FCC1)
1119 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1120                                     unsigned int fcc_offset)
1121 {
1122     gen_mov_reg_FCC0(dst, src, fcc_offset);
1123     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1124     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1125     tcg_gen_xori_tl(dst, dst, 0x1);
1126 }
1127
1128 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1129                                target_ulong pc2, TCGv r_cond)
1130 {
1131     int l1;
1132
1133     l1 = gen_new_label();
1134
1135     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1136
1137     gen_goto_tb(dc, 0, pc1, pc1 + 4);
1138
1139     gen_set_label(l1);
1140     gen_goto_tb(dc, 1, pc2, pc2 + 4);
1141 }
1142
1143 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1144                                 target_ulong pc2, TCGv r_cond)
1145 {
1146     int l1;
1147
1148     l1 = gen_new_label();
1149
1150     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1151
1152     gen_goto_tb(dc, 0, pc2, pc1);
1153
1154     gen_set_label(l1);
1155     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1156 }
1157
1158 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1159                                       TCGv r_cond)
1160 {
1161     int l1, l2;
1162
1163     l1 = gen_new_label();
1164     l2 = gen_new_label();
1165
1166     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1167
1168     tcg_gen_movi_tl(cpu_npc, npc1);
1169     tcg_gen_br(l2);
1170
1171     gen_set_label(l1);
1172     tcg_gen_movi_tl(cpu_npc, npc2);
1173     gen_set_label(l2);
1174 }
1175
1176 /* call this function before using the condition register as it may
1177    have been set for a jump */
1178 static inline void flush_cond(DisasContext *dc, TCGv cond)
1179 {
1180     if (dc->npc == JUMP_PC) {
1181         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1182         dc->npc = DYNAMIC_PC;
1183     }
1184 }
1185
1186 static inline void save_npc(DisasContext *dc, TCGv cond)
1187 {
1188     if (dc->npc == JUMP_PC) {
1189         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1190         dc->npc = DYNAMIC_PC;
1191     } else if (dc->npc != DYNAMIC_PC) {
1192         tcg_gen_movi_tl(cpu_npc, dc->npc);
1193     }
1194 }
1195
1196 static inline void save_state(DisasContext *dc, TCGv cond)
1197 {
1198     tcg_gen_movi_tl(cpu_pc, dc->pc);
1199     save_npc(dc, cond);
1200 }
1201
1202 static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1203 {
1204     if (dc->npc == JUMP_PC) {
1205         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1206         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1207         dc->pc = DYNAMIC_PC;
1208     } else if (dc->npc == DYNAMIC_PC) {
1209         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1210         dc->pc = DYNAMIC_PC;
1211     } else {
1212         dc->pc = dc->npc;
1213     }
1214 }
1215
1216 static inline void gen_op_next_insn(void)
1217 {
1218     tcg_gen_mov_tl(cpu_pc, cpu_npc);
1219     tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1220 }
1221
1222 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1223 {
1224     TCGv r_src;
1225
1226 #ifdef TARGET_SPARC64
1227     if (cc)
1228         r_src = cpu_xcc;
1229     else
1230         r_src = cpu_psr;
1231 #else
1232     r_src = cpu_psr;
1233 #endif
1234     switch (cond) {
1235     case 0x0:
1236         gen_op_eval_bn(r_dst);
1237         break;
1238     case 0x1:
1239         gen_op_eval_be(r_dst, r_src);
1240         break;
1241     case 0x2:
1242         gen_op_eval_ble(r_dst, r_src);
1243         break;
1244     case 0x3:
1245         gen_op_eval_bl(r_dst, r_src);
1246         break;
1247     case 0x4:
1248         gen_op_eval_bleu(r_dst, r_src);
1249         break;
1250     case 0x5:
1251         gen_op_eval_bcs(r_dst, r_src);
1252         break;
1253     case 0x6:
1254         gen_op_eval_bneg(r_dst, r_src);
1255         break;
1256     case 0x7:
1257         gen_op_eval_bvs(r_dst, r_src);
1258         break;
1259     case 0x8:
1260         gen_op_eval_ba(r_dst);
1261         break;
1262     case 0x9:
1263         gen_op_eval_bne(r_dst, r_src);
1264         break;
1265     case 0xa:
1266         gen_op_eval_bg(r_dst, r_src);
1267         break;
1268     case 0xb:
1269         gen_op_eval_bge(r_dst, r_src);
1270         break;
1271     case 0xc:
1272         gen_op_eval_bgu(r_dst, r_src);
1273         break;
1274     case 0xd:
1275         gen_op_eval_bcc(r_dst, r_src);
1276         break;
1277     case 0xe:
1278         gen_op_eval_bpos(r_dst, r_src);
1279         break;
1280     case 0xf:
1281         gen_op_eval_bvc(r_dst, r_src);
1282         break;
1283     }
1284 }
1285
1286 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1287 {
1288     unsigned int offset;
1289
1290     switch (cc) {
1291     default:
1292     case 0x0:
1293         offset = 0;
1294         break;
1295     case 0x1:
1296         offset = 32 - 10;
1297         break;
1298     case 0x2:
1299         offset = 34 - 10;
1300         break;
1301     case 0x3:
1302         offset = 36 - 10;
1303         break;
1304     }
1305
1306     switch (cond) {
1307     case 0x0:
1308         gen_op_eval_bn(r_dst);
1309         break;
1310     case 0x1:
1311         gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1312         break;
1313     case 0x2:
1314         gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1315         break;
1316     case 0x3:
1317         gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1318         break;
1319     case 0x4:
1320         gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1321         break;
1322     case 0x5:
1323         gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1324         break;
1325     case 0x6:
1326         gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1327         break;
1328     case 0x7:
1329         gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1330         break;
1331     case 0x8:
1332         gen_op_eval_ba(r_dst);
1333         break;
1334     case 0x9:
1335         gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1336         break;
1337     case 0xa:
1338         gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1339         break;
1340     case 0xb:
1341         gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1342         break;
1343     case 0xc:
1344         gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1345         break;
1346     case 0xd:
1347         gen_op_eval_fble(r_dst, cpu_fsr, offset);
1348         break;
1349     case 0xe:
1350         gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1351         break;
1352     case 0xf:
1353         gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1354         break;
1355     }
1356 }
1357
1358 #ifdef TARGET_SPARC64
1359 // Inverted logic
1360 static const int gen_tcg_cond_reg[8] = {
1361     -1,
1362     TCG_COND_NE,
1363     TCG_COND_GT,
1364     TCG_COND_GE,
1365     -1,
1366     TCG_COND_EQ,
1367     TCG_COND_LE,
1368     TCG_COND_LT,
1369 };
1370
1371 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1372 {
1373     int l1;
1374
1375     l1 = gen_new_label();
1376     tcg_gen_movi_tl(r_dst, 0);
1377     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1378     tcg_gen_movi_tl(r_dst, 1);
1379     gen_set_label(l1);
1380 }
1381 #endif
1382
1383 /* XXX: potentially incorrect if dynamic npc */
1384 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1385                       TCGv r_cond)
1386 {
1387     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1388     target_ulong target = dc->pc + offset;
1389
1390     if (cond == 0x0) {
1391         /* unconditional not taken */
1392         if (a) {
1393             dc->pc = dc->npc + 4;
1394             dc->npc = dc->pc + 4;
1395         } else {
1396             dc->pc = dc->npc;
1397             dc->npc = dc->pc + 4;
1398         }
1399     } else if (cond == 0x8) {
1400         /* unconditional taken */
1401         if (a) {
1402             dc->pc = target;
1403             dc->npc = dc->pc + 4;
1404         } else {
1405             dc->pc = dc->npc;
1406             dc->npc = target;
1407         }
1408     } else {
1409         flush_cond(dc, r_cond);
1410         gen_cond(r_cond, cc, cond);
1411         if (a) {
1412             gen_branch_a(dc, target, dc->npc, r_cond);
1413             dc->is_br = 1;
1414         } else {
1415             dc->pc = dc->npc;
1416             dc->jump_pc[0] = target;
1417             dc->jump_pc[1] = dc->npc + 4;
1418             dc->npc = JUMP_PC;
1419         }
1420     }
1421 }
1422
1423 /* XXX: potentially incorrect if dynamic npc */
1424 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1425                       TCGv r_cond)
1426 {
1427     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1428     target_ulong target = dc->pc + offset;
1429
1430     if (cond == 0x0) {
1431         /* unconditional not taken */
1432         if (a) {
1433             dc->pc = dc->npc + 4;
1434             dc->npc = dc->pc + 4;
1435         } else {
1436             dc->pc = dc->npc;
1437             dc->npc = dc->pc + 4;
1438         }
1439     } else if (cond == 0x8) {
1440         /* unconditional taken */
1441         if (a) {
1442             dc->pc = target;
1443             dc->npc = dc->pc + 4;
1444         } else {
1445             dc->pc = dc->npc;
1446             dc->npc = target;
1447         }
1448     } else {
1449         flush_cond(dc, r_cond);
1450         gen_fcond(r_cond, cc, cond);
1451         if (a) {
1452             gen_branch_a(dc, target, dc->npc, r_cond);
1453             dc->is_br = 1;
1454         } else {
1455             dc->pc = dc->npc;
1456             dc->jump_pc[0] = target;
1457             dc->jump_pc[1] = dc->npc + 4;
1458             dc->npc = JUMP_PC;
1459         }
1460     }
1461 }
1462
1463 #ifdef TARGET_SPARC64
1464 /* XXX: potentially incorrect if dynamic npc */
1465 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1466                           TCGv r_cond, TCGv r_reg)
1467 {
1468     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1469     target_ulong target = dc->pc + offset;
1470
1471     flush_cond(dc, r_cond);
1472     gen_cond_reg(r_cond, cond, r_reg);
1473     if (a) {
1474         gen_branch_a(dc, target, dc->npc, r_cond);
1475         dc->is_br = 1;
1476     } else {
1477         dc->pc = dc->npc;
1478         dc->jump_pc[0] = target;
1479         dc->jump_pc[1] = dc->npc + 4;
1480         dc->npc = JUMP_PC;
1481     }
1482 }
1483
1484 static GenOpFunc * const gen_fcmps[4] = {
1485     helper_fcmps,
1486     helper_fcmps_fcc1,
1487     helper_fcmps_fcc2,
1488     helper_fcmps_fcc3,
1489 };
1490
1491 static GenOpFunc * const gen_fcmpd[4] = {
1492     helper_fcmpd,
1493     helper_fcmpd_fcc1,
1494     helper_fcmpd_fcc2,
1495     helper_fcmpd_fcc3,
1496 };
1497
1498 static GenOpFunc * const gen_fcmpq[4] = {
1499     helper_fcmpq,
1500     helper_fcmpq_fcc1,
1501     helper_fcmpq_fcc2,
1502     helper_fcmpq_fcc3,
1503 };
1504
1505 static GenOpFunc * const gen_fcmpes[4] = {
1506     helper_fcmpes,
1507     helper_fcmpes_fcc1,
1508     helper_fcmpes_fcc2,
1509     helper_fcmpes_fcc3,
1510 };
1511
1512 static GenOpFunc * const gen_fcmped[4] = {
1513     helper_fcmped,
1514     helper_fcmped_fcc1,
1515     helper_fcmped_fcc2,
1516     helper_fcmped_fcc3,
1517 };
1518
1519 static GenOpFunc * const gen_fcmpeq[4] = {
1520     helper_fcmpeq,
1521     helper_fcmpeq_fcc1,
1522     helper_fcmpeq_fcc2,
1523     helper_fcmpeq_fcc3,
1524 };
1525
1526 static inline void gen_op_fcmps(int fccno)
1527 {
1528     tcg_gen_helper_0_0(gen_fcmps[fccno]);
1529 }
1530
1531 static inline void gen_op_fcmpd(int fccno)
1532 {
1533     tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1534 }
1535
1536 static inline void gen_op_fcmpq(int fccno)
1537 {
1538     tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1539 }
1540
1541 static inline void gen_op_fcmpes(int fccno)
1542 {
1543     tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1544 }
1545
1546 static inline void gen_op_fcmped(int fccno)
1547 {
1548     tcg_gen_helper_0_0(gen_fcmped[fccno]);
1549 }
1550
1551 static inline void gen_op_fcmpeq(int fccno)
1552 {
1553     tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1554 }
1555
1556 #else
1557
1558 static inline void gen_op_fcmps(int fccno)
1559 {
1560     tcg_gen_helper_0_0(helper_fcmps);
1561 }
1562
1563 static inline void gen_op_fcmpd(int fccno)
1564 {
1565     tcg_gen_helper_0_0(helper_fcmpd);
1566 }
1567
1568 static inline void gen_op_fcmpq(int fccno)
1569 {
1570     tcg_gen_helper_0_0(helper_fcmpq);
1571 }
1572
1573 static inline void gen_op_fcmpes(int fccno)
1574 {
1575     tcg_gen_helper_0_0(helper_fcmpes);
1576 }
1577
1578 static inline void gen_op_fcmped(int fccno)
1579 {
1580     tcg_gen_helper_0_0(helper_fcmped);
1581 }
1582
1583 static inline void gen_op_fcmpeq(int fccno)
1584 {
1585     tcg_gen_helper_0_0(helper_fcmpeq);
1586 }
1587 #endif
1588
1589 static inline void gen_op_fpexception_im(int fsr_flags)
1590 {
1591     TCGv r_const;
1592
1593     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1594     tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1595     r_const = tcg_const_i32(TT_FP_EXCP);
1596     tcg_gen_helper_0_1(raise_exception, r_const);
1597     tcg_temp_free(r_const);
1598 }
1599
1600 static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1601 {
1602 #if !defined(CONFIG_USER_ONLY)
1603     if (!dc->fpu_enabled) {
1604         TCGv r_const;
1605
1606         save_state(dc, r_cond);
1607         r_const = tcg_const_i32(TT_NFPU_INSN);
1608         tcg_gen_helper_0_1(raise_exception, r_const);
1609         tcg_temp_free(r_const);
1610         dc->is_br = 1;
1611         return 1;
1612     }
1613 #endif
1614     return 0;
1615 }
1616
1617 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1618 {
1619     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1620 }
1621
1622 static inline void gen_clear_float_exceptions(void)
1623 {
1624     tcg_gen_helper_0_0(helper_clear_float_exceptions);
1625 }
1626
1627 /* asi moves */
1628 #ifdef TARGET_SPARC64
1629 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1630 {
1631     int asi, offset;
1632     TCGv r_asi;
1633
1634     if (IS_IMM) {
1635         r_asi = tcg_temp_new(TCG_TYPE_I32);
1636         offset = GET_FIELD(insn, 25, 31);
1637         tcg_gen_addi_tl(r_addr, r_addr, offset);
1638         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1639     } else {
1640         asi = GET_FIELD(insn, 19, 26);
1641         r_asi = tcg_const_i32(asi);
1642     }
1643     return r_asi;
1644 }
1645
1646 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1647                               int sign)
1648 {
1649     TCGv r_asi, r_size, r_sign;
1650
1651     r_asi = gen_get_asi(insn, addr);
1652     r_size = tcg_const_i32(size);
1653     r_sign = tcg_const_i32(sign);
1654     tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1655     tcg_temp_free(r_sign);
1656     tcg_temp_free(r_size);
1657     tcg_temp_free(r_asi);
1658 }
1659
1660 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1661 {
1662     TCGv r_asi, r_size;
1663
1664     r_asi = gen_get_asi(insn, addr);
1665     r_size = tcg_const_i32(size);
1666     tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1667     tcg_temp_free(r_size);
1668     tcg_temp_free(r_asi);
1669 }
1670
1671 static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1672 {
1673     TCGv r_asi, r_size, r_rd;
1674
1675     r_asi = gen_get_asi(insn, addr);
1676     r_size = tcg_const_i32(size);
1677     r_rd = tcg_const_i32(rd);
1678     tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1679     tcg_temp_free(r_rd);
1680     tcg_temp_free(r_size);
1681     tcg_temp_free(r_asi);
1682 }
1683
1684 static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1685 {
1686     TCGv r_asi, r_size, r_rd;
1687
1688     r_asi = gen_get_asi(insn, addr);
1689     r_size = tcg_const_i32(size);
1690     r_rd = tcg_const_i32(rd);
1691     tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1692     tcg_temp_free(r_rd);
1693     tcg_temp_free(r_size);
1694     tcg_temp_free(r_asi);
1695 }
1696
1697 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1698 {
1699     TCGv r_asi, r_size, r_sign;
1700
1701     r_asi = gen_get_asi(insn, addr);
1702     r_size = tcg_const_i32(4);
1703     r_sign = tcg_const_i32(0);
1704     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1705     tcg_temp_free(r_sign);
1706     tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1707     tcg_temp_free(r_size);
1708     tcg_temp_free(r_asi);
1709     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1710 }
1711
1712 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1713 {
1714     TCGv r_asi, r_size, r_sign;
1715
1716     r_asi = gen_get_asi(insn, addr);
1717     r_size = tcg_const_i32(8);
1718     r_sign = tcg_const_i32(0);
1719     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1720     tcg_temp_free(r_sign);
1721     tcg_temp_free(r_size);
1722     tcg_temp_free(r_asi);
1723     tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1724     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1725     tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1726 }
1727
1728 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1729 {
1730     TCGv r_temp, r_asi, r_size;
1731
1732     r_temp = tcg_temp_new(TCG_TYPE_TL);
1733     gen_movl_reg_TN(rd + 1, r_temp);
1734     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1735                        r_temp);
1736     tcg_temp_free(r_temp);
1737     r_asi = gen_get_asi(insn, addr);
1738     r_size = tcg_const_i32(8);
1739     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1740     tcg_temp_free(r_size);
1741     tcg_temp_free(r_asi);
1742 }
1743
1744 static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1745                                int rd)
1746 {
1747     TCGv r_val1, r_asi;
1748
1749     r_val1 = tcg_temp_new(TCG_TYPE_TL);
1750     gen_movl_reg_TN(rd, r_val1);
1751     r_asi = gen_get_asi(insn, addr);
1752     tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1753     tcg_temp_free(r_asi);
1754     tcg_temp_free(r_val1);
1755 }
1756
1757 static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1758                                 int rd)
1759 {
1760     TCGv r_asi;
1761
1762     gen_movl_reg_TN(rd, cpu_tmp64);
1763     r_asi = gen_get_asi(insn, addr);
1764     tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1765     tcg_temp_free(r_asi);
1766 }
1767
1768 #elif !defined(CONFIG_USER_ONLY)
1769
1770 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1771                               int sign)
1772 {
1773     TCGv r_asi, r_size, r_sign;
1774
1775     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1776     r_size = tcg_const_i32(size);
1777     r_sign = tcg_const_i32(sign);
1778     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1779     tcg_temp_free(r_sign);
1780     tcg_temp_free(r_size);
1781     tcg_temp_free(r_asi);
1782     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1783 }
1784
1785 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1786 {
1787     TCGv r_asi, r_size;
1788
1789     tcg_gen_extu_tl_i64(cpu_tmp64, src);
1790     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1791     r_size = tcg_const_i32(size);
1792     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1793     tcg_temp_free(r_size);
1794     tcg_temp_free(r_asi);
1795 }
1796
1797 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1798 {
1799     TCGv r_asi, r_size, r_sign;
1800
1801     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1802     r_size = tcg_const_i32(4);
1803     r_sign = tcg_const_i32(0);
1804     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1805     tcg_temp_free(r_sign);
1806     tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1807     tcg_temp_free(r_size);
1808     tcg_temp_free(r_asi);
1809     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1810 }
1811
1812 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1813 {
1814     TCGv r_asi, r_size, r_sign;
1815
1816     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1817     r_size = tcg_const_i32(8);
1818     r_sign = tcg_const_i32(0);
1819     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1820     tcg_temp_free(r_sign);
1821     tcg_temp_free(r_size);
1822     tcg_temp_free(r_asi);
1823     tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1824     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1825     tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1826 }
1827
1828 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1829 {
1830     TCGv r_temp, r_asi, r_size;
1831
1832     r_temp = tcg_temp_new(TCG_TYPE_TL);
1833     gen_movl_reg_TN(rd + 1, r_temp);
1834     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1835     tcg_temp_free(r_temp);
1836     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1837     r_size = tcg_const_i32(8);
1838     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1839     tcg_temp_free(r_size);
1840     tcg_temp_free(r_asi);
1841 }
1842 #endif
1843
1844 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1845 static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1846 {
1847     TCGv r_val, r_asi, r_size;
1848
1849     gen_ld_asi(dst, addr, insn, 1, 0);
1850
1851     r_val = tcg_const_i64(0xffULL);
1852     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1853     r_size = tcg_const_i32(1);
1854     tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1855     tcg_temp_free(r_size);
1856     tcg_temp_free(r_asi);
1857     tcg_temp_free(r_val);
1858 }
1859 #endif
1860
1861 static inline TCGv get_src1(unsigned int insn, TCGv def)
1862 {
1863     TCGv r_rs1 = def;
1864     unsigned int rs1;
1865
1866     rs1 = GET_FIELD(insn, 13, 17);
1867     if (rs1 == 0)
1868         r_rs1 = tcg_const_tl(0); // XXX how to free?
1869     else if (rs1 < 8)
1870         r_rs1 = cpu_gregs[rs1];
1871     else
1872         tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1873     return r_rs1;
1874 }
1875
1876 static inline TCGv get_src2(unsigned int insn, TCGv def)
1877 {
1878     TCGv r_rs2 = def;
1879     unsigned int rs2;
1880
1881     if (IS_IMM) { /* immediate */
1882         rs2 = GET_FIELDs(insn, 19, 31);
1883         r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1884     } else { /* register */
1885         rs2 = GET_FIELD(insn, 27, 31);
1886         if (rs2 == 0)
1887             r_rs2 = tcg_const_tl(0); // XXX how to free?
1888         else if (rs2 < 8)
1889             r_rs2 = cpu_gregs[rs2];
1890         else
1891             tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1892     }
1893     return r_rs2;
1894 }
1895
1896 #define CHECK_IU_FEATURE(dc, FEATURE)                      \
1897     if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1898         goto illegal_insn;
1899 #define CHECK_FPU_FEATURE(dc, FEATURE)                     \
1900     if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1901         goto nfpu_insn;
1902
1903 /* before an instruction, dc->pc must be static */
1904 static void disas_sparc_insn(DisasContext * dc)
1905 {
1906     unsigned int insn, opc, rs1, rs2, rd;
1907
1908     if (unlikely(loglevel & CPU_LOG_TB_OP))
1909         tcg_gen_debug_insn_start(dc->pc);
1910     insn = ldl_code(dc->pc);
1911     opc = GET_FIELD(insn, 0, 1);
1912
1913     rd = GET_FIELD(insn, 2, 6);
1914
1915     cpu_dst = cpu_T[0];
1916     cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1917     cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
1918
1919     // loads and stores
1920     cpu_addr = cpu_T[0];
1921
1922     switch (opc) {
1923     case 0:                     /* branches/sethi */
1924         {
1925             unsigned int xop = GET_FIELD(insn, 7, 9);
1926             int32_t target;
1927             switch (xop) {
1928 #ifdef TARGET_SPARC64
1929             case 0x1:           /* V9 BPcc */
1930                 {
1931                     int cc;
1932
1933                     target = GET_FIELD_SP(insn, 0, 18);
1934                     target = sign_extend(target, 18);
1935                     target <<= 2;
1936                     cc = GET_FIELD_SP(insn, 20, 21);
1937                     if (cc == 0)
1938                         do_branch(dc, target, insn, 0, cpu_cond);
1939                     else if (cc == 2)
1940                         do_branch(dc, target, insn, 1, cpu_cond);
1941                     else
1942                         goto illegal_insn;
1943                     goto jmp_insn;
1944                 }
1945             case 0x3:           /* V9 BPr */
1946                 {
1947                     target = GET_FIELD_SP(insn, 0, 13) |
1948                         (GET_FIELD_SP(insn, 20, 21) << 14);
1949                     target = sign_extend(target, 16);
1950                     target <<= 2;
1951                     cpu_src1 = get_src1(insn, cpu_src1);
1952                     do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1953                     goto jmp_insn;
1954                 }
1955             case 0x5:           /* V9 FBPcc */
1956                 {
1957                     int cc = GET_FIELD_SP(insn, 20, 21);
1958                     if (gen_trap_ifnofpu(dc, cpu_cond))
1959                         goto jmp_insn;
1960                     target = GET_FIELD_SP(insn, 0, 18);
1961                     target = sign_extend(target, 19);
1962                     target <<= 2;
1963                     do_fbranch(dc, target, insn, cc, cpu_cond);
1964                     goto jmp_insn;
1965                 }
1966 #else
1967             case 0x7:           /* CBN+x */
1968                 {
1969                     goto ncp_insn;
1970                 }
1971 #endif
1972             case 0x2:           /* BN+x */
1973                 {
1974                     target = GET_FIELD(insn, 10, 31);
1975                     target = sign_extend(target, 22);
1976                     target <<= 2;
1977                     do_branch(dc, target, insn, 0, cpu_cond);
1978                     goto jmp_insn;
1979                 }
1980             case 0x6:           /* FBN+x */
1981                 {
1982                     if (gen_trap_ifnofpu(dc, cpu_cond))
1983                         goto jmp_insn;
1984                     target = GET_FIELD(insn, 10, 31);
1985                     target = sign_extend(target, 22);
1986                     target <<= 2;
1987                     do_fbranch(dc, target, insn, 0, cpu_cond);
1988                     goto jmp_insn;
1989                 }
1990             case 0x4:           /* SETHI */
1991                 if (rd) { // nop
1992                     uint32_t value = GET_FIELD(insn, 10, 31);
1993                     TCGv r_const;
1994
1995                     r_const = tcg_const_tl(value << 10);
1996                     gen_movl_TN_reg(rd, r_const);
1997                     tcg_temp_free(r_const);
1998                 }
1999                 break;
2000             case 0x0:           /* UNIMPL */
2001             default:
2002                 goto illegal_insn;
2003             }
2004             break;
2005         }
2006         break;
2007     case 1:
2008         /*CALL*/ {
2009             target_long target = GET_FIELDs(insn, 2, 31) << 2;
2010             TCGv r_const;
2011
2012             r_const = tcg_const_tl(dc->pc);
2013             gen_movl_TN_reg(15, r_const);
2014             tcg_temp_free(r_const);
2015             target += dc->pc;
2016             gen_mov_pc_npc(dc, cpu_cond);
2017             dc->npc = target;
2018         }
2019         goto jmp_insn;
2020     case 2:                     /* FPU & Logical Operations */
2021         {
2022             unsigned int xop = GET_FIELD(insn, 7, 12);
2023             if (xop == 0x3a) {  /* generate trap */
2024                 int cond;
2025
2026                 cpu_src1 = get_src1(insn, cpu_src1);
2027                 if (IS_IMM) {
2028                     rs2 = GET_FIELD(insn, 25, 31);
2029                     tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2030                 } else {
2031                     rs2 = GET_FIELD(insn, 27, 31);
2032                     if (rs2 != 0) {
2033                         gen_movl_reg_TN(rs2, cpu_src2);
2034                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2035                     } else
2036                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
2037                 }
2038                 cond = GET_FIELD(insn, 3, 6);
2039                 if (cond == 0x8) {
2040                     save_state(dc, cpu_cond);
2041                     tcg_gen_helper_0_1(helper_trap, cpu_dst);
2042                 } else if (cond != 0) {
2043                     TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2044 #ifdef TARGET_SPARC64
2045                     /* V9 icc/xcc */
2046                     int cc = GET_FIELD_SP(insn, 11, 12);
2047
2048                     save_state(dc, cpu_cond);
2049                     if (cc == 0)
2050                         gen_cond(r_cond, 0, cond);
2051                     else if (cc == 2)
2052                         gen_cond(r_cond, 1, cond);
2053                     else
2054                         goto illegal_insn;
2055 #else
2056                     save_state(dc, cpu_cond);
2057                     gen_cond(r_cond, 0, cond);
2058 #endif
2059                     tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2060                     tcg_temp_free(r_cond);
2061                 }
2062                 gen_op_next_insn();
2063                 tcg_gen_exit_tb(0);
2064                 dc->is_br = 1;
2065                 goto jmp_insn;
2066             } else if (xop == 0x28) {
2067                 rs1 = GET_FIELD(insn, 13, 17);
2068                 switch(rs1) {
2069                 case 0: /* rdy */
2070 #ifndef TARGET_SPARC64
2071                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2072                                        manual, rdy on the microSPARC
2073                                        II */
2074                 case 0x0f:          /* stbar in the SPARCv8 manual,
2075                                        rdy on the microSPARC II */
2076                 case 0x10 ... 0x1f: /* implementation-dependent in the
2077                                        SPARCv8 manual, rdy on the
2078                                        microSPARC II */
2079 #endif
2080                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2081                                   offsetof(CPUSPARCState, y));
2082                     gen_movl_TN_reg(rd, cpu_tmp0);
2083                     break;
2084 #ifdef TARGET_SPARC64
2085                 case 0x2: /* V9 rdccr */
2086                     tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2087                     gen_movl_TN_reg(rd, cpu_dst);
2088                     break;
2089                 case 0x3: /* V9 rdasi */
2090                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2091                                    offsetof(CPUSPARCState, asi));
2092                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2093                     gen_movl_TN_reg(rd, cpu_dst);
2094                     break;
2095                 case 0x4: /* V9 rdtick */
2096                     {
2097                         TCGv r_tickptr;
2098
2099                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2100                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2101                                        offsetof(CPUState, tick));
2102                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2103                                            r_tickptr);
2104                         tcg_temp_free(r_tickptr);
2105                         gen_movl_TN_reg(rd, cpu_dst);
2106                     }
2107                     break;
2108                 case 0x5: /* V9 rdpc */
2109                     {
2110                         TCGv r_const;
2111
2112                         r_const = tcg_const_tl(dc->pc);
2113                         gen_movl_TN_reg(rd, r_const);
2114                         tcg_temp_free(r_const);
2115                     }
2116                     break;
2117                 case 0x6: /* V9 rdfprs */
2118                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2119                                    offsetof(CPUSPARCState, fprs));
2120                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2121                     gen_movl_TN_reg(rd, cpu_dst);
2122                     break;
2123                 case 0xf: /* V9 membar */
2124                     break; /* no effect */
2125                 case 0x13: /* Graphics Status */
2126                     if (gen_trap_ifnofpu(dc, cpu_cond))
2127                         goto jmp_insn;
2128                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2129                                   offsetof(CPUSPARCState, gsr));
2130                     gen_movl_TN_reg(rd, cpu_tmp0);
2131                     break;
2132                 case 0x17: /* Tick compare */
2133                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2134                                   offsetof(CPUSPARCState, tick_cmpr));
2135                     gen_movl_TN_reg(rd, cpu_tmp0);
2136                     break;
2137                 case 0x18: /* System tick */
2138                     {
2139                         TCGv r_tickptr;
2140
2141                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2142                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2143                                        offsetof(CPUState, stick));
2144                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2145                                            r_tickptr);
2146                         tcg_temp_free(r_tickptr);
2147                         gen_movl_TN_reg(rd, cpu_dst);
2148                     }
2149                     break;
2150                 case 0x19: /* System tick compare */
2151                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2152                                   offsetof(CPUSPARCState, stick_cmpr));
2153                     gen_movl_TN_reg(rd, cpu_tmp0);
2154                     break;
2155                 case 0x10: /* Performance Control */
2156                 case 0x11: /* Performance Instrumentation Counter */
2157                 case 0x12: /* Dispatch Control */
2158                 case 0x14: /* Softint set, WO */
2159                 case 0x15: /* Softint clear, WO */
2160                 case 0x16: /* Softint write */
2161 #endif
2162                 default:
2163                     goto illegal_insn;
2164                 }
2165 #if !defined(CONFIG_USER_ONLY)
2166             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2167 #ifndef TARGET_SPARC64
2168                 if (!supervisor(dc))
2169                     goto priv_insn;
2170                 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2171 #else
2172                 if (!hypervisor(dc))
2173                     goto priv_insn;
2174                 rs1 = GET_FIELD(insn, 13, 17);
2175                 switch (rs1) {
2176                 case 0: // hpstate
2177                     // gen_op_rdhpstate();
2178                     break;
2179                 case 1: // htstate
2180                     // gen_op_rdhtstate();
2181                     break;
2182                 case 3: // hintp
2183                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2184                                    offsetof(CPUSPARCState, hintp));
2185                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2186                     break;
2187                 case 5: // htba
2188                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2189                                    offsetof(CPUSPARCState, htba));
2190                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2191                     break;
2192                 case 6: // hver
2193                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2194                                    offsetof(CPUSPARCState, hver));
2195                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2196                     break;
2197                 case 31: // hstick_cmpr
2198                     tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2199                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
2200                                    offsetof(CPUSPARCState, hstick_cmpr));
2201                     break;
2202                 default:
2203                     goto illegal_insn;
2204                 }
2205 #endif
2206                 gen_movl_TN_reg(rd, cpu_dst);
2207                 break;
2208             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2209                 if (!supervisor(dc))
2210                     goto priv_insn;
2211 #ifdef TARGET_SPARC64
2212                 rs1 = GET_FIELD(insn, 13, 17);
2213                 switch (rs1) {
2214                 case 0: // tpc
2215                     {
2216                         TCGv r_tsptr;
2217
2218                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2219                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2220                                        offsetof(CPUState, tsptr));
2221                         tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2222                                       offsetof(trap_state, tpc));
2223                         tcg_temp_free(r_tsptr);
2224                     }
2225                     break;
2226                 case 1: // tnpc
2227                     {
2228                         TCGv r_tsptr;
2229
2230                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2231                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2232                                        offsetof(CPUState, tsptr));
2233                         tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2234                                       offsetof(trap_state, tnpc));
2235                         tcg_temp_free(r_tsptr);
2236                     }
2237                     break;
2238                 case 2: // tstate
2239                     {
2240                         TCGv r_tsptr;
2241
2242                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2243                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2244                                        offsetof(CPUState, tsptr));
2245                         tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2246                                       offsetof(trap_state, tstate));
2247                         tcg_temp_free(r_tsptr);
2248                     }
2249                     break;
2250                 case 3: // tt
2251                     {
2252                         TCGv r_tsptr;
2253
2254                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2255                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2256                                        offsetof(CPUState, tsptr));
2257                         tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
2258                                        offsetof(trap_state, tt));
2259                         tcg_temp_free(r_tsptr);
2260                     }
2261                     break;
2262                 case 4: // tick
2263                     {
2264                         TCGv r_tickptr;
2265
2266                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2267                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2268                                        offsetof(CPUState, tick));
2269                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
2270                                            r_tickptr);
2271                         gen_movl_TN_reg(rd, cpu_tmp0);
2272                         tcg_temp_free(r_tickptr);
2273                     }
2274                     break;
2275                 case 5: // tba
2276                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2277                                   offsetof(CPUSPARCState, tbr));
2278                     break;
2279                 case 6: // pstate
2280                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2281                                    offsetof(CPUSPARCState, pstate));
2282                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2283                     break;
2284                 case 7: // tl
2285                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2286                                    offsetof(CPUSPARCState, tl));
2287                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2288                     break;
2289                 case 8: // pil
2290                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2291                                    offsetof(CPUSPARCState, psrpil));
2292                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2293                     break;
2294                 case 9: // cwp
2295                     tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
2296                     break;
2297                 case 10: // cansave
2298                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2299                                    offsetof(CPUSPARCState, cansave));
2300                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2301                     break;
2302                 case 11: // canrestore
2303                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2304                                    offsetof(CPUSPARCState, canrestore));
2305                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2306                     break;
2307                 case 12: // cleanwin
2308                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2309                                    offsetof(CPUSPARCState, cleanwin));
2310                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2311                     break;
2312                 case 13: // otherwin
2313                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2314                                    offsetof(CPUSPARCState, otherwin));
2315                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2316                     break;
2317                 case 14: // wstate
2318                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2319                                    offsetof(CPUSPARCState, wstate));
2320                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2321                     break;
2322                 case 16: // UA2005 gl
2323                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2324                                    offsetof(CPUSPARCState, gl));
2325                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2326                     break;
2327                 case 26: // UA2005 strand status
2328                     if (!hypervisor(dc))
2329                         goto priv_insn;
2330                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2331                                    offsetof(CPUSPARCState, ssr));
2332                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2333                     break;
2334                 case 31: // ver
2335                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2336                                   offsetof(CPUSPARCState, version));
2337                     break;
2338                 case 15: // fq
2339                 default:
2340                     goto illegal_insn;
2341                 }
2342 #else
2343                 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2344                                offsetof(CPUSPARCState, wim));
2345                 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2346 #endif
2347                 gen_movl_TN_reg(rd, cpu_tmp0);
2348                 break;
2349             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2350 #ifdef TARGET_SPARC64
2351                 tcg_gen_helper_0_0(helper_flushw);
2352 #else
2353                 if (!supervisor(dc))
2354                     goto priv_insn;
2355                 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr));
2356                 gen_movl_TN_reg(rd, cpu_tmp0);
2357 #endif
2358                 break;
2359 #endif
2360             } else if (xop == 0x34) {   /* FPU Operations */
2361                 if (gen_trap_ifnofpu(dc, cpu_cond))
2362                     goto jmp_insn;
2363                 gen_op_clear_ieee_excp_and_FTT();
2364                 rs1 = GET_FIELD(insn, 13, 17);
2365                 rs2 = GET_FIELD(insn, 27, 31);
2366                 xop = GET_FIELD(insn, 18, 26);
2367                 switch (xop) {
2368                     case 0x1: /* fmovs */
2369                         gen_op_load_fpr_FT0(rs2);
2370                         gen_op_store_FT0_fpr(rd);
2371                         break;
2372                     case 0x5: /* fnegs */
2373                         gen_op_load_fpr_FT1(rs2);
2374                         tcg_gen_helper_0_0(helper_fnegs);
2375                         gen_op_store_FT0_fpr(rd);
2376                         break;
2377                     case 0x9: /* fabss */
2378                         gen_op_load_fpr_FT1(rs2);
2379                         tcg_gen_helper_0_0(helper_fabss);
2380                         gen_op_store_FT0_fpr(rd);
2381                         break;
2382                     case 0x29: /* fsqrts */
2383                         CHECK_FPU_FEATURE(dc, FSQRT);
2384                         gen_op_load_fpr_FT1(rs2);
2385                         gen_clear_float_exceptions();
2386                         tcg_gen_helper_0_0(helper_fsqrts);
2387                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2388                         gen_op_store_FT0_fpr(rd);
2389                         break;
2390                     case 0x2a: /* fsqrtd */
2391                         CHECK_FPU_FEATURE(dc, FSQRT);
2392                         gen_op_load_fpr_DT1(DFPREG(rs2));
2393                         gen_clear_float_exceptions();
2394                         tcg_gen_helper_0_0(helper_fsqrtd);
2395                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2396                         gen_op_store_DT0_fpr(DFPREG(rd));
2397                         break;
2398                     case 0x2b: /* fsqrtq */
2399                         CHECK_FPU_FEATURE(dc, FLOAT128);
2400                         gen_op_load_fpr_QT1(QFPREG(rs2));
2401                         gen_clear_float_exceptions();
2402                         tcg_gen_helper_0_0(helper_fsqrtq);
2403                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2404                         gen_op_store_QT0_fpr(QFPREG(rd));
2405                         break;
2406                     case 0x41:
2407                         gen_op_load_fpr_FT0(rs1);
2408                         gen_op_load_fpr_FT1(rs2);
2409                         gen_clear_float_exceptions();
2410                         tcg_gen_helper_0_0(helper_fadds);
2411                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2412                         gen_op_store_FT0_fpr(rd);
2413                         break;
2414                     case 0x42:
2415                         gen_op_load_fpr_DT0(DFPREG(rs1));
2416                         gen_op_load_fpr_DT1(DFPREG(rs2));
2417                         gen_clear_float_exceptions();
2418                         tcg_gen_helper_0_0(helper_faddd);
2419                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2420                         gen_op_store_DT0_fpr(DFPREG(rd));
2421                         break;
2422                     case 0x43: /* faddq */
2423                         CHECK_FPU_FEATURE(dc, FLOAT128);
2424                         gen_op_load_fpr_QT0(QFPREG(rs1));
2425                         gen_op_load_fpr_QT1(QFPREG(rs2));
2426                         gen_clear_float_exceptions();
2427                         tcg_gen_helper_0_0(helper_faddq);
2428                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2429                         gen_op_store_QT0_fpr(QFPREG(rd));
2430                         break;
2431                     case 0x45:
2432                         gen_op_load_fpr_FT0(rs1);
2433                         gen_op_load_fpr_FT1(rs2);
2434                         gen_clear_float_exceptions();
2435                         tcg_gen_helper_0_0(helper_fsubs);
2436                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2437                         gen_op_store_FT0_fpr(rd);
2438                         break;
2439                     case 0x46:
2440                         gen_op_load_fpr_DT0(DFPREG(rs1));
2441                         gen_op_load_fpr_DT1(DFPREG(rs2));
2442                         gen_clear_float_exceptions();
2443                         tcg_gen_helper_0_0(helper_fsubd);
2444                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2445                         gen_op_store_DT0_fpr(DFPREG(rd));
2446                         break;
2447                     case 0x47: /* fsubq */
2448                         CHECK_FPU_FEATURE(dc, FLOAT128);
2449                         gen_op_load_fpr_QT0(QFPREG(rs1));
2450                         gen_op_load_fpr_QT1(QFPREG(rs2));
2451                         gen_clear_float_exceptions();
2452                         tcg_gen_helper_0_0(helper_fsubq);
2453                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2454                         gen_op_store_QT0_fpr(QFPREG(rd));
2455                         break;
2456                     case 0x49: /* fmuls */
2457                         CHECK_FPU_FEATURE(dc, FMUL);
2458                         gen_op_load_fpr_FT0(rs1);
2459                         gen_op_load_fpr_FT1(rs2);
2460                         gen_clear_float_exceptions();
2461                         tcg_gen_helper_0_0(helper_fmuls);
2462                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2463                         gen_op_store_FT0_fpr(rd);
2464                         break;
2465                     case 0x4a: /* fmuld */
2466                         CHECK_FPU_FEATURE(dc, FMUL);
2467                         gen_op_load_fpr_DT0(DFPREG(rs1));
2468                         gen_op_load_fpr_DT1(DFPREG(rs2));
2469                         gen_clear_float_exceptions();
2470                         tcg_gen_helper_0_0(helper_fmuld);
2471                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2472                         gen_op_store_DT0_fpr(DFPREG(rd));
2473                         break;
2474                     case 0x4b: /* fmulq */
2475                         CHECK_FPU_FEATURE(dc, FLOAT128);
2476                         CHECK_FPU_FEATURE(dc, FMUL);
2477                         gen_op_load_fpr_QT0(QFPREG(rs1));
2478                         gen_op_load_fpr_QT1(QFPREG(rs2));
2479                         gen_clear_float_exceptions();
2480                         tcg_gen_helper_0_0(helper_fmulq);
2481                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2482                         gen_op_store_QT0_fpr(QFPREG(rd));
2483                         break;
2484                     case 0x4d:
2485                         gen_op_load_fpr_FT0(rs1);
2486                         gen_op_load_fpr_FT1(rs2);
2487                         gen_clear_float_exceptions();
2488                         tcg_gen_helper_0_0(helper_fdivs);
2489                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2490                         gen_op_store_FT0_fpr(rd);
2491                         break;
2492                     case 0x4e:
2493                         gen_op_load_fpr_DT0(DFPREG(rs1));
2494                         gen_op_load_fpr_DT1(DFPREG(rs2));
2495                         gen_clear_float_exceptions();
2496                         tcg_gen_helper_0_0(helper_fdivd);
2497                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2498                         gen_op_store_DT0_fpr(DFPREG(rd));
2499                         break;
2500                     case 0x4f: /* fdivq */
2501                         CHECK_FPU_FEATURE(dc, FLOAT128);
2502                         gen_op_load_fpr_QT0(QFPREG(rs1));
2503                         gen_op_load_fpr_QT1(QFPREG(rs2));
2504                         gen_clear_float_exceptions();
2505                         tcg_gen_helper_0_0(helper_fdivq);
2506                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2507                         gen_op_store_QT0_fpr(QFPREG(rd));
2508                         break;
2509                     case 0x69:
2510                         CHECK_FPU_FEATURE(dc, FSMULD);
2511                         gen_op_load_fpr_FT0(rs1);
2512                         gen_op_load_fpr_FT1(rs2);
2513                         gen_clear_float_exceptions();
2514                         tcg_gen_helper_0_0(helper_fsmuld);
2515                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2516                         gen_op_store_DT0_fpr(DFPREG(rd));
2517                         break;
2518                     case 0x6e: /* fdmulq */
2519                         CHECK_FPU_FEATURE(dc, FLOAT128);
2520                         gen_op_load_fpr_DT0(DFPREG(rs1));
2521                         gen_op_load_fpr_DT1(DFPREG(rs2));
2522                         gen_clear_float_exceptions();
2523                         tcg_gen_helper_0_0(helper_fdmulq);
2524                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2525                         gen_op_store_QT0_fpr(QFPREG(rd));
2526                         break;
2527                     case 0xc4:
2528                         gen_op_load_fpr_FT1(rs2);
2529                         gen_clear_float_exceptions();
2530                         tcg_gen_helper_0_0(helper_fitos);
2531                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2532                         gen_op_store_FT0_fpr(rd);
2533                         break;
2534                     case 0xc6:
2535                         gen_op_load_fpr_DT1(DFPREG(rs2));
2536                         gen_clear_float_exceptions();
2537                         tcg_gen_helper_0_0(helper_fdtos);
2538                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2539                         gen_op_store_FT0_fpr(rd);
2540                         break;
2541                     case 0xc7: /* fqtos */
2542                         CHECK_FPU_FEATURE(dc, FLOAT128);
2543                         gen_op_load_fpr_QT1(QFPREG(rs2));
2544                         gen_clear_float_exceptions();
2545                         tcg_gen_helper_0_0(helper_fqtos);
2546                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2547                         gen_op_store_FT0_fpr(rd);
2548                         break;
2549                     case 0xc8:
2550                         gen_op_load_fpr_FT1(rs2);
2551                         tcg_gen_helper_0_0(helper_fitod);
2552                         gen_op_store_DT0_fpr(DFPREG(rd));
2553                         break;
2554                     case 0xc9:
2555                         gen_op_load_fpr_FT1(rs2);
2556                         tcg_gen_helper_0_0(helper_fstod);
2557                         gen_op_store_DT0_fpr(DFPREG(rd));
2558                         break;
2559                     case 0xcb: /* fqtod */
2560                         CHECK_FPU_FEATURE(dc, FLOAT128);
2561                         gen_op_load_fpr_QT1(QFPREG(rs2));
2562                         gen_clear_float_exceptions();
2563                         tcg_gen_helper_0_0(helper_fqtod);
2564                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2565                         gen_op_store_DT0_fpr(DFPREG(rd));
2566                         break;
2567                     case 0xcc: /* fitoq */
2568                         CHECK_FPU_FEATURE(dc, FLOAT128);
2569                         gen_op_load_fpr_FT1(rs2);
2570                         tcg_gen_helper_0_0(helper_fitoq);
2571                         gen_op_store_QT0_fpr(QFPREG(rd));
2572                         break;
2573                     case 0xcd: /* fstoq */
2574                         CHECK_FPU_FEATURE(dc, FLOAT128);
2575                         gen_op_load_fpr_FT1(rs2);
2576                         tcg_gen_helper_0_0(helper_fstoq);
2577                         gen_op_store_QT0_fpr(QFPREG(rd));
2578                         break;
2579                     case 0xce: /* fdtoq */
2580                         CHECK_FPU_FEATURE(dc, FLOAT128);
2581                         gen_op_load_fpr_DT1(DFPREG(rs2));
2582                         tcg_gen_helper_0_0(helper_fdtoq);
2583                         gen_op_store_QT0_fpr(QFPREG(rd));
2584                         break;
2585                     case 0xd1:
2586                         gen_op_load_fpr_FT1(rs2);
2587                         gen_clear_float_exceptions();
2588                         tcg_gen_helper_0_0(helper_fstoi);
2589                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2590                         gen_op_store_FT0_fpr(rd);
2591                         break;
2592                     case 0xd2:
2593                         gen_op_load_fpr_DT1(DFPREG(rs2));
2594                         gen_clear_float_exceptions();
2595                         tcg_gen_helper_0_0(helper_fdtoi);
2596                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2597                         gen_op_store_FT0_fpr(rd);
2598                         break;
2599                     case 0xd3: /* fqtoi */
2600                         CHECK_FPU_FEATURE(dc, FLOAT128);
2601                         gen_op_load_fpr_QT1(QFPREG(rs2));
2602                         gen_clear_float_exceptions();
2603                         tcg_gen_helper_0_0(helper_fqtoi);
2604                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2605                         gen_op_store_FT0_fpr(rd);
2606                         break;
2607 #ifdef TARGET_SPARC64
2608                     case 0x2: /* V9 fmovd */
2609                         gen_op_load_fpr_DT0(DFPREG(rs2));
2610                         gen_op_store_DT0_fpr(DFPREG(rd));
2611                         break;
2612                     case 0x3: /* V9 fmovq */
2613                         CHECK_FPU_FEATURE(dc, FLOAT128);
2614                         gen_op_load_fpr_QT0(QFPREG(rs2));
2615                         gen_op_store_QT0_fpr(QFPREG(rd));
2616                         break;
2617                     case 0x6: /* V9 fnegd */
2618                         gen_op_load_fpr_DT1(DFPREG(rs2));
2619                         tcg_gen_helper_0_0(helper_fnegd);
2620                         gen_op_store_DT0_fpr(DFPREG(rd));
2621                         break;
2622                     case 0x7: /* V9 fnegq */
2623                         CHECK_FPU_FEATURE(dc, FLOAT128);
2624                         gen_op_load_fpr_QT1(QFPREG(rs2));
2625                         tcg_gen_helper_0_0(helper_fnegq);
2626                         gen_op_store_QT0_fpr(QFPREG(rd));
2627                         break;
2628                     case 0xa: /* V9 fabsd */
2629                         gen_op_load_fpr_DT1(DFPREG(rs2));
2630                         tcg_gen_helper_0_0(helper_fabsd);
2631                         gen_op_store_DT0_fpr(DFPREG(rd));
2632                         break;
2633                     case 0xb: /* V9 fabsq */
2634                         CHECK_FPU_FEATURE(dc, FLOAT128);
2635                         gen_op_load_fpr_QT1(QFPREG(rs2));
2636                         tcg_gen_helper_0_0(helper_fabsq);
2637                         gen_op_store_QT0_fpr(QFPREG(rd));
2638                         break;
2639                     case 0x81: /* V9 fstox */
2640                         gen_op_load_fpr_FT1(rs2);
2641                         gen_clear_float_exceptions();
2642                         tcg_gen_helper_0_0(helper_fstox);
2643                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2644                         gen_op_store_DT0_fpr(DFPREG(rd));
2645                         break;
2646                     case 0x82: /* V9 fdtox */
2647                         gen_op_load_fpr_DT1(DFPREG(rs2));
2648                         gen_clear_float_exceptions();
2649                         tcg_gen_helper_0_0(helper_fdtox);
2650                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2651                         gen_op_store_DT0_fpr(DFPREG(rd));
2652                         break;
2653                     case 0x83: /* V9 fqtox */
2654                         CHECK_FPU_FEATURE(dc, FLOAT128);
2655                         gen_op_load_fpr_QT1(QFPREG(rs2));
2656                         gen_clear_float_exceptions();
2657                         tcg_gen_helper_0_0(helper_fqtox);
2658                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2659                         gen_op_store_DT0_fpr(DFPREG(rd));
2660                         break;
2661                     case 0x84: /* V9 fxtos */
2662                         gen_op_load_fpr_DT1(DFPREG(rs2));
2663                         gen_clear_float_exceptions();
2664                         tcg_gen_helper_0_0(helper_fxtos);
2665                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2666                         gen_op_store_FT0_fpr(rd);
2667                         break;
2668                     case 0x88: /* V9 fxtod */
2669                         gen_op_load_fpr_DT1(DFPREG(rs2));
2670                         gen_clear_float_exceptions();
2671                         tcg_gen_helper_0_0(helper_fxtod);
2672                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2673                         gen_op_store_DT0_fpr(DFPREG(rd));
2674                         break;
2675                     case 0x8c: /* V9 fxtoq */
2676                         CHECK_FPU_FEATURE(dc, FLOAT128);
2677                         gen_op_load_fpr_DT1(DFPREG(rs2));
2678                         gen_clear_float_exceptions();
2679                         tcg_gen_helper_0_0(helper_fxtoq);
2680                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2681                         gen_op_store_QT0_fpr(QFPREG(rd));
2682                         break;
2683 #endif
2684                     default:
2685                         goto illegal_insn;
2686                 }
2687             } else if (xop == 0x35) {   /* FPU Operations */
2688 #ifdef TARGET_SPARC64
2689                 int cond;
2690 #endif
2691                 if (gen_trap_ifnofpu(dc, cpu_cond))
2692                     goto jmp_insn;
2693                 gen_op_clear_ieee_excp_and_FTT();
2694                 rs1 = GET_FIELD(insn, 13, 17);
2695                 rs2 = GET_FIELD(insn, 27, 31);
2696                 xop = GET_FIELD(insn, 18, 26);
2697 #ifdef TARGET_SPARC64
2698                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2699                     int l1;
2700
2701                     l1 = gen_new_label();
2702                     cond = GET_FIELD_SP(insn, 14, 17);
2703                     cpu_src1 = get_src1(insn, cpu_src1);
2704                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2705                                        0, l1);
2706                     gen_op_load_fpr_FT0(rs2);
2707                     gen_op_store_FT0_fpr(rd);
2708                     gen_set_label(l1);
2709                     break;
2710                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2711                     int l1;
2712
2713                     l1 = gen_new_label();
2714                     cond = GET_FIELD_SP(insn, 14, 17);
2715                     cpu_src1 = get_src1(insn, cpu_src1);
2716                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2717                                        0, l1);
2718                     gen_op_load_fpr_DT0(DFPREG(rs2));
2719                     gen_op_store_DT0_fpr(DFPREG(rd));
2720                     gen_set_label(l1);
2721                     break;
2722                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2723                     int l1;
2724
2725                     CHECK_FPU_FEATURE(dc, FLOAT128);
2726                     l1 = gen_new_label();
2727                     cond = GET_FIELD_SP(insn, 14, 17);
2728                     cpu_src1 = get_src1(insn, cpu_src1);
2729                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2730                                        0, l1);
2731                     gen_op_load_fpr_QT0(QFPREG(rs2));
2732                     gen_op_store_QT0_fpr(QFPREG(rd));
2733                     gen_set_label(l1);
2734                     break;
2735                 }
2736 #endif
2737                 switch (xop) {
2738 #ifdef TARGET_SPARC64
2739 #define FMOVCC(size_FDQ, fcc)                                           \
2740                     {                                                   \
2741                         TCGv r_cond;                                    \
2742                         int l1;                                         \
2743                                                                         \
2744                         l1 = gen_new_label();                           \
2745                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2746                         cond = GET_FIELD_SP(insn, 14, 17);              \
2747                         gen_fcond(r_cond, fcc, cond);                   \
2748                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2749                                            0, l1);                      \
2750                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2751                             (glue(size_FDQ, FPREG(rs2)));               \
2752                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2753                             (glue(size_FDQ, FPREG(rd)));                \
2754                         gen_set_label(l1);                              \
2755                         tcg_temp_free(r_cond);                          \
2756                     }
2757                     case 0x001: /* V9 fmovscc %fcc0 */
2758                         FMOVCC(F, 0);
2759                         break;
2760                     case 0x002: /* V9 fmovdcc %fcc0 */
2761                         FMOVCC(D, 0);
2762                         break;
2763                     case 0x003: /* V9 fmovqcc %fcc0 */
2764                         CHECK_FPU_FEATURE(dc, FLOAT128);
2765                         FMOVCC(Q, 0);
2766                         break;
2767                     case 0x041: /* V9 fmovscc %fcc1 */
2768                         FMOVCC(F, 1);
2769                         break;
2770                     case 0x042: /* V9 fmovdcc %fcc1 */
2771                         FMOVCC(D, 1);
2772                         break;
2773                     case 0x043: /* V9 fmovqcc %fcc1 */
2774                         CHECK_FPU_FEATURE(dc, FLOAT128);
2775                         FMOVCC(Q, 1);
2776                         break;
2777                     case 0x081: /* V9 fmovscc %fcc2 */
2778                         FMOVCC(F, 2);
2779                         break;
2780                     case 0x082: /* V9 fmovdcc %fcc2 */
2781                         FMOVCC(D, 2);
2782                         break;
2783                     case 0x083: /* V9 fmovqcc %fcc2 */
2784                         CHECK_FPU_FEATURE(dc, FLOAT128);
2785                         FMOVCC(Q, 2);
2786                         break;
2787                     case 0x0c1: /* V9 fmovscc %fcc3 */
2788                         FMOVCC(F, 3);
2789                         break;
2790                     case 0x0c2: /* V9 fmovdcc %fcc3 */
2791                         FMOVCC(D, 3);
2792                         break;
2793                     case 0x0c3: /* V9 fmovqcc %fcc3 */
2794                         CHECK_FPU_FEATURE(dc, FLOAT128);
2795                         FMOVCC(Q, 3);
2796                         break;
2797 #undef FMOVCC
2798 #define FMOVCC(size_FDQ, icc)                                           \
2799                     {                                                   \
2800                         TCGv r_cond;                                    \
2801                         int l1;                                         \
2802                                                                         \
2803                         l1 = gen_new_label();                           \
2804                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2805                         cond = GET_FIELD_SP(insn, 14, 17);              \
2806                         gen_cond(r_cond, icc, cond);                    \
2807                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2808                                            0, l1);                      \
2809                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2810                             (glue(size_FDQ, FPREG(rs2)));               \
2811                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2812                             (glue(size_FDQ, FPREG(rd)));                \
2813                         gen_set_label(l1);                              \
2814                         tcg_temp_free(r_cond);                          \
2815                     }
2816
2817                     case 0x101: /* V9 fmovscc %icc */
2818                         FMOVCC(F, 0);
2819                         break;
2820                     case 0x102: /* V9 fmovdcc %icc */
2821                         FMOVCC(D, 0);
2822                     case 0x103: /* V9 fmovqcc %icc */
2823                         CHECK_FPU_FEATURE(dc, FLOAT128);
2824                         FMOVCC(Q, 0);
2825                         break;
2826                     case 0x181: /* V9 fmovscc %xcc */
2827                         FMOVCC(F, 1);
2828                         break;
2829                     case 0x182: /* V9 fmovdcc %xcc */
2830                         FMOVCC(D, 1);
2831                         break;
2832                     case 0x183: /* V9 fmovqcc %xcc */
2833                         CHECK_FPU_FEATURE(dc, FLOAT128);
2834                         FMOVCC(Q, 1);
2835                         break;
2836 #undef FMOVCC
2837 #endif
2838                     case 0x51: /* fcmps, V9 %fcc */
2839                         gen_op_load_fpr_FT0(rs1);
2840                         gen_op_load_fpr_FT1(rs2);
2841                         gen_op_fcmps(rd & 3);
2842                         break;
2843                     case 0x52: /* fcmpd, V9 %fcc */
2844                         gen_op_load_fpr_DT0(DFPREG(rs1));
2845                         gen_op_load_fpr_DT1(DFPREG(rs2));
2846                         gen_op_fcmpd(rd & 3);
2847                         break;
2848                     case 0x53: /* fcmpq, V9 %fcc */
2849                         CHECK_FPU_FEATURE(dc, FLOAT128);
2850                         gen_op_load_fpr_QT0(QFPREG(rs1));
2851                         gen_op_load_fpr_QT1(QFPREG(rs2));
2852                         gen_op_fcmpq(rd & 3);
2853                         break;
2854                     case 0x55: /* fcmpes, V9 %fcc */
2855                         gen_op_load_fpr_FT0(rs1);
2856                         gen_op_load_fpr_FT1(rs2);
2857                         gen_op_fcmpes(rd & 3);
2858                         break;
2859                     case 0x56: /* fcmped, V9 %fcc */
2860                         gen_op_load_fpr_DT0(DFPREG(rs1));
2861                         gen_op_load_fpr_DT1(DFPREG(rs2));
2862                         gen_op_fcmped(rd & 3);
2863                         break;
2864                     case 0x57: /* fcmpeq, V9 %fcc */
2865                         CHECK_FPU_FEATURE(dc, FLOAT128);
2866                         gen_op_load_fpr_QT0(QFPREG(rs1));
2867                         gen_op_load_fpr_QT1(QFPREG(rs2));
2868                         gen_op_fcmpeq(rd & 3);
2869                         break;
2870                     default:
2871                         goto illegal_insn;
2872                 }
2873             } else if (xop == 0x2) {
2874                 // clr/mov shortcut
2875
2876                 rs1 = GET_FIELD(insn, 13, 17);
2877                 if (rs1 == 0) {
2878                     // or %g0, x, y -> mov T0, x; mov y, T0
2879                     if (IS_IMM) {       /* immediate */
2880                         TCGv r_const;
2881
2882                         rs2 = GET_FIELDs(insn, 19, 31);
2883                         r_const = tcg_const_tl((int)rs2);
2884                         gen_movl_TN_reg(rd, r_const);
2885                         tcg_temp_free(r_const);
2886                     } else {            /* register */
2887                         rs2 = GET_FIELD(insn, 27, 31);
2888                         gen_movl_reg_TN(rs2, cpu_dst);
2889                         gen_movl_TN_reg(rd, cpu_dst);
2890                     }
2891                 } else {
2892                     cpu_src1 = get_src1(insn, cpu_src1);
2893                     if (IS_IMM) {       /* immediate */
2894                         rs2 = GET_FIELDs(insn, 19, 31);
2895                         tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2896                         gen_movl_TN_reg(rd, cpu_dst);
2897                     } else {            /* register */
2898                         // or x, %g0, y -> mov T1, x; mov y, T1
2899                         rs2 = GET_FIELD(insn, 27, 31);
2900                         if (rs2 != 0) {
2901                             gen_movl_reg_TN(rs2, cpu_src2);
2902                             tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2903                             gen_movl_TN_reg(rd, cpu_dst);
2904                         } else
2905                             gen_movl_TN_reg(rd, cpu_src1);
2906                     }
2907                 }
2908 #ifdef TARGET_SPARC64
2909             } else if (xop == 0x25) { /* sll, V9 sllx */
2910                 cpu_src1 = get_src1(insn, cpu_src1);
2911                 if (IS_IMM) {   /* immediate */
2912                     rs2 = GET_FIELDs(insn, 20, 31);
2913                     if (insn & (1 << 12)) {
2914                         tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2915                     } else {
2916                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2917                         tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2918                     }
2919                 } else {                /* register */
2920                     rs2 = GET_FIELD(insn, 27, 31);
2921                     gen_movl_reg_TN(rs2, cpu_src2);
2922                     if (insn & (1 << 12)) {
2923                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2924                         tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2925                     } else {
2926                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2927                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2928                         tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2929                     }
2930                 }
2931                 gen_movl_TN_reg(rd, cpu_dst);
2932             } else if (xop == 0x26) { /* srl, V9 srlx */
2933                 cpu_src1 = get_src1(insn, cpu_src1);
2934                 if (IS_IMM) {   /* immediate */
2935                     rs2 = GET_FIELDs(insn, 20, 31);
2936                     if (insn & (1 << 12)) {
2937                         tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2938                     } else {
2939                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2940                         tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2941                     }
2942                 } else {                /* register */
2943                     rs2 = GET_FIELD(insn, 27, 31);
2944                     gen_movl_reg_TN(rs2, cpu_src2);
2945                     if (insn & (1 << 12)) {
2946                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2947                         tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2948                     } else {
2949                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2950                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2951                         tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2952                     }
2953                 }
2954                 gen_movl_TN_reg(rd, cpu_dst);
2955             } else if (xop == 0x27) { /* sra, V9 srax */
2956                 cpu_src1 = get_src1(insn, cpu_src1);
2957                 if (IS_IMM) {   /* immediate */
2958                     rs2 = GET_FIELDs(insn, 20, 31);
2959                     if (insn & (1 << 12)) {
2960                         tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2961                     } else {
2962                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2963                         tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2964                         tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2965                     }
2966                 } else {                /* register */
2967                     rs2 = GET_FIELD(insn, 27, 31);
2968                     gen_movl_reg_TN(rs2, cpu_src2);
2969                     if (insn & (1 << 12)) {
2970                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2971                         tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2972                     } else {
2973                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2974                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2975                         tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2976                     }
2977                 }
2978                 gen_movl_TN_reg(rd, cpu_dst);
2979 #endif
2980             } else if (xop < 0x36) {
2981                 cpu_src1 = get_src1(insn, cpu_src1);
2982                 cpu_src2 = get_src2(insn, cpu_src2);
2983                 if (xop < 0x20) {
2984                     switch (xop & ~0x10) {
2985                     case 0x0:
2986                         if (xop & 0x10)
2987                             gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2988                         else
2989                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2990                         break;
2991                     case 0x1:
2992                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2993                         if (xop & 0x10)
2994                             gen_op_logic_cc(cpu_dst);
2995                         break;
2996                     case 0x2:
2997                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2998                         if (xop & 0x10)
2999                             gen_op_logic_cc(cpu_dst);
3000                         break;
3001                     case 0x3:
3002                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3003                         if (xop & 0x10)
3004                             gen_op_logic_cc(cpu_dst);
3005                         break;
3006                     case 0x4:
3007                         if (xop & 0x10)
3008                             gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3009                         else
3010                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3011                         break;
3012                     case 0x5:
3013                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3014                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3015                         if (xop & 0x10)
3016                             gen_op_logic_cc(cpu_dst);
3017                         break;
3018                     case 0x6:
3019                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3020                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3021                         if (xop & 0x10)
3022                             gen_op_logic_cc(cpu_dst);
3023                         break;
3024                     case 0x7:
3025                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3026                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3027                         if (xop & 0x10)
3028                             gen_op_logic_cc(cpu_dst);
3029                         break;
3030                     case 0x8:
3031                         if (xop & 0x10)
3032                             gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3033                         else {
3034                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3035                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3036                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3037                         }
3038                         break;
3039 #ifdef TARGET_SPARC64
3040                     case 0x9: /* V9 mulx */
3041                         tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3042                         break;
3043 #endif
3044                     case 0xa:
3045                         CHECK_IU_FEATURE(dc, MUL);
3046                         gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3047                         if (xop & 0x10)
3048                             gen_op_logic_cc(cpu_dst);
3049                         break;
3050                     case 0xb:
3051                         CHECK_IU_FEATURE(dc, MUL);
3052                         gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3053                         if (xop & 0x10)
3054                             gen_op_logic_cc(cpu_dst);
3055                         break;
3056                     case 0xc:
3057                         if (xop & 0x10)
3058                             gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3059                         else {
3060                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3061                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3062                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3063                         }
3064                         break;
3065 #ifdef TARGET_SPARC64
3066                     case 0xd: /* V9 udivx */
3067                         tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3068                         tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3069                         gen_trap_ifdivzero_tl(cpu_cc_src2);
3070                         tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3071                         break;
3072 #endif
3073                     case 0xe:
3074                         CHECK_IU_FEATURE(dc, DIV);
3075                         tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3076                                            cpu_src2);
3077                         if (xop & 0x10)
3078                             gen_op_div_cc(cpu_dst);
3079                         break;
3080                     case 0xf:
3081                         CHECK_IU_FEATURE(dc, DIV);
3082                         tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3083                                            cpu_src2);
3084                         if (xop & 0x10)
3085                             gen_op_div_cc(cpu_dst);
3086                         break;
3087                     default:
3088                         goto illegal_insn;
3089                     }
3090                     gen_movl_TN_reg(rd, cpu_dst);
3091                 } else {
3092                     switch (xop) {
3093                     case 0x20: /* taddcc */
3094                         gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3095                         gen_movl_TN_reg(rd, cpu_dst);
3096                         break;
3097                     case 0x21: /* tsubcc */
3098                         gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3099                         gen_movl_TN_reg(rd, cpu_dst);
3100                         break;
3101                     case 0x22: /* taddcctv */
3102                         save_state(dc, cpu_cond);
3103                         gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3104                         gen_movl_TN_reg(rd, cpu_dst);
3105                         break;
3106                     case 0x23: /* tsubcctv */
3107                         save_state(dc, cpu_cond);
3108                         gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3109                         gen_movl_TN_reg(rd, cpu_dst);
3110                         break;
3111                     case 0x24: /* mulscc */
3112                         gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3113                         gen_movl_TN_reg(rd, cpu_dst);
3114                         break;
3115 #ifndef TARGET_SPARC64
3116                     case 0x25:  /* sll */
3117                         if (IS_IMM) { /* immediate */
3118                             rs2 = GET_FIELDs(insn, 20, 31);
3119                             tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3120                         } else { /* register */
3121                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3122                             tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3123                         }
3124                         gen_movl_TN_reg(rd, cpu_dst);
3125                         break;
3126                     case 0x26:  /* srl */
3127                         if (IS_IMM) { /* immediate */
3128                             rs2 = GET_FIELDs(insn, 20, 31);
3129                             tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3130                         } else { /* register */
3131                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3132                             tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3133                         }
3134                         gen_movl_TN_reg(rd, cpu_dst);
3135                         break;
3136                     case 0x27:  /* sra */
3137                         if (IS_IMM) { /* immediate */
3138                             rs2 = GET_FIELDs(insn, 20, 31);
3139                             tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3140                         } else { /* register */
3141                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3142                             tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3143                         }
3144                         gen_movl_TN_reg(rd, cpu_dst);
3145                         break;
3146 #endif
3147                     case 0x30:
3148                         {
3149                             switch(rd) {
3150                             case 0: /* wry */
3151                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3152                                 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3153                                               offsetof(CPUSPARCState, y));
3154                                 break;
3155 #ifndef TARGET_SPARC64
3156                             case 0x01 ... 0x0f: /* undefined in the
3157                                                    SPARCv8 manual, nop
3158                                                    on the microSPARC
3159                                                    II */
3160                             case 0x10 ... 0x1f: /* implementation-dependent
3161                                                    in the SPARCv8
3162                                                    manual, nop on the
3163                                                    microSPARC II */
3164                                 break;
3165 #else
3166                             case 0x2: /* V9 wrccr */
3167                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3168                                 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3169                                 break;
3170                             case 0x3: /* V9 wrasi */
3171                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3172                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3173                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3174                                                offsetof(CPUSPARCState, asi));
3175                                 break;
3176                             case 0x6: /* V9 wrfprs */
3177                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3178                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3179                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3180                                                offsetof(CPUSPARCState, fprs));
3181                                 save_state(dc, cpu_cond);
3182                                 gen_op_next_insn();
3183                                 tcg_gen_exit_tb(0);
3184                                 dc->is_br = 1;
3185                                 break;
3186                             case 0xf: /* V9 sir, nop if user */
3187 #if !defined(CONFIG_USER_ONLY)
3188                                 if (supervisor(dc))
3189                                     ; // XXX
3190 #endif
3191                                 break;
3192                             case 0x13: /* Graphics Status */
3193                                 if (gen_trap_ifnofpu(dc, cpu_cond))
3194                                     goto jmp_insn;
3195                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3196                                 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3197                                               offsetof(CPUSPARCState, gsr));
3198                                 break;
3199                             case 0x17: /* Tick compare */
3200 #if !defined(CONFIG_USER_ONLY)
3201                                 if (!supervisor(dc))
3202                                     goto illegal_insn;
3203 #endif
3204                                 {
3205                                     TCGv r_tickptr;
3206
3207                                     tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3208                                                    cpu_src2);
3209                                     tcg_gen_st_tl(cpu_tmp0, cpu_env,
3210                                                   offsetof(CPUSPARCState,
3211                                                            tick_cmpr));
3212                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3213                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3214                                                    offsetof(CPUState, tick));
3215                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3216                                                        r_tickptr, cpu_tmp0);
3217                                     tcg_temp_free(r_tickptr);
3218                                 }
3219                                 break;
3220                             case 0x18: /* System tick */
3221 #if !defined(CONFIG_USER_ONLY)
3222                                 if (!supervisor(dc))
3223                                     goto illegal_insn;
3224 #endif
3225                                 {
3226                                     TCGv r_tickptr;
3227
3228                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3229                                                    cpu_src2);
3230                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3231                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3232                                                    offsetof(CPUState, stick));
3233                                     tcg_gen_helper_0_2(helper_tick_set_count,
3234                                                        r_tickptr, cpu_dst);
3235                                     tcg_temp_free(r_tickptr);
3236                                 }
3237                                 break;
3238                             case 0x19: /* System tick compare */
3239 #if !defined(CONFIG_USER_ONLY)
3240                                 if (!supervisor(dc))
3241                                     goto illegal_insn;
3242 #endif
3243                                 {
3244                                     TCGv r_tickptr;
3245
3246                                     tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3247                                                    cpu_src2);
3248                                     tcg_gen_st_tl(cpu_tmp0, cpu_env,
3249                                                   offsetof(CPUSPARCState,
3250                                                            stick_cmpr));
3251                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3252                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3253                                                    offsetof(CPUState, stick));
3254                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3255                                                        r_tickptr, cpu_tmp0);
3256                                     tcg_temp_free(r_tickptr);
3257                                 }
3258                                 break;
3259
3260                             case 0x10: /* Performance Control */
3261                             case 0x11: /* Performance Instrumentation
3262                                           Counter */
3263                             case 0x12: /* Dispatch Control */
3264                             case 0x14: /* Softint set */
3265                             case 0x15: /* Softint clear */
3266                             case 0x16: /* Softint write */
3267 #endif
3268                             default:
3269                                 goto illegal_insn;
3270                             }
3271                         }
3272                         break;
3273 #if !defined(CONFIG_USER_ONLY)
3274                     case 0x31: /* wrpsr, V9 saved, restored */
3275                         {
3276                             if (!supervisor(dc))
3277                                 goto priv_insn;
3278 #ifdef TARGET_SPARC64
3279                             switch (rd) {
3280                             case 0:
3281                                 tcg_gen_helper_0_0(helper_saved);
3282                                 break;
3283                             case 1:
3284                                 tcg_gen_helper_0_0(helper_restored);
3285                                 break;
3286                             case 2: /* UA2005 allclean */
3287                             case 3: /* UA2005 otherw */
3288                             case 4: /* UA2005 normalw */
3289                             case 5: /* UA2005 invalw */
3290                                 // XXX
3291                             default:
3292                                 goto illegal_insn;
3293                             }
3294 #else
3295                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3296                             tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3297                             save_state(dc, cpu_cond);
3298                             gen_op_next_insn();
3299                             tcg_gen_exit_tb(0);
3300                             dc->is_br = 1;
3301 #endif
3302                         }
3303                         break;
3304                     case 0x32: /* wrwim, V9 wrpr */
3305                         {
3306                             if (!supervisor(dc))
3307                                 goto priv_insn;
3308                             tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3309 #ifdef TARGET_SPARC64
3310                             switch (rd) {
3311                             case 0: // tpc
3312                                 {
3313                                     TCGv r_tsptr;
3314
3315                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3316                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3317                                                    offsetof(CPUState, tsptr));
3318                                     tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3319                                                   offsetof(trap_state, tpc));
3320                                     tcg_temp_free(r_tsptr);
3321                                 }
3322                                 break;
3323                             case 1: // tnpc
3324                                 {
3325                                     TCGv r_tsptr;
3326
3327                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3328                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3329                                                    offsetof(CPUState, tsptr));
3330                                     tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3331                                                   offsetof(trap_state, tnpc));
3332                                     tcg_temp_free(r_tsptr);
3333                                 }
3334                                 break;
3335                             case 2: // tstate
3336                                 {
3337                                     TCGv r_tsptr;
3338
3339                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3340                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3341                                                    offsetof(CPUState, tsptr));
3342                                     tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3343                                                   offsetof(trap_state,
3344                                                            tstate));
3345                                     tcg_temp_free(r_tsptr);
3346                                 }
3347                                 break;
3348                             case 3: // tt
3349                                 {
3350                                     TCGv r_tsptr;
3351
3352                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3353                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3354                                                    offsetof(CPUState, tsptr));
3355                                     tcg_gen_st_i32(cpu_tmp0, r_tsptr,
3356                                                    offsetof(trap_state, tt));
3357                                     tcg_temp_free(r_tsptr);
3358                                 }
3359                                 break;
3360                             case 4: // tick
3361                                 {
3362                                     TCGv r_tickptr;
3363
3364                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3365                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3366                                                    offsetof(CPUState, tick));
3367                                     tcg_gen_helper_0_2(helper_tick_set_count,
3368                                                        r_tickptr, cpu_tmp0);
3369                                     tcg_temp_free(r_tickptr);
3370                                 }
3371                                 break;
3372                             case 5: // tba
3373                                 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3374                                               offsetof(CPUSPARCState, tbr));
3375                                 break;
3376                             case 6: // pstate
3377                                 save_state(dc, cpu_cond);
3378                                 tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
3379                                 gen_op_next_insn();
3380                                 tcg_gen_exit_tb(0);
3381                                 dc->is_br = 1;
3382                                 break;
3383                             case 7: // tl
3384                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3385                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3386                                                offsetof(CPUSPARCState, tl));
3387                                 break;
3388                             case 8: // pil
3389                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3390                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3391                                                offsetof(CPUSPARCState,
3392                                                         psrpil));
3393                                 break;
3394                             case 9: // cwp
3395                                 tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
3396                                 break;
3397                             case 10: // cansave
3398                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3399                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3400                                                offsetof(CPUSPARCState,
3401                                                         cansave));
3402                                 break;
3403                             case 11: // canrestore
3404                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3405                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3406                                                offsetof(CPUSPARCState,
3407                                                         canrestore));
3408                                 break;
3409                             case 12: // cleanwin
3410                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3411                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3412                                                offsetof(CPUSPARCState,
3413                                                         cleanwin));
3414                                 break;
3415                             case 13: // otherwin
3416                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3417                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3418                                                offsetof(CPUSPARCState,
3419                                                         otherwin));
3420                                 break;
3421                             case 14: // wstate
3422                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3423                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3424                                                offsetof(CPUSPARCState,
3425                                                         wstate));
3426                                 break;
3427                             case 16: // UA2005 gl
3428                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3429                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3430                                                offsetof(CPUSPARCState, gl));
3431                                 break;
3432                             case 26: // UA2005 strand status
3433                                 if (!hypervisor(dc))
3434                                     goto priv_insn;
3435                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3436                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3437                                                offsetof(CPUSPARCState, ssr));
3438                                 break;
3439                             default:
3440                                 goto illegal_insn;
3441                             }
3442 #else
3443                             tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3444                             tcg_gen_st_i32(cpu_tmp32, cpu_env,
3445                                            offsetof(CPUSPARCState, wim));
3446 #endif
3447                         }
3448                         break;
3449                     case 0x33: /* wrtbr, UA2005 wrhpr */
3450                         {
3451 #ifndef TARGET_SPARC64
3452                             if (!supervisor(dc))
3453                                 goto priv_insn;
3454                             tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3455                             tcg_gen_st_tl(cpu_tmp0, cpu_env,
3456                                           offsetof(CPUSPARCState, tbr));
3457 #else
3458                             if (!hypervisor(dc))
3459                                 goto priv_insn;
3460                             tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3461                             switch (rd) {
3462                             case 0: // hpstate
3463                                 // XXX gen_op_wrhpstate();
3464                                 save_state(dc, cpu_cond);
3465                                 gen_op_next_insn();
3466                                 tcg_gen_exit_tb(0);
3467                                 dc->is_br = 1;
3468                                 break;
3469                             case 1: // htstate
3470                                 // XXX gen_op_wrhtstate();
3471                                 break;
3472                             case 3: // hintp
3473                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3474                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3475                                                offsetof(CPUSPARCState, hintp));
3476                                 break;
3477                             case 5: // htba
3478                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3479                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3480                                                offsetof(CPUSPARCState, htba));
3481                                 break;
3482                             case 31: // hstick_cmpr
3483                                 {
3484                                     TCGv r_tickptr;
3485
3486                                     tcg_gen_st_tl(cpu_tmp0, cpu_env,
3487                                                   offsetof(CPUSPARCState,
3488                                                            hstick_cmpr));
3489                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3490                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3491                                                    offsetof(CPUState, hstick));
3492                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3493                                                        r_tickptr, cpu_tmp0);
3494                                     tcg_temp_free(r_tickptr);
3495                                 }
3496                                 break;
3497                             case 6: // hver readonly
3498                             default:
3499                                 goto illegal_insn;
3500                             }
3501 #endif
3502                         }
3503                         break;
3504 #endif
3505 #ifdef TARGET_SPARC64
3506                     case 0x2c: /* V9 movcc */
3507                         {
3508                             int cc = GET_FIELD_SP(insn, 11, 12);
3509                             int cond = GET_FIELD_SP(insn, 14, 17);
3510                             TCGv r_cond;
3511                             int l1;
3512
3513                             r_cond = tcg_temp_new(TCG_TYPE_TL);
3514                             if (insn & (1 << 18)) {
3515                                 if (cc == 0)
3516                                     gen_cond(r_cond, 0, cond);
3517                                 else if (cc == 2)
3518                                     gen_cond(r_cond, 1, cond);
3519                                 else
3520                                     goto illegal_insn;
3521                             } else {
3522                                 gen_fcond(r_cond, cc, cond);
3523                             }
3524
3525                             l1 = gen_new_label();
3526
3527                             tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3528                             if (IS_IMM) {       /* immediate */
3529                                 TCGv r_const;
3530
3531                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
3532                                 r_const = tcg_const_tl((int)rs2);
3533                                 gen_movl_TN_reg(rd, r_const);
3534                                 tcg_temp_free(r_const);
3535                             } else {
3536                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3537                                 gen_movl_reg_TN(rs2, cpu_tmp0);
3538                                 gen_movl_TN_reg(rd, cpu_tmp0);
3539                             }
3540                             gen_set_label(l1);
3541                             tcg_temp_free(r_cond);
3542                             break;
3543                         }
3544                     case 0x2d: /* V9 sdivx */
3545                         gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3546                         gen_movl_TN_reg(rd, cpu_dst);
3547                         break;
3548                     case 0x2e: /* V9 popc */
3549                         {
3550                             cpu_src2 = get_src2(insn, cpu_src2);
3551                             tcg_gen_helper_1_1(helper_popc, cpu_dst,
3552                                                cpu_src2);
3553                             gen_movl_TN_reg(rd, cpu_dst);
3554                         }
3555                     case 0x2f: /* V9 movr */
3556                         {
3557                             int cond = GET_FIELD_SP(insn, 10, 12);
3558                             int l1;
3559
3560                             cpu_src1 = get_src1(insn, cpu_src1);
3561
3562                             l1 = gen_new_label();
3563
3564                             tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3565                                               cpu_src1, 0, l1);
3566                             if (IS_IMM) {       /* immediate */
3567                                 TCGv r_const;
3568
3569                                 rs2 = GET_FIELD_SPs(insn, 0, 9);
3570                                 r_const = tcg_const_tl((int)rs2);
3571                                 gen_movl_TN_reg(rd, r_const);
3572                                 tcg_temp_free(r_const);
3573                             } else {
3574                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3575                                 gen_movl_reg_TN(rs2, cpu_tmp0);
3576                                 gen_movl_TN_reg(rd, cpu_tmp0);
3577                             }
3578                             gen_set_label(l1);
3579                             break;
3580                         }
3581 #endif
3582                     default:
3583                         goto illegal_insn;
3584                     }
3585                 }
3586             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3587 #ifdef TARGET_SPARC64
3588                 int opf = GET_FIELD_SP(insn, 5, 13);
3589                 rs1 = GET_FIELD(insn, 13, 17);
3590                 rs2 = GET_FIELD(insn, 27, 31);
3591                 if (gen_trap_ifnofpu(dc, cpu_cond))
3592                     goto jmp_insn;
3593
3594                 switch (opf) {
3595                 case 0x000: /* VIS I edge8cc */
3596                 case 0x001: /* VIS II edge8n */
3597                 case 0x002: /* VIS I edge8lcc */
3598                 case 0x003: /* VIS II edge8ln */
3599                 case 0x004: /* VIS I edge16cc */
3600                 case 0x005: /* VIS II edge16n */
3601                 case 0x006: /* VIS I edge16lcc */
3602                 case 0x007: /* VIS II edge16ln */
3603                 case 0x008: /* VIS I edge32cc */
3604                 case 0x009: /* VIS II edge32n */
3605                 case 0x00a: /* VIS I edge32lcc */
3606                 case 0x00b: /* VIS II edge32ln */
3607                     // XXX
3608                     goto illegal_insn;
3609                 case 0x010: /* VIS I array8 */
3610                     CHECK_FPU_FEATURE(dc, VIS1);
3611                     cpu_src1 = get_src1(insn, cpu_src1);
3612                     gen_movl_reg_TN(rs2, cpu_src2);
3613                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3614                                        cpu_src2);
3615                     gen_movl_TN_reg(rd, cpu_dst);
3616                     break;
3617                 case 0x012: /* VIS I array16 */
3618                     CHECK_FPU_FEATURE(dc, VIS1);
3619                     cpu_src1 = get_src1(insn, cpu_src1);
3620                     gen_movl_reg_TN(rs2, cpu_src2);
3621                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3622                                        cpu_src2);
3623                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3624                     gen_movl_TN_reg(rd, cpu_dst);
3625                     break;
3626                 case 0x014: /* VIS I array32 */
3627                     CHECK_FPU_FEATURE(dc, VIS1);
3628                     cpu_src1 = get_src1(insn, cpu_src1);
3629                     gen_movl_reg_TN(rs2, cpu_src2);
3630                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3631                                        cpu_src2);
3632                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3633                     gen_movl_TN_reg(rd, cpu_dst);
3634                     break;
3635                 case 0x018: /* VIS I alignaddr */
3636                     CHECK_FPU_FEATURE(dc, VIS1);
3637                     cpu_src1 = get_src1(insn, cpu_src1);
3638                     gen_movl_reg_TN(rs2, cpu_src2);
3639                     tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3640                                        cpu_src2);
3641                     gen_movl_TN_reg(rd, cpu_dst);
3642                     break;
3643                 case 0x019: /* VIS II bmask */
3644                 case 0x01a: /* VIS I alignaddrl */
3645                     // XXX
3646                     goto illegal_insn;
3647                 case 0x020: /* VIS I fcmple16 */
3648                     CHECK_FPU_FEATURE(dc, VIS1);
3649                     gen_op_load_fpr_DT0(DFPREG(rs1));
3650                     gen_op_load_fpr_DT1(DFPREG(rs2));
3651                     tcg_gen_helper_0_0(helper_fcmple16);
3652                     gen_op_store_DT0_fpr(DFPREG(rd));
3653                     break;
3654                 case 0x022: /* VIS I fcmpne16 */
3655                     CHECK_FPU_FEATURE(dc, VIS1);
3656                     gen_op_load_fpr_DT0(DFPREG(rs1));
3657                     gen_op_load_fpr_DT1(DFPREG(rs2));
3658                     tcg_gen_helper_0_0(helper_fcmpne16);
3659                     gen_op_store_DT0_fpr(DFPREG(rd));
3660                     break;
3661                 case 0x024: /* VIS I fcmple32 */
3662                     CHECK_FPU_FEATURE(dc, VIS1);
3663                     gen_op_load_fpr_DT0(DFPREG(rs1));
3664                     gen_op_load_fpr_DT1(DFPREG(rs2));
3665                     tcg_gen_helper_0_0(helper_fcmple32);
3666                     gen_op_store_DT0_fpr(DFPREG(rd));
3667                     break;
3668                 case 0x026: /* VIS I fcmpne32 */
3669                     CHECK_FPU_FEATURE(dc, VIS1);
3670                     gen_op_load_fpr_DT0(DFPREG(rs1));
3671                     gen_op_load_fpr_DT1(DFPREG(rs2));
3672                     tcg_gen_helper_0_0(helper_fcmpne32);
3673                     gen_op_store_DT0_fpr(DFPREG(rd));
3674                     break;
3675                 case 0x028: /* VIS I fcmpgt16 */
3676                     CHECK_FPU_FEATURE(dc, VIS1);
3677                     gen_op_load_fpr_DT0(DFPREG(rs1));
3678                     gen_op_load_fpr_DT1(DFPREG(rs2));
3679                     tcg_gen_helper_0_0(helper_fcmpgt16);
3680                     gen_op_store_DT0_fpr(DFPREG(rd));
3681                     break;
3682                 case 0x02a: /* VIS I fcmpeq16 */
3683                     CHECK_FPU_FEATURE(dc, VIS1);
3684                     gen_op_load_fpr_DT0(DFPREG(rs1));
3685                     gen_op_load_fpr_DT1(DFPREG(rs2));
3686                     tcg_gen_helper_0_0(helper_fcmpeq16);
3687                     gen_op_store_DT0_fpr(DFPREG(rd));
3688                     break;
3689                 case 0x02c: /* VIS I fcmpgt32 */
3690                     CHECK_FPU_FEATURE(dc, VIS1);
3691                     gen_op_load_fpr_DT0(DFPREG(rs1));
3692                     gen_op_load_fpr_DT1(DFPREG(rs2));
3693                     tcg_gen_helper_0_0(helper_fcmpgt32);
3694                     gen_op_store_DT0_fpr(DFPREG(rd));
3695                     break;
3696                 case 0x02e: /* VIS I fcmpeq32 */
3697                     CHECK_FPU_FEATURE(dc, VIS1);
3698                     gen_op_load_fpr_DT0(DFPREG(rs1));
3699                     gen_op_load_fpr_DT1(DFPREG(rs2));
3700                     tcg_gen_helper_0_0(helper_fcmpeq32);
3701                     gen_op_store_DT0_fpr(DFPREG(rd));
3702                     break;
3703                 case 0x031: /* VIS I fmul8x16 */
3704                     CHECK_FPU_FEATURE(dc, VIS1);
3705                     gen_op_load_fpr_DT0(DFPREG(rs1));
3706                     gen_op_load_fpr_DT1(DFPREG(rs2));
3707                     tcg_gen_helper_0_0(helper_fmul8x16);
3708                     gen_op_store_DT0_fpr(DFPREG(rd));
3709                     break;
3710                 case 0x033: /* VIS I fmul8x16au */
3711                     CHECK_FPU_FEATURE(dc, VIS1);
3712                     gen_op_load_fpr_DT0(DFPREG(rs1));
3713                     gen_op_load_fpr_DT1(DFPREG(rs2));
3714                     tcg_gen_helper_0_0(helper_fmul8x16au);
3715                     gen_op_store_DT0_fpr(DFPREG(rd));
3716                     break;
3717                 case 0x035: /* VIS I fmul8x16al */
3718                     CHECK_FPU_FEATURE(dc, VIS1);
3719                     gen_op_load_fpr_DT0(DFPREG(rs1));
3720                     gen_op_load_fpr_DT1(DFPREG(rs2));
3721                     tcg_gen_helper_0_0(helper_fmul8x16al);
3722                     gen_op_store_DT0_fpr(DFPREG(rd));
3723                     break;
3724                 case 0x036: /* VIS I fmul8sux16 */
3725                     CHECK_FPU_FEATURE(dc, VIS1);
3726                     gen_op_load_fpr_DT0(DFPREG(rs1));
3727                     gen_op_load_fpr_DT1(DFPREG(rs2));
3728                     tcg_gen_helper_0_0(helper_fmul8sux16);
3729                     gen_op_store_DT0_fpr(DFPREG(rd));
3730                     break;
3731                 case 0x037: /* VIS I fmul8ulx16 */
3732                     CHECK_FPU_FEATURE(dc, VIS1);
3733                     gen_op_load_fpr_DT0(DFPREG(rs1));
3734                     gen_op_load_fpr_DT1(DFPREG(rs2));
3735                     tcg_gen_helper_0_0(helper_fmul8ulx16);
3736                     gen_op_store_DT0_fpr(DFPREG(rd));
3737                     break;
3738                 case 0x038: /* VIS I fmuld8sux16 */
3739                     CHECK_FPU_FEATURE(dc, VIS1);
3740                     gen_op_load_fpr_DT0(DFPREG(rs1));
3741                     gen_op_load_fpr_DT1(DFPREG(rs2));
3742                     tcg_gen_helper_0_0(helper_fmuld8sux16);
3743                     gen_op_store_DT0_fpr(DFPREG(rd));
3744                     break;
3745                 case 0x039: /* VIS I fmuld8ulx16 */
3746                     CHECK_FPU_FEATURE(dc, VIS1);
3747                     gen_op_load_fpr_DT0(DFPREG(rs1));
3748                     gen_op_load_fpr_DT1(DFPREG(rs2));
3749                     tcg_gen_helper_0_0(helper_fmuld8ulx16);
3750                     gen_op_store_DT0_fpr(DFPREG(rd));
3751                     break;
3752                 case 0x03a: /* VIS I fpack32 */
3753                 case 0x03b: /* VIS I fpack16 */
3754                 case 0x03d: /* VIS I fpackfix */
3755                 case 0x03e: /* VIS I pdist */
3756                     // XXX
3757                     goto illegal_insn;
3758                 case 0x048: /* VIS I faligndata */
3759                     CHECK_FPU_FEATURE(dc, VIS1);
3760                     gen_op_load_fpr_DT0(DFPREG(rs1));
3761                     gen_op_load_fpr_DT1(DFPREG(rs2));
3762                     tcg_gen_helper_0_0(helper_faligndata);
3763                     gen_op_store_DT0_fpr(DFPREG(rd));
3764                     break;
3765                 case 0x04b: /* VIS I fpmerge */
3766                     CHECK_FPU_FEATURE(dc, VIS1);
3767                     gen_op_load_fpr_DT0(DFPREG(rs1));
3768                     gen_op_load_fpr_DT1(DFPREG(rs2));
3769                     tcg_gen_helper_0_0(helper_fpmerge);
3770                     gen_op_store_DT0_fpr(DFPREG(rd));
3771                     break;
3772                 case 0x04c: /* VIS II bshuffle */
3773                     // XXX
3774                     goto illegal_insn;
3775                 case 0x04d: /* VIS I fexpand */
3776                     CHECK_FPU_FEATURE(dc, VIS1);
3777                     gen_op_load_fpr_DT0(DFPREG(rs1));
3778                     gen_op_load_fpr_DT1(DFPREG(rs2));
3779                     tcg_gen_helper_0_0(helper_fexpand);
3780                     gen_op_store_DT0_fpr(DFPREG(rd));
3781                     break;
3782                 case 0x050: /* VIS I fpadd16 */
3783                     CHECK_FPU_FEATURE(dc, VIS1);
3784                     gen_op_load_fpr_DT0(DFPREG(rs1));
3785                     gen_op_load_fpr_DT1(DFPREG(rs2));
3786                     tcg_gen_helper_0_0(helper_fpadd16);
3787                     gen_op_store_DT0_fpr(DFPREG(rd));
3788                     break;
3789                 case 0x051: /* VIS I fpadd16s */
3790                     CHECK_FPU_FEATURE(dc, VIS1);
3791                     gen_op_load_fpr_FT0(rs1);
3792                     gen_op_load_fpr_FT1(rs2);
3793                     tcg_gen_helper_0_0(helper_fpadd16s);
3794                     gen_op_store_FT0_fpr(rd);
3795                     break;
3796                 case 0x052: /* VIS I fpadd32 */
3797                     CHECK_FPU_FEATURE(dc, VIS1);
3798                     gen_op_load_fpr_DT0(DFPREG(rs1));
3799                     gen_op_load_fpr_DT1(DFPREG(rs2));
3800                     tcg_gen_helper_0_0(helper_fpadd32);
3801                     gen_op_store_DT0_fpr(DFPREG(rd));
3802                     break;
3803                 case 0x053: /* VIS I fpadd32s */
3804                     CHECK_FPU_FEATURE(dc, VIS1);
3805                     gen_op_load_fpr_FT0(rs1);
3806                     gen_op_load_fpr_FT1(rs2);
3807                     tcg_gen_helper_0_0(helper_fpadd32s);
3808                     gen_op_store_FT0_fpr(rd);
3809                     break;
3810                 case 0x054: /* VIS I fpsub16 */
3811                     CHECK_FPU_FEATURE(dc, VIS1);
3812                     gen_op_load_fpr_DT0(DFPREG(rs1));
3813                     gen_op_load_fpr_DT1(DFPREG(rs2));
3814                     tcg_gen_helper_0_0(helper_fpsub16);
3815                     gen_op_store_DT0_fpr(DFPREG(rd));
3816                     break;
3817                 case 0x055: /* VIS I fpsub16s */
3818                     CHECK_FPU_FEATURE(dc, VIS1);
3819                     gen_op_load_fpr_FT0(rs1);
3820                     gen_op_load_fpr_FT1(rs2);
3821                     tcg_gen_helper_0_0(helper_fpsub16s);
3822                     gen_op_store_FT0_fpr(rd);
3823                     break;
3824                 case 0x056: /* VIS I fpsub32 */
3825                     CHECK_FPU_FEATURE(dc, VIS1);
3826                     gen_op_load_fpr_DT0(DFPREG(rs1));
3827                     gen_op_load_fpr_DT1(DFPREG(rs2));
3828                     tcg_gen_helper_0_0(helper_fpadd32);
3829                     gen_op_store_DT0_fpr(DFPREG(rd));
3830                     break;
3831                 case 0x057: /* VIS I fpsub32s */
3832                     CHECK_FPU_FEATURE(dc, VIS1);
3833                     gen_op_load_fpr_FT0(rs1);
3834                     gen_op_load_fpr_FT1(rs2);
3835                     tcg_gen_helper_0_0(helper_fpsub32s);
3836                     gen_op_store_FT0_fpr(rd);
3837                     break;
3838                 case 0x060: /* VIS I fzero */
3839                     CHECK_FPU_FEATURE(dc, VIS1);
3840                     tcg_gen_helper_0_0(helper_movl_DT0_0);
3841                     gen_op_store_DT0_fpr(DFPREG(rd));
3842                     break;
3843                 case 0x061: /* VIS I fzeros */
3844                     CHECK_FPU_FEATURE(dc, VIS1);
3845                     tcg_gen_helper_0_0(helper_movl_FT0_0);
3846                     gen_op_store_FT0_fpr(rd);
3847                     break;
3848                 case 0x062: /* VIS I fnor */
3849                     CHECK_FPU_FEATURE(dc, VIS1);
3850                     gen_op_load_fpr_DT0(DFPREG(rs1));
3851                     gen_op_load_fpr_DT1(DFPREG(rs2));
3852                     tcg_gen_helper_0_0(helper_fnor);
3853                     gen_op_store_DT0_fpr(DFPREG(rd));
3854                     break;
3855                 case 0x063: /* VIS I fnors */
3856                     CHECK_FPU_FEATURE(dc, VIS1);
3857                     gen_op_load_fpr_FT0(rs1);
3858                     gen_op_load_fpr_FT1(rs2);
3859                     tcg_gen_helper_0_0(helper_fnors);
3860                     gen_op_store_FT0_fpr(rd);
3861                     break;
3862                 case 0x064: /* VIS I fandnot2 */
3863                     CHECK_FPU_FEATURE(dc, VIS1);
3864                     gen_op_load_fpr_DT1(DFPREG(rs1));
3865                     gen_op_load_fpr_DT0(DFPREG(rs2));
3866                     tcg_gen_helper_0_0(helper_fandnot);
3867                     gen_op_store_DT0_fpr(DFPREG(rd));
3868                     break;
3869                 case 0x065: /* VIS I fandnot2s */
3870                     CHECK_FPU_FEATURE(dc, VIS1);
3871                     gen_op_load_fpr_FT1(rs1);
3872                     gen_op_load_fpr_FT0(rs2);
3873                     tcg_gen_helper_0_0(helper_fandnots);
3874                     gen_op_store_FT0_fpr(rd);
3875                     break;
3876                 case 0x066: /* VIS I fnot2 */
3877                     CHECK_FPU_FEATURE(dc, VIS1);
3878                     gen_op_load_fpr_DT1(DFPREG(rs2));
3879                     tcg_gen_helper_0_0(helper_fnot);
3880                     gen_op_store_DT0_fpr(DFPREG(rd));
3881                     break;
3882                 case 0x067: /* VIS I fnot2s */
3883                     CHECK_FPU_FEATURE(dc, VIS1);
3884                     gen_op_load_fpr_FT1(rs2);
3885                     tcg_gen_helper_0_0(helper_fnot);
3886                     gen_op_store_FT0_fpr(rd);
3887                     break;
3888                 case 0x068: /* VIS I fandnot1 */
3889                     CHECK_FPU_FEATURE(dc, VIS1);
3890                     gen_op_load_fpr_DT0(DFPREG(rs1));
3891                     gen_op_load_fpr_DT1(DFPREG(rs2));
3892                     tcg_gen_helper_0_0(helper_fandnot);
3893                     gen_op_store_DT0_fpr(DFPREG(rd));
3894                     break;
3895                 case 0x069: /* VIS I fandnot1s */
3896                     CHECK_FPU_FEATURE(dc, VIS1);
3897                     gen_op_load_fpr_FT0(rs1);
3898                     gen_op_load_fpr_FT1(rs2);
3899                     tcg_gen_helper_0_0(helper_fandnots);
3900                     gen_op_store_FT0_fpr(rd);
3901                     break;
3902                 case 0x06a: /* VIS I fnot1 */
3903                     CHECK_FPU_FEATURE(dc, VIS1);
3904                     gen_op_load_fpr_DT1(DFPREG(rs1));
3905                     tcg_gen_helper_0_0(helper_fnot);
3906                     gen_op_store_DT0_fpr(DFPREG(rd));
3907                     break;
3908                 case 0x06b: /* VIS I fnot1s */
3909                     CHECK_FPU_FEATURE(dc, VIS1);
3910                     gen_op_load_fpr_FT1(rs1);
3911                     tcg_gen_helper_0_0(helper_fnot);
3912                     gen_op_store_FT0_fpr(rd);
3913                     break;
3914                 case 0x06c: /* VIS I fxor */
3915                     CHECK_FPU_FEATURE(dc, VIS1);
3916                     gen_op_load_fpr_DT0(DFPREG(rs1));
3917                     gen_op_load_fpr_DT1(DFPREG(rs2));
3918                     tcg_gen_helper_0_0(helper_fxor);
3919                     gen_op_store_DT0_fpr(DFPREG(rd));
3920                     break;
3921                 case 0x06d: /* VIS I fxors */
3922                     CHECK_FPU_FEATURE(dc, VIS1);
3923                     gen_op_load_fpr_FT0(rs1);
3924                     gen_op_load_fpr_FT1(rs2);
3925                     tcg_gen_helper_0_0(helper_fxors);
3926                     gen_op_store_FT0_fpr(rd);
3927                     break;
3928                 case 0x06e: /* VIS I fnand */
3929                     CHECK_FPU_FEATURE(dc, VIS1);
3930                     gen_op_load_fpr_DT0(DFPREG(rs1));
3931                     gen_op_load_fpr_DT1(DFPREG(rs2));
3932                     tcg_gen_helper_0_0(helper_fnand);
3933                     gen_op_store_DT0_fpr(DFPREG(rd));
3934                     break;
3935                 case 0x06f: /* VIS I fnands */
3936                     CHECK_FPU_FEATURE(dc, VIS1);
3937                     gen_op_load_fpr_FT0(rs1);
3938                     gen_op_load_fpr_FT1(rs2);
3939                     tcg_gen_helper_0_0(helper_fnands);
3940                     gen_op_store_FT0_fpr(rd);
3941                     break;
3942                 case 0x070: /* VIS I fand */
3943                     CHECK_FPU_FEATURE(dc, VIS1);
3944                     gen_op_load_fpr_DT0(DFPREG(rs1));
3945                     gen_op_load_fpr_DT1(DFPREG(rs2));
3946                     tcg_gen_helper_0_0(helper_fand);
3947                     gen_op_store_DT0_fpr(DFPREG(rd));
3948                     break;
3949                 case 0x071: /* VIS I fands */
3950                     CHECK_FPU_FEATURE(dc, VIS1);
3951                     gen_op_load_fpr_FT0(rs1);
3952                     gen_op_load_fpr_FT1(rs2);
3953                     tcg_gen_helper_0_0(helper_fands);
3954                     gen_op_store_FT0_fpr(rd);
3955                     break;
3956                 case 0x072: /* VIS I fxnor */
3957                     CHECK_FPU_FEATURE(dc, VIS1);
3958                     gen_op_load_fpr_DT0(DFPREG(rs1));
3959                     gen_op_load_fpr_DT1(DFPREG(rs2));
3960                     tcg_gen_helper_0_0(helper_fxnor);
3961                     gen_op_store_DT0_fpr(DFPREG(rd));
3962                     break;
3963                 case 0x073: /* VIS I fxnors */
3964                     CHECK_FPU_FEATURE(dc, VIS1);
3965                     gen_op_load_fpr_FT0(rs1);
3966                     gen_op_load_fpr_FT1(rs2);
3967                     tcg_gen_helper_0_0(helper_fxnors);
3968                     gen_op_store_FT0_fpr(rd);
3969                     break;
3970                 case 0x074: /* VIS I fsrc1 */
3971                     CHECK_FPU_FEATURE(dc, VIS1);
3972                     gen_op_load_fpr_DT0(DFPREG(rs1));
3973                     gen_op_store_DT0_fpr(DFPREG(rd));
3974                     break;
3975                 case 0x075: /* VIS I fsrc1s */
3976                     CHECK_FPU_FEATURE(dc, VIS1);
3977                     gen_op_load_fpr_FT0(rs1);
3978                     gen_op_store_FT0_fpr(rd);
3979                     break;
3980                 case 0x076: /* VIS I fornot2 */
3981                     CHECK_FPU_FEATURE(dc, VIS1);
3982                     gen_op_load_fpr_DT1(DFPREG(rs1));
3983                     gen_op_load_fpr_DT0(DFPREG(rs2));
3984                     tcg_gen_helper_0_0(helper_fornot);
3985                     gen_op_store_DT0_fpr(DFPREG(rd));
3986                     break;
3987                 case 0x077: /* VIS I fornot2s */
3988                     CHECK_FPU_FEATURE(dc, VIS1);
3989                     gen_op_load_fpr_FT1(rs1);
3990                     gen_op_load_fpr_FT0(rs2);
3991                     tcg_gen_helper_0_0(helper_fornots);
3992                     gen_op_store_FT0_fpr(rd);
3993                     break;
3994                 case 0x078: /* VIS I fsrc2 */
3995                     CHECK_FPU_FEATURE(dc, VIS1);
3996                     gen_op_load_fpr_DT0(DFPREG(rs2));
3997                     gen_op_store_DT0_fpr(DFPREG(rd));
3998                     break;
3999                 case 0x079: /* VIS I fsrc2s */
4000                     CHECK_FPU_FEATURE(dc, VIS1);
4001                     gen_op_load_fpr_FT0(rs2);
4002                     gen_op_store_FT0_fpr(rd);
4003                     break;
4004                 case 0x07a: /* VIS I fornot1 */
4005                     CHECK_FPU_FEATURE(dc, VIS1);
4006                     gen_op_load_fpr_DT0(DFPREG(rs1));
4007                     gen_op_load_fpr_DT1(DFPREG(rs2));
4008                     tcg_gen_helper_0_0(helper_fornot);
4009                     gen_op_store_DT0_fpr(DFPREG(rd));
4010                     break;
4011                 case 0x07b: /* VIS I fornot1s */
4012                     CHECK_FPU_FEATURE(dc, VIS1);
4013                     gen_op_load_fpr_FT0(rs1);
4014                     gen_op_load_fpr_FT1(rs2);
4015                     tcg_gen_helper_0_0(helper_fornots);
4016                     gen_op_store_FT0_fpr(rd);
4017                     break;
4018                 case 0x07c: /* VIS I for */
4019                     CHECK_FPU_FEATURE(dc, VIS1);
4020                     gen_op_load_fpr_DT0(DFPREG(rs1));
4021                     gen_op_load_fpr_DT1(DFPREG(rs2));
4022                     tcg_gen_helper_0_0(helper_for);
4023                     gen_op_store_DT0_fpr(DFPREG(rd));
4024                     break;
4025                 case 0x07d: /* VIS I fors */
4026                     CHECK_FPU_FEATURE(dc, VIS1);
4027                     gen_op_load_fpr_FT0(rs1);
4028                     gen_op_load_fpr_FT1(rs2);
4029                     tcg_gen_helper_0_0(helper_fors);
4030                     gen_op_store_FT0_fpr(rd);
4031                     break;
4032                 case 0x07e: /* VIS I fone */
4033                     CHECK_FPU_FEATURE(dc, VIS1);
4034                     tcg_gen_helper_0_0(helper_movl_DT0_1);
4035                     gen_op_store_DT0_fpr(DFPREG(rd));
4036                     break;
4037                 case 0x07f: /* VIS I fones */
4038                     CHECK_FPU_FEATURE(dc, VIS1);
4039                     tcg_gen_helper_0_0(helper_movl_FT0_1);
4040                     gen_op_store_FT0_fpr(rd);
4041                     break;
4042                 case 0x080: /* VIS I shutdown */
4043                 case 0x081: /* VIS II siam */
4044                     // XXX
4045                     goto illegal_insn;
4046                 default:
4047                     goto illegal_insn;
4048                 }
4049 #else
4050                 goto ncp_insn;
4051 #endif
4052             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4053 #ifdef TARGET_SPARC64
4054                 goto illegal_insn;
4055 #else
4056                 goto ncp_insn;
4057 #endif
4058 #ifdef TARGET_SPARC64
4059             } else if (xop == 0x39) { /* V9 return */
4060                 TCGv r_const;
4061
4062                 save_state(dc, cpu_cond);
4063                 cpu_src1 = get_src1(insn, cpu_src1);
4064                 if (IS_IMM) {   /* immediate */
4065                     rs2 = GET_FIELDs(insn, 19, 31);
4066                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4067                 } else {                /* register */
4068                     rs2 = GET_FIELD(insn, 27, 31);
4069                     if (rs2) {
4070                         gen_movl_reg_TN(rs2, cpu_src2);
4071                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4072                     } else
4073                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
4074                 }
4075                 tcg_gen_helper_0_0(helper_restore);
4076                 gen_mov_pc_npc(dc, cpu_cond);
4077                 r_const = tcg_const_i32(3);
4078                 tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4079                 tcg_temp_free(r_const);
4080                 tcg_gen_mov_tl(cpu_npc, cpu_dst);
4081                 dc->npc = DYNAMIC_PC;
4082                 goto jmp_insn;
4083 #endif
4084             } else {
4085                 cpu_src1 = get_src1(insn, cpu_src1);
4086                 if (IS_IMM) {   /* immediate */
4087                     rs2 = GET_FIELDs(insn, 19, 31);
4088                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4089                 } else {                /* register */
4090                     rs2 = GET_FIELD(insn, 27, 31);
4091                     if (rs2) {
4092                         gen_movl_reg_TN(rs2, cpu_src2);
4093                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4094                     } else
4095                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
4096                 }
4097                 switch (xop) {
4098                 case 0x38:      /* jmpl */
4099                     {
4100                         TCGv r_const;
4101
4102                         r_const = tcg_const_tl(dc->pc);
4103                         gen_movl_TN_reg(rd, r_const);
4104                         tcg_temp_free(r_const);
4105                         gen_mov_pc_npc(dc, cpu_cond);
4106                         r_const = tcg_const_i32(3);
4107                         tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4108                                            r_const);
4109                         tcg_temp_free(r_const);
4110                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
4111                         dc->npc = DYNAMIC_PC;
4112                     }
4113                     goto jmp_insn;
4114 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4115                 case 0x39:      /* rett, V9 return */
4116                     {
4117                         TCGv r_const;
4118
4119                         if (!supervisor(dc))
4120                             goto priv_insn;
4121                         gen_mov_pc_npc(dc, cpu_cond);
4122                         r_const = tcg_const_i32(3);
4123                         tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4124                                            r_const);
4125                         tcg_temp_free(r_const);
4126                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
4127                         dc->npc = DYNAMIC_PC;
4128                         tcg_gen_helper_0_0(helper_rett);
4129                     }
4130                     goto jmp_insn;
4131 #endif
4132                 case 0x3b: /* flush */
4133                     if (!((dc)->features & CPU_FEATURE_FLUSH))
4134                         goto unimp_flush;
4135                     tcg_gen_helper_0_1(helper_flush, cpu_dst);
4136                     break;
4137                 case 0x3c:      /* save */
4138                     save_state(dc, cpu_cond);
4139                     tcg_gen_helper_0_0(helper_save);
4140                     gen_movl_TN_reg(rd, cpu_dst);
4141                     break;
4142                 case 0x3d:      /* restore */
4143                     save_state(dc, cpu_cond);
4144                     tcg_gen_helper_0_0(helper_restore);
4145                     gen_movl_TN_reg(rd, cpu_dst);
4146                     break;
4147 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4148                 case 0x3e:      /* V9 done/retry */
4149                     {
4150                         switch (rd) {
4151                         case 0:
4152                             if (!supervisor(dc))
4153                                 goto priv_insn;
4154                             dc->npc = DYNAMIC_PC;
4155                             dc->pc = DYNAMIC_PC;
4156                             tcg_gen_helper_0_0(helper_done);
4157                             goto jmp_insn;
4158                         case 1:
4159                             if (!supervisor(dc))
4160                                 goto priv_insn;
4161                             dc->npc = DYNAMIC_PC;
4162                             dc->pc = DYNAMIC_PC;
4163                             tcg_gen_helper_0_0(helper_retry);
4164                             goto jmp_insn;
4165                         default:
4166                             goto illegal_insn;
4167                         }
4168                     }
4169                     break;
4170 #endif
4171                 default:
4172                     goto illegal_insn;
4173                 }
4174             }
4175             break;
4176         }
4177         break;
4178     case 3:                     /* load/store instructions */
4179         {
4180             unsigned int xop = GET_FIELD(insn, 7, 12);
4181
4182             cpu_src1 = get_src1(insn, cpu_src1);
4183             if (xop == 0x3c || xop == 0x3e)
4184             {
4185                 rs2 = GET_FIELD(insn, 27, 31);
4186                 gen_movl_reg_TN(rs2, cpu_src2);
4187             }
4188             else if (IS_IMM) {       /* immediate */
4189                 rs2 = GET_FIELDs(insn, 19, 31);
4190                 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4191             } else {            /* register */
4192                 rs2 = GET_FIELD(insn, 27, 31);
4193                 if (rs2 != 0) {
4194                     gen_movl_reg_TN(rs2, cpu_src2);
4195                     tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4196                 } else
4197                     tcg_gen_mov_tl(cpu_addr, cpu_src1);
4198             }
4199             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4200                 (xop > 0x17 && xop <= 0x1d ) ||
4201                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4202                 switch (xop) {
4203                 case 0x0:       /* load unsigned word */
4204                     ABI32_MASK(cpu_addr);
4205                     tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4206                     break;
4207                 case 0x1:       /* load unsigned byte */
4208                     ABI32_MASK(cpu_addr);
4209                     tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4210                     break;
4211                 case 0x2:       /* load unsigned halfword */
4212                     ABI32_MASK(cpu_addr);
4213                     tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4214                     break;
4215                 case 0x3:       /* load double word */
4216                     if (rd & 1)
4217                         goto illegal_insn;
4218                     else {
4219                         TCGv r_const;
4220
4221                         save_state(dc, cpu_cond);
4222                         r_const = tcg_const_i32(7);
4223                         tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4224                                            r_const); // XXX remove
4225                         tcg_temp_free(r_const);
4226                         ABI32_MASK(cpu_addr);
4227                         tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4228                         tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4229                         tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4230                         gen_movl_TN_reg(rd + 1, cpu_tmp0);
4231                         tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4232                         tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4233                         tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4234                     }
4235                     break;
4236                 case 0x9:       /* load signed byte */
4237                     ABI32_MASK(cpu_addr);
4238                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4239                     break;
4240                 case 0xa:       /* load signed halfword */
4241                     ABI32_MASK(cpu_addr);
4242                     tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4243                     break;
4244                 case 0xd:       /* ldstub -- XXX: should be atomically */
4245                     {
4246                         TCGv r_const;
4247
4248                         ABI32_MASK(cpu_addr);
4249                         tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4250                         r_const = tcg_const_tl(0xff);
4251                         tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4252                         tcg_temp_free(r_const);
4253                     }
4254                     break;
4255                 case 0x0f:      /* swap register with memory. Also
4256                                    atomically */
4257                     CHECK_IU_FEATURE(dc, SWAP);
4258                     gen_movl_reg_TN(rd, cpu_val);
4259                     ABI32_MASK(cpu_addr);
4260                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4261                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4262                     tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4263                     break;
4264 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4265                 case 0x10:      /* load word alternate */
4266 #ifndef TARGET_SPARC64
4267                     if (IS_IMM)
4268                         goto illegal_insn;
4269                     if (!supervisor(dc))
4270                         goto priv_insn;
4271 #endif
4272                     save_state(dc, cpu_cond);
4273                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4274                     break;
4275                 case 0x11:      /* load unsigned byte alternate */
4276 #ifndef TARGET_SPARC64
4277                     if (IS_IMM)
4278                         goto illegal_insn;
4279                     if (!supervisor(dc))
4280                         goto priv_insn;
4281 #endif
4282                     save_state(dc, cpu_cond);
4283                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4284                     break;
4285                 case 0x12:      /* load unsigned halfword alternate */
4286 #ifndef TARGET_SPARC64
4287                     if (IS_IMM)
4288                         goto illegal_insn;
4289                     if (!supervisor(dc))
4290                         goto priv_insn;
4291 #endif
4292                     save_state(dc, cpu_cond);
4293                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4294                     break;
4295                 case 0x13:      /* load double word alternate */
4296 #ifndef TARGET_SPARC64
4297                     if (IS_IMM)
4298                         goto illegal_insn;
4299                     if (!supervisor(dc))
4300                         goto priv_insn;
4301 #endif
4302                     if (rd & 1)
4303                         goto illegal_insn;
4304                     save_state(dc, cpu_cond);
4305                     gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4306                     gen_movl_TN_reg(rd + 1, cpu_tmp0);
4307                     break;
4308                 case 0x19:      /* load signed byte alternate */
4309 #ifndef TARGET_SPARC64
4310                     if (IS_IMM)
4311                         goto illegal_insn;
4312                     if (!supervisor(dc))
4313                         goto priv_insn;
4314 #endif
4315                     save_state(dc, cpu_cond);
4316                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4317                     break;
4318                 case 0x1a:      /* load signed halfword alternate */
4319 #ifndef TARGET_SPARC64
4320                     if (IS_IMM)
4321                         goto illegal_insn;
4322                     if (!supervisor(dc))
4323                         goto priv_insn;
4324 #endif
4325                     save_state(dc, cpu_cond);
4326                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4327                     break;
4328                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
4329 #ifndef TARGET_SPARC64
4330                     if (IS_IMM)
4331                         goto illegal_insn;
4332                     if (!supervisor(dc))
4333                         goto priv_insn;
4334 #endif
4335                     save_state(dc, cpu_cond);
4336                     gen_ldstub_asi(cpu_val, cpu_addr, insn);
4337                     break;
4338                 case 0x1f:      /* swap reg with alt. memory. Also
4339                                    atomically */
4340                     CHECK_IU_FEATURE(dc, SWAP);
4341 #ifndef TARGET_SPARC64
4342                     if (IS_IMM)
4343                         goto illegal_insn;
4344                     if (!supervisor(dc))
4345                         goto priv_insn;
4346 #endif
4347                     save_state(dc, cpu_cond);
4348                     gen_movl_reg_TN(rd, cpu_val);
4349                     gen_swap_asi(cpu_val, cpu_addr, insn);
4350                     break;
4351
4352 #ifndef TARGET_SPARC64
4353                 case 0x30: /* ldc */
4354                 case 0x31: /* ldcsr */
4355                 case 0x33: /* lddc */
4356                     goto ncp_insn;
4357 #endif
4358 #endif
4359 #ifdef TARGET_SPARC64
4360                 case 0x08: /* V9 ldsw */
4361                     ABI32_MASK(cpu_addr);
4362                     tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4363                     break;
4364                 case 0x0b: /* V9 ldx */
4365                     ABI32_MASK(cpu_addr);
4366                     tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4367                     break;
4368                 case 0x18: /* V9 ldswa */
4369                     save_state(dc, cpu_cond);
4370                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4371                     break;
4372                 case 0x1b: /* V9 ldxa */
4373                     save_state(dc, cpu_cond);
4374                     gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4375                     break;
4376                 case 0x2d: /* V9 prefetch, no effect */
4377                     goto skip_move;
4378                 case 0x30: /* V9 ldfa */
4379                     save_state(dc, cpu_cond);
4380                     gen_ldf_asi(cpu_addr, insn, 4, rd);
4381                     goto skip_move;
4382                 case 0x33: /* V9 lddfa */
4383                     save_state(dc, cpu_cond);
4384                     gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4385                     goto skip_move;
4386                 case 0x3d: /* V9 prefetcha, no effect */
4387                     goto skip_move;
4388                 case 0x32: /* V9 ldqfa */
4389                     CHECK_FPU_FEATURE(dc, FLOAT128);
4390                     save_state(dc, cpu_cond);
4391                     gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4392                     goto skip_move;
4393 #endif
4394                 default:
4395                     goto illegal_insn;
4396                 }
4397                 gen_movl_TN_reg(rd, cpu_val);
4398 #ifdef TARGET_SPARC64
4399             skip_move: ;
4400 #endif
4401             } else if (xop >= 0x20 && xop < 0x24) {
4402                 if (gen_trap_ifnofpu(dc, cpu_cond))
4403                     goto jmp_insn;
4404                 save_state(dc, cpu_cond);
4405                 switch (xop) {
4406                 case 0x20:      /* load fpreg */
4407                     ABI32_MASK(cpu_addr);
4408                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4409                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4410                                    offsetof(CPUState, fpr[rd]));
4411                     break;
4412                 case 0x21:      /* load fsr */
4413                     ABI32_MASK(cpu_addr);
4414                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4415                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4416                                    offsetof(CPUState, ft0));
4417                     tcg_gen_helper_0_0(helper_ldfsr);
4418                     break;
4419                 case 0x22:      /* load quad fpreg */
4420                     {
4421                         TCGv r_const;
4422
4423                         CHECK_FPU_FEATURE(dc, FLOAT128);
4424                         r_const = tcg_const_i32(dc->mem_idx);
4425                         tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4426                         tcg_temp_free(r_const);
4427                         gen_op_store_QT0_fpr(QFPREG(rd));
4428                     }
4429                     break;
4430                 case 0x23:      /* load double fpreg */
4431                     {
4432                         TCGv r_const;
4433
4434                         r_const = tcg_const_i32(dc->mem_idx);
4435                         tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4436                         tcg_temp_free(r_const);
4437                         gen_op_store_DT0_fpr(DFPREG(rd));
4438                     }
4439                     break;
4440                 default:
4441                     goto illegal_insn;
4442                 }
4443             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4444                        xop == 0xe || xop == 0x1e) {
4445                 gen_movl_reg_TN(rd, cpu_val);
4446                 switch (xop) {
4447                 case 0x4: /* store word */
4448                     ABI32_MASK(cpu_addr);
4449                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4450                     break;
4451                 case 0x5: /* store byte */
4452                     ABI32_MASK(cpu_addr);
4453                     tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4454                     break;
4455                 case 0x6: /* store halfword */
4456                     ABI32_MASK(cpu_addr);
4457                     tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4458                     break;
4459                 case 0x7: /* store double word */
4460                     if (rd & 1)
4461                         goto illegal_insn;
4462                     else {
4463                         TCGv r_low, r_const;
4464
4465                         save_state(dc, cpu_cond);
4466                         ABI32_MASK(cpu_addr);
4467                         r_const = tcg_const_i32(7);
4468                         tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4469                                            r_const); // XXX remove
4470                         tcg_temp_free(r_const);
4471                         r_low = tcg_temp_new(TCG_TYPE_TL);
4472                         gen_movl_reg_TN(rd + 1, r_low);
4473                         tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4474                                            r_low);
4475                         tcg_temp_free(r_low);
4476                         tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4477                     }
4478                     break;
4479 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4480                 case 0x14: /* store word alternate */
4481 #ifndef TARGET_SPARC64
4482                     if (IS_IMM)
4483                         goto illegal_insn;
4484                     if (!supervisor(dc))
4485                         goto priv_insn;
4486 #endif
4487                     save_state(dc, cpu_cond);
4488                     gen_st_asi(cpu_val, cpu_addr, insn, 4);
4489                     break;
4490                 case 0x15: /* store byte alternate */
4491 #ifndef TARGET_SPARC64
4492                     if (IS_IMM)
4493                         goto illegal_insn;
4494                     if (!supervisor(dc))
4495                         goto priv_insn;
4496 #endif
4497                     save_state(dc, cpu_cond);
4498                     gen_st_asi(cpu_val, cpu_addr, insn, 1);
4499                     break;
4500                 case 0x16: /* store halfword alternate */
4501 #ifndef TARGET_SPARC64
4502                     if (IS_IMM)
4503                         goto illegal_insn;
4504                     if (!supervisor(dc))
4505                         goto priv_insn;
4506 #endif
4507                     save_state(dc, cpu_cond);
4508                     gen_st_asi(cpu_val, cpu_addr, insn, 2);
4509                     break;
4510                 case 0x17: /* store double word alternate */
4511 #ifndef TARGET_SPARC64
4512                     if (IS_IMM)
4513                         goto illegal_insn;
4514                     if (!supervisor(dc))
4515                         goto priv_insn;
4516 #endif
4517                     if (rd & 1)
4518                         goto illegal_insn;
4519                     else {
4520                         save_state(dc, cpu_cond);
4521                         gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4522                     }
4523                     break;
4524 #endif
4525 #ifdef TARGET_SPARC64
4526                 case 0x0e: /* V9 stx */
4527                     ABI32_MASK(cpu_addr);
4528                     tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4529                     break;
4530                 case 0x1e: /* V9 stxa */
4531                     save_state(dc, cpu_cond);
4532                     gen_st_asi(cpu_val, cpu_addr, insn, 8);
4533                     break;
4534 #endif
4535                 default:
4536                     goto illegal_insn;
4537                 }
4538             } else if (xop > 0x23 && xop < 0x28) {
4539                 if (gen_trap_ifnofpu(dc, cpu_cond))
4540                     goto jmp_insn;
4541                 save_state(dc, cpu_cond);
4542                 switch (xop) {
4543                 case 0x24: /* store fpreg */
4544                     ABI32_MASK(cpu_addr);
4545                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4546                                    offsetof(CPUState, fpr[rd]));
4547                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4548                     break;
4549                 case 0x25: /* stfsr, V9 stxfsr */
4550                     ABI32_MASK(cpu_addr);
4551                     tcg_gen_helper_0_0(helper_stfsr);
4552                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4553                                    offsetof(CPUState, ft0));
4554                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4555                     break;
4556                 case 0x26:
4557 #ifdef TARGET_SPARC64
4558                     /* V9 stqf, store quad fpreg */
4559                     {
4560                         TCGv r_const;
4561
4562                         CHECK_FPU_FEATURE(dc, FLOAT128);
4563                         gen_op_load_fpr_QT0(QFPREG(rd));
4564                         r_const = tcg_const_i32(dc->mem_idx);
4565                         tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4566                         tcg_temp_free(r_const);
4567                     }
4568                     break;
4569 #else /* !TARGET_SPARC64 */
4570                     /* stdfq, store floating point queue */
4571 #if defined(CONFIG_USER_ONLY)
4572                     goto illegal_insn;
4573 #else
4574                     if (!supervisor(dc))
4575                         goto priv_insn;
4576                     if (gen_trap_ifnofpu(dc, cpu_cond))
4577                         goto jmp_insn;
4578                     goto nfq_insn;
4579 #endif
4580 #endif
4581                 case 0x27: /* store double fpreg */
4582                     {
4583                         TCGv r_const;
4584
4585                         gen_op_load_fpr_DT0(DFPREG(rd));
4586                         r_const = tcg_const_i32(dc->mem_idx);
4587                         tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4588                         tcg_temp_free(r_const);
4589                     }
4590                     break;
4591                 default:
4592                     goto illegal_insn;
4593                 }
4594             } else if (xop > 0x33 && xop < 0x3f) {
4595                 save_state(dc, cpu_cond);
4596                 switch (xop) {
4597 #ifdef TARGET_SPARC64
4598                 case 0x34: /* V9 stfa */
4599                     gen_op_load_fpr_FT0(rd);
4600                     gen_stf_asi(cpu_addr, insn, 4, rd);
4601                     break;
4602                 case 0x36: /* V9 stqfa */
4603                     {
4604                         TCGv r_const;
4605
4606                         CHECK_FPU_FEATURE(dc, FLOAT128);
4607                         r_const = tcg_const_i32(7);
4608                         tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4609                                            r_const);
4610                         tcg_temp_free(r_const);
4611                         gen_op_load_fpr_QT0(QFPREG(rd));
4612                         gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4613                     }
4614                     break;
4615                 case 0x37: /* V9 stdfa */
4616                     gen_op_load_fpr_DT0(DFPREG(rd));
4617                     gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4618                     break;
4619                 case 0x3c: /* V9 casa */
4620                     gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4621                     gen_movl_TN_reg(rd, cpu_val);
4622                     break;
4623                 case 0x3e: /* V9 casxa */
4624                     gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4625                     gen_movl_TN_reg(rd, cpu_val);
4626                     break;
4627 #else
4628                 case 0x34: /* stc */
4629                 case 0x35: /* stcsr */
4630                 case 0x36: /* stdcq */
4631                 case 0x37: /* stdc */
4632                     goto ncp_insn;
4633 #endif
4634                 default:
4635                     goto illegal_insn;
4636                 }
4637             }
4638             else
4639                 goto illegal_insn;
4640         }
4641         break;
4642     }
4643     /* default case for non jump instructions */
4644     if (dc->npc == DYNAMIC_PC) {
4645         dc->pc = DYNAMIC_PC;
4646         gen_op_next_insn();
4647     } else if (dc->npc == JUMP_PC) {
4648         /* we can do a static jump */
4649         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4650         dc->is_br = 1;
4651     } else {
4652         dc->pc = dc->npc;
4653         dc->npc = dc->npc + 4;
4654     }
4655  jmp_insn:
4656     return;
4657  illegal_insn:
4658     {
4659         TCGv r_const;
4660
4661         save_state(dc, cpu_cond);
4662         r_const = tcg_const_i32(TT_ILL_INSN);
4663         tcg_gen_helper_0_1(raise_exception, r_const);
4664         tcg_temp_free(r_const);
4665         dc->is_br = 1;
4666     }
4667     return;
4668  unimp_flush:
4669     {
4670         TCGv r_const;
4671
4672         save_state(dc, cpu_cond);
4673         r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4674         tcg_gen_helper_0_1(raise_exception, r_const);
4675         tcg_temp_free(r_const);
4676         dc->is_br = 1;
4677     }
4678     return;
4679 #if !defined(CONFIG_USER_ONLY)
4680  priv_insn:
4681     {
4682         TCGv r_const;
4683
4684         save_state(dc, cpu_cond);
4685         r_const = tcg_const_i32(TT_PRIV_INSN);
4686         tcg_gen_helper_0_1(raise_exception, r_const);
4687         tcg_temp_free(r_const);
4688         dc->is_br = 1;
4689     }
4690     return;
4691 #endif
4692  nfpu_insn:
4693     save_state(dc, cpu_cond);
4694     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4695     dc->is_br = 1;
4696     return;
4697 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4698  nfq_insn:
4699     save_state(dc, cpu_cond);
4700     gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4701     dc->is_br = 1;
4702     return;
4703 #endif
4704 #ifndef TARGET_SPARC64
4705  ncp_insn:
4706     {
4707         TCGv r_const;
4708
4709         save_state(dc, cpu_cond);
4710         r_const = tcg_const_i32(TT_NCP_INSN);
4711         tcg_gen_helper_0_1(raise_exception, r_const);
4712         tcg_temp_free(r_const);
4713         dc->is_br = 1;
4714     }
4715     return;
4716 #endif
4717 }
4718
4719 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4720                                                  int spc, CPUSPARCState *env)
4721 {
4722     target_ulong pc_start, last_pc;
4723     uint16_t *gen_opc_end;
4724     DisasContext dc1, *dc = &dc1;
4725     int j, lj = -1;
4726
4727     memset(dc, 0, sizeof(DisasContext));
4728     dc->tb = tb;
4729     pc_start = tb->pc;
4730     dc->pc = pc_start;
4731     last_pc = dc->pc;
4732     dc->npc = (target_ulong) tb->cs_base;
4733     dc->mem_idx = cpu_mmu_index(env);
4734     dc->features = env->features;
4735     if ((dc->features & CPU_FEATURE_FLOAT)) {
4736         dc->fpu_enabled = cpu_fpu_enabled(env);
4737 #if defined(CONFIG_USER_ONLY)
4738         dc->features |= CPU_FEATURE_FLOAT128;
4739 #endif
4740     } else
4741         dc->fpu_enabled = 0;
4742     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4743
4744     cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4745     cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4746     cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4747     cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
4748
4749     do {
4750         if (env->nb_breakpoints > 0) {
4751             for(j = 0; j < env->nb_breakpoints; j++) {
4752                 if (env->breakpoints[j] == dc->pc) {
4753                     if (dc->pc != pc_start)
4754                         save_state(dc, cpu_cond);
4755                     tcg_gen_helper_0_0(helper_debug);
4756                     tcg_gen_exit_tb(0);
4757                     dc->is_br = 1;
4758                     goto exit_gen_loop;
4759                 }
4760             }
4761         }
4762         if (spc) {
4763             if (loglevel > 0)
4764                 fprintf(logfile, "Search PC...\n");
4765             j = gen_opc_ptr - gen_opc_buf;
4766             if (lj < j) {
4767                 lj++;
4768                 while (lj < j)
4769                     gen_opc_instr_start[lj++] = 0;
4770                 gen_opc_pc[lj] = dc->pc;
4771                 gen_opc_npc[lj] = dc->npc;
4772                 gen_opc_instr_start[lj] = 1;
4773             }
4774         }
4775         last_pc = dc->pc;
4776         disas_sparc_insn(dc);
4777
4778         if (dc->is_br)
4779             break;
4780         /* if the next PC is different, we abort now */
4781         if (dc->pc != (last_pc + 4))
4782             break;
4783         /* if we reach a page boundary, we stop generation so that the
4784            PC of a TT_TFAULT exception is always in the right page */
4785         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4786             break;
4787         /* if single step mode, we generate only one instruction and
4788            generate an exception */
4789         if (env->singlestep_enabled) {
4790             tcg_gen_movi_tl(cpu_pc, dc->pc);
4791             tcg_gen_exit_tb(0);
4792             break;
4793         }
4794     } while ((gen_opc_ptr < gen_opc_end) &&
4795              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4796
4797  exit_gen_loop:
4798     tcg_temp_free(cpu_val);
4799     tcg_temp_free(cpu_tmp64);
4800     tcg_temp_free(cpu_tmp32);
4801     tcg_temp_free(cpu_tmp0);
4802     if (!dc->is_br) {
4803         if (dc->pc != DYNAMIC_PC &&
4804             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4805             /* static PC and NPC: we can use direct chaining */
4806             gen_goto_tb(dc, 0, dc->pc, dc->npc);
4807         } else {
4808             if (dc->pc != DYNAMIC_PC)
4809                 tcg_gen_movi_tl(cpu_pc, dc->pc);
4810             save_npc(dc, cpu_cond);
4811             tcg_gen_exit_tb(0);
4812         }
4813     }
4814     *gen_opc_ptr = INDEX_op_end;
4815     if (spc) {
4816         j = gen_opc_ptr - gen_opc_buf;
4817         lj++;
4818         while (lj <= j)
4819             gen_opc_instr_start[lj++] = 0;
4820 #if 0
4821         if (loglevel > 0) {
4822             page_dump(logfile);
4823         }
4824 #endif
4825         gen_opc_jump_pc[0] = dc->jump_pc[0];
4826         gen_opc_jump_pc[1] = dc->jump_pc[1];
4827     } else {
4828         tb->size = last_pc + 4 - pc_start;
4829     }
4830 #ifdef DEBUG_DISAS
4831     if (loglevel & CPU_LOG_TB_IN_ASM) {
4832         fprintf(logfile, "--------------\n");
4833         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4834         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4835         fprintf(logfile, "\n");
4836     }
4837 #endif
4838     return 0;
4839 }
4840
4841 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4842 {
4843     return gen_intermediate_code_internal(tb, 0, env);
4844 }
4845
4846 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4847 {
4848     return gen_intermediate_code_internal(tb, 1, env);
4849 }
4850
4851 void gen_intermediate_code_init(CPUSPARCState *env)
4852 {
4853     unsigned int i;
4854     static int inited;
4855     static const char * const gregnames[8] = {
4856         NULL, // g0 not used
4857         "g1",
4858         "g2",
4859         "g3",
4860         "g4",
4861         "g5",
4862         "g6",
4863         "g7",
4864     };
4865
4866     /* init various static tables */
4867     if (!inited) {
4868         inited = 1;
4869
4870         cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4871         cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4872                                          offsetof(CPUState, regwptr),
4873                                          "regwptr");
4874 #ifdef TARGET_SPARC64
4875         cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4876                                      TCG_AREG0, offsetof(CPUState, xcc),
4877                                      "xcc");
4878 #endif
4879         /* XXX: T0 should be a temporary */
4880         cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4881                                       TCG_AREG0, offsetof(CPUState, t0), "T0");
4882         cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4883                                       TCG_AREG0, offsetof(CPUState, cond),
4884                                       "cond");
4885         cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4886                                         TCG_AREG0, offsetof(CPUState, cc_src),
4887                                         "cc_src");
4888         cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4889                                          offsetof(CPUState, cc_src2),
4890                                          "cc_src2");
4891         cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4892                                         TCG_AREG0, offsetof(CPUState, cc_dst),
4893                                         "cc_dst");
4894         cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4895                                      TCG_AREG0, offsetof(CPUState, psr),
4896                                      "psr");
4897         cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4898                                      TCG_AREG0, offsetof(CPUState, fsr),
4899                                      "fsr");
4900         cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4901                                     TCG_AREG0, offsetof(CPUState, pc),
4902                                     "pc");
4903         cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4904                                     TCG_AREG0, offsetof(CPUState, npc),
4905                                     "npc");
4906         for (i = 1; i < 8; i++)
4907             cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4908                                               offsetof(CPUState, gregs[i]),
4909                                               gregnames[i]);
4910         /* register helpers */
4911
4912 #undef DEF_HELPER
4913 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4914 #include "helper.h"
4915     }
4916 }
4917
4918 void gen_pc_load(CPUState *env, TranslationBlock *tb,
4919                 unsigned long searched_pc, int pc_pos, void *puc)
4920 {
4921     target_ulong npc;
4922     env->pc = gen_opc_pc[pc_pos];
4923     npc = gen_opc_npc[pc_pos];
4924     if (npc == 1) {
4925         /* dynamic NPC: already stored */
4926     } else if (npc == 2) {
4927         target_ulong t2 = (target_ulong)(unsigned long)puc;
4928         /* jump PC: use T2 and the jump targets of the translation */
4929         if (t2)
4930             env->npc = gen_opc_jump_pc[0];
4931         else
4932             env->npc = gen_opc_jump_pc[1];
4933     } else {
4934         env->npc = npc;
4935     }
4936 }