4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 Rest of V9 instructions, VIS instructions
26 NPC/PC static optimisations (use JUMP_TB when possible)
27 Optimize synthetic instructions
44 #define DYNAMIC_PC 1 /* dynamic pc value */
45 #define JUMP_PC 2 /* dynamic pc value which takes only two values
46 according to jump_pc[T2] */
48 /* global register indexes */
49 static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
50 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
54 /* local register indexes (only used inside old micro ops) */
57 typedef struct DisasContext {
58 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
59 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
60 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
64 struct TranslationBlock *tb;
67 typedef struct sparc_def_t sparc_def_t;
70 const unsigned char *name;
71 target_ulong iu_version;
75 uint32_t mmu_ctpr_mask;
76 uint32_t mmu_cxr_mask;
77 uint32_t mmu_sfsr_mask;
78 uint32_t mmu_trcr_mask;
81 static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
86 // This function uses non-native bit order
87 #define GET_FIELD(X, FROM, TO) \
88 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
90 // This function uses the order in the manuals, i.e. bit 0 is 2^0
91 #define GET_FIELD_SP(X, FROM, TO) \
92 GET_FIELD(X, 31 - (TO), 31 - (FROM))
94 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
95 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
99 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
100 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
102 #define FFPREG(r) (r)
103 #define DFPREG(r) (r & 0x1e)
104 #define QFPREG(r) (r & 0x1c)
107 static int sign_extend(int x, int len)
110 return (x << len) >> len;
113 #define IS_IMM (insn & (1<<13))
115 static void disas_sparc_insn(DisasContext * dc);
117 /* floating point registers moves */
118 static void gen_op_load_fpr_FT0(unsigned int src)
120 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
121 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0));
124 static void gen_op_load_fpr_FT1(unsigned int src)
126 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
127 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft1));
130 static void gen_op_store_FT0_fpr(unsigned int dst)
132 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0));
133 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
136 static void gen_op_load_fpr_DT0(unsigned int src)
138 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
139 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
140 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
141 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
144 static void gen_op_load_fpr_DT1(unsigned int src)
146 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
147 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
148 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
149 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
152 static void gen_op_store_DT0_fpr(unsigned int dst)
154 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
155 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
156 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
157 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
160 #ifdef CONFIG_USER_ONLY
161 static void gen_op_load_fpr_QT0(unsigned int src)
163 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
164 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
165 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
166 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
167 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
168 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
169 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
170 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
173 static void gen_op_load_fpr_QT1(unsigned int src)
175 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
176 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
177 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
178 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
179 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
180 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
181 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
182 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
185 static void gen_op_store_QT0_fpr(unsigned int dst)
187 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
188 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
189 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
190 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
191 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
192 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
193 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
194 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
199 #ifdef CONFIG_USER_ONLY
200 #define supervisor(dc) 0
201 #ifdef TARGET_SPARC64
202 #define hypervisor(dc) 0
204 #define gen_op_ldst(name) gen_op_##name##_raw()
206 #define supervisor(dc) (dc->mem_idx >= 1)
207 #ifdef TARGET_SPARC64
208 #define hypervisor(dc) (dc->mem_idx == 2)
209 #define OP_LD_TABLE(width) \
210 static GenOpFunc * const gen_op_##width[] = { \
211 &gen_op_##width##_user, \
212 &gen_op_##width##_kernel, \
213 &gen_op_##width##_hypv, \
216 #define OP_LD_TABLE(width) \
217 static GenOpFunc * const gen_op_##width[] = { \
218 &gen_op_##width##_user, \
219 &gen_op_##width##_kernel, \
222 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
225 #ifndef CONFIG_USER_ONLY
228 #endif /* __i386__ */
236 #define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL);
238 #define ABI32_MASK(addr)
241 static inline void gen_movl_simm_T1(int32_t val)
243 tcg_gen_movi_tl(cpu_T[1], val);
246 static inline void gen_movl_reg_TN(int reg, TCGv tn)
249 tcg_gen_movi_tl(tn, 0);
251 tcg_gen_mov_tl(tn, cpu_gregs[reg]);
253 tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
257 static inline void gen_movl_reg_T0(int reg)
259 gen_movl_reg_TN(reg, cpu_T[0]);
262 static inline void gen_movl_reg_T1(int reg)
264 gen_movl_reg_TN(reg, cpu_T[1]);
268 static inline void gen_movl_reg_T2(int reg)
270 gen_movl_reg_TN(reg, cpu_T[2]);
273 #endif /* __i386__ */
274 static inline void gen_movl_TN_reg(int reg, TCGv tn)
279 tcg_gen_mov_tl(cpu_gregs[reg], tn);
281 tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
285 static inline void gen_movl_T0_reg(int reg)
287 gen_movl_TN_reg(reg, cpu_T[0]);
290 static inline void gen_movl_T1_reg(int reg)
292 gen_movl_TN_reg(reg, cpu_T[1]);
295 static inline void gen_op_movl_T0_env(size_t offset)
297 tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
300 static inline void gen_op_movl_env_T0(size_t offset)
302 tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
305 static inline void gen_op_movtl_T0_env(size_t offset)
307 tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);
310 static inline void gen_op_movtl_env_T0(size_t offset)
312 tcg_gen_st_tl(cpu_T[0], cpu_env, offset);
315 static inline void gen_op_add_T1_T0(void)
317 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
320 static inline void gen_op_or_T1_T0(void)
322 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
325 static inline void gen_op_xor_T1_T0(void)
327 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
330 static inline void gen_jmp_im(target_ulong pc)
332 tcg_gen_movi_tl(cpu_pc, pc);
335 static inline void gen_movl_npc_im(target_ulong npc)
337 tcg_gen_movi_tl(cpu_npc, npc);
340 static inline void gen_goto_tb(DisasContext *s, int tb_num,
341 target_ulong pc, target_ulong npc)
343 TranslationBlock *tb;
346 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
347 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
348 /* jump to same page: we can use a direct jump */
349 tcg_gen_goto_tb(tb_num);
351 gen_movl_npc_im(npc);
352 tcg_gen_exit_tb((long)tb + tb_num);
354 /* jump to another page: currently not optimized */
356 gen_movl_npc_im(npc);
362 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
364 tcg_gen_shri_i32(reg, src, 23);
365 tcg_gen_andi_tl(reg, reg, 0x1);
368 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
370 tcg_gen_shri_i32(reg, src, 22);
371 tcg_gen_andi_tl(reg, reg, 0x1);
374 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
376 tcg_gen_shri_i32(reg, src, 21);
377 tcg_gen_andi_tl(reg, reg, 0x1);
380 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
382 tcg_gen_shri_i32(reg, src, 20);
383 tcg_gen_andi_tl(reg, reg, 0x1);
386 static inline void gen_op_exception(int exception)
388 tcg_gen_movi_i32(cpu_tmp0, exception);
389 tcg_gen_helper_0_1(raise_exception, cpu_tmp0);
392 static inline void gen_cc_clear(void)
394 tcg_gen_movi_i32(cpu_psr, 0);
395 #ifdef TARGET_SPARC64
396 tcg_gen_movi_i32(cpu_xcc, 0);
402 env->psr |= PSR_ZERO;
403 if ((int32_t) T0 < 0)
406 static inline void gen_cc_NZ(TCGv dst)
410 l1 = gen_new_label();
411 l2 = gen_new_label();
412 tcg_gen_brcond_i32(TCG_COND_NE, dst, tcg_const_i32(0), l1);
413 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
415 tcg_gen_brcond_i32(TCG_COND_GE, dst, tcg_const_i32(0), l2);
416 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
418 #ifdef TARGET_SPARC64
422 l3 = gen_new_label();
423 l4 = gen_new_label();
424 tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l3);
425 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
427 tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l4);
428 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
436 env->psr |= PSR_CARRY;
438 static inline void gen_cc_C_add(TCGv dst, TCGv src1)
442 l1 = gen_new_label();
443 tcg_gen_brcond_i32(TCG_COND_GEU, dst, src1, l1);
444 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
446 #ifdef TARGET_SPARC64
450 l2 = gen_new_label();
451 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2);
452 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
459 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
462 static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2)
467 l1 = gen_new_label();
469 r_temp = tcg_temp_new(TCG_TYPE_TL);
470 tcg_gen_xor_tl(r_temp, src1, src2);
471 tcg_gen_xori_tl(r_temp, r_temp, -1);
472 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
473 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
474 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
475 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
476 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
478 #ifdef TARGET_SPARC64
482 l2 = gen_new_label();
483 tcg_gen_xor_tl(r_temp, src1, src2);
484 tcg_gen_xori_tl(r_temp, r_temp, -1);
485 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
486 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
487 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
488 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
489 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
493 tcg_gen_discard_tl(r_temp);
496 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
501 l1 = gen_new_label();
503 r_temp = tcg_temp_new(TCG_TYPE_TL);
504 tcg_gen_xor_tl(r_temp, src1, src2);
505 tcg_gen_xori_tl(r_temp, r_temp, -1);
506 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
507 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
508 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
509 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
510 gen_op_exception(TT_TOVF);
512 #ifdef TARGET_SPARC64
516 l2 = gen_new_label();
517 tcg_gen_xor_tl(r_temp, src1, src2);
518 tcg_gen_xori_tl(r_temp, r_temp, -1);
519 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
520 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
521 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
522 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
523 gen_op_exception(TT_TOVF);
527 tcg_gen_discard_tl(r_temp);
530 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
534 l1 = gen_new_label();
535 tcg_gen_or_tl(cpu_tmp0, src1, src2);
536 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
537 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
538 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
542 static inline void gen_tag_tv(TCGv src1, TCGv src2)
546 l1 = gen_new_label();
547 tcg_gen_or_tl(cpu_tmp0, src1, src2);
548 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
549 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
550 gen_op_exception(TT_TOVF);
554 static inline void gen_op_add_T1_T0_cc(void)
556 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
557 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
560 gen_cc_C_add(cpu_T[0], cpu_cc_src);
561 gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
564 static inline void gen_op_addx_T1_T0_cc(void)
566 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
567 gen_mov_reg_C(cpu_tmp0, cpu_psr);
568 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
570 gen_cc_C_add(cpu_T[0], cpu_cc_src);
571 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
572 gen_cc_C_add(cpu_T[0], cpu_cc_src);
574 gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
577 static inline void gen_op_tadd_T1_T0_cc(void)
579 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
580 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
583 gen_cc_C_add(cpu_T[0], cpu_cc_src);
584 gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
585 gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
588 static inline void gen_op_tadd_T1_T0_ccTV(void)
590 gen_tag_tv(cpu_T[0], cpu_T[1]);
591 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
592 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
593 gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
596 gen_cc_C_add(cpu_T[0], cpu_cc_src);
601 env->psr |= PSR_CARRY;
603 static inline void gen_cc_C_sub(TCGv src1, TCGv src2)
607 l1 = gen_new_label();
608 tcg_gen_brcond_i32(TCG_COND_GEU, src1, src2, l1);
609 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
611 #ifdef TARGET_SPARC64
615 l2 = gen_new_label();
616 tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2);
617 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
624 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
627 static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2)
632 l1 = gen_new_label();
634 r_temp = tcg_temp_new(TCG_TYPE_TL);
635 tcg_gen_xor_tl(r_temp, src1, src2);
636 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
637 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
638 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
639 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
640 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
642 #ifdef TARGET_SPARC64
646 l2 = gen_new_label();
647 tcg_gen_xor_tl(r_temp, src1, src2);
648 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
649 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
650 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
651 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
652 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
656 tcg_gen_discard_tl(r_temp);
659 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
664 l1 = gen_new_label();
666 r_temp = tcg_temp_new(TCG_TYPE_TL);
667 tcg_gen_xor_tl(r_temp, src1, src2);
668 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
669 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
670 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
671 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
672 gen_op_exception(TT_TOVF);
674 #ifdef TARGET_SPARC64
678 l2 = gen_new_label();
679 tcg_gen_xor_tl(r_temp, src1, src2);
680 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
681 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
682 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
683 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
684 gen_op_exception(TT_TOVF);
688 tcg_gen_discard_tl(r_temp);
691 static inline void gen_op_sub_T1_T0_cc(void)
693 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
694 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
697 gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
698 gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
701 static inline void gen_op_subx_T1_T0_cc(void)
703 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
704 gen_mov_reg_C(cpu_tmp0, cpu_psr);
705 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
707 gen_cc_C_sub(cpu_T[0], cpu_cc_src);
708 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
709 gen_cc_C_sub(cpu_T[0], cpu_cc_src);
711 gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
714 static inline void gen_op_tsub_T1_T0_cc(void)
716 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
717 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
720 gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
721 gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
722 gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
725 static inline void gen_op_tsub_T1_T0_ccTV(void)
727 gen_tag_tv(cpu_T[0], cpu_T[1]);
728 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
729 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
730 gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
733 gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
736 static inline void gen_op_mulscc_T1_T0(void)
741 l1 = gen_new_label();
742 l2 = gen_new_label();
743 r_temp = tcg_temp_new(TCG_TYPE_TL);
749 tcg_gen_ld_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
750 tcg_gen_andi_i32(r_temp, r_temp, 0x1);
751 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
752 tcg_gen_mov_tl(cpu_cc_src2, cpu_T[1]);
753 gen_op_jmp_label(l2);
755 tcg_gen_movi_tl(cpu_cc_src2, 0);
759 // env->y = (b2 << 31) | (env->y >> 1);
760 tcg_gen_shli_i32(r_temp, cpu_T[0], 31);
761 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
762 tcg_gen_shri_i32(cpu_tmp0, cpu_tmp0, 1);
763 tcg_gen_or_i32(cpu_tmp0, cpu_tmp0, r_temp);
764 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
767 gen_mov_reg_N(cpu_tmp0, cpu_psr);
768 gen_mov_reg_V(r_temp, cpu_psr);
769 tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
771 // T0 = (b1 << 31) | (T0 >> 1);
773 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
774 tcg_gen_shri_tl(cpu_cc_src, cpu_T[0], 1);
775 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
777 /* do addition and update flags */
778 tcg_gen_add_tl(cpu_T[0], cpu_cc_src, cpu_cc_src2);
779 tcg_gen_discard_tl(r_temp);
783 gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_cc_src2);
784 gen_cc_C_add(cpu_T[0], cpu_cc_src);
787 static inline void gen_op_umul_T1_T0(void)
789 TCGv r_temp, r_temp2;
791 r_temp = tcg_temp_new(TCG_TYPE_I64);
792 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
794 tcg_gen_extu_i32_i64(r_temp, cpu_T[1]);
795 tcg_gen_extu_i32_i64(r_temp2, cpu_T[0]);
796 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
798 tcg_gen_shri_i64(r_temp, r_temp2, 32);
799 tcg_gen_trunc_i64_i32(r_temp, r_temp);
800 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
801 #ifdef TARGET_SPARC64
802 tcg_gen_mov_i64(cpu_T[0], r_temp2);
804 tcg_gen_trunc_i64_i32(cpu_T[0], r_temp2);
807 tcg_gen_discard_i64(r_temp);
808 tcg_gen_discard_i64(r_temp2);
811 static inline void gen_op_smul_T1_T0(void)
813 TCGv r_temp, r_temp2;
815 r_temp = tcg_temp_new(TCG_TYPE_I64);
816 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
818 tcg_gen_ext_i32_i64(r_temp, cpu_T[1]);
819 tcg_gen_ext_i32_i64(r_temp2, cpu_T[0]);
820 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
822 tcg_gen_shri_i64(r_temp, r_temp2, 32);
823 tcg_gen_trunc_i64_i32(r_temp, r_temp);
824 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
825 #ifdef TARGET_SPARC64
826 tcg_gen_mov_i64(cpu_T[0], r_temp2);
828 tcg_gen_trunc_i64_i32(cpu_T[0], r_temp2);
831 tcg_gen_discard_i64(r_temp);
832 tcg_gen_discard_i64(r_temp2);
835 static inline void gen_op_udiv_T1_T0(void)
837 tcg_gen_helper_1_2(helper_udiv, cpu_T[0], cpu_T[0], cpu_T[1]);
840 static inline void gen_op_sdiv_T1_T0(void)
842 tcg_gen_helper_1_2(helper_sdiv, cpu_T[0], cpu_T[0], cpu_T[1]);
845 #ifdef TARGET_SPARC64
846 static inline void gen_trap_ifdivzero_i64(TCGv divisor)
850 l1 = gen_new_label();
851 tcg_gen_brcond_i64(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
852 gen_op_exception(TT_DIV_ZERO);
856 static inline void gen_op_sdivx_T1_T0(void)
860 l1 = gen_new_label();
861 l2 = gen_new_label();
862 gen_trap_ifdivzero_i64(cpu_T[1]);
863 tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[0], tcg_const_i64(INT64_MIN), l1);
864 tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[1], tcg_const_i64(-1), l1);
865 tcg_gen_movi_i64(cpu_T[0], INT64_MIN);
866 gen_op_jmp_label(l2);
868 tcg_gen_div_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
873 static inline void gen_op_div_cc(void)
879 l1 = gen_new_label();
880 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
881 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
882 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
886 static inline void gen_op_logic_T0_cc(void)
893 static inline void gen_op_eval_ba(TCGv dst)
895 tcg_gen_movi_tl(dst, 1);
899 static inline void gen_op_eval_be(TCGv dst, TCGv src)
901 gen_mov_reg_Z(dst, src);
905 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
907 gen_mov_reg_N(cpu_tmp0, src);
908 gen_mov_reg_V(dst, src);
909 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
910 gen_mov_reg_Z(cpu_tmp0, src);
911 tcg_gen_or_tl(dst, dst, cpu_tmp0);
915 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
917 gen_mov_reg_V(cpu_tmp0, src);
918 gen_mov_reg_N(dst, src);
919 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
923 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
925 gen_mov_reg_Z(cpu_tmp0, src);
926 gen_mov_reg_C(dst, src);
927 tcg_gen_or_tl(dst, dst, cpu_tmp0);
931 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
933 gen_mov_reg_C(dst, src);
937 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
939 gen_mov_reg_V(dst, src);
943 static inline void gen_op_eval_bn(TCGv dst)
945 tcg_gen_movi_tl(dst, 0);
949 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
951 gen_mov_reg_N(dst, src);
955 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
957 gen_mov_reg_Z(dst, src);
958 tcg_gen_xori_tl(dst, dst, 0x1);
962 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
964 gen_mov_reg_N(cpu_tmp0, src);
965 gen_mov_reg_V(dst, src);
966 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
967 gen_mov_reg_Z(cpu_tmp0, src);
968 tcg_gen_or_tl(dst, dst, cpu_tmp0);
969 tcg_gen_xori_tl(dst, dst, 0x1);
973 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
975 gen_mov_reg_V(cpu_tmp0, src);
976 gen_mov_reg_N(dst, src);
977 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
978 tcg_gen_xori_tl(dst, dst, 0x1);
982 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
984 gen_mov_reg_Z(cpu_tmp0, src);
985 gen_mov_reg_C(dst, src);
986 tcg_gen_or_tl(dst, dst, cpu_tmp0);
987 tcg_gen_xori_tl(dst, dst, 0x1);
991 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
993 gen_mov_reg_C(dst, src);
994 tcg_gen_xori_tl(dst, dst, 0x1);
998 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
1000 gen_mov_reg_N(dst, src);
1001 tcg_gen_xori_tl(dst, dst, 0x1);
1005 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
1007 gen_mov_reg_V(dst, src);
1008 tcg_gen_xori_tl(dst, dst, 0x1);
1012 FPSR bit field FCC1 | FCC0:
1018 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
1019 unsigned int fcc_offset)
1021 tcg_gen_shri_i32(reg, src, 10 + fcc_offset);
1022 tcg_gen_andi_tl(reg, reg, 0x1);
1025 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
1026 unsigned int fcc_offset)
1028 tcg_gen_shri_i32(reg, src, 11 + fcc_offset);
1029 tcg_gen_andi_tl(reg, reg, 0x1);
1033 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1034 unsigned int fcc_offset)
1036 gen_mov_reg_FCC0(dst, src, fcc_offset);
1037 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1038 tcg_gen_or_tl(dst, dst, cpu_tmp0);
1041 // 1 or 2: FCC0 ^ FCC1
1042 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1043 unsigned int fcc_offset)
1045 gen_mov_reg_FCC0(dst, src, fcc_offset);
1046 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1047 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1051 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1052 unsigned int fcc_offset)
1054 gen_mov_reg_FCC0(dst, src, fcc_offset);
1058 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1059 unsigned int fcc_offset)
1061 gen_mov_reg_FCC0(dst, src, fcc_offset);
1062 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1063 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1064 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1068 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1069 unsigned int fcc_offset)
1071 gen_mov_reg_FCC1(dst, src, fcc_offset);
1075 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1076 unsigned int fcc_offset)
1078 gen_mov_reg_FCC0(dst, src, fcc_offset);
1079 tcg_gen_xori_tl(dst, dst, 0x1);
1080 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1081 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1085 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1086 unsigned int fcc_offset)
1088 gen_mov_reg_FCC0(dst, src, fcc_offset);
1089 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1090 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1093 // 0: !(FCC0 | FCC1)
1094 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1095 unsigned int fcc_offset)
1097 gen_mov_reg_FCC0(dst, src, fcc_offset);
1098 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1099 tcg_gen_or_tl(dst, dst, cpu_tmp0);
1100 tcg_gen_xori_tl(dst, dst, 0x1);
1103 // 0 or 3: !(FCC0 ^ FCC1)
1104 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1105 unsigned int fcc_offset)
1107 gen_mov_reg_FCC0(dst, src, fcc_offset);
1108 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1109 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1110 tcg_gen_xori_tl(dst, dst, 0x1);
1114 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1115 unsigned int fcc_offset)
1117 gen_mov_reg_FCC0(dst, src, fcc_offset);
1118 tcg_gen_xori_tl(dst, dst, 0x1);
1121 // !1: !(FCC0 & !FCC1)
1122 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1123 unsigned int fcc_offset)
1125 gen_mov_reg_FCC0(dst, src, fcc_offset);
1126 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1127 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1128 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1129 tcg_gen_xori_tl(dst, dst, 0x1);
1133 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1134 unsigned int fcc_offset)
1136 gen_mov_reg_FCC1(dst, src, fcc_offset);
1137 tcg_gen_xori_tl(dst, dst, 0x1);
1140 // !2: !(!FCC0 & FCC1)
1141 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1142 unsigned int fcc_offset)
1144 gen_mov_reg_FCC0(dst, src, fcc_offset);
1145 tcg_gen_xori_tl(dst, dst, 0x1);
1146 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1147 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1148 tcg_gen_xori_tl(dst, dst, 0x1);
1151 // !3: !(FCC0 & FCC1)
1152 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1153 unsigned int fcc_offset)
1155 gen_mov_reg_FCC0(dst, src, fcc_offset);
1156 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1157 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1158 tcg_gen_xori_tl(dst, dst, 0x1);
1161 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1162 target_ulong pc2, TCGv r_cond)
1166 l1 = gen_new_label();
1168 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1170 gen_goto_tb(dc, 0, pc1, pc1 + 4);
1173 gen_goto_tb(dc, 1, pc2, pc2 + 4);
1176 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1177 target_ulong pc2, TCGv r_cond)
1181 l1 = gen_new_label();
1183 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1185 gen_goto_tb(dc, 0, pc2, pc1);
1188 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1191 static inline void gen_branch(DisasContext *dc, target_ulong pc,
1194 gen_goto_tb(dc, 0, pc, npc);
1197 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1202 l1 = gen_new_label();
1203 l2 = gen_new_label();
1205 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1207 gen_movl_npc_im(npc1);
1208 gen_op_jmp_label(l2);
1211 gen_movl_npc_im(npc2);
1215 /* call this function before using T2 as it may have been set for a jump */
1216 static inline void flush_T2(DisasContext * dc)
1218 if (dc->npc == JUMP_PC) {
1219 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
1220 dc->npc = DYNAMIC_PC;
1224 static inline void save_npc(DisasContext * dc)
1226 if (dc->npc == JUMP_PC) {
1227 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
1228 dc->npc = DYNAMIC_PC;
1229 } else if (dc->npc != DYNAMIC_PC) {
1230 gen_movl_npc_im(dc->npc);
1234 static inline void save_state(DisasContext * dc)
1240 static inline void gen_mov_pc_npc(DisasContext * dc)
1242 if (dc->npc == JUMP_PC) {
1243 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
1244 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1245 dc->pc = DYNAMIC_PC;
1246 } else if (dc->npc == DYNAMIC_PC) {
1247 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1248 dc->pc = DYNAMIC_PC;
1254 static inline void gen_op_next_insn(void)
1256 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1257 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1260 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1264 #ifdef TARGET_SPARC64
1274 gen_op_eval_bn(r_dst);
1277 gen_op_eval_be(r_dst, r_src);
1280 gen_op_eval_ble(r_dst, r_src);
1283 gen_op_eval_bl(r_dst, r_src);
1286 gen_op_eval_bleu(r_dst, r_src);
1289 gen_op_eval_bcs(r_dst, r_src);
1292 gen_op_eval_bneg(r_dst, r_src);
1295 gen_op_eval_bvs(r_dst, r_src);
1298 gen_op_eval_ba(r_dst);
1301 gen_op_eval_bne(r_dst, r_src);
1304 gen_op_eval_bg(r_dst, r_src);
1307 gen_op_eval_bge(r_dst, r_src);
1310 gen_op_eval_bgu(r_dst, r_src);
1313 gen_op_eval_bcc(r_dst, r_src);
1316 gen_op_eval_bpos(r_dst, r_src);
1319 gen_op_eval_bvc(r_dst, r_src);
1324 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1326 unsigned int offset;
1346 gen_op_eval_bn(r_dst);
1349 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1352 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1355 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1358 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1361 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1364 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1367 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1370 gen_op_eval_ba(r_dst);
1373 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1376 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1379 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1382 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1385 gen_op_eval_fble(r_dst, cpu_fsr, offset);
1388 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1391 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1396 #ifdef TARGET_SPARC64
1398 static const int gen_tcg_cond_reg[8] = {
1409 static inline void gen_cond_reg(TCGv r_dst, int cond)
1413 l1 = gen_new_label();
1414 tcg_gen_movi_tl(r_dst, 0);
1415 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], tcg_const_tl(0), l1);
1416 tcg_gen_movi_tl(r_dst, 1);
1421 /* XXX: potentially incorrect if dynamic npc */
1422 static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1424 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1425 target_ulong target = dc->pc + offset;
1428 /* unconditional not taken */
1430 dc->pc = dc->npc + 4;
1431 dc->npc = dc->pc + 4;
1434 dc->npc = dc->pc + 4;
1436 } else if (cond == 0x8) {
1437 /* unconditional taken */
1440 dc->npc = dc->pc + 4;
1447 gen_cond(cpu_T[2], cc, cond);
1449 gen_branch_a(dc, target, dc->npc, cpu_T[2]);
1453 dc->jump_pc[0] = target;
1454 dc->jump_pc[1] = dc->npc + 4;
1460 /* XXX: potentially incorrect if dynamic npc */
1461 static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1463 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1464 target_ulong target = dc->pc + offset;
1467 /* unconditional not taken */
1469 dc->pc = dc->npc + 4;
1470 dc->npc = dc->pc + 4;
1473 dc->npc = dc->pc + 4;
1475 } else if (cond == 0x8) {
1476 /* unconditional taken */
1479 dc->npc = dc->pc + 4;
1486 gen_fcond(cpu_T[2], cc, cond);
1488 gen_branch_a(dc, target, dc->npc, cpu_T[2]);
1492 dc->jump_pc[0] = target;
1493 dc->jump_pc[1] = dc->npc + 4;
1499 #ifdef TARGET_SPARC64
1500 /* XXX: potentially incorrect if dynamic npc */
1501 static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
1503 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1504 target_ulong target = dc->pc + offset;
1507 gen_cond_reg(cpu_T[2], cond);
1509 gen_branch_a(dc, target, dc->npc, cpu_T[2]);
1513 dc->jump_pc[0] = target;
1514 dc->jump_pc[1] = dc->npc + 4;
1519 static GenOpFunc * const gen_fcmps[4] = {
1526 static GenOpFunc * const gen_fcmpd[4] = {
1533 #if defined(CONFIG_USER_ONLY)
1534 static GenOpFunc * const gen_fcmpq[4] = {
1542 static GenOpFunc * const gen_fcmpes[4] = {
1549 static GenOpFunc * const gen_fcmped[4] = {
1556 #if defined(CONFIG_USER_ONLY)
1557 static GenOpFunc * const gen_fcmpeq[4] = {
1565 static inline void gen_op_fcmps(int fccno)
1567 tcg_gen_helper_0_0(gen_fcmps[fccno]);
1570 static inline void gen_op_fcmpd(int fccno)
1572 tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1575 #if defined(CONFIG_USER_ONLY)
1576 static inline void gen_op_fcmpq(int fccno)
1578 tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1582 static inline void gen_op_fcmpes(int fccno)
1584 tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1587 static inline void gen_op_fcmped(int fccno)
1589 tcg_gen_helper_0_0(gen_fcmped[fccno]);
1592 #if defined(CONFIG_USER_ONLY)
1593 static inline void gen_op_fcmpeq(int fccno)
1595 tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1601 static inline void gen_op_fcmps(int fccno)
1603 tcg_gen_helper_0_0(helper_fcmps);
1606 static inline void gen_op_fcmpd(int fccno)
1608 tcg_gen_helper_0_0(helper_fcmpd);
1611 #if defined(CONFIG_USER_ONLY)
1612 static inline void gen_op_fcmpq(int fccno)
1614 tcg_gen_helper_0_0(helper_fcmpq);
1618 static inline void gen_op_fcmpes(int fccno)
1620 tcg_gen_helper_0_0(helper_fcmpes);
1623 static inline void gen_op_fcmped(int fccno)
1625 tcg_gen_helper_0_0(helper_fcmped);
1628 #if defined(CONFIG_USER_ONLY)
1629 static inline void gen_op_fcmpeq(int fccno)
1631 tcg_gen_helper_0_0(helper_fcmpeq);
1637 static inline void gen_op_fpexception_im(int fsr_flags)
1639 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1640 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1641 gen_op_exception(TT_FP_EXCP);
1644 static int gen_trap_ifnofpu(DisasContext * dc)
1646 #if !defined(CONFIG_USER_ONLY)
1647 if (!dc->fpu_enabled) {
1649 gen_op_exception(TT_NFPU_INSN);
1657 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1659 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1662 static inline void gen_clear_float_exceptions(void)
1664 tcg_gen_helper_0_0(helper_clear_float_exceptions);
1668 #ifdef TARGET_SPARC64
1669 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1675 r_asi = tcg_temp_new(TCG_TYPE_I32);
1676 offset = GET_FIELD(insn, 25, 31);
1677 tcg_gen_addi_tl(r_addr, r_addr, offset);
1678 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1680 asi = GET_FIELD(insn, 19, 26);
1681 r_asi = tcg_const_i32(asi);
1686 static inline void gen_ld_asi(int insn, int size, int sign)
1690 r_asi = gen_get_asi(insn, cpu_T[0]);
1691 tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], r_asi,
1692 tcg_const_i32(size), tcg_const_i32(sign));
1693 tcg_gen_discard_i32(r_asi);
1696 static inline void gen_st_asi(int insn, int size)
1700 r_asi = gen_get_asi(insn, cpu_T[0]);
1701 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi,
1702 tcg_const_i32(size));
1703 tcg_gen_discard_i32(r_asi);
1706 static inline void gen_ldf_asi(int insn, int size, int rd)
1710 r_asi = gen_get_asi(insn, cpu_T[0]);
1711 tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, tcg_const_i32(size),
1713 tcg_gen_discard_i32(r_asi);
1716 static inline void gen_stf_asi(int insn, int size, int rd)
1720 r_asi = gen_get_asi(insn, cpu_T[0]);
1721 tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, tcg_const_i32(size),
1723 tcg_gen_discard_i32(r_asi);
1726 static inline void gen_swap_asi(int insn)
1730 r_temp = tcg_temp_new(TCG_TYPE_I32);
1731 r_asi = gen_get_asi(insn, cpu_T[0]);
1732 tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], r_asi,
1733 tcg_const_i32(4), tcg_const_i32(0));
1734 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_temp, r_asi,
1736 tcg_gen_mov_i32(cpu_T[1], r_temp);
1737 tcg_gen_discard_i32(r_asi);
1738 tcg_gen_discard_i32(r_temp);
1741 static inline void gen_ldda_asi(int insn)
1743 TCGv r_dword, r_asi;
1745 r_dword = tcg_temp_new(TCG_TYPE_I64);
1746 r_asi = gen_get_asi(insn, cpu_T[0]);
1747 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], r_asi,
1748 tcg_const_i32(8), tcg_const_i32(0));
1749 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1750 tcg_gen_shri_i64(r_dword, r_dword, 32);
1751 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1752 tcg_gen_discard_i32(r_asi);
1753 tcg_gen_discard_i64(r_dword);
1756 static inline void gen_stda_asi(int insn, int rd)
1758 TCGv r_dword, r_temp, r_asi;
1760 r_dword = tcg_temp_new(TCG_TYPE_I64);
1761 r_temp = tcg_temp_new(TCG_TYPE_I32);
1762 gen_movl_reg_TN(rd + 1, r_temp);
1763 tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
1765 r_asi = gen_get_asi(insn, cpu_T[0]);
1766 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi,
1768 tcg_gen_discard_i32(r_asi);
1769 tcg_gen_discard_i32(r_temp);
1770 tcg_gen_discard_i64(r_dword);
1773 static inline void gen_cas_asi(int insn, int rd)
1777 r_val1 = tcg_temp_new(TCG_TYPE_I32);
1778 gen_movl_reg_TN(rd, r_val1);
1779 r_asi = gen_get_asi(insn, cpu_T[0]);
1780 tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1782 tcg_gen_discard_i32(r_asi);
1783 tcg_gen_discard_i32(r_val1);
1786 static inline void gen_casx_asi(int insn, int rd)
1790 r_val1 = tcg_temp_new(TCG_TYPE_I64);
1791 gen_movl_reg_TN(rd, r_val1);
1792 r_asi = gen_get_asi(insn, cpu_T[0]);
1793 tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1795 tcg_gen_discard_i32(r_asi);
1796 tcg_gen_discard_i32(r_val1);
1799 #elif !defined(CONFIG_USER_ONLY)
1801 static inline void gen_ld_asi(int insn, int size, int sign)
1806 r_dword = tcg_temp_new(TCG_TYPE_I64);
1807 asi = GET_FIELD(insn, 19, 26);
1808 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], tcg_const_i32(asi),
1809 tcg_const_i32(size), tcg_const_i32(sign));
1810 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1811 tcg_gen_discard_i64(r_dword);
1814 static inline void gen_st_asi(int insn, int size)
1819 r_dword = tcg_temp_new(TCG_TYPE_I64);
1820 tcg_gen_extu_i32_i64(r_dword, cpu_T[1]);
1821 asi = GET_FIELD(insn, 19, 26);
1822 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, tcg_const_i32(asi),
1823 tcg_const_i32(size));
1824 tcg_gen_discard_i64(r_dword);
1827 static inline void gen_swap_asi(int insn)
1832 r_temp = tcg_temp_new(TCG_TYPE_I32);
1833 asi = GET_FIELD(insn, 19, 26);
1834 tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], tcg_const_i32(asi),
1835 tcg_const_i32(4), tcg_const_i32(0));
1836 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], tcg_const_i32(asi),
1838 tcg_gen_mov_i32(cpu_T[1], r_temp);
1839 tcg_gen_discard_i32(r_temp);
1842 static inline void gen_ldda_asi(int insn)
1847 r_dword = tcg_temp_new(TCG_TYPE_I64);
1848 asi = GET_FIELD(insn, 19, 26);
1849 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], tcg_const_i32(asi),
1850 tcg_const_i32(8), tcg_const_i32(0));
1851 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1852 tcg_gen_shri_i64(r_dword, r_dword, 32);
1853 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1854 tcg_gen_discard_i64(r_dword);
1857 static inline void gen_stda_asi(int insn, int rd)
1860 TCGv r_dword, r_temp;
1862 r_dword = tcg_temp_new(TCG_TYPE_I64);
1863 r_temp = tcg_temp_new(TCG_TYPE_I32);
1864 gen_movl_reg_TN(rd + 1, r_temp);
1865 tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1], r_temp);
1866 asi = GET_FIELD(insn, 19, 26);
1867 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, tcg_const_i32(asi),
1869 tcg_gen_discard_i64(r_dword);
1873 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1874 static inline void gen_ldstub_asi(int insn)
1878 gen_ld_asi(insn, 1, 0);
1880 asi = GET_FIELD(insn, 19, 26);
1881 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], tcg_const_i64(0xff),
1882 tcg_const_i32(asi), tcg_const_i32(1));
1886 /* before an instruction, dc->pc must be static */
1887 static void disas_sparc_insn(DisasContext * dc)
1889 unsigned int insn, opc, rs1, rs2, rd;
1891 insn = ldl_code(dc->pc);
1892 opc = GET_FIELD(insn, 0, 1);
1894 rd = GET_FIELD(insn, 2, 6);
1896 case 0: /* branches/sethi */
1898 unsigned int xop = GET_FIELD(insn, 7, 9);
1901 #ifdef TARGET_SPARC64
1902 case 0x1: /* V9 BPcc */
1906 target = GET_FIELD_SP(insn, 0, 18);
1907 target = sign_extend(target, 18);
1909 cc = GET_FIELD_SP(insn, 20, 21);
1911 do_branch(dc, target, insn, 0);
1913 do_branch(dc, target, insn, 1);
1918 case 0x3: /* V9 BPr */
1920 target = GET_FIELD_SP(insn, 0, 13) |
1921 (GET_FIELD_SP(insn, 20, 21) << 14);
1922 target = sign_extend(target, 16);
1924 rs1 = GET_FIELD(insn, 13, 17);
1925 gen_movl_reg_T0(rs1);
1926 do_branch_reg(dc, target, insn);
1929 case 0x5: /* V9 FBPcc */
1931 int cc = GET_FIELD_SP(insn, 20, 21);
1932 if (gen_trap_ifnofpu(dc))
1934 target = GET_FIELD_SP(insn, 0, 18);
1935 target = sign_extend(target, 19);
1937 do_fbranch(dc, target, insn, cc);
1941 case 0x7: /* CBN+x */
1946 case 0x2: /* BN+x */
1948 target = GET_FIELD(insn, 10, 31);
1949 target = sign_extend(target, 22);
1951 do_branch(dc, target, insn, 0);
1954 case 0x6: /* FBN+x */
1956 if (gen_trap_ifnofpu(dc))
1958 target = GET_FIELD(insn, 10, 31);
1959 target = sign_extend(target, 22);
1961 do_fbranch(dc, target, insn, 0);
1964 case 0x4: /* SETHI */
1969 uint32_t value = GET_FIELD(insn, 10, 31);
1970 tcg_gen_movi_tl(cpu_T[0], value << 10);
1971 gen_movl_T0_reg(rd);
1976 case 0x0: /* UNIMPL */
1985 target_long target = GET_FIELDs(insn, 2, 31) << 2;
1987 gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
1993 case 2: /* FPU & Logical Operations */
1995 unsigned int xop = GET_FIELD(insn, 7, 12);
1996 if (xop == 0x3a) { /* generate trap */
1999 rs1 = GET_FIELD(insn, 13, 17);
2000 gen_movl_reg_T0(rs1);
2002 rs2 = GET_FIELD(insn, 25, 31);
2003 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2);
2005 rs2 = GET_FIELD(insn, 27, 31);
2009 gen_movl_reg_T1(rs2);
2015 cond = GET_FIELD(insn, 3, 6);
2018 tcg_gen_helper_0_1(helper_trap, cpu_T[0]);
2019 } else if (cond != 0) {
2020 TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2021 #ifdef TARGET_SPARC64
2023 int cc = GET_FIELD_SP(insn, 11, 12);
2027 gen_cond(r_cond, 0, cond);
2029 gen_cond(r_cond, 1, cond);
2034 gen_cond(r_cond, 0, cond);
2036 tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], r_cond);
2037 tcg_gen_discard_tl(r_cond);
2043 } else if (xop == 0x28) {
2044 rs1 = GET_FIELD(insn, 13, 17);
2047 #ifndef TARGET_SPARC64
2048 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2049 manual, rdy on the microSPARC
2051 case 0x0f: /* stbar in the SPARCv8 manual,
2052 rdy on the microSPARC II */
2053 case 0x10 ... 0x1f: /* implementation-dependent in the
2054 SPARCv8 manual, rdy on the
2057 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
2058 gen_movl_T0_reg(rd);
2060 #ifdef TARGET_SPARC64
2061 case 0x2: /* V9 rdccr */
2062 tcg_gen_helper_1_0(helper_rdccr, cpu_T[0]);
2063 gen_movl_T0_reg(rd);
2065 case 0x3: /* V9 rdasi */
2066 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
2067 gen_movl_T0_reg(rd);
2069 case 0x4: /* V9 rdtick */
2073 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2074 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2075 offsetof(CPUState, tick));
2076 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2078 gen_movl_T0_reg(rd);
2079 tcg_gen_discard_ptr(r_tickptr);
2082 case 0x5: /* V9 rdpc */
2083 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2084 gen_movl_T0_reg(rd);
2086 case 0x6: /* V9 rdfprs */
2087 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
2088 gen_movl_T0_reg(rd);
2090 case 0xf: /* V9 membar */
2091 break; /* no effect */
2092 case 0x13: /* Graphics Status */
2093 if (gen_trap_ifnofpu(dc))
2095 gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
2096 gen_movl_T0_reg(rd);
2098 case 0x17: /* Tick compare */
2099 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
2100 gen_movl_T0_reg(rd);
2102 case 0x18: /* System tick */
2106 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2107 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2108 offsetof(CPUState, stick));
2109 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2111 gen_movl_T0_reg(rd);
2112 tcg_gen_discard_ptr(r_tickptr);
2115 case 0x19: /* System tick compare */
2116 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
2117 gen_movl_T0_reg(rd);
2119 case 0x10: /* Performance Control */
2120 case 0x11: /* Performance Instrumentation Counter */
2121 case 0x12: /* Dispatch Control */
2122 case 0x14: /* Softint set, WO */
2123 case 0x15: /* Softint clear, WO */
2124 case 0x16: /* Softint write */
2129 #if !defined(CONFIG_USER_ONLY)
2130 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2131 #ifndef TARGET_SPARC64
2132 if (!supervisor(dc))
2134 tcg_gen_helper_1_0(helper_rdpsr, cpu_T[0]);
2136 if (!hypervisor(dc))
2138 rs1 = GET_FIELD(insn, 13, 17);
2141 // gen_op_rdhpstate();
2144 // gen_op_rdhtstate();
2147 gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
2150 gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
2153 gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
2155 case 31: // hstick_cmpr
2156 gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2162 gen_movl_T0_reg(rd);
2164 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2165 if (!supervisor(dc))
2167 #ifdef TARGET_SPARC64
2168 rs1 = GET_FIELD(insn, 13, 17);
2174 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2175 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2176 offsetof(CPUState, tsptr));
2177 tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2178 offsetof(trap_state, tpc));
2179 tcg_gen_discard_ptr(r_tsptr);
2186 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2187 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2188 offsetof(CPUState, tsptr));
2189 tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2190 offsetof(trap_state, tnpc));
2191 tcg_gen_discard_ptr(r_tsptr);
2198 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2199 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2200 offsetof(CPUState, tsptr));
2201 tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2202 offsetof(trap_state, tstate));
2203 tcg_gen_discard_ptr(r_tsptr);
2210 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2211 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2212 offsetof(CPUState, tsptr));
2213 tcg_gen_ld_i32(cpu_T[0], r_tsptr,
2214 offsetof(trap_state, tt));
2215 tcg_gen_discard_ptr(r_tsptr);
2222 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2223 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2224 offsetof(CPUState, tick));
2225 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2227 gen_movl_T0_reg(rd);
2228 tcg_gen_discard_ptr(r_tickptr);
2232 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
2235 gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate));
2238 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
2241 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
2244 tcg_gen_helper_1_0(helper_rdcwp, cpu_T[0]);
2247 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
2249 case 11: // canrestore
2250 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
2252 case 12: // cleanwin
2253 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
2255 case 13: // otherwin
2256 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
2259 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
2261 case 16: // UA2005 gl
2262 gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
2264 case 26: // UA2005 strand status
2265 if (!hypervisor(dc))
2267 gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
2270 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
2277 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
2279 gen_movl_T0_reg(rd);
2281 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2282 #ifdef TARGET_SPARC64
2285 if (!supervisor(dc))
2287 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
2288 gen_movl_T0_reg(rd);
2292 } else if (xop == 0x34) { /* FPU Operations */
2293 if (gen_trap_ifnofpu(dc))
2295 gen_op_clear_ieee_excp_and_FTT();
2296 rs1 = GET_FIELD(insn, 13, 17);
2297 rs2 = GET_FIELD(insn, 27, 31);
2298 xop = GET_FIELD(insn, 18, 26);
2300 case 0x1: /* fmovs */
2301 gen_op_load_fpr_FT0(rs2);
2302 gen_op_store_FT0_fpr(rd);
2304 case 0x5: /* fnegs */
2305 gen_op_load_fpr_FT1(rs2);
2306 tcg_gen_helper_0_0(helper_fnegs);
2307 gen_op_store_FT0_fpr(rd);
2309 case 0x9: /* fabss */
2310 gen_op_load_fpr_FT1(rs2);
2311 tcg_gen_helper_0_0(helper_fabss);
2312 gen_op_store_FT0_fpr(rd);
2314 case 0x29: /* fsqrts */
2315 gen_op_load_fpr_FT1(rs2);
2316 gen_clear_float_exceptions();
2317 tcg_gen_helper_0_0(helper_fsqrts);
2318 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2319 gen_op_store_FT0_fpr(rd);
2321 case 0x2a: /* fsqrtd */
2322 gen_op_load_fpr_DT1(DFPREG(rs2));
2323 gen_clear_float_exceptions();
2324 tcg_gen_helper_0_0(helper_fsqrtd);
2325 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2326 gen_op_store_DT0_fpr(DFPREG(rd));
2328 case 0x2b: /* fsqrtq */
2329 #if defined(CONFIG_USER_ONLY)
2330 gen_op_load_fpr_QT1(QFPREG(rs2));
2331 gen_clear_float_exceptions();
2332 tcg_gen_helper_0_0(helper_fsqrtq);
2333 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2334 gen_op_store_QT0_fpr(QFPREG(rd));
2340 gen_op_load_fpr_FT0(rs1);
2341 gen_op_load_fpr_FT1(rs2);
2342 gen_clear_float_exceptions();
2343 tcg_gen_helper_0_0(helper_fadds);
2344 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2345 gen_op_store_FT0_fpr(rd);
2348 gen_op_load_fpr_DT0(DFPREG(rs1));
2349 gen_op_load_fpr_DT1(DFPREG(rs2));
2350 gen_clear_float_exceptions();
2351 tcg_gen_helper_0_0(helper_faddd);
2352 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2353 gen_op_store_DT0_fpr(DFPREG(rd));
2355 case 0x43: /* faddq */
2356 #if defined(CONFIG_USER_ONLY)
2357 gen_op_load_fpr_QT0(QFPREG(rs1));
2358 gen_op_load_fpr_QT1(QFPREG(rs2));
2359 gen_clear_float_exceptions();
2360 tcg_gen_helper_0_0(helper_faddq);
2361 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2362 gen_op_store_QT0_fpr(QFPREG(rd));
2368 gen_op_load_fpr_FT0(rs1);
2369 gen_op_load_fpr_FT1(rs2);
2370 gen_clear_float_exceptions();
2371 tcg_gen_helper_0_0(helper_fsubs);
2372 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2373 gen_op_store_FT0_fpr(rd);
2376 gen_op_load_fpr_DT0(DFPREG(rs1));
2377 gen_op_load_fpr_DT1(DFPREG(rs2));
2378 gen_clear_float_exceptions();
2379 tcg_gen_helper_0_0(helper_fsubd);
2380 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2381 gen_op_store_DT0_fpr(DFPREG(rd));
2383 case 0x47: /* fsubq */
2384 #if defined(CONFIG_USER_ONLY)
2385 gen_op_load_fpr_QT0(QFPREG(rs1));
2386 gen_op_load_fpr_QT1(QFPREG(rs2));
2387 gen_clear_float_exceptions();
2388 tcg_gen_helper_0_0(helper_fsubq);
2389 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2390 gen_op_store_QT0_fpr(QFPREG(rd));
2396 gen_op_load_fpr_FT0(rs1);
2397 gen_op_load_fpr_FT1(rs2);
2398 gen_clear_float_exceptions();
2399 tcg_gen_helper_0_0(helper_fmuls);
2400 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2401 gen_op_store_FT0_fpr(rd);
2404 gen_op_load_fpr_DT0(DFPREG(rs1));
2405 gen_op_load_fpr_DT1(DFPREG(rs2));
2406 gen_clear_float_exceptions();
2407 tcg_gen_helper_0_0(helper_fmuld);
2408 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2409 gen_op_store_DT0_fpr(DFPREG(rd));
2411 case 0x4b: /* fmulq */
2412 #if defined(CONFIG_USER_ONLY)
2413 gen_op_load_fpr_QT0(QFPREG(rs1));
2414 gen_op_load_fpr_QT1(QFPREG(rs2));
2415 gen_clear_float_exceptions();
2416 tcg_gen_helper_0_0(helper_fmulq);
2417 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2418 gen_op_store_QT0_fpr(QFPREG(rd));
2424 gen_op_load_fpr_FT0(rs1);
2425 gen_op_load_fpr_FT1(rs2);
2426 gen_clear_float_exceptions();
2427 tcg_gen_helper_0_0(helper_fdivs);
2428 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2429 gen_op_store_FT0_fpr(rd);
2432 gen_op_load_fpr_DT0(DFPREG(rs1));
2433 gen_op_load_fpr_DT1(DFPREG(rs2));
2434 gen_clear_float_exceptions();
2435 tcg_gen_helper_0_0(helper_fdivd);
2436 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2437 gen_op_store_DT0_fpr(DFPREG(rd));
2439 case 0x4f: /* fdivq */
2440 #if defined(CONFIG_USER_ONLY)
2441 gen_op_load_fpr_QT0(QFPREG(rs1));
2442 gen_op_load_fpr_QT1(QFPREG(rs2));
2443 gen_clear_float_exceptions();
2444 tcg_gen_helper_0_0(helper_fdivq);
2445 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2446 gen_op_store_QT0_fpr(QFPREG(rd));
2452 gen_op_load_fpr_FT0(rs1);
2453 gen_op_load_fpr_FT1(rs2);
2454 gen_clear_float_exceptions();
2455 tcg_gen_helper_0_0(helper_fsmuld);
2456 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2457 gen_op_store_DT0_fpr(DFPREG(rd));
2459 case 0x6e: /* fdmulq */
2460 #if defined(CONFIG_USER_ONLY)
2461 gen_op_load_fpr_DT0(DFPREG(rs1));
2462 gen_op_load_fpr_DT1(DFPREG(rs2));
2463 gen_clear_float_exceptions();
2464 tcg_gen_helper_0_0(helper_fdmulq);
2465 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2466 gen_op_store_QT0_fpr(QFPREG(rd));
2472 gen_op_load_fpr_FT1(rs2);
2473 gen_clear_float_exceptions();
2474 tcg_gen_helper_0_0(helper_fitos);
2475 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2476 gen_op_store_FT0_fpr(rd);
2479 gen_op_load_fpr_DT1(DFPREG(rs2));
2480 gen_clear_float_exceptions();
2481 tcg_gen_helper_0_0(helper_fdtos);
2482 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2483 gen_op_store_FT0_fpr(rd);
2485 case 0xc7: /* fqtos */
2486 #if defined(CONFIG_USER_ONLY)
2487 gen_op_load_fpr_QT1(QFPREG(rs2));
2488 gen_clear_float_exceptions();
2489 tcg_gen_helper_0_0(helper_fqtos);
2490 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2491 gen_op_store_FT0_fpr(rd);
2497 gen_op_load_fpr_FT1(rs2);
2498 tcg_gen_helper_0_0(helper_fitod);
2499 gen_op_store_DT0_fpr(DFPREG(rd));
2502 gen_op_load_fpr_FT1(rs2);
2503 tcg_gen_helper_0_0(helper_fstod);
2504 gen_op_store_DT0_fpr(DFPREG(rd));
2506 case 0xcb: /* fqtod */
2507 #if defined(CONFIG_USER_ONLY)
2508 gen_op_load_fpr_QT1(QFPREG(rs2));
2509 gen_clear_float_exceptions();
2510 tcg_gen_helper_0_0(helper_fqtod);
2511 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2512 gen_op_store_DT0_fpr(DFPREG(rd));
2517 case 0xcc: /* fitoq */
2518 #if defined(CONFIG_USER_ONLY)
2519 gen_op_load_fpr_FT1(rs2);
2520 tcg_gen_helper_0_0(helper_fitoq);
2521 gen_op_store_QT0_fpr(QFPREG(rd));
2526 case 0xcd: /* fstoq */
2527 #if defined(CONFIG_USER_ONLY)
2528 gen_op_load_fpr_FT1(rs2);
2529 tcg_gen_helper_0_0(helper_fstoq);
2530 gen_op_store_QT0_fpr(QFPREG(rd));
2535 case 0xce: /* fdtoq */
2536 #if defined(CONFIG_USER_ONLY)
2537 gen_op_load_fpr_DT1(DFPREG(rs2));
2538 tcg_gen_helper_0_0(helper_fdtoq);
2539 gen_op_store_QT0_fpr(QFPREG(rd));
2545 gen_op_load_fpr_FT1(rs2);
2546 gen_clear_float_exceptions();
2547 tcg_gen_helper_0_0(helper_fstoi);
2548 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2549 gen_op_store_FT0_fpr(rd);
2552 gen_op_load_fpr_DT1(DFPREG(rs2));
2553 gen_clear_float_exceptions();
2554 tcg_gen_helper_0_0(helper_fdtoi);
2555 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2556 gen_op_store_FT0_fpr(rd);
2558 case 0xd3: /* fqtoi */
2559 #if defined(CONFIG_USER_ONLY)
2560 gen_op_load_fpr_QT1(QFPREG(rs2));
2561 gen_clear_float_exceptions();
2562 tcg_gen_helper_0_0(helper_fqtoi);
2563 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2564 gen_op_store_FT0_fpr(rd);
2569 #ifdef TARGET_SPARC64
2570 case 0x2: /* V9 fmovd */
2571 gen_op_load_fpr_DT0(DFPREG(rs2));
2572 gen_op_store_DT0_fpr(DFPREG(rd));
2574 case 0x3: /* V9 fmovq */
2575 #if defined(CONFIG_USER_ONLY)
2576 gen_op_load_fpr_QT0(QFPREG(rs2));
2577 gen_op_store_QT0_fpr(QFPREG(rd));
2582 case 0x6: /* V9 fnegd */
2583 gen_op_load_fpr_DT1(DFPREG(rs2));
2584 tcg_gen_helper_0_0(helper_fnegd);
2585 gen_op_store_DT0_fpr(DFPREG(rd));
2587 case 0x7: /* V9 fnegq */
2588 #if defined(CONFIG_USER_ONLY)
2589 gen_op_load_fpr_QT1(QFPREG(rs2));
2590 tcg_gen_helper_0_0(helper_fnegq);
2591 gen_op_store_QT0_fpr(QFPREG(rd));
2596 case 0xa: /* V9 fabsd */
2597 gen_op_load_fpr_DT1(DFPREG(rs2));
2598 tcg_gen_helper_0_0(helper_fabsd);
2599 gen_op_store_DT0_fpr(DFPREG(rd));
2601 case 0xb: /* V9 fabsq */
2602 #if defined(CONFIG_USER_ONLY)
2603 gen_op_load_fpr_QT1(QFPREG(rs2));
2604 tcg_gen_helper_0_0(helper_fabsq);
2605 gen_op_store_QT0_fpr(QFPREG(rd));
2610 case 0x81: /* V9 fstox */
2611 gen_op_load_fpr_FT1(rs2);
2612 gen_clear_float_exceptions();
2613 tcg_gen_helper_0_0(helper_fstox);
2614 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2615 gen_op_store_DT0_fpr(DFPREG(rd));
2617 case 0x82: /* V9 fdtox */
2618 gen_op_load_fpr_DT1(DFPREG(rs2));
2619 gen_clear_float_exceptions();
2620 tcg_gen_helper_0_0(helper_fdtox);
2621 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2622 gen_op_store_DT0_fpr(DFPREG(rd));
2624 case 0x83: /* V9 fqtox */
2625 #if defined(CONFIG_USER_ONLY)
2626 gen_op_load_fpr_QT1(QFPREG(rs2));
2627 gen_clear_float_exceptions();
2628 tcg_gen_helper_0_0(helper_fqtox);
2629 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2630 gen_op_store_DT0_fpr(DFPREG(rd));
2635 case 0x84: /* V9 fxtos */
2636 gen_op_load_fpr_DT1(DFPREG(rs2));
2637 gen_clear_float_exceptions();
2638 tcg_gen_helper_0_0(helper_fxtos);
2639 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2640 gen_op_store_FT0_fpr(rd);
2642 case 0x88: /* V9 fxtod */
2643 gen_op_load_fpr_DT1(DFPREG(rs2));
2644 gen_clear_float_exceptions();
2645 tcg_gen_helper_0_0(helper_fxtod);
2646 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2647 gen_op_store_DT0_fpr(DFPREG(rd));
2649 case 0x8c: /* V9 fxtoq */
2650 #if defined(CONFIG_USER_ONLY)
2651 gen_op_load_fpr_DT1(DFPREG(rs2));
2652 gen_clear_float_exceptions();
2653 tcg_gen_helper_0_0(helper_fxtoq);
2654 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2655 gen_op_store_QT0_fpr(QFPREG(rd));
2664 } else if (xop == 0x35) { /* FPU Operations */
2665 #ifdef TARGET_SPARC64
2668 if (gen_trap_ifnofpu(dc))
2670 gen_op_clear_ieee_excp_and_FTT();
2671 rs1 = GET_FIELD(insn, 13, 17);
2672 rs2 = GET_FIELD(insn, 27, 31);
2673 xop = GET_FIELD(insn, 18, 26);
2674 #ifdef TARGET_SPARC64
2675 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2678 l1 = gen_new_label();
2679 cond = GET_FIELD_SP(insn, 14, 17);
2680 rs1 = GET_FIELD(insn, 13, 17);
2681 gen_movl_reg_T0(rs1);
2682 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
2683 tcg_const_tl(0), l1);
2684 gen_op_load_fpr_FT0(rs2);
2685 gen_op_store_FT0_fpr(rd);
2688 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2691 l1 = gen_new_label();
2692 cond = GET_FIELD_SP(insn, 14, 17);
2693 rs1 = GET_FIELD(insn, 13, 17);
2694 gen_movl_reg_T0(rs1);
2695 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
2696 tcg_const_tl(0), l1);
2697 gen_op_load_fpr_DT0(DFPREG(rs2));
2698 gen_op_store_DT0_fpr(DFPREG(rd));
2701 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2702 #if defined(CONFIG_USER_ONLY)
2705 l1 = gen_new_label();
2706 cond = GET_FIELD_SP(insn, 14, 17);
2707 rs1 = GET_FIELD(insn, 13, 17);
2708 gen_movl_reg_T0(rs1);
2709 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
2710 tcg_const_tl(0), l1);
2711 gen_op_load_fpr_QT0(QFPREG(rs2));
2712 gen_op_store_QT0_fpr(QFPREG(rd));
2721 #ifdef TARGET_SPARC64
2722 #define FMOVCC(size_FDQ, fcc) \
2727 l1 = gen_new_label(); \
2728 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2729 cond = GET_FIELD_SP(insn, 14, 17); \
2730 gen_fcond(r_cond, fcc, cond); \
2731 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
2732 tcg_const_tl(0), l1); \
2733 glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2734 glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2735 gen_set_label(l1); \
2736 tcg_gen_discard_tl(r_cond); \
2738 case 0x001: /* V9 fmovscc %fcc0 */
2741 case 0x002: /* V9 fmovdcc %fcc0 */
2744 case 0x003: /* V9 fmovqcc %fcc0 */
2745 #if defined(CONFIG_USER_ONLY)
2751 case 0x041: /* V9 fmovscc %fcc1 */
2754 case 0x042: /* V9 fmovdcc %fcc1 */
2757 case 0x043: /* V9 fmovqcc %fcc1 */
2758 #if defined(CONFIG_USER_ONLY)
2764 case 0x081: /* V9 fmovscc %fcc2 */
2767 case 0x082: /* V9 fmovdcc %fcc2 */
2770 case 0x083: /* V9 fmovqcc %fcc2 */
2771 #if defined(CONFIG_USER_ONLY)
2777 case 0x0c1: /* V9 fmovscc %fcc3 */
2780 case 0x0c2: /* V9 fmovdcc %fcc3 */
2783 case 0x0c3: /* V9 fmovqcc %fcc3 */
2784 #if defined(CONFIG_USER_ONLY)
2791 #define FMOVCC(size_FDQ, icc) \
2796 l1 = gen_new_label(); \
2797 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2798 cond = GET_FIELD_SP(insn, 14, 17); \
2799 gen_cond(r_cond, icc, cond); \
2800 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
2801 tcg_const_tl(0), l1); \
2802 glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2803 glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2804 gen_set_label(l1); \
2805 tcg_gen_discard_tl(r_cond); \
2808 case 0x101: /* V9 fmovscc %icc */
2811 case 0x102: /* V9 fmovdcc %icc */
2813 case 0x103: /* V9 fmovqcc %icc */
2814 #if defined(CONFIG_USER_ONLY)
2820 case 0x181: /* V9 fmovscc %xcc */
2823 case 0x182: /* V9 fmovdcc %xcc */
2826 case 0x183: /* V9 fmovqcc %xcc */
2827 #if defined(CONFIG_USER_ONLY)
2835 case 0x51: /* fcmps, V9 %fcc */
2836 gen_op_load_fpr_FT0(rs1);
2837 gen_op_load_fpr_FT1(rs2);
2838 gen_op_fcmps(rd & 3);
2840 case 0x52: /* fcmpd, V9 %fcc */
2841 gen_op_load_fpr_DT0(DFPREG(rs1));
2842 gen_op_load_fpr_DT1(DFPREG(rs2));
2843 gen_op_fcmpd(rd & 3);
2845 case 0x53: /* fcmpq, V9 %fcc */
2846 #if defined(CONFIG_USER_ONLY)
2847 gen_op_load_fpr_QT0(QFPREG(rs1));
2848 gen_op_load_fpr_QT1(QFPREG(rs2));
2849 gen_op_fcmpq(rd & 3);
2851 #else /* !defined(CONFIG_USER_ONLY) */
2854 case 0x55: /* fcmpes, V9 %fcc */
2855 gen_op_load_fpr_FT0(rs1);
2856 gen_op_load_fpr_FT1(rs2);
2857 gen_op_fcmpes(rd & 3);
2859 case 0x56: /* fcmped, V9 %fcc */
2860 gen_op_load_fpr_DT0(DFPREG(rs1));
2861 gen_op_load_fpr_DT1(DFPREG(rs2));
2862 gen_op_fcmped(rd & 3);
2864 case 0x57: /* fcmpeq, V9 %fcc */
2865 #if defined(CONFIG_USER_ONLY)
2866 gen_op_load_fpr_QT0(QFPREG(rs1));
2867 gen_op_load_fpr_QT1(QFPREG(rs2));
2868 gen_op_fcmpeq(rd & 3);
2870 #else/* !defined(CONFIG_USER_ONLY) */
2877 } else if (xop == 0x2) {
2880 rs1 = GET_FIELD(insn, 13, 17);
2882 // or %g0, x, y -> mov T0, x; mov y, T0
2883 if (IS_IMM) { /* immediate */
2884 rs2 = GET_FIELDs(insn, 19, 31);
2885 tcg_gen_movi_tl(cpu_T[0], (int)rs2);
2886 } else { /* register */
2887 rs2 = GET_FIELD(insn, 27, 31);
2888 gen_movl_reg_T0(rs2);
2891 gen_movl_reg_T0(rs1);
2892 if (IS_IMM) { /* immediate */
2893 rs2 = GET_FIELDs(insn, 19, 31);
2894 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2);
2895 } else { /* register */
2896 // or x, %g0, y -> mov T1, x; mov y, T1
2897 rs2 = GET_FIELD(insn, 27, 31);
2899 gen_movl_reg_T1(rs2);
2904 gen_movl_T0_reg(rd);
2906 #ifdef TARGET_SPARC64
2907 } else if (xop == 0x25) { /* sll, V9 sllx */
2908 rs1 = GET_FIELD(insn, 13, 17);
2909 gen_movl_reg_T0(rs1);
2910 if (IS_IMM) { /* immediate */
2911 rs2 = GET_FIELDs(insn, 20, 31);
2912 if (insn & (1 << 12)) {
2913 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2915 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2916 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2918 } else { /* register */
2919 rs2 = GET_FIELD(insn, 27, 31);
2920 gen_movl_reg_T1(rs2);
2921 if (insn & (1 << 12)) {
2922 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2923 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2925 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2926 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2927 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2930 gen_movl_T0_reg(rd);
2931 } else if (xop == 0x26) { /* srl, V9 srlx */
2932 rs1 = GET_FIELD(insn, 13, 17);
2933 gen_movl_reg_T0(rs1);
2934 if (IS_IMM) { /* immediate */
2935 rs2 = GET_FIELDs(insn, 20, 31);
2936 if (insn & (1 << 12)) {
2937 tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2939 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2940 tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2942 } else { /* register */
2943 rs2 = GET_FIELD(insn, 27, 31);
2944 gen_movl_reg_T1(rs2);
2945 if (insn & (1 << 12)) {
2946 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2947 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2949 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2950 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2951 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2954 gen_movl_T0_reg(rd);
2955 } else if (xop == 0x27) { /* sra, V9 srax */
2956 rs1 = GET_FIELD(insn, 13, 17);
2957 gen_movl_reg_T0(rs1);
2958 if (IS_IMM) { /* immediate */
2959 rs2 = GET_FIELDs(insn, 20, 31);
2960 if (insn & (1 << 12)) {
2961 tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2963 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2964 tcg_gen_ext_i32_i64(cpu_T[0], cpu_T[0]);
2965 tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2967 } else { /* register */
2968 rs2 = GET_FIELD(insn, 27, 31);
2969 gen_movl_reg_T1(rs2);
2970 if (insn & (1 << 12)) {
2971 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2972 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2974 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2975 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2976 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2979 gen_movl_T0_reg(rd);
2981 } else if (xop < 0x36) {
2982 rs1 = GET_FIELD(insn, 13, 17);
2983 gen_movl_reg_T0(rs1);
2984 if (IS_IMM) { /* immediate */
2985 rs2 = GET_FIELDs(insn, 19, 31);
2986 gen_movl_simm_T1(rs2);
2987 } else { /* register */
2988 rs2 = GET_FIELD(insn, 27, 31);
2989 gen_movl_reg_T1(rs2);
2992 switch (xop & ~0x10) {
2995 gen_op_add_T1_T0_cc();
3000 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3002 gen_op_logic_T0_cc();
3005 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3007 gen_op_logic_T0_cc();
3010 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3012 gen_op_logic_T0_cc();
3016 gen_op_sub_T1_T0_cc();
3018 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3021 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3022 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3024 gen_op_logic_T0_cc();
3027 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3028 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3030 gen_op_logic_T0_cc();
3033 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3034 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3036 gen_op_logic_T0_cc();
3040 gen_op_addx_T1_T0_cc();
3042 gen_mov_reg_C(cpu_tmp0, cpu_psr);
3043 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
3044 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3047 #ifdef TARGET_SPARC64
3048 case 0x9: /* V9 mulx */
3049 tcg_gen_mul_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
3053 gen_op_umul_T1_T0();
3055 gen_op_logic_T0_cc();
3058 gen_op_smul_T1_T0();
3060 gen_op_logic_T0_cc();
3064 gen_op_subx_T1_T0_cc();
3066 gen_mov_reg_C(cpu_tmp0, cpu_psr);
3067 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
3068 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3071 #ifdef TARGET_SPARC64
3072 case 0xd: /* V9 udivx */
3073 gen_trap_ifdivzero_i64(cpu_T[1]);
3074 tcg_gen_divu_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
3078 gen_op_udiv_T1_T0();
3083 gen_op_sdiv_T1_T0();
3090 gen_movl_T0_reg(rd);
3093 case 0x20: /* taddcc */
3094 gen_op_tadd_T1_T0_cc();
3095 gen_movl_T0_reg(rd);
3097 case 0x21: /* tsubcc */
3098 gen_op_tsub_T1_T0_cc();
3099 gen_movl_T0_reg(rd);
3101 case 0x22: /* taddcctv */
3103 gen_op_tadd_T1_T0_ccTV();
3104 gen_movl_T0_reg(rd);
3106 case 0x23: /* tsubcctv */
3108 gen_op_tsub_T1_T0_ccTV();
3109 gen_movl_T0_reg(rd);
3111 case 0x24: /* mulscc */
3112 gen_op_mulscc_T1_T0();
3113 gen_movl_T0_reg(rd);
3115 #ifndef TARGET_SPARC64
3116 case 0x25: /* sll */
3117 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3118 tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
3119 gen_movl_T0_reg(rd);
3121 case 0x26: /* srl */
3122 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3123 tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
3124 gen_movl_T0_reg(rd);
3126 case 0x27: /* sra */
3127 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3128 tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
3129 gen_movl_T0_reg(rd);
3137 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
3139 #ifndef TARGET_SPARC64
3140 case 0x01 ... 0x0f: /* undefined in the
3144 case 0x10 ... 0x1f: /* implementation-dependent
3150 case 0x2: /* V9 wrccr */
3152 tcg_gen_helper_0_1(helper_wrccr, cpu_T[0]);
3154 case 0x3: /* V9 wrasi */
3156 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
3158 case 0x6: /* V9 wrfprs */
3160 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
3166 case 0xf: /* V9 sir, nop if user */
3167 #if !defined(CONFIG_USER_ONLY)
3172 case 0x13: /* Graphics Status */
3173 if (gen_trap_ifnofpu(dc))
3176 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
3178 case 0x17: /* Tick compare */
3179 #if !defined(CONFIG_USER_ONLY)
3180 if (!supervisor(dc))
3187 gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3189 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3190 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3191 offsetof(CPUState, tick));
3192 tcg_gen_helper_0_2(helper_tick_set_limit,
3193 r_tickptr, cpu_T[0]);
3194 tcg_gen_discard_ptr(r_tickptr);
3197 case 0x18: /* System tick */
3198 #if !defined(CONFIG_USER_ONLY)
3199 if (!supervisor(dc))
3206 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3207 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3208 offsetof(CPUState, stick));
3209 tcg_gen_helper_0_2(helper_tick_set_count,
3210 r_tickptr, cpu_T[0]);
3211 tcg_gen_discard_ptr(r_tickptr);
3214 case 0x19: /* System tick compare */
3215 #if !defined(CONFIG_USER_ONLY)
3216 if (!supervisor(dc))
3223 gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3225 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3226 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3227 offsetof(CPUState, stick));
3228 tcg_gen_helper_0_2(helper_tick_set_limit,
3229 r_tickptr, cpu_T[0]);
3230 tcg_gen_discard_ptr(r_tickptr);
3234 case 0x10: /* Performance Control */
3235 case 0x11: /* Performance Instrumentation Counter */
3236 case 0x12: /* Dispatch Control */
3237 case 0x14: /* Softint set */
3238 case 0x15: /* Softint clear */
3239 case 0x16: /* Softint write */
3246 #if !defined(CONFIG_USER_ONLY)
3247 case 0x31: /* wrpsr, V9 saved, restored */
3249 if (!supervisor(dc))
3251 #ifdef TARGET_SPARC64
3259 case 2: /* UA2005 allclean */
3260 case 3: /* UA2005 otherw */
3261 case 4: /* UA2005 normalw */
3262 case 5: /* UA2005 invalw */
3269 tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
3277 case 0x32: /* wrwim, V9 wrpr */
3279 if (!supervisor(dc))
3282 #ifdef TARGET_SPARC64
3288 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3289 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3290 offsetof(CPUState, tsptr));
3291 tcg_gen_st_tl(cpu_T[0], r_tsptr,
3292 offsetof(trap_state, tpc));
3293 tcg_gen_discard_ptr(r_tsptr);
3300 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3301 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3302 offsetof(CPUState, tsptr));
3303 tcg_gen_st_tl(cpu_T[0], r_tsptr,
3304 offsetof(trap_state, tnpc));
3305 tcg_gen_discard_ptr(r_tsptr);
3312 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3313 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3314 offsetof(CPUState, tsptr));
3315 tcg_gen_st_tl(cpu_T[0], r_tsptr,
3316 offsetof(trap_state, tstate));
3317 tcg_gen_discard_ptr(r_tsptr);
3324 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3325 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3326 offsetof(CPUState, tsptr));
3327 tcg_gen_st_i32(cpu_T[0], r_tsptr,
3328 offsetof(trap_state, tt));
3329 tcg_gen_discard_ptr(r_tsptr);
3336 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3337 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3338 offsetof(CPUState, tick));
3339 tcg_gen_helper_0_2(helper_tick_set_count,
3340 r_tickptr, cpu_T[0]);
3341 tcg_gen_discard_ptr(r_tickptr);
3345 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3349 tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]);
3355 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
3358 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
3361 tcg_gen_helper_0_1(helper_wrcwp, cpu_T[0]);
3364 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
3366 case 11: // canrestore
3367 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
3369 case 12: // cleanwin
3370 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
3372 case 13: // otherwin
3373 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
3376 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
3378 case 16: // UA2005 gl
3379 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
3381 case 26: // UA2005 strand status
3382 if (!hypervisor(dc))
3384 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
3390 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
3391 gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
3395 case 0x33: /* wrtbr, UA2005 wrhpr */
3397 #ifndef TARGET_SPARC64
3398 if (!supervisor(dc))
3401 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3403 if (!hypervisor(dc))
3408 // XXX gen_op_wrhpstate();
3415 // XXX gen_op_wrhtstate();
3418 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
3421 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
3423 case 31: // hstick_cmpr
3427 gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3429 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3430 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3431 offsetof(CPUState, hstick));
3432 tcg_gen_helper_0_2(helper_tick_set_limit,
3433 r_tickptr, cpu_T[0]);
3434 tcg_gen_discard_ptr(r_tickptr);
3437 case 6: // hver readonly
3445 #ifdef TARGET_SPARC64
3446 case 0x2c: /* V9 movcc */
3448 int cc = GET_FIELD_SP(insn, 11, 12);
3449 int cond = GET_FIELD_SP(insn, 14, 17);
3453 r_cond = tcg_temp_new(TCG_TYPE_TL);
3454 if (insn & (1 << 18)) {
3456 gen_cond(r_cond, 0, cond);
3458 gen_cond(r_cond, 1, cond);
3462 gen_fcond(r_cond, cc, cond);
3465 l1 = gen_new_label();
3467 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,
3468 tcg_const_tl(0), l1);
3469 if (IS_IMM) { /* immediate */
3470 rs2 = GET_FIELD_SPs(insn, 0, 10);
3471 gen_movl_simm_T1(rs2);
3473 rs2 = GET_FIELD_SP(insn, 0, 4);
3474 gen_movl_reg_T1(rs2);
3476 gen_movl_T1_reg(rd);
3478 tcg_gen_discard_tl(r_cond);
3481 case 0x2d: /* V9 sdivx */
3482 gen_op_sdivx_T1_T0();
3483 gen_movl_T0_reg(rd);
3485 case 0x2e: /* V9 popc */
3487 if (IS_IMM) { /* immediate */
3488 rs2 = GET_FIELD_SPs(insn, 0, 12);
3489 gen_movl_simm_T1(rs2);
3490 // XXX optimize: popc(constant)
3493 rs2 = GET_FIELD_SP(insn, 0, 4);
3494 gen_movl_reg_T1(rs2);
3496 tcg_gen_helper_1_1(helper_popc, cpu_T[0],
3498 gen_movl_T0_reg(rd);
3500 case 0x2f: /* V9 movr */
3502 int cond = GET_FIELD_SP(insn, 10, 12);
3505 rs1 = GET_FIELD(insn, 13, 17);
3506 gen_movl_reg_T0(rs1);
3508 l1 = gen_new_label();
3510 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
3511 tcg_const_tl(0), l1);
3512 if (IS_IMM) { /* immediate */
3513 rs2 = GET_FIELD_SPs(insn, 0, 9);
3514 gen_movl_simm_T1(rs2);
3516 rs2 = GET_FIELD_SP(insn, 0, 4);
3517 gen_movl_reg_T1(rs2);
3519 gen_movl_T1_reg(rd);
3528 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3529 #ifdef TARGET_SPARC64
3530 int opf = GET_FIELD_SP(insn, 5, 13);
3531 rs1 = GET_FIELD(insn, 13, 17);
3532 rs2 = GET_FIELD(insn, 27, 31);
3533 if (gen_trap_ifnofpu(dc))
3537 case 0x000: /* VIS I edge8cc */
3538 case 0x001: /* VIS II edge8n */
3539 case 0x002: /* VIS I edge8lcc */
3540 case 0x003: /* VIS II edge8ln */
3541 case 0x004: /* VIS I edge16cc */
3542 case 0x005: /* VIS II edge16n */
3543 case 0x006: /* VIS I edge16lcc */
3544 case 0x007: /* VIS II edge16ln */
3545 case 0x008: /* VIS I edge32cc */
3546 case 0x009: /* VIS II edge32n */
3547 case 0x00a: /* VIS I edge32lcc */
3548 case 0x00b: /* VIS II edge32ln */
3551 case 0x010: /* VIS I array8 */
3552 gen_movl_reg_T0(rs1);
3553 gen_movl_reg_T1(rs2);
3554 tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
3556 gen_movl_T0_reg(rd);
3558 case 0x012: /* VIS I array16 */
3559 gen_movl_reg_T0(rs1);
3560 gen_movl_reg_T1(rs2);
3561 tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
3563 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 1);
3564 gen_movl_T0_reg(rd);
3566 case 0x014: /* VIS I array32 */
3567 gen_movl_reg_T0(rs1);
3568 gen_movl_reg_T1(rs2);
3569 tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
3571 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2);
3572 gen_movl_T0_reg(rd);
3574 case 0x018: /* VIS I alignaddr */
3575 gen_movl_reg_T0(rs1);
3576 gen_movl_reg_T1(rs2);
3577 tcg_gen_helper_1_2(helper_alignaddr, cpu_T[0], cpu_T[0],
3579 gen_movl_T0_reg(rd);
3581 case 0x019: /* VIS II bmask */
3582 case 0x01a: /* VIS I alignaddrl */
3585 case 0x020: /* VIS I fcmple16 */
3586 gen_op_load_fpr_DT0(DFPREG(rs1));
3587 gen_op_load_fpr_DT1(DFPREG(rs2));
3588 tcg_gen_helper_0_0(helper_fcmple16);
3589 gen_op_store_DT0_fpr(DFPREG(rd));
3591 case 0x022: /* VIS I fcmpne16 */
3592 gen_op_load_fpr_DT0(DFPREG(rs1));
3593 gen_op_load_fpr_DT1(DFPREG(rs2));
3594 tcg_gen_helper_0_0(helper_fcmpne16);
3595 gen_op_store_DT0_fpr(DFPREG(rd));
3597 case 0x024: /* VIS I fcmple32 */
3598 gen_op_load_fpr_DT0(DFPREG(rs1));
3599 gen_op_load_fpr_DT1(DFPREG(rs2));
3600 tcg_gen_helper_0_0(helper_fcmple32);
3601 gen_op_store_DT0_fpr(DFPREG(rd));
3603 case 0x026: /* VIS I fcmpne32 */
3604 gen_op_load_fpr_DT0(DFPREG(rs1));
3605 gen_op_load_fpr_DT1(DFPREG(rs2));
3606 tcg_gen_helper_0_0(helper_fcmpne32);
3607 gen_op_store_DT0_fpr(DFPREG(rd));
3609 case 0x028: /* VIS I fcmpgt16 */
3610 gen_op_load_fpr_DT0(DFPREG(rs1));
3611 gen_op_load_fpr_DT1(DFPREG(rs2));
3612 tcg_gen_helper_0_0(helper_fcmpgt16);
3613 gen_op_store_DT0_fpr(DFPREG(rd));
3615 case 0x02a: /* VIS I fcmpeq16 */
3616 gen_op_load_fpr_DT0(DFPREG(rs1));
3617 gen_op_load_fpr_DT1(DFPREG(rs2));
3618 tcg_gen_helper_0_0(helper_fcmpeq16);
3619 gen_op_store_DT0_fpr(DFPREG(rd));
3621 case 0x02c: /* VIS I fcmpgt32 */
3622 gen_op_load_fpr_DT0(DFPREG(rs1));
3623 gen_op_load_fpr_DT1(DFPREG(rs2));
3624 tcg_gen_helper_0_0(helper_fcmpgt32);
3625 gen_op_store_DT0_fpr(DFPREG(rd));
3627 case 0x02e: /* VIS I fcmpeq32 */
3628 gen_op_load_fpr_DT0(DFPREG(rs1));
3629 gen_op_load_fpr_DT1(DFPREG(rs2));
3630 tcg_gen_helper_0_0(helper_fcmpeq32);
3631 gen_op_store_DT0_fpr(DFPREG(rd));
3633 case 0x031: /* VIS I fmul8x16 */
3634 gen_op_load_fpr_DT0(DFPREG(rs1));
3635 gen_op_load_fpr_DT1(DFPREG(rs2));
3636 tcg_gen_helper_0_0(helper_fmul8x16);
3637 gen_op_store_DT0_fpr(DFPREG(rd));
3639 case 0x033: /* VIS I fmul8x16au */
3640 gen_op_load_fpr_DT0(DFPREG(rs1));
3641 gen_op_load_fpr_DT1(DFPREG(rs2));
3642 tcg_gen_helper_0_0(helper_fmul8x16au);
3643 gen_op_store_DT0_fpr(DFPREG(rd));
3645 case 0x035: /* VIS I fmul8x16al */
3646 gen_op_load_fpr_DT0(DFPREG(rs1));
3647 gen_op_load_fpr_DT1(DFPREG(rs2));
3648 tcg_gen_helper_0_0(helper_fmul8x16al);
3649 gen_op_store_DT0_fpr(DFPREG(rd));
3651 case 0x036: /* VIS I fmul8sux16 */
3652 gen_op_load_fpr_DT0(DFPREG(rs1));
3653 gen_op_load_fpr_DT1(DFPREG(rs2));
3654 tcg_gen_helper_0_0(helper_fmul8sux16);
3655 gen_op_store_DT0_fpr(DFPREG(rd));
3657 case 0x037: /* VIS I fmul8ulx16 */
3658 gen_op_load_fpr_DT0(DFPREG(rs1));
3659 gen_op_load_fpr_DT1(DFPREG(rs2));
3660 tcg_gen_helper_0_0(helper_fmul8ulx16);
3661 gen_op_store_DT0_fpr(DFPREG(rd));
3663 case 0x038: /* VIS I fmuld8sux16 */
3664 gen_op_load_fpr_DT0(DFPREG(rs1));
3665 gen_op_load_fpr_DT1(DFPREG(rs2));
3666 tcg_gen_helper_0_0(helper_fmuld8sux16);
3667 gen_op_store_DT0_fpr(DFPREG(rd));
3669 case 0x039: /* VIS I fmuld8ulx16 */
3670 gen_op_load_fpr_DT0(DFPREG(rs1));
3671 gen_op_load_fpr_DT1(DFPREG(rs2));
3672 tcg_gen_helper_0_0(helper_fmuld8ulx16);
3673 gen_op_store_DT0_fpr(DFPREG(rd));
3675 case 0x03a: /* VIS I fpack32 */
3676 case 0x03b: /* VIS I fpack16 */
3677 case 0x03d: /* VIS I fpackfix */
3678 case 0x03e: /* VIS I pdist */
3681 case 0x048: /* VIS I faligndata */
3682 gen_op_load_fpr_DT0(DFPREG(rs1));
3683 gen_op_load_fpr_DT1(DFPREG(rs2));
3684 tcg_gen_helper_0_0(helper_faligndata);
3685 gen_op_store_DT0_fpr(DFPREG(rd));
3687 case 0x04b: /* VIS I fpmerge */
3688 gen_op_load_fpr_DT0(DFPREG(rs1));
3689 gen_op_load_fpr_DT1(DFPREG(rs2));
3690 tcg_gen_helper_0_0(helper_fpmerge);
3691 gen_op_store_DT0_fpr(DFPREG(rd));
3693 case 0x04c: /* VIS II bshuffle */
3696 case 0x04d: /* VIS I fexpand */
3697 gen_op_load_fpr_DT0(DFPREG(rs1));
3698 gen_op_load_fpr_DT1(DFPREG(rs2));
3699 tcg_gen_helper_0_0(helper_fexpand);
3700 gen_op_store_DT0_fpr(DFPREG(rd));
3702 case 0x050: /* VIS I fpadd16 */
3703 gen_op_load_fpr_DT0(DFPREG(rs1));
3704 gen_op_load_fpr_DT1(DFPREG(rs2));
3705 tcg_gen_helper_0_0(helper_fpadd16);
3706 gen_op_store_DT0_fpr(DFPREG(rd));
3708 case 0x051: /* VIS I fpadd16s */
3709 gen_op_load_fpr_FT0(rs1);
3710 gen_op_load_fpr_FT1(rs2);
3711 tcg_gen_helper_0_0(helper_fpadd16s);
3712 gen_op_store_FT0_fpr(rd);
3714 case 0x052: /* VIS I fpadd32 */
3715 gen_op_load_fpr_DT0(DFPREG(rs1));
3716 gen_op_load_fpr_DT1(DFPREG(rs2));
3717 tcg_gen_helper_0_0(helper_fpadd32);
3718 gen_op_store_DT0_fpr(DFPREG(rd));
3720 case 0x053: /* VIS I fpadd32s */
3721 gen_op_load_fpr_FT0(rs1);
3722 gen_op_load_fpr_FT1(rs2);
3723 tcg_gen_helper_0_0(helper_fpadd32s);
3724 gen_op_store_FT0_fpr(rd);
3726 case 0x054: /* VIS I fpsub16 */
3727 gen_op_load_fpr_DT0(DFPREG(rs1));
3728 gen_op_load_fpr_DT1(DFPREG(rs2));
3729 tcg_gen_helper_0_0(helper_fpsub16);
3730 gen_op_store_DT0_fpr(DFPREG(rd));
3732 case 0x055: /* VIS I fpsub16s */
3733 gen_op_load_fpr_FT0(rs1);
3734 gen_op_load_fpr_FT1(rs2);
3735 tcg_gen_helper_0_0(helper_fpsub16s);
3736 gen_op_store_FT0_fpr(rd);
3738 case 0x056: /* VIS I fpsub32 */
3739 gen_op_load_fpr_DT0(DFPREG(rs1));
3740 gen_op_load_fpr_DT1(DFPREG(rs2));
3741 tcg_gen_helper_0_0(helper_fpadd32);
3742 gen_op_store_DT0_fpr(DFPREG(rd));
3744 case 0x057: /* VIS I fpsub32s */
3745 gen_op_load_fpr_FT0(rs1);
3746 gen_op_load_fpr_FT1(rs2);
3747 tcg_gen_helper_0_0(helper_fpsub32s);
3748 gen_op_store_FT0_fpr(rd);
3750 case 0x060: /* VIS I fzero */
3751 tcg_gen_helper_0_0(helper_movl_DT0_0);
3752 gen_op_store_DT0_fpr(DFPREG(rd));
3754 case 0x061: /* VIS I fzeros */
3755 tcg_gen_helper_0_0(helper_movl_FT0_0);
3756 gen_op_store_FT0_fpr(rd);
3758 case 0x062: /* VIS I fnor */
3759 gen_op_load_fpr_DT0(DFPREG(rs1));
3760 gen_op_load_fpr_DT1(DFPREG(rs2));
3761 tcg_gen_helper_0_0(helper_fnor);
3762 gen_op_store_DT0_fpr(DFPREG(rd));
3764 case 0x063: /* VIS I fnors */
3765 gen_op_load_fpr_FT0(rs1);
3766 gen_op_load_fpr_FT1(rs2);
3767 tcg_gen_helper_0_0(helper_fnors);
3768 gen_op_store_FT0_fpr(rd);
3770 case 0x064: /* VIS I fandnot2 */
3771 gen_op_load_fpr_DT1(DFPREG(rs1));
3772 gen_op_load_fpr_DT0(DFPREG(rs2));
3773 tcg_gen_helper_0_0(helper_fandnot);
3774 gen_op_store_DT0_fpr(DFPREG(rd));
3776 case 0x065: /* VIS I fandnot2s */
3777 gen_op_load_fpr_FT1(rs1);
3778 gen_op_load_fpr_FT0(rs2);
3779 tcg_gen_helper_0_0(helper_fandnots);
3780 gen_op_store_FT0_fpr(rd);
3782 case 0x066: /* VIS I fnot2 */
3783 gen_op_load_fpr_DT1(DFPREG(rs2));
3784 tcg_gen_helper_0_0(helper_fnot);
3785 gen_op_store_DT0_fpr(DFPREG(rd));
3787 case 0x067: /* VIS I fnot2s */
3788 gen_op_load_fpr_FT1(rs2);
3789 tcg_gen_helper_0_0(helper_fnot);
3790 gen_op_store_FT0_fpr(rd);
3792 case 0x068: /* VIS I fandnot1 */
3793 gen_op_load_fpr_DT0(DFPREG(rs1));
3794 gen_op_load_fpr_DT1(DFPREG(rs2));
3795 tcg_gen_helper_0_0(helper_fandnot);
3796 gen_op_store_DT0_fpr(DFPREG(rd));
3798 case 0x069: /* VIS I fandnot1s */
3799 gen_op_load_fpr_FT0(rs1);
3800 gen_op_load_fpr_FT1(rs2);
3801 tcg_gen_helper_0_0(helper_fandnots);
3802 gen_op_store_FT0_fpr(rd);
3804 case 0x06a: /* VIS I fnot1 */
3805 gen_op_load_fpr_DT1(DFPREG(rs1));
3806 tcg_gen_helper_0_0(helper_fnot);
3807 gen_op_store_DT0_fpr(DFPREG(rd));
3809 case 0x06b: /* VIS I fnot1s */
3810 gen_op_load_fpr_FT1(rs1);
3811 tcg_gen_helper_0_0(helper_fnot);
3812 gen_op_store_FT0_fpr(rd);
3814 case 0x06c: /* VIS I fxor */
3815 gen_op_load_fpr_DT0(DFPREG(rs1));
3816 gen_op_load_fpr_DT1(DFPREG(rs2));
3817 tcg_gen_helper_0_0(helper_fxor);
3818 gen_op_store_DT0_fpr(DFPREG(rd));
3820 case 0x06d: /* VIS I fxors */
3821 gen_op_load_fpr_FT0(rs1);
3822 gen_op_load_fpr_FT1(rs2);
3823 tcg_gen_helper_0_0(helper_fxors);
3824 gen_op_store_FT0_fpr(rd);
3826 case 0x06e: /* VIS I fnand */
3827 gen_op_load_fpr_DT0(DFPREG(rs1));
3828 gen_op_load_fpr_DT1(DFPREG(rs2));
3829 tcg_gen_helper_0_0(helper_fnand);
3830 gen_op_store_DT0_fpr(DFPREG(rd));
3832 case 0x06f: /* VIS I fnands */
3833 gen_op_load_fpr_FT0(rs1);
3834 gen_op_load_fpr_FT1(rs2);
3835 tcg_gen_helper_0_0(helper_fnands);
3836 gen_op_store_FT0_fpr(rd);
3838 case 0x070: /* VIS I fand */
3839 gen_op_load_fpr_DT0(DFPREG(rs1));
3840 gen_op_load_fpr_DT1(DFPREG(rs2));
3841 tcg_gen_helper_0_0(helper_fand);
3842 gen_op_store_DT0_fpr(DFPREG(rd));
3844 case 0x071: /* VIS I fands */
3845 gen_op_load_fpr_FT0(rs1);
3846 gen_op_load_fpr_FT1(rs2);
3847 tcg_gen_helper_0_0(helper_fands);
3848 gen_op_store_FT0_fpr(rd);
3850 case 0x072: /* VIS I fxnor */
3851 gen_op_load_fpr_DT0(DFPREG(rs1));
3852 gen_op_load_fpr_DT1(DFPREG(rs2));
3853 tcg_gen_helper_0_0(helper_fxnor);
3854 gen_op_store_DT0_fpr(DFPREG(rd));
3856 case 0x073: /* VIS I fxnors */
3857 gen_op_load_fpr_FT0(rs1);
3858 gen_op_load_fpr_FT1(rs2);
3859 tcg_gen_helper_0_0(helper_fxnors);
3860 gen_op_store_FT0_fpr(rd);
3862 case 0x074: /* VIS I fsrc1 */
3863 gen_op_load_fpr_DT0(DFPREG(rs1));
3864 gen_op_store_DT0_fpr(DFPREG(rd));
3866 case 0x075: /* VIS I fsrc1s */
3867 gen_op_load_fpr_FT0(rs1);
3868 gen_op_store_FT0_fpr(rd);
3870 case 0x076: /* VIS I fornot2 */
3871 gen_op_load_fpr_DT1(DFPREG(rs1));
3872 gen_op_load_fpr_DT0(DFPREG(rs2));
3873 tcg_gen_helper_0_0(helper_fornot);
3874 gen_op_store_DT0_fpr(DFPREG(rd));
3876 case 0x077: /* VIS I fornot2s */
3877 gen_op_load_fpr_FT1(rs1);
3878 gen_op_load_fpr_FT0(rs2);
3879 tcg_gen_helper_0_0(helper_fornots);
3880 gen_op_store_FT0_fpr(rd);
3882 case 0x078: /* VIS I fsrc2 */
3883 gen_op_load_fpr_DT0(DFPREG(rs2));
3884 gen_op_store_DT0_fpr(DFPREG(rd));
3886 case 0x079: /* VIS I fsrc2s */
3887 gen_op_load_fpr_FT0(rs2);
3888 gen_op_store_FT0_fpr(rd);
3890 case 0x07a: /* VIS I fornot1 */
3891 gen_op_load_fpr_DT0(DFPREG(rs1));
3892 gen_op_load_fpr_DT1(DFPREG(rs2));
3893 tcg_gen_helper_0_0(helper_fornot);
3894 gen_op_store_DT0_fpr(DFPREG(rd));
3896 case 0x07b: /* VIS I fornot1s */
3897 gen_op_load_fpr_FT0(rs1);
3898 gen_op_load_fpr_FT1(rs2);
3899 tcg_gen_helper_0_0(helper_fornots);
3900 gen_op_store_FT0_fpr(rd);
3902 case 0x07c: /* VIS I for */
3903 gen_op_load_fpr_DT0(DFPREG(rs1));
3904 gen_op_load_fpr_DT1(DFPREG(rs2));
3905 tcg_gen_helper_0_0(helper_for);
3906 gen_op_store_DT0_fpr(DFPREG(rd));
3908 case 0x07d: /* VIS I fors */
3909 gen_op_load_fpr_FT0(rs1);
3910 gen_op_load_fpr_FT1(rs2);
3911 tcg_gen_helper_0_0(helper_fors);
3912 gen_op_store_FT0_fpr(rd);
3914 case 0x07e: /* VIS I fone */
3915 tcg_gen_helper_0_0(helper_movl_DT0_1);
3916 gen_op_store_DT0_fpr(DFPREG(rd));
3918 case 0x07f: /* VIS I fones */
3919 tcg_gen_helper_0_0(helper_movl_FT0_1);
3920 gen_op_store_FT0_fpr(rd);
3922 case 0x080: /* VIS I shutdown */
3923 case 0x081: /* VIS II siam */
3932 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
3933 #ifdef TARGET_SPARC64
3938 #ifdef TARGET_SPARC64
3939 } else if (xop == 0x39) { /* V9 return */
3940 rs1 = GET_FIELD(insn, 13, 17);
3942 gen_movl_reg_T0(rs1);
3943 if (IS_IMM) { /* immediate */
3944 rs2 = GET_FIELDs(insn, 19, 31);
3945 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
3946 } else { /* register */
3947 rs2 = GET_FIELD(insn, 27, 31);
3951 gen_movl_reg_T1(rs2);
3959 gen_op_check_align_T0_3();
3960 tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
3961 dc->npc = DYNAMIC_PC;
3965 rs1 = GET_FIELD(insn, 13, 17);
3966 gen_movl_reg_T0(rs1);
3967 if (IS_IMM) { /* immediate */
3968 rs2 = GET_FIELDs(insn, 19, 31);
3969 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
3970 } else { /* register */
3971 rs2 = GET_FIELD(insn, 27, 31);
3975 gen_movl_reg_T1(rs2);
3982 case 0x38: /* jmpl */
3985 tcg_gen_movi_tl(cpu_T[1], dc->pc);
3986 gen_movl_T1_reg(rd);
3989 gen_op_check_align_T0_3();
3990 tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
3991 dc->npc = DYNAMIC_PC;
3994 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3995 case 0x39: /* rett, V9 return */
3997 if (!supervisor(dc))
4000 gen_op_check_align_T0_3();
4001 tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
4002 dc->npc = DYNAMIC_PC;
4003 tcg_gen_helper_0_0(helper_rett);
4007 case 0x3b: /* flush */
4008 tcg_gen_helper_0_1(helper_flush, cpu_T[0]);
4010 case 0x3c: /* save */
4013 gen_movl_T0_reg(rd);
4015 case 0x3d: /* restore */
4018 gen_movl_T0_reg(rd);
4020 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4021 case 0x3e: /* V9 done/retry */
4025 if (!supervisor(dc))
4027 dc->npc = DYNAMIC_PC;
4028 dc->pc = DYNAMIC_PC;
4029 tcg_gen_helper_0_0(helper_done);
4032 if (!supervisor(dc))
4034 dc->npc = DYNAMIC_PC;
4035 dc->pc = DYNAMIC_PC;
4036 tcg_gen_helper_0_0(helper_retry);
4051 case 3: /* load/store instructions */
4053 unsigned int xop = GET_FIELD(insn, 7, 12);
4054 rs1 = GET_FIELD(insn, 13, 17);
4056 gen_movl_reg_T0(rs1);
4057 if (xop == 0x3c || xop == 0x3e)
4059 rs2 = GET_FIELD(insn, 27, 31);
4060 gen_movl_reg_T1(rs2);
4062 else if (IS_IMM) { /* immediate */
4063 rs2 = GET_FIELDs(insn, 19, 31);
4064 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
4065 } else { /* register */
4066 rs2 = GET_FIELD(insn, 27, 31);
4070 gen_movl_reg_T1(rs2);
4076 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4077 (xop > 0x17 && xop <= 0x1d ) ||
4078 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4080 case 0x0: /* load unsigned word */
4081 gen_op_check_align_T0_3();
4082 ABI32_MASK(cpu_T[0]);
4083 tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx);
4085 case 0x1: /* load unsigned byte */
4086 ABI32_MASK(cpu_T[0]);
4087 tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx);
4089 case 0x2: /* load unsigned halfword */
4090 gen_op_check_align_T0_1();
4091 ABI32_MASK(cpu_T[0]);
4092 tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx);
4094 case 0x3: /* load double word */
4100 r_dword = tcg_temp_new(TCG_TYPE_I64);
4101 gen_op_check_align_T0_7();
4102 ABI32_MASK(cpu_T[0]);
4103 tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx);
4104 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
4105 gen_movl_T0_reg(rd + 1);
4106 tcg_gen_shri_i64(r_dword, r_dword, 32);
4107 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
4108 tcg_gen_discard_i64(r_dword);
4111 case 0x9: /* load signed byte */
4112 ABI32_MASK(cpu_T[0]);
4113 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
4115 case 0xa: /* load signed halfword */
4116 gen_op_check_align_T0_1();
4117 ABI32_MASK(cpu_T[0]);
4118 tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx);
4120 case 0xd: /* ldstub -- XXX: should be atomically */
4121 tcg_gen_movi_i32(cpu_tmp0, 0xff);
4122 ABI32_MASK(cpu_T[0]);
4123 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
4124 tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx);
4126 case 0x0f: /* swap register with memory. Also atomically */
4127 gen_op_check_align_T0_3();
4128 gen_movl_reg_T1(rd);
4129 ABI32_MASK(cpu_T[0]);
4130 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx);
4131 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
4132 tcg_gen_mov_i32(cpu_T[1], cpu_tmp0);
4134 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4135 case 0x10: /* load word alternate */
4136 #ifndef TARGET_SPARC64
4139 if (!supervisor(dc))
4142 gen_op_check_align_T0_3();
4143 gen_ld_asi(insn, 4, 0);
4145 case 0x11: /* load unsigned byte alternate */
4146 #ifndef TARGET_SPARC64
4149 if (!supervisor(dc))
4152 gen_ld_asi(insn, 1, 0);
4154 case 0x12: /* load unsigned halfword alternate */
4155 #ifndef TARGET_SPARC64
4158 if (!supervisor(dc))
4161 gen_op_check_align_T0_1();
4162 gen_ld_asi(insn, 2, 0);
4164 case 0x13: /* load double word alternate */
4165 #ifndef TARGET_SPARC64
4168 if (!supervisor(dc))
4173 gen_op_check_align_T0_7();
4175 gen_movl_T0_reg(rd + 1);
4177 case 0x19: /* load signed byte alternate */
4178 #ifndef TARGET_SPARC64
4181 if (!supervisor(dc))
4184 gen_ld_asi(insn, 1, 1);
4186 case 0x1a: /* load signed halfword alternate */
4187 #ifndef TARGET_SPARC64
4190 if (!supervisor(dc))
4193 gen_op_check_align_T0_1();
4194 gen_ld_asi(insn, 2, 1);
4196 case 0x1d: /* ldstuba -- XXX: should be atomically */
4197 #ifndef TARGET_SPARC64
4200 if (!supervisor(dc))
4203 gen_ldstub_asi(insn);
4205 case 0x1f: /* swap reg with alt. memory. Also atomically */
4206 #ifndef TARGET_SPARC64
4209 if (!supervisor(dc))
4212 gen_op_check_align_T0_3();
4213 gen_movl_reg_T1(rd);
4217 #ifndef TARGET_SPARC64
4218 case 0x30: /* ldc */
4219 case 0x31: /* ldcsr */
4220 case 0x33: /* lddc */
4224 #ifdef TARGET_SPARC64
4225 case 0x08: /* V9 ldsw */
4226 gen_op_check_align_T0_3();
4227 ABI32_MASK(cpu_T[0]);
4228 tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx);
4230 case 0x0b: /* V9 ldx */
4231 gen_op_check_align_T0_7();
4232 ABI32_MASK(cpu_T[0]);
4233 tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx);
4235 case 0x18: /* V9 ldswa */
4236 gen_op_check_align_T0_3();
4237 gen_ld_asi(insn, 4, 1);
4239 case 0x1b: /* V9 ldxa */
4240 gen_op_check_align_T0_7();
4241 gen_ld_asi(insn, 8, 0);
4243 case 0x2d: /* V9 prefetch, no effect */
4245 case 0x30: /* V9 ldfa */
4246 gen_op_check_align_T0_3();
4247 gen_ldf_asi(insn, 4, rd);
4249 case 0x33: /* V9 lddfa */
4250 gen_op_check_align_T0_3();
4251 gen_ldf_asi(insn, 8, DFPREG(rd));
4253 case 0x3d: /* V9 prefetcha, no effect */
4255 case 0x32: /* V9 ldqfa */
4256 #if defined(CONFIG_USER_ONLY)
4257 gen_op_check_align_T0_3();
4258 gen_ldf_asi(insn, 16, QFPREG(rd));
4267 gen_movl_T1_reg(rd);
4268 #ifdef TARGET_SPARC64
4271 } else if (xop >= 0x20 && xop < 0x24) {
4272 if (gen_trap_ifnofpu(dc))
4275 case 0x20: /* load fpreg */
4276 gen_op_check_align_T0_3();
4278 gen_op_store_FT0_fpr(rd);
4280 case 0x21: /* load fsr */
4281 gen_op_check_align_T0_3();
4283 tcg_gen_helper_0_0(helper_ldfsr);
4285 case 0x22: /* load quad fpreg */
4286 #if defined(CONFIG_USER_ONLY)
4287 gen_op_check_align_T0_7();
4289 gen_op_store_QT0_fpr(QFPREG(rd));
4294 case 0x23: /* load double fpreg */
4295 gen_op_check_align_T0_7();
4297 gen_op_store_DT0_fpr(DFPREG(rd));
4302 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4303 xop == 0xe || xop == 0x1e) {
4304 gen_movl_reg_T1(rd);
4306 case 0x4: /* store word */
4307 gen_op_check_align_T0_3();
4308 ABI32_MASK(cpu_T[0]);
4309 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
4311 case 0x5: /* store byte */
4312 ABI32_MASK(cpu_T[0]);
4313 tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx);
4315 case 0x6: /* store halfword */
4316 gen_op_check_align_T0_1();
4317 ABI32_MASK(cpu_T[0]);
4318 tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx);
4320 case 0x7: /* store double word */
4325 TCGv r_dword, r_low;
4327 gen_op_check_align_T0_7();
4328 r_dword = tcg_temp_new(TCG_TYPE_I64);
4329 r_low = tcg_temp_new(TCG_TYPE_I32);
4330 gen_movl_reg_TN(rd + 1, r_low);
4331 tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
4333 tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx);
4334 tcg_gen_discard_i64(r_dword);
4336 #else /* __i386__ */
4337 gen_op_check_align_T0_7();
4339 gen_movl_reg_T2(rd + 1);
4341 #endif /* __i386__ */
4343 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4344 case 0x14: /* store word alternate */
4345 #ifndef TARGET_SPARC64
4348 if (!supervisor(dc))
4351 gen_op_check_align_T0_3();
4352 gen_st_asi(insn, 4);
4354 case 0x15: /* store byte alternate */
4355 #ifndef TARGET_SPARC64
4358 if (!supervisor(dc))
4361 gen_st_asi(insn, 1);
4363 case 0x16: /* store halfword alternate */
4364 #ifndef TARGET_SPARC64
4367 if (!supervisor(dc))
4370 gen_op_check_align_T0_1();
4371 gen_st_asi(insn, 2);
4373 case 0x17: /* store double word alternate */
4374 #ifndef TARGET_SPARC64
4377 if (!supervisor(dc))
4383 gen_op_check_align_T0_7();
4384 gen_stda_asi(insn, rd);
4388 #ifdef TARGET_SPARC64
4389 case 0x0e: /* V9 stx */
4390 gen_op_check_align_T0_7();
4391 ABI32_MASK(cpu_T[0]);
4392 tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx);
4394 case 0x1e: /* V9 stxa */
4395 gen_op_check_align_T0_7();
4396 gen_st_asi(insn, 8);
4402 } else if (xop > 0x23 && xop < 0x28) {
4403 if (gen_trap_ifnofpu(dc))
4407 gen_op_check_align_T0_3();
4408 gen_op_load_fpr_FT0(rd);
4411 case 0x25: /* stfsr, V9 stxfsr */
4412 #ifdef CONFIG_USER_ONLY
4413 gen_op_check_align_T0_3();
4415 tcg_gen_helper_0_0(helper_stfsr);
4419 #ifdef TARGET_SPARC64
4420 #if defined(CONFIG_USER_ONLY)
4421 /* V9 stqf, store quad fpreg */
4422 gen_op_check_align_T0_7();
4423 gen_op_load_fpr_QT0(QFPREG(rd));
4429 #else /* !TARGET_SPARC64 */
4430 /* stdfq, store floating point queue */
4431 #if defined(CONFIG_USER_ONLY)
4434 if (!supervisor(dc))
4436 if (gen_trap_ifnofpu(dc))
4442 gen_op_check_align_T0_7();
4443 gen_op_load_fpr_DT0(DFPREG(rd));
4449 } else if (xop > 0x33 && xop < 0x3f) {
4451 #ifdef TARGET_SPARC64
4452 case 0x34: /* V9 stfa */
4453 gen_op_check_align_T0_3();
4454 gen_op_load_fpr_FT0(rd);
4455 gen_stf_asi(insn, 4, rd);
4457 case 0x36: /* V9 stqfa */
4458 #if defined(CONFIG_USER_ONLY)
4459 gen_op_check_align_T0_7();
4460 gen_op_load_fpr_QT0(QFPREG(rd));
4461 gen_stf_asi(insn, 16, QFPREG(rd));
4466 case 0x37: /* V9 stdfa */
4467 gen_op_check_align_T0_3();
4468 gen_op_load_fpr_DT0(DFPREG(rd));
4469 gen_stf_asi(insn, 8, DFPREG(rd));
4471 case 0x3c: /* V9 casa */
4472 gen_op_check_align_T0_3();
4473 gen_cas_asi(insn, rd);
4474 gen_movl_T1_reg(rd);
4476 case 0x3e: /* V9 casxa */
4477 gen_op_check_align_T0_7();
4478 gen_casx_asi(insn, rd);
4479 gen_movl_T1_reg(rd);
4482 case 0x34: /* stc */
4483 case 0x35: /* stcsr */
4484 case 0x36: /* stdcq */
4485 case 0x37: /* stdc */
4497 /* default case for non jump instructions */
4498 if (dc->npc == DYNAMIC_PC) {
4499 dc->pc = DYNAMIC_PC;
4501 } else if (dc->npc == JUMP_PC) {
4502 /* we can do a static jump */
4503 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
4507 dc->npc = dc->npc + 4;
4513 gen_op_exception(TT_ILL_INSN);
4516 #if !defined(CONFIG_USER_ONLY)
4519 gen_op_exception(TT_PRIV_INSN);
4524 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4527 #ifndef TARGET_SPARC64
4530 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4535 #ifndef TARGET_SPARC64
4538 gen_op_exception(TT_NCP_INSN);
4544 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
4548 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4549 int spc, CPUSPARCState *env)
4551 target_ulong pc_start, last_pc;
4552 uint16_t *gen_opc_end;
4553 DisasContext dc1, *dc = &dc1;
4556 memset(dc, 0, sizeof(DisasContext));
4561 dc->npc = (target_ulong) tb->cs_base;
4562 dc->mem_idx = cpu_mmu_index(env);
4563 dc->fpu_enabled = cpu_fpu_enabled(env);
4564 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4566 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4569 if (env->nb_breakpoints > 0) {
4570 for(j = 0; j < env->nb_breakpoints; j++) {
4571 if (env->breakpoints[j] == dc->pc) {
4572 if (dc->pc != pc_start)
4574 tcg_gen_helper_0_0(helper_debug);
4583 fprintf(logfile, "Search PC...\n");
4584 j = gen_opc_ptr - gen_opc_buf;
4588 gen_opc_instr_start[lj++] = 0;
4589 gen_opc_pc[lj] = dc->pc;
4590 gen_opc_npc[lj] = dc->npc;
4591 gen_opc_instr_start[lj] = 1;
4595 disas_sparc_insn(dc);
4599 /* if the next PC is different, we abort now */
4600 if (dc->pc != (last_pc + 4))
4602 /* if we reach a page boundary, we stop generation so that the
4603 PC of a TT_TFAULT exception is always in the right page */
4604 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4606 /* if single step mode, we generate only one instruction and
4607 generate an exception */
4608 if (env->singlestep_enabled) {
4613 } while ((gen_opc_ptr < gen_opc_end) &&
4614 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4618 if (dc->pc != DYNAMIC_PC &&
4619 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4620 /* static PC and NPC: we can use direct chaining */
4621 gen_branch(dc, dc->pc, dc->npc);
4623 if (dc->pc != DYNAMIC_PC)
4629 *gen_opc_ptr = INDEX_op_end;
4631 j = gen_opc_ptr - gen_opc_buf;
4634 gen_opc_instr_start[lj++] = 0;
4640 gen_opc_jump_pc[0] = dc->jump_pc[0];
4641 gen_opc_jump_pc[1] = dc->jump_pc[1];
4643 tb->size = last_pc + 4 - pc_start;
4646 if (loglevel & CPU_LOG_TB_IN_ASM) {
4647 fprintf(logfile, "--------------\n");
4648 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4649 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4650 fprintf(logfile, "\n");
4656 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4658 return gen_intermediate_code_internal(tb, 0, env);
4661 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4663 return gen_intermediate_code_internal(tb, 1, env);
4666 void cpu_reset(CPUSPARCState *env)
4671 env->regwptr = env->regbase + (env->cwp * 16);
4672 #if defined(CONFIG_USER_ONLY)
4673 env->user_mode_only = 1;
4674 #ifdef TARGET_SPARC64
4675 env->cleanwin = NWINDOWS - 2;
4676 env->cansave = NWINDOWS - 2;
4677 env->pstate = PS_RMO | PS_PEF | PS_IE;
4678 env->asi = 0x82; // Primary no-fault
4684 #ifdef TARGET_SPARC64
4685 env->pstate = PS_PRIV;
4686 env->hpstate = HS_PRIV;
4687 env->pc = 0x1fff0000000ULL;
4688 env->tsptr = &env->ts[env->tl];
4691 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
4692 env->mmuregs[0] |= env->mmu_bm;
4694 env->npc = env->pc + 4;
4698 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
4701 const sparc_def_t *def;
4704 static const char * const gregnames[8] = {
4705 NULL, // g0 not used
4715 def = cpu_sparc_find_by_name(cpu_model);
4719 env = qemu_mallocz(sizeof(CPUSPARCState));
4723 env->cpu_model_str = cpu_model;
4724 env->version = def->iu_version;
4725 env->fsr = def->fpu_version;
4726 #if !defined(TARGET_SPARC64)
4727 env->mmu_bm = def->mmu_bm;
4728 env->mmu_ctpr_mask = def->mmu_ctpr_mask;
4729 env->mmu_cxr_mask = def->mmu_cxr_mask;
4730 env->mmu_sfsr_mask = def->mmu_sfsr_mask;
4731 env->mmu_trcr_mask = def->mmu_trcr_mask;
4732 env->mmuregs[0] |= def->mmu_version;
4733 cpu_sparc_set_id(env, 0);
4736 /* init various static tables */
4740 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
4741 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4742 cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4743 offsetof(CPUState, regwptr),
4745 //#if TARGET_LONG_BITS > HOST_LONG_BITS
4746 #ifdef TARGET_SPARC64
4747 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4748 TCG_AREG0, offsetof(CPUState, t0), "T0");
4749 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4750 TCG_AREG0, offsetof(CPUState, t1), "T1");
4751 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4752 TCG_AREG0, offsetof(CPUState, t2), "T2");
4753 cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4754 TCG_AREG0, offsetof(CPUState, xcc),
4757 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4758 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4759 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4761 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4762 TCG_AREG0, offsetof(CPUState, cc_src),
4764 cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4765 offsetof(CPUState, cc_src2),
4767 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4768 TCG_AREG0, offsetof(CPUState, cc_dst),
4770 cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4771 TCG_AREG0, offsetof(CPUState, psr),
4773 cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4774 TCG_AREG0, offsetof(CPUState, fsr),
4776 cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4777 TCG_AREG0, offsetof(CPUState, pc),
4779 cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4780 TCG_AREG0, offsetof(CPUState, npc),
4782 for (i = 1; i < 8; i++)
4783 cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4784 offsetof(CPUState, gregs[i]),
4793 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
4795 #if !defined(TARGET_SPARC64)
4796 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
4800 static const sparc_def_t sparc_defs[] = {
4801 #ifdef TARGET_SPARC64
4803 .name = "Fujitsu Sparc64",
4804 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
4805 | (MAXTL << 8) | (NWINDOWS - 1)),
4806 .fpu_version = 0x00000000,
4810 .name = "Fujitsu Sparc64 III",
4811 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
4812 | (MAXTL << 8) | (NWINDOWS - 1)),
4813 .fpu_version = 0x00000000,
4817 .name = "Fujitsu Sparc64 IV",
4818 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
4819 | (MAXTL << 8) | (NWINDOWS - 1)),
4820 .fpu_version = 0x00000000,
4824 .name = "Fujitsu Sparc64 V",
4825 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
4826 | (MAXTL << 8) | (NWINDOWS - 1)),
4827 .fpu_version = 0x00000000,
4831 .name = "TI UltraSparc I",
4832 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
4833 | (MAXTL << 8) | (NWINDOWS - 1)),
4834 .fpu_version = 0x00000000,
4838 .name = "TI UltraSparc II",
4839 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
4840 | (MAXTL << 8) | (NWINDOWS - 1)),
4841 .fpu_version = 0x00000000,
4845 .name = "TI UltraSparc IIi",
4846 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
4847 | (MAXTL << 8) | (NWINDOWS - 1)),
4848 .fpu_version = 0x00000000,
4852 .name = "TI UltraSparc IIe",
4853 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
4854 | (MAXTL << 8) | (NWINDOWS - 1)),
4855 .fpu_version = 0x00000000,
4859 .name = "Sun UltraSparc III",
4860 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
4861 | (MAXTL << 8) | (NWINDOWS - 1)),
4862 .fpu_version = 0x00000000,
4866 .name = "Sun UltraSparc III Cu",
4867 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
4868 | (MAXTL << 8) | (NWINDOWS - 1)),
4869 .fpu_version = 0x00000000,
4873 .name = "Sun UltraSparc IIIi",
4874 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
4875 | (MAXTL << 8) | (NWINDOWS - 1)),
4876 .fpu_version = 0x00000000,
4880 .name = "Sun UltraSparc IV",
4881 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
4882 | (MAXTL << 8) | (NWINDOWS - 1)),
4883 .fpu_version = 0x00000000,
4887 .name = "Sun UltraSparc IV+",
4888 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
4889 | (MAXTL << 8) | (NWINDOWS - 1)),
4890 .fpu_version = 0x00000000,
4894 .name = "Sun UltraSparc IIIi+",
4895 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
4896 | (MAXTL << 8) | (NWINDOWS - 1)),
4897 .fpu_version = 0x00000000,
4901 .name = "NEC UltraSparc I",
4902 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
4903 | (MAXTL << 8) | (NWINDOWS - 1)),
4904 .fpu_version = 0x00000000,
4909 .name = "Fujitsu MB86900",
4910 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
4911 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4912 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
4913 .mmu_bm = 0x00004000,
4914 .mmu_ctpr_mask = 0x007ffff0,
4915 .mmu_cxr_mask = 0x0000003f,
4916 .mmu_sfsr_mask = 0xffffffff,
4917 .mmu_trcr_mask = 0xffffffff,
4920 .name = "Fujitsu MB86904",
4921 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
4922 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4923 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
4924 .mmu_bm = 0x00004000,
4925 .mmu_ctpr_mask = 0x00ffffc0,
4926 .mmu_cxr_mask = 0x000000ff,
4927 .mmu_sfsr_mask = 0x00016fff,
4928 .mmu_trcr_mask = 0x00ffffff,
4931 .name = "Fujitsu MB86907",
4932 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
4933 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4934 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
4935 .mmu_bm = 0x00004000,
4936 .mmu_ctpr_mask = 0xffffffc0,
4937 .mmu_cxr_mask = 0x000000ff,
4938 .mmu_sfsr_mask = 0x00016fff,
4939 .mmu_trcr_mask = 0xffffffff,
4942 .name = "LSI L64811",
4943 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
4944 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
4945 .mmu_version = 0x10 << 24,
4946 .mmu_bm = 0x00004000,
4947 .mmu_ctpr_mask = 0x007ffff0,
4948 .mmu_cxr_mask = 0x0000003f,
4949 .mmu_sfsr_mask = 0xffffffff,
4950 .mmu_trcr_mask = 0xffffffff,
4953 .name = "Cypress CY7C601",
4954 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
4955 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4956 .mmu_version = 0x10 << 24,
4957 .mmu_bm = 0x00004000,
4958 .mmu_ctpr_mask = 0x007ffff0,
4959 .mmu_cxr_mask = 0x0000003f,
4960 .mmu_sfsr_mask = 0xffffffff,
4961 .mmu_trcr_mask = 0xffffffff,
4964 .name = "Cypress CY7C611",
4965 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
4966 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4967 .mmu_version = 0x10 << 24,
4968 .mmu_bm = 0x00004000,
4969 .mmu_ctpr_mask = 0x007ffff0,
4970 .mmu_cxr_mask = 0x0000003f,
4971 .mmu_sfsr_mask = 0xffffffff,
4972 .mmu_trcr_mask = 0xffffffff,
4975 .name = "TI SuperSparc II",
4976 .iu_version = 0x40000000,
4977 .fpu_version = 0 << 17,
4978 .mmu_version = 0x04000000,
4979 .mmu_bm = 0x00002000,
4980 .mmu_ctpr_mask = 0xffffffc0,
4981 .mmu_cxr_mask = 0x0000ffff,
4982 .mmu_sfsr_mask = 0xffffffff,
4983 .mmu_trcr_mask = 0xffffffff,
4986 .name = "TI MicroSparc I",
4987 .iu_version = 0x41000000,
4988 .fpu_version = 4 << 17,
4989 .mmu_version = 0x41000000,
4990 .mmu_bm = 0x00004000,
4991 .mmu_ctpr_mask = 0x007ffff0,
4992 .mmu_cxr_mask = 0x0000003f,
4993 .mmu_sfsr_mask = 0x00016fff,
4994 .mmu_trcr_mask = 0x0000003f,
4997 .name = "TI MicroSparc II",
4998 .iu_version = 0x42000000,
4999 .fpu_version = 4 << 17,
5000 .mmu_version = 0x02000000,
5001 .mmu_bm = 0x00004000,
5002 .mmu_ctpr_mask = 0x00ffffc0,
5003 .mmu_cxr_mask = 0x000000ff,
5004 .mmu_sfsr_mask = 0x00016fff,
5005 .mmu_trcr_mask = 0x00ffffff,
5008 .name = "TI MicroSparc IIep",
5009 .iu_version = 0x42000000,
5010 .fpu_version = 4 << 17,
5011 .mmu_version = 0x04000000,
5012 .mmu_bm = 0x00004000,
5013 .mmu_ctpr_mask = 0x00ffffc0,
5014 .mmu_cxr_mask = 0x000000ff,
5015 .mmu_sfsr_mask = 0x00016bff,
5016 .mmu_trcr_mask = 0x00ffffff,
5019 .name = "TI SuperSparc 51",
5020 .iu_version = 0x43000000,
5021 .fpu_version = 0 << 17,
5022 .mmu_version = 0x04000000,
5023 .mmu_bm = 0x00002000,
5024 .mmu_ctpr_mask = 0xffffffc0,
5025 .mmu_cxr_mask = 0x0000ffff,
5026 .mmu_sfsr_mask = 0xffffffff,
5027 .mmu_trcr_mask = 0xffffffff,
5030 .name = "TI SuperSparc 61",
5031 .iu_version = 0x44000000,
5032 .fpu_version = 0 << 17,
5033 .mmu_version = 0x04000000,
5034 .mmu_bm = 0x00002000,
5035 .mmu_ctpr_mask = 0xffffffc0,
5036 .mmu_cxr_mask = 0x0000ffff,
5037 .mmu_sfsr_mask = 0xffffffff,
5038 .mmu_trcr_mask = 0xffffffff,
5041 .name = "Ross RT625",
5042 .iu_version = 0x1e000000,
5043 .fpu_version = 1 << 17,
5044 .mmu_version = 0x1e000000,
5045 .mmu_bm = 0x00004000,
5046 .mmu_ctpr_mask = 0x007ffff0,
5047 .mmu_cxr_mask = 0x0000003f,
5048 .mmu_sfsr_mask = 0xffffffff,
5049 .mmu_trcr_mask = 0xffffffff,
5052 .name = "Ross RT620",
5053 .iu_version = 0x1f000000,
5054 .fpu_version = 1 << 17,
5055 .mmu_version = 0x1f000000,
5056 .mmu_bm = 0x00004000,
5057 .mmu_ctpr_mask = 0x007ffff0,
5058 .mmu_cxr_mask = 0x0000003f,
5059 .mmu_sfsr_mask = 0xffffffff,
5060 .mmu_trcr_mask = 0xffffffff,
5063 .name = "BIT B5010",
5064 .iu_version = 0x20000000,
5065 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
5066 .mmu_version = 0x20000000,
5067 .mmu_bm = 0x00004000,
5068 .mmu_ctpr_mask = 0x007ffff0,
5069 .mmu_cxr_mask = 0x0000003f,
5070 .mmu_sfsr_mask = 0xffffffff,
5071 .mmu_trcr_mask = 0xffffffff,
5074 .name = "Matsushita MN10501",
5075 .iu_version = 0x50000000,
5076 .fpu_version = 0 << 17,
5077 .mmu_version = 0x50000000,
5078 .mmu_bm = 0x00004000,
5079 .mmu_ctpr_mask = 0x007ffff0,
5080 .mmu_cxr_mask = 0x0000003f,
5081 .mmu_sfsr_mask = 0xffffffff,
5082 .mmu_trcr_mask = 0xffffffff,
5085 .name = "Weitek W8601",
5086 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
5087 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
5088 .mmu_version = 0x10 << 24,
5089 .mmu_bm = 0x00004000,
5090 .mmu_ctpr_mask = 0x007ffff0,
5091 .mmu_cxr_mask = 0x0000003f,
5092 .mmu_sfsr_mask = 0xffffffff,
5093 .mmu_trcr_mask = 0xffffffff,
5097 .iu_version = 0xf2000000,
5098 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
5099 .mmu_version = 0xf2000000,
5100 .mmu_bm = 0x00004000,
5101 .mmu_ctpr_mask = 0x007ffff0,
5102 .mmu_cxr_mask = 0x0000003f,
5103 .mmu_sfsr_mask = 0xffffffff,
5104 .mmu_trcr_mask = 0xffffffff,
5108 .iu_version = 0xf3000000,
5109 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
5110 .mmu_version = 0xf3000000,
5111 .mmu_bm = 0x00004000,
5112 .mmu_ctpr_mask = 0x007ffff0,
5113 .mmu_cxr_mask = 0x0000003f,
5114 .mmu_sfsr_mask = 0xffffffff,
5115 .mmu_trcr_mask = 0xffffffff,
5120 static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name)
5124 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
5125 if (strcasecmp(name, sparc_defs[i].name) == 0) {
5126 return &sparc_defs[i];
5132 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
5136 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
5137 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
5139 sparc_defs[i].iu_version,
5140 sparc_defs[i].fpu_version,
5141 sparc_defs[i].mmu_version);
5145 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
5147 void cpu_dump_state(CPUState *env, FILE *f,
5148 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
5153 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
5154 cpu_fprintf(f, "General Registers:\n");
5155 for (i = 0; i < 4; i++)
5156 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
5157 cpu_fprintf(f, "\n");
5159 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
5160 cpu_fprintf(f, "\nCurrent Register Window:\n");
5161 for (x = 0; x < 3; x++) {
5162 for (i = 0; i < 4; i++)
5163 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
5164 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
5165 env->regwptr[i + x * 8]);
5166 cpu_fprintf(f, "\n");
5168 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
5169 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
5170 env->regwptr[i + x * 8]);
5171 cpu_fprintf(f, "\n");
5173 cpu_fprintf(f, "\nFloating Point Registers:\n");
5174 for (i = 0; i < 32; i++) {
5176 cpu_fprintf(f, "%%f%02d:", i);
5177 cpu_fprintf(f, " %016lf", env->fpr[i]);
5179 cpu_fprintf(f, "\n");
5181 #ifdef TARGET_SPARC64
5182 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
5183 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
5184 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
5185 env->cansave, env->canrestore, env->otherwin, env->wstate,
5186 env->cleanwin, NWINDOWS - 1 - env->cwp);
5188 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
5189 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
5190 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
5191 env->psrs?'S':'-', env->psrps?'P':'-',
5192 env->psret?'E':'-', env->wim);
5194 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
5197 #if defined(CONFIG_USER_ONLY)
5198 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
5204 extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
5205 int *access_index, target_ulong address, int rw,
5208 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
5210 target_phys_addr_t phys_addr;
5211 int prot, access_index;
5213 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
5214 MMU_KERNEL_IDX) != 0)
5215 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
5216 0, MMU_KERNEL_IDX) != 0)
5218 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
5224 void helper_flush(target_ulong addr)
5227 tb_invalidate_page_range(addr, addr + 8);