git.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23    TODO-list:
  24
  25    Rest of V9 instructions, VIS instructions
  26    NPC/PC static optimisations (use JUMP_TB when possible)
  27    Optimize synthetic instructions
  28 */
  29
  30 #include <stdarg.h>
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <string.h>
  34 #include <inttypes.h>
  35
  36 #include "cpu.h"
  37 #include "exec-all.h"
  38 #include "disas.h"
  39 #include "helper.h"
  40 #include "tcg-op.h"
  41
  42 #define DEBUG_DISAS
  43
  44 #define DYNAMIC_PC  1 /* dynamic pc value */
  45 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  46                          according to jump_pc[T2] */
  47
  48 /* global register indexes */
  49 static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
  50 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
  51 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
  52 #ifdef TARGET_SPARC64
  53 static TCGv cpu_xcc;
  54 #endif
  55 /* local register indexes (only used inside old micro ops) */
  56 static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
  57
  58 typedef struct DisasContext {
  59     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  60     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  61     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  62     int is_br;
  63     int mem_idx;
  64     int fpu_enabled;
  65     struct TranslationBlock *tb;
  66 } DisasContext;
  67
  68 extern FILE *logfile;
  69 extern int loglevel;
  70
  71 // This function uses non-native bit order
  72 #define GET_FIELD(X, FROM, TO) \
  73   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  74
  75 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  76 #define GET_FIELD_SP(X, FROM, TO) \
  77     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  78
  79 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  80 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
  81
  82 #ifdef TARGET_SPARC64
  83 #define FFPREG(r) (r)
  84 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
  85 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
  86 #else
  87 #define FFPREG(r) (r)
  88 #define DFPREG(r) (r & 0x1e)
  89 #define QFPREG(r) (r & 0x1c)
  90 #endif
  91
  92 static int sign_extend(int x, int len)
  93 {
  94     len = 32 - len;
  95     return (x << len) >> len;
  96 }
  97
  98 #define IS_IMM (insn & (1<<13))
  99
 100 /* floating point registers moves */
 101 static void gen_op_load_fpr_FT0(unsigned int src)
 102 {
 103     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 104     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
 105 }
 106
 107 static void gen_op_load_fpr_FT1(unsigned int src)
 108 {
 109     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 110     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
 111 }
 112
 113 static void gen_op_store_FT0_fpr(unsigned int dst)
 114 {
 115     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
 116     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 117 }
 118
 119 static void gen_op_load_fpr_DT0(unsigned int src)
 120 {
 121     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 122     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
 123     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 124     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
 125 }
 126
 127 static void gen_op_load_fpr_DT1(unsigned int src)
 128 {
 129     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 130     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
 131     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 132     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
 133 }
 134
 135 static void gen_op_store_DT0_fpr(unsigned int dst)
 136 {
 137     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
 138     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 139     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
 140     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 141 }
 142
 143 #ifdef CONFIG_USER_ONLY
 144 static void gen_op_load_fpr_QT0(unsigned int src)
 145 {
 146     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 147     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
 148     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 149     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
 150     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 151     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
 152     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 153     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
 154 }
 155
 156 static void gen_op_load_fpr_QT1(unsigned int src)
 157 {
 158     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 159     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
 160     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 161     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
 162     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 163     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
 164     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 165     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
 166 }
 167
 168 static void gen_op_store_QT0_fpr(unsigned int dst)
 169 {
 170     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
 171     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 172     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
 173     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 174     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
 175     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
 176     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
 177     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
 178 }
 179 #endif
 180
 181 /* moves */
 182 #ifdef CONFIG_USER_ONLY
 183 #define supervisor(dc) 0
 184 #ifdef TARGET_SPARC64
 185 #define hypervisor(dc) 0
 186 #endif
 187 #define gen_op_ldst(name)        gen_op_##name##_raw()
 188 #else
 189 #define supervisor(dc) (dc->mem_idx >= 1)
 190 #ifdef TARGET_SPARC64
 191 #define hypervisor(dc) (dc->mem_idx == 2)
 192 #define OP_LD_TABLE(width)                                              \
 193     static GenOpFunc * const gen_op_##width[] = {                       \
 194         &gen_op_##width##_user,                                         \
 195         &gen_op_##width##_kernel,                                       \
 196         &gen_op_##width##_hypv,                                         \
 197     };
 198 #else
 199 #define OP_LD_TABLE(width)                                              \
 200     static GenOpFunc * const gen_op_##width[] = {                       \
 201         &gen_op_##width##_user,                                         \
 202         &gen_op_##width##_kernel,                                       \
 203     };
 204 #endif
 205 #define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
 206 #endif
 207
 208 #ifndef CONFIG_USER_ONLY
 209 #ifdef __i386__
 210 OP_LD_TABLE(std);
 211 #endif /* __i386__ */
 212 OP_LD_TABLE(stdf);
 213 OP_LD_TABLE(lddf);
 214 #endif
 215
 216 #ifdef TARGET_ABI32
 217 #define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
 218 #else
 219 #define ABI32_MASK(addr)
 220 #endif
 221
 222 static inline void gen_movl_reg_TN(int reg, TCGv tn)
 223 {
 224     if (reg == 0)
 225         tcg_gen_movi_tl(tn, 0);
 226     else if (reg < 8)
 227         tcg_gen_mov_tl(tn, cpu_gregs[reg]);
 228     else {
 229         tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 230     }
 231 }
 232
 233 static inline void gen_movl_TN_reg(int reg, TCGv tn)
 234 {
 235     if (reg == 0)
 236         return;
 237     else if (reg < 8)
 238         tcg_gen_mov_tl(cpu_gregs[reg], tn);
 239     else {
 240         tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 241     }
 242 }
 243
 244 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 245                                target_ulong pc, target_ulong npc)
 246 {
 247     TranslationBlock *tb;
 248
 249     tb = s->tb;
 250     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 251         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 252         /* jump to same page: we can use a direct jump */
 253         tcg_gen_goto_tb(tb_num);
 254         tcg_gen_movi_tl(cpu_pc, pc);
 255         tcg_gen_movi_tl(cpu_npc, npc);
 256         tcg_gen_exit_tb((long)tb + tb_num);
 257     } else {
 258         /* jump to another page: currently not optimized */
 259         tcg_gen_movi_tl(cpu_pc, pc);
 260         tcg_gen_movi_tl(cpu_npc, npc);
 261         tcg_gen_exit_tb(0);
 262     }
 263 }
 264
 265 // XXX suboptimal
 266 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
 267 {
 268     tcg_gen_extu_i32_tl(reg, src);
 269     tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
 270     tcg_gen_andi_tl(reg, reg, 0x1);
 271 }
 272
 273 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
 274 {
 275     tcg_gen_extu_i32_tl(reg, src);
 276     tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
 277     tcg_gen_andi_tl(reg, reg, 0x1);
 278 }
 279
 280 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
 281 {
 282     tcg_gen_extu_i32_tl(reg, src);
 283     tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
 284     tcg_gen_andi_tl(reg, reg, 0x1);
 285 }
 286
 287 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
 288 {
 289     tcg_gen_extu_i32_tl(reg, src);
 290     tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
 291     tcg_gen_andi_tl(reg, reg, 0x1);
 292 }
 293
 294 static inline void gen_cc_clear_icc(void)
 295 {
 296     tcg_gen_movi_i32(cpu_psr, 0);
 297 }
 298
 299 #ifdef TARGET_SPARC64
 300 static inline void gen_cc_clear_xcc(void)
 301 {
 302     tcg_gen_movi_i32(cpu_xcc, 0);
 303 }
 304 #endif
 305
 306 /* old op:
 307     if (!T0)
 308         env->psr |= PSR_ZERO;
 309     if ((int32_t) T0 < 0)
 310         env->psr |= PSR_NEG;
 311 */
 312 static inline void gen_cc_NZ_icc(TCGv dst)
 313 {
 314     TCGv r_temp;
 315     int l1, l2;
 316
 317     l1 = gen_new_label();
 318     l2 = gen_new_label();
 319     r_temp = tcg_temp_new(TCG_TYPE_TL);
 320     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 321     tcg_gen_brcond_tl(TCG_COND_NE, r_temp, tcg_const_tl(0), l1);
 322     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
 323     gen_set_label(l1);
 324     tcg_gen_ext_i32_tl(r_temp, dst);
 325     tcg_gen_brcond_tl(TCG_COND_GE, r_temp, tcg_const_tl(0), l2);
 326     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
 327     gen_set_label(l2);
 328 }
 329
 330 #ifdef TARGET_SPARC64
 331 static inline void gen_cc_NZ_xcc(TCGv dst)
 332 {
 333     int l1, l2;
 334
 335     l1 = gen_new_label();
 336     l2 = gen_new_label();
 337     tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l1);
 338     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
 339     gen_set_label(l1);
 340     tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l2);
 341     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
 342     gen_set_label(l2);
 343 }
 344 #endif
 345
 346 /* old op:
 347     if (T0 < src1)
 348         env->psr |= PSR_CARRY;
 349 */
 350 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
 351 {
 352     TCGv r_temp;
 353     int l1;
 354
 355     l1 = gen_new_label();
 356     r_temp = tcg_temp_new(TCG_TYPE_TL);
 357     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 358     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 359     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 360     gen_set_label(l1);
 361 }
 362
 363 #ifdef TARGET_SPARC64
 364 static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
 365 {
 366     int l1;
 367
 368     l1 = gen_new_label();
 369     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 370     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 371     gen_set_label(l1);
 372 }
 373 #endif
 374
 375 /* old op:
 376     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
 377         env->psr |= PSR_OVF;
 378 */
 379 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
 380 {
 381     TCGv r_temp;
 382     int l1;
 383
 384     l1 = gen_new_label();
 385
 386     r_temp = tcg_temp_new(TCG_TYPE_TL);
 387     tcg_gen_xor_tl(r_temp, src1, src2);
 388     tcg_gen_xori_tl(r_temp, r_temp, -1);
 389     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 390     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 391     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 392     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 393     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 394     gen_set_label(l1);
 395 }
 396
 397 #ifdef TARGET_SPARC64
 398 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
 399 {
 400     TCGv r_temp;
 401     int l1;
 402
 403     l1 = gen_new_label();
 404
 405     r_temp = tcg_temp_new(TCG_TYPE_TL);
 406     tcg_gen_xor_tl(r_temp, src1, src2);
 407     tcg_gen_xori_tl(r_temp, r_temp, -1);
 408     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 409     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 410     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 411     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 412     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
 413     gen_set_label(l1);
 414 }
 415 #endif
 416
 417 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
 418 {
 419     TCGv r_temp;
 420     int l1;
 421
 422     l1 = gen_new_label();
 423
 424     r_temp = tcg_temp_new(TCG_TYPE_TL);
 425     tcg_gen_xor_tl(r_temp, src1, src2);
 426     tcg_gen_xori_tl(r_temp, r_temp, -1);
 427     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 428     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 429     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 430     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 431     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 432     gen_set_label(l1);
 433 }
 434
 435 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
 436 {
 437     int l1;
 438
 439     l1 = gen_new_label();
 440     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 441     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 442     tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
 443     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 444     gen_set_label(l1);
 445 }
 446
 447 static inline void gen_tag_tv(TCGv src1, TCGv src2)
 448 {
 449     int l1;
 450
 451     l1 = gen_new_label();
 452     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 453     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 454     tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
 455     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 456     gen_set_label(l1);
 457 }
 458
 459 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
 460 {
 461     tcg_gen_mov_tl(cpu_cc_src, src1);
 462     tcg_gen_add_tl(dst, src1, src2);
 463     gen_cc_clear_icc();
 464     gen_cc_NZ_icc(dst);
 465     gen_cc_C_add_icc(dst, cpu_cc_src);
 466     gen_cc_V_add_icc(dst, cpu_cc_src, src2);
 467 #ifdef TARGET_SPARC64
 468     gen_cc_clear_xcc();
 469     gen_cc_NZ_xcc(dst);
 470     gen_cc_C_add_xcc(dst, cpu_cc_src);
 471     gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
 472 #endif
 473 }
 474
 475 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
 476 {
 477     tcg_gen_mov_tl(cpu_cc_src, src1);
 478     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 479     tcg_gen_add_tl(dst, src1, cpu_tmp0);
 480     gen_cc_clear_icc();
 481     gen_cc_C_add_icc(dst, cpu_cc_src);
 482 #ifdef TARGET_SPARC64
 483     gen_cc_clear_xcc();
 484     gen_cc_C_add_xcc(dst, cpu_cc_src);
 485 #endif
 486     tcg_gen_add_tl(dst, dst, src2);
 487     gen_cc_NZ_icc(dst);
 488     gen_cc_C_add_icc(dst, cpu_cc_src);
 489     gen_cc_V_add_icc(dst, cpu_cc_src, src2);
 490 #ifdef TARGET_SPARC64
 491     gen_cc_NZ_xcc(dst);
 492     gen_cc_C_add_xcc(dst, cpu_cc_src);
 493     gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
 494 #endif
 495 }
 496
 497 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
 498 {
 499     tcg_gen_mov_tl(cpu_cc_src, src1);
 500     tcg_gen_add_tl(dst, src1, src2);
 501     gen_cc_clear_icc();
 502     gen_cc_NZ_icc(dst);
 503     gen_cc_C_add_icc(dst, cpu_cc_src);
 504     gen_cc_V_add_icc(dst, cpu_cc_src, src2);
 505     gen_cc_V_tag(cpu_cc_src, src2);
 506 #ifdef TARGET_SPARC64
 507     gen_cc_clear_xcc();
 508     gen_cc_NZ_xcc(dst);
 509     gen_cc_C_add_xcc(dst, cpu_cc_src);
 510     gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
 511 #endif
 512 }
 513
 514 static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
 515 {
 516     gen_tag_tv(src1, src2);
 517     tcg_gen_mov_tl(cpu_cc_src, src1);
 518     tcg_gen_add_tl(dst, src1, src2);
 519     gen_add_tv(dst, cpu_cc_src, src2);
 520     gen_cc_clear_icc();
 521     gen_cc_NZ_icc(dst);
 522     gen_cc_C_add_icc(dst, cpu_cc_src);
 523 #ifdef TARGET_SPARC64
 524     gen_cc_clear_xcc();
 525     gen_cc_NZ_xcc(dst);
 526     gen_cc_C_add_xcc(dst, cpu_cc_src);
 527     gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
 528 #endif
 529 }
 530
 531 /* old op:
 532     if (src1 < T1)
 533         env->psr |= PSR_CARRY;
 534 */
 535 static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
 536 {
 537     TCGv r_temp1, r_temp2;
 538     int l1;
 539
 540     l1 = gen_new_label();
 541     r_temp1 = tcg_temp_new(TCG_TYPE_TL);
 542     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 543     tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
 544     tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
 545     tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
 546     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 547     gen_set_label(l1);
 548 }
 549
 550 #ifdef TARGET_SPARC64
 551 static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
 552 {
 553     int l1;
 554
 555     l1 = gen_new_label();
 556     tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
 557     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 558     gen_set_label(l1);
 559 }
 560 #endif
 561
 562 /* old op:
 563     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
 564         env->psr |= PSR_OVF;
 565 */
 566 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
 567 {
 568     TCGv r_temp;
 569     int l1;
 570
 571     l1 = gen_new_label();
 572
 573     r_temp = tcg_temp_new(TCG_TYPE_TL);
 574     tcg_gen_xor_tl(r_temp, src1, src2);
 575     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 576     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 577     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 578     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 579     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 580     gen_set_label(l1);
 581 }
 582
 583 #ifdef TARGET_SPARC64
 584 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
 585 {
 586     TCGv r_temp;
 587     int l1;
 588
 589     l1 = gen_new_label();
 590
 591     r_temp = tcg_temp_new(TCG_TYPE_TL);
 592     tcg_gen_xor_tl(r_temp, src1, src2);
 593     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 594     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 595     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 596     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 597     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
 598     gen_set_label(l1);
 599 }
 600 #endif
 601
 602 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
 603 {
 604     TCGv r_temp;
 605     int l1;
 606
 607     l1 = gen_new_label();
 608
 609     r_temp = tcg_temp_new(TCG_TYPE_TL);
 610     tcg_gen_xor_tl(r_temp, src1, src2);
 611     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 612     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 613     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 614     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 615     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 616     gen_set_label(l1);
 617 }
 618
 619 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
 620 {
 621     tcg_gen_mov_tl(cpu_cc_src, src1);
 622     tcg_gen_sub_tl(dst, src1, src2);
 623     gen_cc_clear_icc();
 624     gen_cc_NZ_icc(dst);
 625     gen_cc_C_sub_icc(cpu_cc_src, src2);
 626     gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
 627 #ifdef TARGET_SPARC64
 628     gen_cc_clear_xcc();
 629     gen_cc_NZ_xcc(dst);
 630     gen_cc_C_sub_xcc(cpu_cc_src, src2);
 631     gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
 632 #endif
 633 }
 634
 635 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
 636 {
 637     tcg_gen_mov_tl(cpu_cc_src, src1);
 638     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 639     tcg_gen_sub_tl(dst, src1, cpu_tmp0);
 640     gen_cc_clear_icc();
 641     gen_cc_C_sub_icc(dst, cpu_cc_src);
 642 #ifdef TARGET_SPARC64
 643     gen_cc_clear_xcc();
 644     gen_cc_C_sub_xcc(dst, cpu_cc_src);
 645 #endif
 646     tcg_gen_sub_tl(dst, dst, src2);
 647     gen_cc_NZ_icc(dst);
 648     gen_cc_C_sub_icc(dst, cpu_cc_src);
 649     gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
 650 #ifdef TARGET_SPARC64
 651     gen_cc_NZ_xcc(dst);
 652     gen_cc_C_sub_xcc(dst, cpu_cc_src);
 653     gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
 654 #endif
 655 }
 656
 657 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
 658 {
 659     tcg_gen_mov_tl(cpu_cc_src, src1);
 660     tcg_gen_sub_tl(dst, src1, src2);
 661     gen_cc_clear_icc();
 662     gen_cc_NZ_icc(dst);
 663     gen_cc_C_sub_icc(cpu_cc_src, src2);
 664     gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
 665     gen_cc_V_tag(cpu_cc_src, src2);
 666 #ifdef TARGET_SPARC64
 667     gen_cc_clear_xcc();
 668     gen_cc_NZ_xcc(dst);
 669     gen_cc_C_sub_xcc(cpu_cc_src, src2);
 670     gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
 671 #endif
 672 }
 673
 674 static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
 675 {
 676     gen_tag_tv(src1, src2);
 677     tcg_gen_mov_tl(cpu_cc_src, src1);
 678     tcg_gen_sub_tl(dst, src1, src2);
 679     gen_sub_tv(dst, cpu_cc_src, src2);
 680     gen_cc_clear_icc();
 681     gen_cc_NZ_icc(dst);
 682     gen_cc_C_sub_icc(cpu_cc_src, src2);
 683 #ifdef TARGET_SPARC64
 684     gen_cc_clear_xcc();
 685     gen_cc_NZ_xcc(dst);
 686     gen_cc_C_sub_xcc(cpu_cc_src, src2);
 687     gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
 688 #endif
 689 }
 690
 691 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
 692 {
 693     TCGv r_temp, r_temp2;
 694     int l1, l2;
 695
 696     l1 = gen_new_label();
 697     l2 = gen_new_label();
 698     r_temp = tcg_temp_new(TCG_TYPE_TL);
 699     r_temp2 = tcg_temp_new(TCG_TYPE_I32);
 700
 701     /* old op:
 702     if (!(env->y & 1))
 703         T1 = 0;
 704     */
 705     tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 706     tcg_gen_trunc_tl_i32(r_temp2, r_temp);
 707     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 708     tcg_gen_brcond_i32(TCG_COND_EQ, r_temp2, tcg_const_i32(0), l1);
 709     tcg_gen_mov_tl(cpu_cc_src2, src2);
 710     tcg_gen_br(l2);
 711     gen_set_label(l1);
 712     tcg_gen_movi_tl(cpu_cc_src2, 0);
 713     gen_set_label(l2);
 714
 715     // b2 = T0 & 1;
 716     // env->y = (b2 << 31) | (env->y >> 1);
 717     tcg_gen_trunc_tl_i32(r_temp2, src1);
 718     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 719     tcg_gen_shli_i32(r_temp2, r_temp2, 31);
 720     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 721     tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
 722     tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
 723     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 724
 725     // b1 = N ^ V;
 726     gen_mov_reg_N(cpu_tmp0, cpu_psr);
 727     gen_mov_reg_V(r_temp, cpu_psr);
 728     tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
 729
 730     // T0 = (b1 << 31) | (T0 >> 1);
 731     // src1 = T0;
 732     tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
 733     tcg_gen_shri_tl(cpu_cc_src, src1, 1);
 734     tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
 735
 736     /* do addition and update flags */
 737     tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
 738
 739     gen_cc_clear_icc();
 740     gen_cc_NZ_icc(dst);
 741     gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2);
 742     gen_cc_C_add_icc(dst, cpu_cc_src);
 743 }
 744
 745 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
 746 {
 747     TCGv r_temp, r_temp2;
 748
 749     r_temp = tcg_temp_new(TCG_TYPE_I64);
 750     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 751
 752     tcg_gen_extu_tl_i64(r_temp, src2);
 753     tcg_gen_extu_tl_i64(r_temp2, src1);
 754     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 755
 756     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 757     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 758     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 759 #ifdef TARGET_SPARC64
 760     tcg_gen_mov_i64(dst, r_temp2);
 761 #else
 762     tcg_gen_trunc_i64_tl(dst, r_temp2);
 763 #endif
 764 }
 765
 766 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
 767 {
 768     TCGv r_temp, r_temp2;
 769
 770     r_temp = tcg_temp_new(TCG_TYPE_I64);
 771     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 772
 773     tcg_gen_ext_tl_i64(r_temp, src2);
 774     tcg_gen_ext_tl_i64(r_temp2, src1);
 775     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 776
 777     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 778     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 779     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 780 #ifdef TARGET_SPARC64
 781     tcg_gen_mov_i64(dst, r_temp2);
 782 #else
 783     tcg_gen_trunc_i64_tl(dst, r_temp2);
 784 #endif
 785 }
 786
 787 #ifdef TARGET_SPARC64
 788 static inline void gen_trap_ifdivzero_tl(TCGv divisor)
 789 {
 790     int l1;
 791
 792     l1 = gen_new_label();
 793     tcg_gen_brcond_tl(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
 794     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO));
 795     gen_set_label(l1);
 796 }
 797
 798 static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
 799 {
 800     int l1, l2;
 801
 802     l1 = gen_new_label();
 803     l2 = gen_new_label();
 804     gen_trap_ifdivzero_tl(src2);
 805     tcg_gen_brcond_tl(TCG_COND_NE, src1, tcg_const_tl(INT64_MIN), l1);
 806     tcg_gen_brcond_tl(TCG_COND_NE, src2, tcg_const_tl(-1), l1);
 807     tcg_gen_movi_i64(dst, INT64_MIN);
 808     tcg_gen_br(l2);
 809     gen_set_label(l1);
 810     tcg_gen_div_i64(dst, src1, src2);
 811     gen_set_label(l2);
 812 }
 813 #endif
 814
 815 static inline void gen_op_div_cc(TCGv dst)
 816 {
 817     int l1;
 818
 819     gen_cc_clear_icc();
 820     gen_cc_NZ_icc(dst);
 821     l1 = gen_new_label();
 822     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
 823     tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
 824     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 825     gen_set_label(l1);
 826 }
 827
 828 static inline void gen_op_logic_cc(TCGv dst)
 829 {
 830     gen_cc_clear_icc();
 831     gen_cc_NZ_icc(dst);
 832 #ifdef TARGET_SPARC64
 833     gen_cc_clear_xcc();
 834     gen_cc_NZ_xcc(dst);
 835 #endif
 836 }
 837
 838 // 1
 839 static inline void gen_op_eval_ba(TCGv dst)
 840 {
 841     tcg_gen_movi_tl(dst, 1);
 842 }
 843
 844 // Z
 845 static inline void gen_op_eval_be(TCGv dst, TCGv src)
 846 {
 847     gen_mov_reg_Z(dst, src);
 848 }
 849
 850 // Z | (N ^ V)
 851 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
 852 {
 853     gen_mov_reg_N(cpu_tmp0, src);
 854     gen_mov_reg_V(dst, src);
 855     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 856     gen_mov_reg_Z(cpu_tmp0, src);
 857     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 858 }
 859
 860 // N ^ V
 861 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
 862 {
 863     gen_mov_reg_V(cpu_tmp0, src);
 864     gen_mov_reg_N(dst, src);
 865     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 866 }
 867
 868 // C | Z
 869 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
 870 {
 871     gen_mov_reg_Z(cpu_tmp0, src);
 872     gen_mov_reg_C(dst, src);
 873     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 874 }
 875
 876 // C
 877 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
 878 {
 879     gen_mov_reg_C(dst, src);
 880 }
 881
 882 // V
 883 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
 884 {
 885     gen_mov_reg_V(dst, src);
 886 }
 887
 888 // 0
 889 static inline void gen_op_eval_bn(TCGv dst)
 890 {
 891     tcg_gen_movi_tl(dst, 0);
 892 }
 893
 894 // N
 895 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
 896 {
 897     gen_mov_reg_N(dst, src);
 898 }
 899
 900 // !Z
 901 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
 902 {
 903     gen_mov_reg_Z(dst, src);
 904     tcg_gen_xori_tl(dst, dst, 0x1);
 905 }
 906
 907 // !(Z | (N ^ V))
 908 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
 909 {
 910     gen_mov_reg_N(cpu_tmp0, src);
 911     gen_mov_reg_V(dst, src);
 912     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 913     gen_mov_reg_Z(cpu_tmp0, src);
 914     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 915     tcg_gen_xori_tl(dst, dst, 0x1);
 916 }
 917
 918 // !(N ^ V)
 919 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
 920 {
 921     gen_mov_reg_V(cpu_tmp0, src);
 922     gen_mov_reg_N(dst, src);
 923     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 924     tcg_gen_xori_tl(dst, dst, 0x1);
 925 }
 926
 927 // !(C | Z)
 928 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
 929 {
 930     gen_mov_reg_Z(cpu_tmp0, src);
 931     gen_mov_reg_C(dst, src);
 932     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 933     tcg_gen_xori_tl(dst, dst, 0x1);
 934 }
 935
 936 // !C
 937 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
 938 {
 939     gen_mov_reg_C(dst, src);
 940     tcg_gen_xori_tl(dst, dst, 0x1);
 941 }
 942
 943 // !N
 944 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
 945 {
 946     gen_mov_reg_N(dst, src);
 947     tcg_gen_xori_tl(dst, dst, 0x1);
 948 }
 949
 950 // !V
 951 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
 952 {
 953     gen_mov_reg_V(dst, src);
 954     tcg_gen_xori_tl(dst, dst, 0x1);
 955 }
 956
 957 /*
 958   FPSR bit field FCC1 | FCC0:
 959    0 =
 960    1 <
 961    2 >
 962    3 unordered
 963 */
 964 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
 965                                     unsigned int fcc_offset)
 966 {
 967     tcg_gen_extu_i32_tl(reg, src);
 968     tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
 969     tcg_gen_andi_tl(reg, reg, 0x1);
 970 }
 971
 972 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
 973                                     unsigned int fcc_offset)
 974 {
 975     tcg_gen_extu_i32_tl(reg, src);
 976     tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
 977     tcg_gen_andi_tl(reg, reg, 0x1);
 978 }
 979
 980 // !0: FCC0 | FCC1
 981 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
 982                                     unsigned int fcc_offset)
 983 {
 984     gen_mov_reg_FCC0(dst, src, fcc_offset);
 985     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
 986     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 987 }
 988
 989 // 1 or 2: FCC0 ^ FCC1
 990 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
 991                                     unsigned int fcc_offset)
 992 {
 993     gen_mov_reg_FCC0(dst, src, fcc_offset);
 994     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
 995     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 996 }
 997
 998 // 1 or 3: FCC0
 999 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1000                                     unsigned int fcc_offset)
1001 {
1002     gen_mov_reg_FCC0(dst, src, fcc_offset);
1003 }
1004
1005 // 1: FCC0 & !FCC1
1006 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1007                                     unsigned int fcc_offset)
1008 {
1009     gen_mov_reg_FCC0(dst, src, fcc_offset);
1010     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1011     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1012     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1013 }
1014
1015 // 2 or 3: FCC1
1016 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1017                                     unsigned int fcc_offset)
1018 {
1019     gen_mov_reg_FCC1(dst, src, fcc_offset);
1020 }
1021
1022 // 2: !FCC0 & FCC1
1023 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1024                                     unsigned int fcc_offset)
1025 {
1026     gen_mov_reg_FCC0(dst, src, fcc_offset);
1027     tcg_gen_xori_tl(dst, dst, 0x1);
1028     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1029     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1030 }
1031
1032 // 3: FCC0 & FCC1
1033 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1034                                     unsigned int fcc_offset)
1035 {
1036     gen_mov_reg_FCC0(dst, src, fcc_offset);
1037     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1038     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1039 }
1040
1041 // 0: !(FCC0 | FCC1)
1042 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1043                                     unsigned int fcc_offset)
1044 {
1045     gen_mov_reg_FCC0(dst, src, fcc_offset);
1046     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1047     tcg_gen_or_tl(dst, dst, cpu_tmp0);
1048     tcg_gen_xori_tl(dst, dst, 0x1);
1049 }
1050
1051 // 0 or 3: !(FCC0 ^ FCC1)
1052 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1053                                     unsigned int fcc_offset)
1054 {
1055     gen_mov_reg_FCC0(dst, src, fcc_offset);
1056     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1057     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1058     tcg_gen_xori_tl(dst, dst, 0x1);
1059 }
1060
1061 // 0 or 2: !FCC0
1062 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1063                                     unsigned int fcc_offset)
1064 {
1065     gen_mov_reg_FCC0(dst, src, fcc_offset);
1066     tcg_gen_xori_tl(dst, dst, 0x1);
1067 }
1068
1069 // !1: !(FCC0 & !FCC1)
1070 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1071                                     unsigned int fcc_offset)
1072 {
1073     gen_mov_reg_FCC0(dst, src, fcc_offset);
1074     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1075     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1076     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1077     tcg_gen_xori_tl(dst, dst, 0x1);
1078 }
1079
1080 // 0 or 1: !FCC1
1081 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1082                                     unsigned int fcc_offset)
1083 {
1084     gen_mov_reg_FCC1(dst, src, fcc_offset);
1085     tcg_gen_xori_tl(dst, dst, 0x1);
1086 }
1087
1088 // !2: !(!FCC0 & FCC1)
1089 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1090                                     unsigned int fcc_offset)
1091 {
1092     gen_mov_reg_FCC0(dst, src, fcc_offset);
1093     tcg_gen_xori_tl(dst, dst, 0x1);
1094     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1095     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1096     tcg_gen_xori_tl(dst, dst, 0x1);
1097 }
1098
1099 // !3: !(FCC0 & FCC1)
1100 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1101                                     unsigned int fcc_offset)
1102 {
1103     gen_mov_reg_FCC0(dst, src, fcc_offset);
1104     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1105     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1106     tcg_gen_xori_tl(dst, dst, 0x1);
1107 }
1108
1109 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1110                                target_ulong pc2, TCGv r_cond)
1111 {
1112     int l1;
1113
1114     l1 = gen_new_label();
1115
1116     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1117
1118     gen_goto_tb(dc, 0, pc1, pc1 + 4);
1119
1120     gen_set_label(l1);
1121     gen_goto_tb(dc, 1, pc2, pc2 + 4);
1122 }
1123
1124 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1125                                 target_ulong pc2, TCGv r_cond)
1126 {
1127     int l1;
1128
1129     l1 = gen_new_label();
1130
1131     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1132
1133     gen_goto_tb(dc, 0, pc2, pc1);
1134
1135     gen_set_label(l1);
1136     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1137 }
1138
1139 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1140                                       TCGv r_cond)
1141 {
1142     int l1, l2;
1143
1144     l1 = gen_new_label();
1145     l2 = gen_new_label();
1146
1147     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1148
1149     tcg_gen_movi_tl(cpu_npc, npc1);
1150     tcg_gen_br(l2);
1151
1152     gen_set_label(l1);
1153     tcg_gen_movi_tl(cpu_npc, npc2);
1154     gen_set_label(l2);
1155 }
1156
1157 /* call this function before using the condition register as it may
1158    have been set for a jump */
1159 static inline void flush_cond(DisasContext *dc, TCGv cond)
1160 {
1161     if (dc->npc == JUMP_PC) {
1162         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1163         dc->npc = DYNAMIC_PC;
1164     }
1165 }
1166
1167 static inline void save_npc(DisasContext *dc, TCGv cond)
1168 {
1169     if (dc->npc == JUMP_PC) {
1170         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1171         dc->npc = DYNAMIC_PC;
1172     } else if (dc->npc != DYNAMIC_PC) {
1173         tcg_gen_movi_tl(cpu_npc, dc->npc);
1174     }
1175 }
1176
1177 static inline void save_state(DisasContext *dc, TCGv cond)
1178 {
1179     tcg_gen_movi_tl(cpu_pc, dc->pc);
1180     save_npc(dc, cond);
1181 }
1182
1183 static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1184 {
1185     if (dc->npc == JUMP_PC) {
1186         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1187         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1188         dc->pc = DYNAMIC_PC;
1189     } else if (dc->npc == DYNAMIC_PC) {
1190         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1191         dc->pc = DYNAMIC_PC;
1192     } else {
1193         dc->pc = dc->npc;
1194     }
1195 }
1196
1197 static inline void gen_op_next_insn(void)
1198 {
1199     tcg_gen_mov_tl(cpu_pc, cpu_npc);
1200     tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1201 }
1202
1203 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1204 {
1205     TCGv r_src;
1206
1207 #ifdef TARGET_SPARC64
1208     if (cc)
1209         r_src = cpu_xcc;
1210     else
1211         r_src = cpu_psr;
1212 #else
1213     r_src = cpu_psr;
1214 #endif
1215     switch (cond) {
1216     case 0x0:
1217         gen_op_eval_bn(r_dst);
1218         break;
1219     case 0x1:
1220         gen_op_eval_be(r_dst, r_src);
1221         break;
1222     case 0x2:
1223         gen_op_eval_ble(r_dst, r_src);
1224         break;
1225     case 0x3:
1226         gen_op_eval_bl(r_dst, r_src);
1227         break;
1228     case 0x4:
1229         gen_op_eval_bleu(r_dst, r_src);
1230         break;
1231     case 0x5:
1232         gen_op_eval_bcs(r_dst, r_src);
1233         break;
1234     case 0x6:
1235         gen_op_eval_bneg(r_dst, r_src);
1236         break;
1237     case 0x7:
1238         gen_op_eval_bvs(r_dst, r_src);
1239         break;
1240     case 0x8:
1241         gen_op_eval_ba(r_dst);
1242         break;
1243     case 0x9:
1244         gen_op_eval_bne(r_dst, r_src);
1245         break;
1246     case 0xa:
1247         gen_op_eval_bg(r_dst, r_src);
1248         break;
1249     case 0xb:
1250         gen_op_eval_bge(r_dst, r_src);
1251         break;
1252     case 0xc:
1253         gen_op_eval_bgu(r_dst, r_src);
1254         break;
1255     case 0xd:
1256         gen_op_eval_bcc(r_dst, r_src);
1257         break;
1258     case 0xe:
1259         gen_op_eval_bpos(r_dst, r_src);
1260         break;
1261     case 0xf:
1262         gen_op_eval_bvc(r_dst, r_src);
1263         break;
1264     }
1265 }
1266
1267 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1268 {
1269     unsigned int offset;
1270
1271     switch (cc) {
1272     default:
1273     case 0x0:
1274         offset = 0;
1275         break;
1276     case 0x1:
1277         offset = 32 - 10;
1278         break;
1279     case 0x2:
1280         offset = 34 - 10;
1281         break;
1282     case 0x3:
1283         offset = 36 - 10;
1284         break;
1285     }
1286
1287     switch (cond) {
1288     case 0x0:
1289         gen_op_eval_bn(r_dst);
1290         break;
1291     case 0x1:
1292         gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1293         break;
1294     case 0x2:
1295         gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1296         break;
1297     case 0x3:
1298         gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1299         break;
1300     case 0x4:
1301         gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1302         break;
1303     case 0x5:
1304         gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1305         break;
1306     case 0x6:
1307         gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1308         break;
1309     case 0x7:
1310         gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1311         break;
1312     case 0x8:
1313         gen_op_eval_ba(r_dst);
1314         break;
1315     case 0x9:
1316         gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1317         break;
1318     case 0xa:
1319         gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1320         break;
1321     case 0xb:
1322         gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1323         break;
1324     case 0xc:
1325         gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1326         break;
1327     case 0xd:
1328         gen_op_eval_fble(r_dst, cpu_fsr, offset);
1329         break;
1330     case 0xe:
1331         gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1332         break;
1333     case 0xf:
1334         gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1335         break;
1336     }
1337 }
1338
1339 #ifdef TARGET_SPARC64
1340 // Inverted logic
1341 static const int gen_tcg_cond_reg[8] = {
1342     -1,
1343     TCG_COND_NE,
1344     TCG_COND_GT,
1345     TCG_COND_GE,
1346     -1,
1347     TCG_COND_EQ,
1348     TCG_COND_LE,
1349     TCG_COND_LT,
1350 };
1351
1352 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1353 {
1354     int l1;
1355
1356     l1 = gen_new_label();
1357     tcg_gen_movi_tl(r_dst, 0);
1358     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], r_src, tcg_const_tl(0), l1);
1359     tcg_gen_movi_tl(r_dst, 1);
1360     gen_set_label(l1);
1361 }
1362 #endif
1363
1364 /* XXX: potentially incorrect if dynamic npc */
1365 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1366                       TCGv r_cond)
1367 {
1368     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1369     target_ulong target = dc->pc + offset;
1370
1371     if (cond == 0x0) {
1372         /* unconditional not taken */
1373         if (a) {
1374             dc->pc = dc->npc + 4;
1375             dc->npc = dc->pc + 4;
1376         } else {
1377             dc->pc = dc->npc;
1378             dc->npc = dc->pc + 4;
1379         }
1380     } else if (cond == 0x8) {
1381         /* unconditional taken */
1382         if (a) {
1383             dc->pc = target;
1384             dc->npc = dc->pc + 4;
1385         } else {
1386             dc->pc = dc->npc;
1387             dc->npc = target;
1388         }
1389     } else {
1390         flush_cond(dc, r_cond);
1391         gen_cond(r_cond, cc, cond);
1392         if (a) {
1393             gen_branch_a(dc, target, dc->npc, r_cond);
1394             dc->is_br = 1;
1395         } else {
1396             dc->pc = dc->npc;
1397             dc->jump_pc[0] = target;
1398             dc->jump_pc[1] = dc->npc + 4;
1399             dc->npc = JUMP_PC;
1400         }
1401     }
1402 }
1403
1404 /* XXX: potentially incorrect if dynamic npc */
1405 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1406                       TCGv r_cond)
1407 {
1408     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1409     target_ulong target = dc->pc + offset;
1410
1411     if (cond == 0x0) {
1412         /* unconditional not taken */
1413         if (a) {
1414             dc->pc = dc->npc + 4;
1415             dc->npc = dc->pc + 4;
1416         } else {
1417             dc->pc = dc->npc;
1418             dc->npc = dc->pc + 4;
1419         }
1420     } else if (cond == 0x8) {
1421         /* unconditional taken */
1422         if (a) {
1423             dc->pc = target;
1424             dc->npc = dc->pc + 4;
1425         } else {
1426             dc->pc = dc->npc;
1427             dc->npc = target;
1428         }
1429     } else {
1430         flush_cond(dc, r_cond);
1431         gen_fcond(r_cond, cc, cond);
1432         if (a) {
1433             gen_branch_a(dc, target, dc->npc, r_cond);
1434             dc->is_br = 1;
1435         } else {
1436             dc->pc = dc->npc;
1437             dc->jump_pc[0] = target;
1438             dc->jump_pc[1] = dc->npc + 4;
1439             dc->npc = JUMP_PC;
1440         }
1441     }
1442 }
1443
1444 #ifdef TARGET_SPARC64
1445 /* XXX: potentially incorrect if dynamic npc */
1446 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1447                           TCGv r_cond, TCGv r_reg)
1448 {
1449     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1450     target_ulong target = dc->pc + offset;
1451
1452     flush_cond(dc, r_cond);
1453     gen_cond_reg(r_cond, cond, r_reg);
1454     if (a) {
1455         gen_branch_a(dc, target, dc->npc, r_cond);
1456         dc->is_br = 1;
1457     } else {
1458         dc->pc = dc->npc;
1459         dc->jump_pc[0] = target;
1460         dc->jump_pc[1] = dc->npc + 4;
1461         dc->npc = JUMP_PC;
1462     }
1463 }
1464
1465 static GenOpFunc * const gen_fcmps[4] = {
1466     helper_fcmps,
1467     helper_fcmps_fcc1,
1468     helper_fcmps_fcc2,
1469     helper_fcmps_fcc3,
1470 };
1471
1472 static GenOpFunc * const gen_fcmpd[4] = {
1473     helper_fcmpd,
1474     helper_fcmpd_fcc1,
1475     helper_fcmpd_fcc2,
1476     helper_fcmpd_fcc3,
1477 };
1478
1479 #if defined(CONFIG_USER_ONLY)
1480 static GenOpFunc * const gen_fcmpq[4] = {
1481     helper_fcmpq,
1482     helper_fcmpq_fcc1,
1483     helper_fcmpq_fcc2,
1484     helper_fcmpq_fcc3,
1485 };
1486 #endif
1487
1488 static GenOpFunc * const gen_fcmpes[4] = {
1489     helper_fcmpes,
1490     helper_fcmpes_fcc1,
1491     helper_fcmpes_fcc2,
1492     helper_fcmpes_fcc3,
1493 };
1494
1495 static GenOpFunc * const gen_fcmped[4] = {
1496     helper_fcmped,
1497     helper_fcmped_fcc1,
1498     helper_fcmped_fcc2,
1499     helper_fcmped_fcc3,
1500 };
1501
1502 #if defined(CONFIG_USER_ONLY)
1503 static GenOpFunc * const gen_fcmpeq[4] = {
1504     helper_fcmpeq,
1505     helper_fcmpeq_fcc1,
1506     helper_fcmpeq_fcc2,
1507     helper_fcmpeq_fcc3,
1508 };
1509 #endif
1510
1511 static inline void gen_op_fcmps(int fccno)
1512 {
1513     tcg_gen_helper_0_0(gen_fcmps[fccno]);
1514 }
1515
1516 static inline void gen_op_fcmpd(int fccno)
1517 {
1518     tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1519 }
1520
1521 #if defined(CONFIG_USER_ONLY)
1522 static inline void gen_op_fcmpq(int fccno)
1523 {
1524     tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1525 }
1526 #endif
1527
1528 static inline void gen_op_fcmpes(int fccno)
1529 {
1530     tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1531 }
1532
1533 static inline void gen_op_fcmped(int fccno)
1534 {
1535     tcg_gen_helper_0_0(gen_fcmped[fccno]);
1536 }
1537
1538 #if defined(CONFIG_USER_ONLY)
1539 static inline void gen_op_fcmpeq(int fccno)
1540 {
1541     tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1542 }
1543 #endif
1544
1545 #else
1546
1547 static inline void gen_op_fcmps(int fccno)
1548 {
1549     tcg_gen_helper_0_0(helper_fcmps);
1550 }
1551
1552 static inline void gen_op_fcmpd(int fccno)
1553 {
1554     tcg_gen_helper_0_0(helper_fcmpd);
1555 }
1556
1557 #if defined(CONFIG_USER_ONLY)
1558 static inline void gen_op_fcmpq(int fccno)
1559 {
1560     tcg_gen_helper_0_0(helper_fcmpq);
1561 }
1562 #endif
1563
1564 static inline void gen_op_fcmpes(int fccno)
1565 {
1566     tcg_gen_helper_0_0(helper_fcmpes);
1567 }
1568
1569 static inline void gen_op_fcmped(int fccno)
1570 {
1571     tcg_gen_helper_0_0(helper_fcmped);
1572 }
1573
1574 #if defined(CONFIG_USER_ONLY)
1575 static inline void gen_op_fcmpeq(int fccno)
1576 {
1577     tcg_gen_helper_0_0(helper_fcmpeq);
1578 }
1579 #endif
1580
1581 #endif
1582
1583 static inline void gen_op_fpexception_im(int fsr_flags)
1584 {
1585     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1586     tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1587     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
1588 }
1589
1590 static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1591 {
1592 #if !defined(CONFIG_USER_ONLY)
1593     if (!dc->fpu_enabled) {
1594         save_state(dc, r_cond);
1595         tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
1596         dc->is_br = 1;
1597         return 1;
1598     }
1599 #endif
1600     return 0;
1601 }
1602
1603 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1604 {
1605     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1606 }
1607
1608 static inline void gen_clear_float_exceptions(void)
1609 {
1610     tcg_gen_helper_0_0(helper_clear_float_exceptions);
1611 }
1612
1613 /* asi moves */
1614 #ifdef TARGET_SPARC64
1615 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1616 {
1617     int asi, offset;
1618     TCGv r_asi;
1619
1620     if (IS_IMM) {
1621         r_asi = tcg_temp_new(TCG_TYPE_I32);
1622         offset = GET_FIELD(insn, 25, 31);
1623         tcg_gen_addi_tl(r_addr, r_addr, offset);
1624         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1625     } else {
1626         asi = GET_FIELD(insn, 19, 26);
1627         r_asi = tcg_const_i32(asi);
1628     }
1629     return r_asi;
1630 }
1631
1632 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1633 {
1634     TCGv r_asi;
1635
1636     r_asi = gen_get_asi(insn, addr);
1637     tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi,
1638                        tcg_const_i32(size), tcg_const_i32(sign));
1639 }
1640
1641 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1642 {
1643     TCGv r_asi;
1644
1645     r_asi = gen_get_asi(insn, addr);
1646     tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, tcg_const_i32(size));
1647 }
1648
1649 static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1650 {
1651     TCGv r_asi;
1652
1653     r_asi = gen_get_asi(insn, addr);
1654     tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, tcg_const_i32(size),
1655                        tcg_const_i32(rd));
1656 }
1657
1658 static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1659 {
1660     TCGv r_asi;
1661
1662     r_asi = gen_get_asi(insn, addr);
1663     tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, tcg_const_i32(size),
1664                        tcg_const_i32(rd));
1665 }
1666
1667 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1668 {
1669     TCGv r_temp, r_asi;
1670
1671     r_temp = tcg_temp_new(TCG_TYPE_I32);
1672     r_asi = gen_get_asi(insn, addr);
1673     tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, r_asi,
1674                        tcg_const_i32(4), tcg_const_i32(0));
1675     tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi,
1676                        tcg_const_i32(4));
1677     tcg_gen_extu_i32_tl(dst, r_temp);
1678 }
1679
1680 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1681 {
1682     TCGv r_asi;
1683
1684     r_asi = gen_get_asi(insn, addr);
1685     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi,
1686                        tcg_const_i32(8), tcg_const_i32(0));
1687     tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1688     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1689     tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1690 }
1691
1692 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1693 {
1694     TCGv r_temp, r_asi;
1695
1696     r_temp = tcg_temp_new(TCG_TYPE_I32);
1697     gen_movl_reg_TN(rd + 1, r_temp);
1698     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1699                        r_temp);
1700     r_asi = gen_get_asi(insn, addr);
1701     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi,
1702                        tcg_const_i32(8));
1703 }
1704
1705 static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1706 {
1707     TCGv r_val1, r_asi;
1708
1709     r_val1 = tcg_temp_new(TCG_TYPE_I32);
1710     gen_movl_reg_TN(rd, r_val1);
1711     r_asi = gen_get_asi(insn, addr);
1712     tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1713 }
1714
1715 static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1716 {
1717     TCGv r_asi;
1718
1719     gen_movl_reg_TN(rd, cpu_tmp64);
1720     r_asi = gen_get_asi(insn, addr);
1721     tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1722 }
1723
1724 #elif !defined(CONFIG_USER_ONLY)
1725
1726 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1727 {
1728     int asi;
1729
1730     asi = GET_FIELD(insn, 19, 26);
1731     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1732                        tcg_const_i32(size), tcg_const_i32(sign));
1733     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1734 }
1735
1736 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1737 {
1738     int asi;
1739
1740     tcg_gen_extu_tl_i64(cpu_tmp64, src);
1741     asi = GET_FIELD(insn, 19, 26);
1742     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1743                        tcg_const_i32(size));
1744 }
1745
1746 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1747 {
1748     int asi;
1749     TCGv r_temp;
1750
1751     r_temp = tcg_temp_new(TCG_TYPE_I32);
1752     asi = GET_FIELD(insn, 19, 26);
1753     tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, tcg_const_i32(asi),
1754                        tcg_const_i32(4), tcg_const_i32(0));
1755     tcg_gen_helper_0_4(helper_st_asi, addr, dst, tcg_const_i32(asi),
1756                        tcg_const_i32(4));
1757     tcg_gen_extu_i32_tl(dst, r_temp);
1758 }
1759
1760 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1761 {
1762     int asi;
1763
1764     asi = GET_FIELD(insn, 19, 26);
1765     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1766                        tcg_const_i32(8), tcg_const_i32(0));
1767     tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1768     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1769     tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1770 }
1771
1772 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1773 {
1774     int asi;
1775     TCGv r_temp;
1776
1777     r_temp = tcg_temp_new(TCG_TYPE_I32);
1778     gen_movl_reg_TN(rd + 1, r_temp);
1779     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1780     asi = GET_FIELD(insn, 19, 26);
1781     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1782                        tcg_const_i32(8));
1783 }
1784 #endif
1785
1786 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1787 static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1788 {
1789     int asi;
1790
1791     gen_ld_asi(dst, addr, insn, 1, 0);
1792
1793     asi = GET_FIELD(insn, 19, 26);
1794     tcg_gen_helper_0_4(helper_st_asi, addr, tcg_const_i64(0xffULL),
1795                        tcg_const_i32(asi), tcg_const_i32(1));
1796 }
1797 #endif
1798
1799 static inline TCGv get_src1(unsigned int insn, TCGv def)
1800 {
1801     TCGv r_rs1 = def;
1802     unsigned int rs1;
1803
1804     rs1 = GET_FIELD(insn, 13, 17);
1805     if (rs1 == 0)
1806         //r_rs1 = tcg_const_tl(0);
1807         tcg_gen_movi_tl(def, 0);
1808     else if (rs1 < 8)
1809         //r_rs1 = cpu_gregs[rs1];
1810         tcg_gen_mov_tl(def, cpu_gregs[rs1]);
1811     else
1812         tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1813     return r_rs1;
1814 }
1815
1816 static inline TCGv get_src2(unsigned int insn, TCGv def)
1817 {
1818     TCGv r_rs2 = def;
1819     unsigned int rs2;
1820
1821     if (IS_IMM) { /* immediate */
1822         rs2 = GET_FIELDs(insn, 19, 31);
1823         r_rs2 = tcg_const_tl((int)rs2);
1824     } else { /* register */
1825         rs2 = GET_FIELD(insn, 27, 31);
1826         if (rs2 == 0)
1827             r_rs2 = tcg_const_tl(0);
1828         else if (rs2 < 8)
1829             r_rs2 = cpu_gregs[rs2];
1830         else
1831             tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1832     }
1833     return r_rs2;
1834 }
1835
1836 /* before an instruction, dc->pc must be static */
1837 static void disas_sparc_insn(DisasContext * dc)
1838 {
1839     unsigned int insn, opc, rs1, rs2, rd;
1840
1841     insn = ldl_code(dc->pc);
1842     opc = GET_FIELD(insn, 0, 1);
1843
1844     rd = GET_FIELD(insn, 2, 6);
1845
1846     cpu_dst = cpu_T[0];
1847     cpu_src1 = cpu_T[0]; // const
1848     cpu_src2 = cpu_T[1]; // const
1849
1850     // loads and stores
1851     cpu_addr = cpu_T[0];
1852     cpu_val = cpu_T[1];
1853
1854     switch (opc) {
1855     case 0:                     /* branches/sethi */
1856         {
1857             unsigned int xop = GET_FIELD(insn, 7, 9);
1858             int32_t target;
1859             switch (xop) {
1860 #ifdef TARGET_SPARC64
1861             case 0x1:           /* V9 BPcc */
1862                 {
1863                     int cc;
1864
1865                     target = GET_FIELD_SP(insn, 0, 18);
1866                     target = sign_extend(target, 18);
1867                     target <<= 2;
1868                     cc = GET_FIELD_SP(insn, 20, 21);
1869                     if (cc == 0)
1870                         do_branch(dc, target, insn, 0, cpu_cond);
1871                     else if (cc == 2)
1872                         do_branch(dc, target, insn, 1, cpu_cond);
1873                     else
1874                         goto illegal_insn;
1875                     goto jmp_insn;
1876                 }
1877             case 0x3:           /* V9 BPr */
1878                 {
1879                     target = GET_FIELD_SP(insn, 0, 13) |
1880                         (GET_FIELD_SP(insn, 20, 21) << 14);
1881                     target = sign_extend(target, 16);
1882                     target <<= 2;
1883                     cpu_src1 = get_src1(insn, cpu_src1);
1884                     do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1885                     goto jmp_insn;
1886                 }
1887             case 0x5:           /* V9 FBPcc */
1888                 {
1889                     int cc = GET_FIELD_SP(insn, 20, 21);
1890                     if (gen_trap_ifnofpu(dc, cpu_cond))
1891                         goto jmp_insn;
1892                     target = GET_FIELD_SP(insn, 0, 18);
1893                     target = sign_extend(target, 19);
1894                     target <<= 2;
1895                     do_fbranch(dc, target, insn, cc, cpu_cond);
1896                     goto jmp_insn;
1897                 }
1898 #else
1899             case 0x7:           /* CBN+x */
1900                 {
1901                     goto ncp_insn;
1902                 }
1903 #endif
1904             case 0x2:           /* BN+x */
1905                 {
1906                     target = GET_FIELD(insn, 10, 31);
1907                     target = sign_extend(target, 22);
1908                     target <<= 2;
1909                     do_branch(dc, target, insn, 0, cpu_cond);
1910                     goto jmp_insn;
1911                 }
1912             case 0x6:           /* FBN+x */
1913                 {
1914                     if (gen_trap_ifnofpu(dc, cpu_cond))
1915                         goto jmp_insn;
1916                     target = GET_FIELD(insn, 10, 31);
1917                     target = sign_extend(target, 22);
1918                     target <<= 2;
1919                     do_fbranch(dc, target, insn, 0, cpu_cond);
1920                     goto jmp_insn;
1921                 }
1922             case 0x4:           /* SETHI */
1923                 if (rd) { // nop
1924                     uint32_t value = GET_FIELD(insn, 10, 31);
1925                     tcg_gen_movi_tl(cpu_dst, value << 10);
1926                     gen_movl_TN_reg(rd, cpu_dst);
1927                 }
1928                 break;
1929             case 0x0:           /* UNIMPL */
1930             default:
1931                 goto illegal_insn;
1932             }
1933             break;
1934         }
1935         break;
1936     case 1:
1937         /*CALL*/ {
1938             target_long target = GET_FIELDs(insn, 2, 31) << 2;
1939
1940             gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
1941             target += dc->pc;
1942             gen_mov_pc_npc(dc, cpu_cond);
1943             dc->npc = target;
1944         }
1945         goto jmp_insn;
1946     case 2:                     /* FPU & Logical Operations */
1947         {
1948             unsigned int xop = GET_FIELD(insn, 7, 12);
1949             if (xop == 0x3a) {  /* generate trap */
1950                 int cond;
1951
1952                 cpu_src1 = get_src1(insn, cpu_src1);
1953                 if (IS_IMM) {
1954                     rs2 = GET_FIELD(insn, 25, 31);
1955                     tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
1956                 } else {
1957                     rs2 = GET_FIELD(insn, 27, 31);
1958                     if (rs2 != 0) {
1959                         gen_movl_reg_TN(rs2, cpu_src2);
1960                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
1961                     }
1962                 }
1963                 cond = GET_FIELD(insn, 3, 6);
1964                 if (cond == 0x8) {
1965                     save_state(dc, cpu_cond);
1966                     tcg_gen_helper_0_1(helper_trap, cpu_dst);
1967                 } else if (cond != 0) {
1968                     TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
1969 #ifdef TARGET_SPARC64
1970                     /* V9 icc/xcc */
1971                     int cc = GET_FIELD_SP(insn, 11, 12);
1972
1973                     save_state(dc, cpu_cond);
1974                     if (cc == 0)
1975                         gen_cond(r_cond, 0, cond);
1976                     else if (cc == 2)
1977                         gen_cond(r_cond, 1, cond);
1978                     else
1979                         goto illegal_insn;
1980 #else
1981                     save_state(dc, cpu_cond);
1982                     gen_cond(r_cond, 0, cond);
1983 #endif
1984                     tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
1985                 }
1986                 gen_op_next_insn();
1987                 tcg_gen_exit_tb(0);
1988                 dc->is_br = 1;
1989                 goto jmp_insn;
1990             } else if (xop == 0x28) {
1991                 rs1 = GET_FIELD(insn, 13, 17);
1992                 switch(rs1) {
1993                 case 0: /* rdy */
1994 #ifndef TARGET_SPARC64
1995                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1996                                        manual, rdy on the microSPARC
1997                                        II */
1998                 case 0x0f:          /* stbar in the SPARCv8 manual,
1999                                        rdy on the microSPARC II */
2000                 case 0x10 ... 0x1f: /* implementation-dependent in the
2001                                        SPARCv8 manual, rdy on the
2002                                        microSPARC II */
2003 #endif
2004                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
2005                     gen_movl_TN_reg(rd, cpu_dst);
2006                     break;
2007 #ifdef TARGET_SPARC64
2008                 case 0x2: /* V9 rdccr */
2009                     tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2010                     gen_movl_TN_reg(rd, cpu_dst);
2011                     break;
2012                 case 0x3: /* V9 rdasi */
2013                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
2014                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2015                     gen_movl_TN_reg(rd, cpu_dst);
2016                     break;
2017                 case 0x4: /* V9 rdtick */
2018                     {
2019                         TCGv r_tickptr;
2020
2021                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2022                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2023                                        offsetof(CPUState, tick));
2024                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2025                                            r_tickptr);
2026                         gen_movl_TN_reg(rd, cpu_dst);
2027                     }
2028                     break;
2029                 case 0x5: /* V9 rdpc */
2030                     tcg_gen_movi_tl(cpu_dst, dc->pc);
2031                     gen_movl_TN_reg(rd, cpu_dst);
2032                     break;
2033                 case 0x6: /* V9 rdfprs */
2034                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
2035                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2036                     gen_movl_TN_reg(rd, cpu_dst);
2037                     break;
2038                 case 0xf: /* V9 membar */
2039                     break; /* no effect */
2040                 case 0x13: /* Graphics Status */
2041                     if (gen_trap_ifnofpu(dc, cpu_cond))
2042                         goto jmp_insn;
2043                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
2044                     gen_movl_TN_reg(rd, cpu_dst);
2045                     break;
2046                 case 0x17: /* Tick compare */
2047                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tick_cmpr));
2048                     gen_movl_TN_reg(rd, cpu_dst);
2049                     break;
2050                 case 0x18: /* System tick */
2051                     {
2052                         TCGv r_tickptr;
2053
2054                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2055                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2056                                        offsetof(CPUState, stick));
2057                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2058                                            r_tickptr);
2059                         gen_movl_TN_reg(rd, cpu_dst);
2060                     }
2061                     break;
2062                 case 0x19: /* System tick compare */
2063                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, stick_cmpr));
2064                     gen_movl_TN_reg(rd, cpu_dst);
2065                     break;
2066                 case 0x10: /* Performance Control */
2067                 case 0x11: /* Performance Instrumentation Counter */
2068                 case 0x12: /* Dispatch Control */
2069                 case 0x14: /* Softint set, WO */
2070                 case 0x15: /* Softint clear, WO */
2071                 case 0x16: /* Softint write */
2072 #endif
2073                 default:
2074                     goto illegal_insn;
2075                 }
2076 #if !defined(CONFIG_USER_ONLY)
2077             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2078 #ifndef TARGET_SPARC64
2079                 if (!supervisor(dc))
2080                     goto priv_insn;
2081                 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2082 #else
2083                 if (!hypervisor(dc))
2084                     goto priv_insn;
2085                 rs1 = GET_FIELD(insn, 13, 17);
2086                 switch (rs1) {
2087                 case 0: // hpstate
2088                     // gen_op_rdhpstate();
2089                     break;
2090                 case 1: // htstate
2091                     // gen_op_rdhtstate();
2092                     break;
2093                 case 3: // hintp
2094                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
2095                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2096                     break;
2097                 case 5: // htba
2098                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
2099                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2100                     break;
2101                 case 6: // hver
2102                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver));
2103                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2104                     break;
2105                 case 31: // hstick_cmpr
2106                     tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2107                     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr));
2108                     break;
2109                 default:
2110                     goto illegal_insn;
2111                 }
2112 #endif
2113                 gen_movl_TN_reg(rd, cpu_dst);
2114                 break;
2115             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2116                 if (!supervisor(dc))
2117                     goto priv_insn;
2118 #ifdef TARGET_SPARC64
2119                 rs1 = GET_FIELD(insn, 13, 17);
2120                 switch (rs1) {
2121                 case 0: // tpc
2122                     {
2123                         TCGv r_tsptr;
2124
2125                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2126                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2127                                        offsetof(CPUState, tsptr));
2128                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2129                                       offsetof(trap_state, tpc));
2130                     }
2131                     break;
2132                 case 1: // tnpc
2133                     {
2134                         TCGv r_tsptr;
2135
2136                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2137                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2138                                        offsetof(CPUState, tsptr));
2139                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2140                                       offsetof(trap_state, tnpc));
2141                     }
2142                     break;
2143                 case 2: // tstate
2144                     {
2145                         TCGv r_tsptr;
2146
2147                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2148                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2149                                        offsetof(CPUState, tsptr));
2150                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2151                                       offsetof(trap_state, tstate));
2152                     }
2153                     break;
2154                 case 3: // tt
2155                     {
2156                         TCGv r_tsptr;
2157
2158                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2159                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2160                                        offsetof(CPUState, tsptr));
2161                         tcg_gen_ld_i32(cpu_dst, r_tsptr,
2162                                        offsetof(trap_state, tt));
2163                     }
2164                     break;
2165                 case 4: // tick
2166                     {
2167                         TCGv r_tickptr;
2168
2169                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2170                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2171                                        offsetof(CPUState, tick));
2172                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2173                                            r_tickptr);
2174                         gen_movl_TN_reg(rd, cpu_dst);
2175                     }
2176                     break;
2177                 case 5: // tba
2178                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2179                     break;
2180                 case 6: // pstate
2181                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate));
2182                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2183                     break;
2184                 case 7: // tl
2185                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
2186                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2187                     break;
2188                 case 8: // pil
2189                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
2190                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2191                     break;
2192                 case 9: // cwp
2193                     tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
2194                     break;
2195                 case 10: // cansave
2196                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
2197                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2198                     break;
2199                 case 11: // canrestore
2200                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
2201                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2202                     break;
2203                 case 12: // cleanwin
2204                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
2205                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2206                     break;
2207                 case 13: // otherwin
2208                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
2209                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2210                     break;
2211                 case 14: // wstate
2212                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
2213                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2214                     break;
2215                 case 16: // UA2005 gl
2216                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
2217                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2218                     break;
2219                 case 26: // UA2005 strand status
2220                     if (!hypervisor(dc))
2221                         goto priv_insn;
2222                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
2223                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2224                     break;
2225                 case 31: // ver
2226                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, version));
2227                     break;
2228                 case 15: // fq
2229                 default:
2230                     goto illegal_insn;
2231                 }
2232 #else
2233                 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
2234                 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2235 #endif
2236                 gen_movl_TN_reg(rd, cpu_dst);
2237                 break;
2238             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2239 #ifdef TARGET_SPARC64
2240                 tcg_gen_helper_0_0(helper_flushw);
2241 #else
2242                 if (!supervisor(dc))
2243                     goto priv_insn;
2244                 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2245                 gen_movl_TN_reg(rd, cpu_dst);
2246 #endif
2247                 break;
2248 #endif
2249             } else if (xop == 0x34) {   /* FPU Operations */
2250                 if (gen_trap_ifnofpu(dc, cpu_cond))
2251                     goto jmp_insn;
2252                 gen_op_clear_ieee_excp_and_FTT();
2253                 rs1 = GET_FIELD(insn, 13, 17);
2254                 rs2 = GET_FIELD(insn, 27, 31);
2255                 xop = GET_FIELD(insn, 18, 26);
2256                 switch (xop) {
2257                     case 0x1: /* fmovs */
2258                         gen_op_load_fpr_FT0(rs2);
2259                         gen_op_store_FT0_fpr(rd);
2260                         break;
2261                     case 0x5: /* fnegs */
2262                         gen_op_load_fpr_FT1(rs2);
2263                         tcg_gen_helper_0_0(helper_fnegs);
2264                         gen_op_store_FT0_fpr(rd);
2265                         break;
2266                     case 0x9: /* fabss */
2267                         gen_op_load_fpr_FT1(rs2);
2268                         tcg_gen_helper_0_0(helper_fabss);
2269                         gen_op_store_FT0_fpr(rd);
2270                         break;
2271                     case 0x29: /* fsqrts */
2272                         gen_op_load_fpr_FT1(rs2);
2273                         gen_clear_float_exceptions();
2274                         tcg_gen_helper_0_0(helper_fsqrts);
2275                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2276                         gen_op_store_FT0_fpr(rd);
2277                         break;
2278                     case 0x2a: /* fsqrtd */
2279                         gen_op_load_fpr_DT1(DFPREG(rs2));
2280                         gen_clear_float_exceptions();
2281                         tcg_gen_helper_0_0(helper_fsqrtd);
2282                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2283                         gen_op_store_DT0_fpr(DFPREG(rd));
2284                         break;
2285                     case 0x2b: /* fsqrtq */
2286 #if defined(CONFIG_USER_ONLY)
2287                         gen_op_load_fpr_QT1(QFPREG(rs2));
2288                         gen_clear_float_exceptions();
2289                         tcg_gen_helper_0_0(helper_fsqrtq);
2290                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2291                         gen_op_store_QT0_fpr(QFPREG(rd));
2292                         break;
2293 #else
2294                         goto nfpu_insn;
2295 #endif
2296                     case 0x41:
2297                         gen_op_load_fpr_FT0(rs1);
2298                         gen_op_load_fpr_FT1(rs2);
2299                         gen_clear_float_exceptions();
2300                         tcg_gen_helper_0_0(helper_fadds);
2301                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2302                         gen_op_store_FT0_fpr(rd);
2303                         break;
2304                     case 0x42:
2305                         gen_op_load_fpr_DT0(DFPREG(rs1));
2306                         gen_op_load_fpr_DT1(DFPREG(rs2));
2307                         gen_clear_float_exceptions();
2308                         tcg_gen_helper_0_0(helper_faddd);
2309                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2310                         gen_op_store_DT0_fpr(DFPREG(rd));
2311                         break;
2312                     case 0x43: /* faddq */
2313 #if defined(CONFIG_USER_ONLY)
2314                         gen_op_load_fpr_QT0(QFPREG(rs1));
2315                         gen_op_load_fpr_QT1(QFPREG(rs2));
2316                         gen_clear_float_exceptions();
2317                         tcg_gen_helper_0_0(helper_faddq);
2318                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2319                         gen_op_store_QT0_fpr(QFPREG(rd));
2320                         break;
2321 #else
2322                         goto nfpu_insn;
2323 #endif
2324                     case 0x45:
2325                         gen_op_load_fpr_FT0(rs1);
2326                         gen_op_load_fpr_FT1(rs2);
2327                         gen_clear_float_exceptions();
2328                         tcg_gen_helper_0_0(helper_fsubs);
2329                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2330                         gen_op_store_FT0_fpr(rd);
2331                         break;
2332                     case 0x46:
2333                         gen_op_load_fpr_DT0(DFPREG(rs1));
2334                         gen_op_load_fpr_DT1(DFPREG(rs2));
2335                         gen_clear_float_exceptions();
2336                         tcg_gen_helper_0_0(helper_fsubd);
2337                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2338                         gen_op_store_DT0_fpr(DFPREG(rd));
2339                         break;
2340                     case 0x47: /* fsubq */
2341 #if defined(CONFIG_USER_ONLY)
2342                         gen_op_load_fpr_QT0(QFPREG(rs1));
2343                         gen_op_load_fpr_QT1(QFPREG(rs2));
2344                         gen_clear_float_exceptions();
2345                         tcg_gen_helper_0_0(helper_fsubq);
2346                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2347                         gen_op_store_QT0_fpr(QFPREG(rd));
2348                         break;
2349 #else
2350                         goto nfpu_insn;
2351 #endif
2352                     case 0x49:
2353                         gen_op_load_fpr_FT0(rs1);
2354                         gen_op_load_fpr_FT1(rs2);
2355                         gen_clear_float_exceptions();
2356                         tcg_gen_helper_0_0(helper_fmuls);
2357                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2358                         gen_op_store_FT0_fpr(rd);
2359                         break;
2360                     case 0x4a:
2361                         gen_op_load_fpr_DT0(DFPREG(rs1));
2362                         gen_op_load_fpr_DT1(DFPREG(rs2));
2363                         gen_clear_float_exceptions();
2364                         tcg_gen_helper_0_0(helper_fmuld);
2365                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2366                         gen_op_store_DT0_fpr(DFPREG(rd));
2367                         break;
2368                     case 0x4b: /* fmulq */
2369 #if defined(CONFIG_USER_ONLY)
2370                         gen_op_load_fpr_QT0(QFPREG(rs1));
2371                         gen_op_load_fpr_QT1(QFPREG(rs2));
2372                         gen_clear_float_exceptions();
2373                         tcg_gen_helper_0_0(helper_fmulq);
2374                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2375                         gen_op_store_QT0_fpr(QFPREG(rd));
2376                         break;
2377 #else
2378                         goto nfpu_insn;
2379 #endif
2380                     case 0x4d:
2381                         gen_op_load_fpr_FT0(rs1);
2382                         gen_op_load_fpr_FT1(rs2);
2383                         gen_clear_float_exceptions();
2384                         tcg_gen_helper_0_0(helper_fdivs);
2385                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2386                         gen_op_store_FT0_fpr(rd);
2387                         break;
2388                     case 0x4e:
2389                         gen_op_load_fpr_DT0(DFPREG(rs1));
2390                         gen_op_load_fpr_DT1(DFPREG(rs2));
2391                         gen_clear_float_exceptions();
2392                         tcg_gen_helper_0_0(helper_fdivd);
2393                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2394                         gen_op_store_DT0_fpr(DFPREG(rd));
2395                         break;
2396                     case 0x4f: /* fdivq */
2397 #if defined(CONFIG_USER_ONLY)
2398                         gen_op_load_fpr_QT0(QFPREG(rs1));
2399                         gen_op_load_fpr_QT1(QFPREG(rs2));
2400                         gen_clear_float_exceptions();
2401                         tcg_gen_helper_0_0(helper_fdivq);
2402                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2403                         gen_op_store_QT0_fpr(QFPREG(rd));
2404                         break;
2405 #else
2406                         goto nfpu_insn;
2407 #endif
2408                     case 0x69:
2409                         gen_op_load_fpr_FT0(rs1);
2410                         gen_op_load_fpr_FT1(rs2);
2411                         gen_clear_float_exceptions();
2412                         tcg_gen_helper_0_0(helper_fsmuld);
2413                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2414                         gen_op_store_DT0_fpr(DFPREG(rd));
2415                         break;
2416                     case 0x6e: /* fdmulq */
2417 #if defined(CONFIG_USER_ONLY)
2418                         gen_op_load_fpr_DT0(DFPREG(rs1));
2419                         gen_op_load_fpr_DT1(DFPREG(rs2));
2420                         gen_clear_float_exceptions();
2421                         tcg_gen_helper_0_0(helper_fdmulq);
2422                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2423                         gen_op_store_QT0_fpr(QFPREG(rd));
2424                         break;
2425 #else
2426                         goto nfpu_insn;
2427 #endif
2428                     case 0xc4:
2429                         gen_op_load_fpr_FT1(rs2);
2430                         gen_clear_float_exceptions();
2431                         tcg_gen_helper_0_0(helper_fitos);
2432                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2433                         gen_op_store_FT0_fpr(rd);
2434                         break;
2435                     case 0xc6:
2436                         gen_op_load_fpr_DT1(DFPREG(rs2));
2437                         gen_clear_float_exceptions();
2438                         tcg_gen_helper_0_0(helper_fdtos);
2439                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2440                         gen_op_store_FT0_fpr(rd);
2441                         break;
2442                     case 0xc7: /* fqtos */
2443 #if defined(CONFIG_USER_ONLY)
2444                         gen_op_load_fpr_QT1(QFPREG(rs2));
2445                         gen_clear_float_exceptions();
2446                         tcg_gen_helper_0_0(helper_fqtos);
2447                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2448                         gen_op_store_FT0_fpr(rd);
2449                         break;
2450 #else
2451                         goto nfpu_insn;
2452 #endif
2453                     case 0xc8:
2454                         gen_op_load_fpr_FT1(rs2);
2455                         tcg_gen_helper_0_0(helper_fitod);
2456                         gen_op_store_DT0_fpr(DFPREG(rd));
2457                         break;
2458                     case 0xc9:
2459                         gen_op_load_fpr_FT1(rs2);
2460                         tcg_gen_helper_0_0(helper_fstod);
2461                         gen_op_store_DT0_fpr(DFPREG(rd));
2462                         break;
2463                     case 0xcb: /* fqtod */
2464 #if defined(CONFIG_USER_ONLY)
2465                         gen_op_load_fpr_QT1(QFPREG(rs2));
2466                         gen_clear_float_exceptions();
2467                         tcg_gen_helper_0_0(helper_fqtod);
2468                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2469                         gen_op_store_DT0_fpr(DFPREG(rd));
2470                         break;
2471 #else
2472                         goto nfpu_insn;
2473 #endif
2474                     case 0xcc: /* fitoq */
2475 #if defined(CONFIG_USER_ONLY)
2476                         gen_op_load_fpr_FT1(rs2);
2477                         tcg_gen_helper_0_0(helper_fitoq);
2478                         gen_op_store_QT0_fpr(QFPREG(rd));
2479                         break;
2480 #else
2481                         goto nfpu_insn;
2482 #endif
2483                     case 0xcd: /* fstoq */
2484 #if defined(CONFIG_USER_ONLY)
2485                         gen_op_load_fpr_FT1(rs2);
2486                         tcg_gen_helper_0_0(helper_fstoq);
2487                         gen_op_store_QT0_fpr(QFPREG(rd));
2488                         break;
2489 #else
2490                         goto nfpu_insn;
2491 #endif
2492                     case 0xce: /* fdtoq */
2493 #if defined(CONFIG_USER_ONLY)
2494                         gen_op_load_fpr_DT1(DFPREG(rs2));
2495                         tcg_gen_helper_0_0(helper_fdtoq);
2496                         gen_op_store_QT0_fpr(QFPREG(rd));
2497                         break;
2498 #else
2499                         goto nfpu_insn;
2500 #endif
2501                     case 0xd1:
2502                         gen_op_load_fpr_FT1(rs2);
2503                         gen_clear_float_exceptions();
2504                         tcg_gen_helper_0_0(helper_fstoi);
2505                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2506                         gen_op_store_FT0_fpr(rd);
2507                         break;
2508                     case 0xd2:
2509                         gen_op_load_fpr_DT1(DFPREG(rs2));
2510                         gen_clear_float_exceptions();
2511                         tcg_gen_helper_0_0(helper_fdtoi);
2512                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2513                         gen_op_store_FT0_fpr(rd);
2514                         break;
2515                     case 0xd3: /* fqtoi */
2516 #if defined(CONFIG_USER_ONLY)
2517                         gen_op_load_fpr_QT1(QFPREG(rs2));
2518                         gen_clear_float_exceptions();
2519                         tcg_gen_helper_0_0(helper_fqtoi);
2520                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2521                         gen_op_store_FT0_fpr(rd);
2522                         break;
2523 #else
2524                         goto nfpu_insn;
2525 #endif
2526 #ifdef TARGET_SPARC64
2527                     case 0x2: /* V9 fmovd */
2528                         gen_op_load_fpr_DT0(DFPREG(rs2));
2529                         gen_op_store_DT0_fpr(DFPREG(rd));
2530                         break;
2531                     case 0x3: /* V9 fmovq */
2532 #if defined(CONFIG_USER_ONLY)
2533                         gen_op_load_fpr_QT0(QFPREG(rs2));
2534                         gen_op_store_QT0_fpr(QFPREG(rd));
2535                         break;
2536 #else
2537                         goto nfpu_insn;
2538 #endif
2539                     case 0x6: /* V9 fnegd */
2540                         gen_op_load_fpr_DT1(DFPREG(rs2));
2541                         tcg_gen_helper_0_0(helper_fnegd);
2542                         gen_op_store_DT0_fpr(DFPREG(rd));
2543                         break;
2544                     case 0x7: /* V9 fnegq */
2545 #if defined(CONFIG_USER_ONLY)
2546                         gen_op_load_fpr_QT1(QFPREG(rs2));
2547                         tcg_gen_helper_0_0(helper_fnegq);
2548                         gen_op_store_QT0_fpr(QFPREG(rd));
2549                         break;
2550 #else
2551                         goto nfpu_insn;
2552 #endif
2553                     case 0xa: /* V9 fabsd */
2554                         gen_op_load_fpr_DT1(DFPREG(rs2));
2555                         tcg_gen_helper_0_0(helper_fabsd);
2556                         gen_op_store_DT0_fpr(DFPREG(rd));
2557                         break;
2558                     case 0xb: /* V9 fabsq */
2559 #if defined(CONFIG_USER_ONLY)
2560                         gen_op_load_fpr_QT1(QFPREG(rs2));
2561                         tcg_gen_helper_0_0(helper_fabsq);
2562                         gen_op_store_QT0_fpr(QFPREG(rd));
2563                         break;
2564 #else
2565                         goto nfpu_insn;
2566 #endif
2567                     case 0x81: /* V9 fstox */
2568                         gen_op_load_fpr_FT1(rs2);
2569                         gen_clear_float_exceptions();
2570                         tcg_gen_helper_0_0(helper_fstox);
2571                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2572                         gen_op_store_DT0_fpr(DFPREG(rd));
2573                         break;
2574                     case 0x82: /* V9 fdtox */
2575                         gen_op_load_fpr_DT1(DFPREG(rs2));
2576                         gen_clear_float_exceptions();
2577                         tcg_gen_helper_0_0(helper_fdtox);
2578                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2579                         gen_op_store_DT0_fpr(DFPREG(rd));
2580                         break;
2581                     case 0x83: /* V9 fqtox */
2582 #if defined(CONFIG_USER_ONLY)
2583                         gen_op_load_fpr_QT1(QFPREG(rs2));
2584                         gen_clear_float_exceptions();
2585                         tcg_gen_helper_0_0(helper_fqtox);
2586                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2587                         gen_op_store_DT0_fpr(DFPREG(rd));
2588                         break;
2589 #else
2590                         goto nfpu_insn;
2591 #endif
2592                     case 0x84: /* V9 fxtos */
2593                         gen_op_load_fpr_DT1(DFPREG(rs2));
2594                         gen_clear_float_exceptions();
2595                         tcg_gen_helper_0_0(helper_fxtos);
2596                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2597                         gen_op_store_FT0_fpr(rd);
2598                         break;
2599                     case 0x88: /* V9 fxtod */
2600                         gen_op_load_fpr_DT1(DFPREG(rs2));
2601                         gen_clear_float_exceptions();
2602                         tcg_gen_helper_0_0(helper_fxtod);
2603                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2604                         gen_op_store_DT0_fpr(DFPREG(rd));
2605                         break;
2606                     case 0x8c: /* V9 fxtoq */
2607 #if defined(CONFIG_USER_ONLY)
2608                         gen_op_load_fpr_DT1(DFPREG(rs2));
2609                         gen_clear_float_exceptions();
2610                         tcg_gen_helper_0_0(helper_fxtoq);
2611                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2612                         gen_op_store_QT0_fpr(QFPREG(rd));
2613                         break;
2614 #else
2615                         goto nfpu_insn;
2616 #endif
2617 #endif
2618                     default:
2619                         goto illegal_insn;
2620                 }
2621             } else if (xop == 0x35) {   /* FPU Operations */
2622 #ifdef TARGET_SPARC64
2623                 int cond;
2624 #endif
2625                 if (gen_trap_ifnofpu(dc, cpu_cond))
2626                     goto jmp_insn;
2627                 gen_op_clear_ieee_excp_and_FTT();
2628                 rs1 = GET_FIELD(insn, 13, 17);
2629                 rs2 = GET_FIELD(insn, 27, 31);
2630                 xop = GET_FIELD(insn, 18, 26);
2631 #ifdef TARGET_SPARC64
2632                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2633                     int l1;
2634
2635                     l1 = gen_new_label();
2636                     cond = GET_FIELD_SP(insn, 14, 17);
2637                     cpu_src1 = get_src1(insn, cpu_src1);
2638                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2639                                       tcg_const_tl(0), l1);
2640                     gen_op_load_fpr_FT0(rs2);
2641                     gen_op_store_FT0_fpr(rd);
2642                     gen_set_label(l1);
2643                     break;
2644                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2645                     int l1;
2646
2647                     l1 = gen_new_label();
2648                     cond = GET_FIELD_SP(insn, 14, 17);
2649                     cpu_src1 = get_src1(insn, cpu_src1);
2650                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2651                                       tcg_const_tl(0), l1);
2652                     gen_op_load_fpr_DT0(DFPREG(rs2));
2653                     gen_op_store_DT0_fpr(DFPREG(rd));
2654                     gen_set_label(l1);
2655                     break;
2656                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2657 #if defined(CONFIG_USER_ONLY)
2658                     int l1;
2659
2660                     l1 = gen_new_label();
2661                     cond = GET_FIELD_SP(insn, 14, 17);
2662                     cpu_src1 = get_src1(insn, cpu_src1);
2663                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2664                                       tcg_const_tl(0), l1);
2665                     gen_op_load_fpr_QT0(QFPREG(rs2));
2666                     gen_op_store_QT0_fpr(QFPREG(rd));
2667                     gen_set_label(l1);
2668                     break;
2669 #else
2670                     goto nfpu_insn;
2671 #endif
2672                 }
2673 #endif
2674                 switch (xop) {
2675 #ifdef TARGET_SPARC64
2676 #define FMOVCC(size_FDQ, fcc)                                           \
2677                     {                                                   \
2678                         TCGv r_cond;                                    \
2679                         int l1;                                         \
2680                                                                         \
2681                         l1 = gen_new_label();                           \
2682                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2683                         cond = GET_FIELD_SP(insn, 14, 17);              \
2684                         gen_fcond(r_cond, fcc, cond);                   \
2685                         tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,          \
2686                                           tcg_const_tl(0), l1);         \
2687                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2688                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2689                         gen_set_label(l1);                              \
2690                     }
2691                     case 0x001: /* V9 fmovscc %fcc0 */
2692                         FMOVCC(F, 0);
2693                         break;
2694                     case 0x002: /* V9 fmovdcc %fcc0 */
2695                         FMOVCC(D, 0);
2696                         break;
2697                     case 0x003: /* V9 fmovqcc %fcc0 */
2698 #if defined(CONFIG_USER_ONLY)
2699                         FMOVCC(Q, 0);
2700                         break;
2701 #else
2702                         goto nfpu_insn;
2703 #endif
2704                     case 0x041: /* V9 fmovscc %fcc1 */
2705                         FMOVCC(F, 1);
2706                         break;
2707                     case 0x042: /* V9 fmovdcc %fcc1 */
2708                         FMOVCC(D, 1);
2709                         break;
2710                     case 0x043: /* V9 fmovqcc %fcc1 */
2711 #if defined(CONFIG_USER_ONLY)
2712                         FMOVCC(Q, 1);
2713                         break;
2714 #else
2715                         goto nfpu_insn;
2716 #endif
2717                     case 0x081: /* V9 fmovscc %fcc2 */
2718                         FMOVCC(F, 2);
2719                         break;
2720                     case 0x082: /* V9 fmovdcc %fcc2 */
2721                         FMOVCC(D, 2);
2722                         break;
2723                     case 0x083: /* V9 fmovqcc %fcc2 */
2724 #if defined(CONFIG_USER_ONLY)
2725                         FMOVCC(Q, 2);
2726                         break;
2727 #else
2728                         goto nfpu_insn;
2729 #endif
2730                     case 0x0c1: /* V9 fmovscc %fcc3 */
2731                         FMOVCC(F, 3);
2732                         break;
2733                     case 0x0c2: /* V9 fmovdcc %fcc3 */
2734                         FMOVCC(D, 3);
2735                         break;
2736                     case 0x0c3: /* V9 fmovqcc %fcc3 */
2737 #if defined(CONFIG_USER_ONLY)
2738                         FMOVCC(Q, 3);
2739                         break;
2740 #else
2741                         goto nfpu_insn;
2742 #endif
2743 #undef FMOVCC
2744 #define FMOVCC(size_FDQ, icc)                                           \
2745                     {                                                   \
2746                         TCGv r_cond;                                    \
2747                         int l1;                                         \
2748                                                                         \
2749                         l1 = gen_new_label();                           \
2750                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2751                         cond = GET_FIELD_SP(insn, 14, 17);              \
2752                         gen_cond(r_cond, icc, cond);                    \
2753                         tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,          \
2754                                           tcg_const_tl(0), l1);         \
2755                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2756                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2757                         gen_set_label(l1);                              \
2758                     }
2759
2760                     case 0x101: /* V9 fmovscc %icc */
2761                         FMOVCC(F, 0);
2762                         break;
2763                     case 0x102: /* V9 fmovdcc %icc */
2764                         FMOVCC(D, 0);
2765                     case 0x103: /* V9 fmovqcc %icc */
2766 #if defined(CONFIG_USER_ONLY)
2767                         FMOVCC(D, 0);
2768                         break;
2769 #else
2770                         goto nfpu_insn;
2771 #endif
2772                     case 0x181: /* V9 fmovscc %xcc */
2773                         FMOVCC(F, 1);
2774                         break;
2775                     case 0x182: /* V9 fmovdcc %xcc */
2776                         FMOVCC(D, 1);
2777                         break;
2778                     case 0x183: /* V9 fmovqcc %xcc */
2779 #if defined(CONFIG_USER_ONLY)
2780                         FMOVCC(Q, 1);
2781                         break;
2782 #else
2783                         goto nfpu_insn;
2784 #endif
2785 #undef FMOVCC
2786 #endif
2787                     case 0x51: /* fcmps, V9 %fcc */
2788                         gen_op_load_fpr_FT0(rs1);
2789                         gen_op_load_fpr_FT1(rs2);
2790                         gen_op_fcmps(rd & 3);
2791                         break;
2792                     case 0x52: /* fcmpd, V9 %fcc */
2793                         gen_op_load_fpr_DT0(DFPREG(rs1));
2794                         gen_op_load_fpr_DT1(DFPREG(rs2));
2795                         gen_op_fcmpd(rd & 3);
2796                         break;
2797                     case 0x53: /* fcmpq, V9 %fcc */
2798 #if defined(CONFIG_USER_ONLY)
2799                         gen_op_load_fpr_QT0(QFPREG(rs1));
2800                         gen_op_load_fpr_QT1(QFPREG(rs2));
2801                         gen_op_fcmpq(rd & 3);
2802                         break;
2803 #else /* !defined(CONFIG_USER_ONLY) */
2804                         goto nfpu_insn;
2805 #endif
2806                     case 0x55: /* fcmpes, V9 %fcc */
2807                         gen_op_load_fpr_FT0(rs1);
2808                         gen_op_load_fpr_FT1(rs2);
2809                         gen_op_fcmpes(rd & 3);
2810                         break;
2811                     case 0x56: /* fcmped, V9 %fcc */
2812                         gen_op_load_fpr_DT0(DFPREG(rs1));
2813                         gen_op_load_fpr_DT1(DFPREG(rs2));
2814                         gen_op_fcmped(rd & 3);
2815                         break;
2816                     case 0x57: /* fcmpeq, V9 %fcc */
2817 #if defined(CONFIG_USER_ONLY)
2818                         gen_op_load_fpr_QT0(QFPREG(rs1));
2819                         gen_op_load_fpr_QT1(QFPREG(rs2));
2820                         gen_op_fcmpeq(rd & 3);
2821                         break;
2822 #else/* !defined(CONFIG_USER_ONLY) */
2823                         goto nfpu_insn;
2824 #endif
2825                     default:
2826                         goto illegal_insn;
2827                 }
2828             } else if (xop == 0x2) {
2829                 // clr/mov shortcut
2830
2831                 rs1 = GET_FIELD(insn, 13, 17);
2832                 if (rs1 == 0) {
2833                     // or %g0, x, y -> mov T0, x; mov y, T0
2834                     if (IS_IMM) {       /* immediate */
2835                         rs2 = GET_FIELDs(insn, 19, 31);
2836                         tcg_gen_movi_tl(cpu_dst, (int)rs2);
2837                     } else {            /* register */
2838                         rs2 = GET_FIELD(insn, 27, 31);
2839                         gen_movl_reg_TN(rs2, cpu_dst);
2840                     }
2841                 } else {
2842                     cpu_src1 = get_src1(insn, cpu_src1);
2843                     if (IS_IMM) {       /* immediate */
2844                         rs2 = GET_FIELDs(insn, 19, 31);
2845                         tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2846                     } else {            /* register */
2847                         // or x, %g0, y -> mov T1, x; mov y, T1
2848                         rs2 = GET_FIELD(insn, 27, 31);
2849                         if (rs2 != 0) {
2850                             gen_movl_reg_TN(rs2, cpu_src2);
2851                             tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2852                         }
2853                     }
2854                 }
2855                 gen_movl_TN_reg(rd, cpu_dst);
2856 #ifdef TARGET_SPARC64
2857             } else if (xop == 0x25) { /* sll, V9 sllx */
2858                 cpu_src1 = get_src1(insn, cpu_src1);
2859                 if (IS_IMM) {   /* immediate */
2860                     rs2 = GET_FIELDs(insn, 20, 31);
2861                     if (insn & (1 << 12)) {
2862                         tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2863                     } else {
2864                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2865                         tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2866                     }
2867                 } else {                /* register */
2868                     rs2 = GET_FIELD(insn, 27, 31);
2869                     gen_movl_reg_TN(rs2, cpu_src2);
2870                     if (insn & (1 << 12)) {
2871                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2872                         tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2873                     } else {
2874                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2875                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2876                         tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2877                     }
2878                 }
2879                 gen_movl_TN_reg(rd, cpu_dst);
2880             } else if (xop == 0x26) { /* srl, V9 srlx */
2881                 cpu_src1 = get_src1(insn, cpu_src1);
2882                 if (IS_IMM) {   /* immediate */
2883                     rs2 = GET_FIELDs(insn, 20, 31);
2884                     if (insn & (1 << 12)) {
2885                         tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2886                     } else {
2887                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2888                         tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2889                     }
2890                 } else {                /* register */
2891                     rs2 = GET_FIELD(insn, 27, 31);
2892                     gen_movl_reg_TN(rs2, cpu_src2);
2893                     if (insn & (1 << 12)) {
2894                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2895                         tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2896                     } else {
2897                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2898                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2899                         tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2900                     }
2901                 }
2902                 gen_movl_TN_reg(rd, cpu_dst);
2903             } else if (xop == 0x27) { /* sra, V9 srax */
2904                 cpu_src1 = get_src1(insn, cpu_src1);
2905                 if (IS_IMM) {   /* immediate */
2906                     rs2 = GET_FIELDs(insn, 20, 31);
2907                     if (insn & (1 << 12)) {
2908                         tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2909                     } else {
2910                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2911                         tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2912                         tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2913                     }
2914                 } else {                /* register */
2915                     rs2 = GET_FIELD(insn, 27, 31);
2916                     gen_movl_reg_TN(rs2, cpu_src2);
2917                     if (insn & (1 << 12)) {
2918                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2919                         tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2920                     } else {
2921                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2922                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2923                         tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2924                     }
2925                 }
2926                 gen_movl_TN_reg(rd, cpu_dst);
2927 #endif
2928             } else if (xop < 0x36) {
2929                 cpu_src1 = get_src1(insn, cpu_src1);
2930                 cpu_src2 = get_src2(insn, cpu_src2);
2931                 if (xop < 0x20) {
2932                     switch (xop & ~0x10) {
2933                     case 0x0:
2934                         if (xop & 0x10)
2935                             gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2936                         else
2937                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2938                         break;
2939                     case 0x1:
2940                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2941                         if (xop & 0x10)
2942                             gen_op_logic_cc(cpu_dst);
2943                         break;
2944                     case 0x2:
2945                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2946                         if (xop & 0x10)
2947                             gen_op_logic_cc(cpu_dst);
2948                         break;
2949                     case 0x3:
2950                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
2951                         if (xop & 0x10)
2952                             gen_op_logic_cc(cpu_dst);
2953                         break;
2954                     case 0x4:
2955                         if (xop & 0x10)
2956                             gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
2957                         else
2958                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
2959                         break;
2960                     case 0x5:
2961                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2962                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
2963                         if (xop & 0x10)
2964                             gen_op_logic_cc(cpu_dst);
2965                         break;
2966                     case 0x6:
2967                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2968                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
2969                         if (xop & 0x10)
2970                             gen_op_logic_cc(cpu_dst);
2971                         break;
2972                     case 0x7:
2973                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2974                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
2975                         if (xop & 0x10)
2976                             gen_op_logic_cc(cpu_dst);
2977                         break;
2978                     case 0x8:
2979                         if (xop & 0x10)
2980                             gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
2981                         else {
2982                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
2983                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
2984                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
2985                         }
2986                         break;
2987 #ifdef TARGET_SPARC64
2988                     case 0x9: /* V9 mulx */
2989                         tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
2990                         break;
2991 #endif
2992                     case 0xa:
2993                         gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
2994                         if (xop & 0x10)
2995                             gen_op_logic_cc(cpu_dst);
2996                         break;
2997                     case 0xb:
2998                         gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
2999                         if (xop & 0x10)
3000                             gen_op_logic_cc(cpu_dst);
3001                         break;
3002                     case 0xc:
3003                         if (xop & 0x10)
3004                             gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3005                         else {
3006                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3007                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3008                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3009                         }
3010                         break;
3011 #ifdef TARGET_SPARC64
3012                     case 0xd: /* V9 udivx */
3013                         gen_trap_ifdivzero_tl(cpu_src2);
3014                         tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2);
3015                         break;
3016 #endif
3017                     case 0xe:
3018                         tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, cpu_src2);
3019                         if (xop & 0x10)
3020                             gen_op_div_cc(cpu_dst);
3021                         break;
3022                     case 0xf:
3023                         tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, cpu_src2);
3024                         if (xop & 0x10)
3025                             gen_op_div_cc(cpu_dst);
3026                         break;
3027                     default:
3028                         goto illegal_insn;
3029                     }
3030                     gen_movl_TN_reg(rd, cpu_dst);
3031                 } else {
3032                     switch (xop) {
3033                     case 0x20: /* taddcc */
3034                         gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3035                         gen_movl_TN_reg(rd, cpu_dst);
3036                         break;
3037                     case 0x21: /* tsubcc */
3038                         gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3039                         gen_movl_TN_reg(rd, cpu_dst);
3040                         break;
3041                     case 0x22: /* taddcctv */
3042                         save_state(dc, cpu_cond);
3043                         gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3044                         gen_movl_TN_reg(rd, cpu_dst);
3045                         break;
3046                     case 0x23: /* tsubcctv */
3047                         save_state(dc, cpu_cond);
3048                         gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3049                         gen_movl_TN_reg(rd, cpu_dst);
3050                         break;
3051                     case 0x24: /* mulscc */
3052                         gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3053                         gen_movl_TN_reg(rd, cpu_dst);
3054                         break;
3055 #ifndef TARGET_SPARC64
3056                     case 0x25:  /* sll */
3057                         tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3058                         tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3059                         gen_movl_TN_reg(rd, cpu_dst);
3060                         break;
3061                     case 0x26:  /* srl */
3062                         tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3063                         tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3064                         gen_movl_TN_reg(rd, cpu_dst);
3065                         break;
3066                     case 0x27:  /* sra */
3067                         tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3068                         tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3069                         gen_movl_TN_reg(rd, cpu_dst);
3070                         break;
3071 #endif
3072                     case 0x30:
3073                         {
3074                             switch(rd) {
3075                             case 0: /* wry */
3076                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3077                                 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
3078                                 break;
3079 #ifndef TARGET_SPARC64
3080                             case 0x01 ... 0x0f: /* undefined in the
3081                                                    SPARCv8 manual, nop
3082                                                    on the microSPARC
3083                                                    II */
3084                             case 0x10 ... 0x1f: /* implementation-dependent
3085                                                    in the SPARCv8
3086                                                    manual, nop on the
3087                                                    microSPARC II */
3088                                 break;
3089 #else
3090                             case 0x2: /* V9 wrccr */
3091                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3092                                 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3093                                 break;
3094                             case 0x3: /* V9 wrasi */
3095                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3096                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3097                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
3098                                 break;
3099                             case 0x6: /* V9 wrfprs */
3100                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3101                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3102                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
3103                                 save_state(dc, cpu_cond);
3104                                 gen_op_next_insn();
3105                                 tcg_gen_exit_tb(0);
3106                                 dc->is_br = 1;
3107                                 break;
3108                             case 0xf: /* V9 sir, nop if user */
3109 #if !defined(CONFIG_USER_ONLY)
3110                                 if (supervisor(dc))
3111                                     ; // XXX
3112 #endif
3113                                 break;
3114                             case 0x13: /* Graphics Status */
3115                                 if (gen_trap_ifnofpu(dc, cpu_cond))
3116                                     goto jmp_insn;
3117                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3118                                 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
3119                                 break;
3120                             case 0x17: /* Tick compare */
3121 #if !defined(CONFIG_USER_ONLY)
3122                                 if (!supervisor(dc))
3123                                     goto illegal_insn;
3124 #endif
3125                                 {
3126                                     TCGv r_tickptr;
3127
3128                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3129                                                    cpu_src2);
3130                                     tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3131                                                                  tick_cmpr));
3132                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3133                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3134                                                    offsetof(CPUState, tick));
3135                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3136                                                        r_tickptr, cpu_dst);
3137                                 }
3138                                 break;
3139                             case 0x18: /* System tick */
3140 #if !defined(CONFIG_USER_ONLY)
3141                                 if (!supervisor(dc))
3142                                     goto illegal_insn;
3143 #endif
3144                                 {
3145                                     TCGv r_tickptr;
3146
3147                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3148                                                    cpu_src2);
3149                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3150                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3151                                                    offsetof(CPUState, stick));
3152                                     tcg_gen_helper_0_2(helper_tick_set_count,
3153                                                        r_tickptr, cpu_dst);
3154                                 }
3155                                 break;
3156                             case 0x19: /* System tick compare */
3157 #if !defined(CONFIG_USER_ONLY)
3158                                 if (!supervisor(dc))
3159                                     goto illegal_insn;
3160 #endif
3161                                 {
3162                                     TCGv r_tickptr;
3163
3164                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3165                                                    cpu_src2);
3166                                     tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3167                                                                  stick_cmpr));
3168                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3169                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3170                                                    offsetof(CPUState, stick));
3171                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3172                                                        r_tickptr, cpu_dst);
3173                                 }
3174                                 break;
3175
3176                             case 0x10: /* Performance Control */
3177                             case 0x11: /* Performance Instrumentation Counter */
3178                             case 0x12: /* Dispatch Control */
3179                             case 0x14: /* Softint set */
3180                             case 0x15: /* Softint clear */
3181                             case 0x16: /* Softint write */
3182 #endif
3183                             default:
3184                                 goto illegal_insn;
3185                             }
3186                         }
3187                         break;
3188 #if !defined(CONFIG_USER_ONLY)
3189                     case 0x31: /* wrpsr, V9 saved, restored */
3190                         {
3191                             if (!supervisor(dc))
3192                                 goto priv_insn;
3193 #ifdef TARGET_SPARC64
3194                             switch (rd) {
3195                             case 0:
3196                                 tcg_gen_helper_0_0(helper_saved);
3197                                 break;
3198                             case 1:
3199                                 tcg_gen_helper_0_0(helper_restored);
3200                                 break;
3201                             case 2: /* UA2005 allclean */
3202                             case 3: /* UA2005 otherw */
3203                             case 4: /* UA2005 normalw */
3204                             case 5: /* UA2005 invalw */
3205                                 // XXX
3206                             default:
3207                                 goto illegal_insn;
3208                             }
3209 #else
3210                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3211                             tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3212                             save_state(dc, cpu_cond);
3213                             gen_op_next_insn();
3214                             tcg_gen_exit_tb(0);
3215                             dc->is_br = 1;
3216 #endif
3217                         }
3218                         break;
3219                     case 0x32: /* wrwim, V9 wrpr */
3220                         {
3221                             if (!supervisor(dc))
3222                                 goto priv_insn;
3223                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3224 #ifdef TARGET_SPARC64
3225                             switch (rd) {
3226                             case 0: // tpc
3227                                 {
3228                                     TCGv r_tsptr;
3229
3230                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3231                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3232                                                    offsetof(CPUState, tsptr));
3233                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3234                                                   offsetof(trap_state, tpc));
3235                                 }
3236                                 break;
3237                             case 1: // tnpc
3238                                 {
3239                                     TCGv r_tsptr;
3240
3241                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3242                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3243                                                    offsetof(CPUState, tsptr));
3244                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3245                                                   offsetof(trap_state, tnpc));
3246                                 }
3247                                 break;
3248                             case 2: // tstate
3249                                 {
3250                                     TCGv r_tsptr;
3251
3252                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3253                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3254                                                    offsetof(CPUState, tsptr));
3255                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3256                                                   offsetof(trap_state, tstate));
3257                                 }
3258                                 break;
3259                             case 3: // tt
3260                                 {
3261                                     TCGv r_tsptr;
3262
3263                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3264                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3265                                                    offsetof(CPUState, tsptr));
3266                                     tcg_gen_st_i32(cpu_dst, r_tsptr,
3267                                                    offsetof(trap_state, tt));
3268                                 }
3269                                 break;
3270                             case 4: // tick
3271                                 {
3272                                     TCGv r_tickptr;
3273
3274                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3275                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3276                                                    offsetof(CPUState, tick));
3277                                     tcg_gen_helper_0_2(helper_tick_set_count,
3278                                                        r_tickptr, cpu_dst);
3279                                 }
3280                                 break;
3281                             case 5: // tba
3282                                 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
3283                                 break;
3284                             case 6: // pstate
3285                                 save_state(dc, cpu_cond);
3286                                 tcg_gen_helper_0_1(helper_wrpstate, cpu_dst);
3287                                 gen_op_next_insn();
3288                                 tcg_gen_exit_tb(0);
3289                                 dc->is_br = 1;
3290                                 break;
3291                             case 7: // tl
3292                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3293                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
3294                                 break;
3295                             case 8: // pil
3296                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3297                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
3298                                 break;
3299                             case 9: // cwp
3300                                 tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
3301                                 break;
3302                             case 10: // cansave
3303                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3304                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
3305                                 break;
3306                             case 11: // canrestore
3307                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3308                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
3309                                 break;
3310                             case 12: // cleanwin
3311                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3312                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
3313                                 break;
3314                             case 13: // otherwin
3315                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3316                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
3317                                 break;
3318                             case 14: // wstate
3319                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3320                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
3321                                 break;
3322                             case 16: // UA2005 gl
3323                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3324                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
3325                                 break;
3326                             case 26: // UA2005 strand status
3327                                 if (!hypervisor(dc))
3328                                     goto priv_insn;
3329                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3330                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
3331                                 break;
3332                             default:
3333                                 goto illegal_insn;
3334                             }
3335 #else
3336                             tcg_gen_andi_tl(cpu_dst, cpu_dst, ((1 << NWINDOWS) - 1));
3337                             tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3338                             tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
3339 #endif
3340                         }
3341                         break;
3342                     case 0x33: /* wrtbr, UA2005 wrhpr */
3343                         {
3344 #ifndef TARGET_SPARC64
3345                             if (!supervisor(dc))
3346                                 goto priv_insn;
3347                             tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3348                             tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
3349 #else
3350                             if (!hypervisor(dc))
3351                                 goto priv_insn;
3352                             tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3353                             switch (rd) {
3354                             case 0: // hpstate
3355                                 // XXX gen_op_wrhpstate();
3356                                 save_state(dc, cpu_cond);
3357                                 gen_op_next_insn();
3358                                 tcg_gen_exit_tb(0);
3359                                 dc->is_br = 1;
3360                                 break;
3361                             case 1: // htstate
3362                                 // XXX gen_op_wrhtstate();
3363                                 break;
3364                             case 3: // hintp
3365                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3366                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
3367                                 break;
3368                             case 5: // htba
3369                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3370                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
3371                                 break;
3372                             case 31: // hstick_cmpr
3373                                 {
3374                                     TCGv r_tickptr;
3375
3376                                     tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3377                                                                  hstick_cmpr));
3378                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3379                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3380                                                    offsetof(CPUState, hstick));
3381                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3382                                                        r_tickptr, cpu_dst);
3383                                 }
3384                                 break;
3385                             case 6: // hver readonly
3386                             default:
3387                                 goto illegal_insn;
3388                             }
3389 #endif
3390                         }
3391                         break;
3392 #endif
3393 #ifdef TARGET_SPARC64
3394                     case 0x2c: /* V9 movcc */
3395                         {
3396                             int cc = GET_FIELD_SP(insn, 11, 12);
3397                             int cond = GET_FIELD_SP(insn, 14, 17);
3398                             TCGv r_cond;
3399                             int l1;
3400
3401                             r_cond = tcg_temp_new(TCG_TYPE_TL);
3402                             if (insn & (1 << 18)) {
3403                                 if (cc == 0)
3404                                     gen_cond(r_cond, 0, cond);
3405                                 else if (cc == 2)
3406                                     gen_cond(r_cond, 1, cond);
3407                                 else
3408                                     goto illegal_insn;
3409                             } else {
3410                                 gen_fcond(r_cond, cc, cond);
3411                             }
3412
3413                             l1 = gen_new_label();
3414
3415                             tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,
3416                                               tcg_const_tl(0), l1);
3417                             if (IS_IMM) {       /* immediate */
3418                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
3419                                 tcg_gen_movi_tl(cpu_dst, (int)rs2);
3420                             } else {
3421                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3422                                 gen_movl_reg_TN(rs2, cpu_dst);
3423                             }
3424                             gen_movl_TN_reg(rd, cpu_dst);
3425                             gen_set_label(l1);
3426                             break;
3427                         }
3428                     case 0x2d: /* V9 sdivx */
3429                         gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3430                         gen_movl_TN_reg(rd, cpu_dst);
3431                         break;
3432                     case 0x2e: /* V9 popc */
3433                         {
3434                             cpu_src2 = get_src2(insn, cpu_src2);
3435                             tcg_gen_helper_1_1(helper_popc, cpu_dst,
3436                                                cpu_src2);
3437                             gen_movl_TN_reg(rd, cpu_dst);
3438                         }
3439                     case 0x2f: /* V9 movr */
3440                         {
3441                             int cond = GET_FIELD_SP(insn, 10, 12);
3442                             int l1;
3443
3444                             cpu_src1 = get_src1(insn, cpu_src1);
3445
3446                             l1 = gen_new_label();
3447
3448                             tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
3449                                               tcg_const_tl(0), l1);
3450                             if (IS_IMM) {       /* immediate */
3451                                 rs2 = GET_FIELD_SPs(insn, 0, 9);
3452                                 tcg_gen_movi_tl(cpu_dst, (int)rs2);
3453                             } else {
3454                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3455                                 gen_movl_reg_TN(rs2, cpu_dst);
3456                             }
3457                             gen_movl_TN_reg(rd, cpu_dst);
3458                             gen_set_label(l1);
3459                             break;
3460                         }
3461 #endif
3462                     default:
3463                         goto illegal_insn;
3464                     }
3465                 }
3466             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3467 #ifdef TARGET_SPARC64
3468                 int opf = GET_FIELD_SP(insn, 5, 13);
3469                 rs1 = GET_FIELD(insn, 13, 17);
3470                 rs2 = GET_FIELD(insn, 27, 31);
3471                 if (gen_trap_ifnofpu(dc, cpu_cond))
3472                     goto jmp_insn;
3473
3474                 switch (opf) {
3475                 case 0x000: /* VIS I edge8cc */
3476                 case 0x001: /* VIS II edge8n */
3477                 case 0x002: /* VIS I edge8lcc */
3478                 case 0x003: /* VIS II edge8ln */
3479                 case 0x004: /* VIS I edge16cc */
3480                 case 0x005: /* VIS II edge16n */
3481                 case 0x006: /* VIS I edge16lcc */
3482                 case 0x007: /* VIS II edge16ln */
3483                 case 0x008: /* VIS I edge32cc */
3484                 case 0x009: /* VIS II edge32n */
3485                 case 0x00a: /* VIS I edge32lcc */
3486                 case 0x00b: /* VIS II edge32ln */
3487                     // XXX
3488                     goto illegal_insn;
3489                 case 0x010: /* VIS I array8 */
3490                     cpu_src1 = get_src1(insn, cpu_src1);
3491                     gen_movl_reg_TN(rs2, cpu_src2);
3492                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3493                                        cpu_src2);
3494                     gen_movl_TN_reg(rd, cpu_dst);
3495                     break;
3496                 case 0x012: /* VIS I array16 */
3497                     cpu_src1 = get_src1(insn, cpu_src1);
3498                     gen_movl_reg_TN(rs2, cpu_src2);
3499                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3500                                        cpu_src2);
3501                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3502                     gen_movl_TN_reg(rd, cpu_dst);
3503                     break;
3504                 case 0x014: /* VIS I array32 */
3505                     cpu_src1 = get_src1(insn, cpu_src1);
3506                     gen_movl_reg_TN(rs2, cpu_src2);
3507                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3508                                        cpu_src2);
3509                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3510                     gen_movl_TN_reg(rd, cpu_dst);
3511                     break;
3512                 case 0x018: /* VIS I alignaddr */
3513                     cpu_src1 = get_src1(insn, cpu_src1);
3514                     gen_movl_reg_TN(rs2, cpu_src2);
3515                     tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3516                                        cpu_src2);
3517                     gen_movl_TN_reg(rd, cpu_dst);
3518                     break;
3519                 case 0x019: /* VIS II bmask */
3520                 case 0x01a: /* VIS I alignaddrl */
3521                     // XXX
3522                     goto illegal_insn;
3523                 case 0x020: /* VIS I fcmple16 */
3524                     gen_op_load_fpr_DT0(DFPREG(rs1));
3525                     gen_op_load_fpr_DT1(DFPREG(rs2));
3526                     tcg_gen_helper_0_0(helper_fcmple16);
3527                     gen_op_store_DT0_fpr(DFPREG(rd));
3528                     break;
3529                 case 0x022: /* VIS I fcmpne16 */
3530                     gen_op_load_fpr_DT0(DFPREG(rs1));
3531                     gen_op_load_fpr_DT1(DFPREG(rs2));
3532                     tcg_gen_helper_0_0(helper_fcmpne16);
3533                     gen_op_store_DT0_fpr(DFPREG(rd));
3534                     break;
3535                 case 0x024: /* VIS I fcmple32 */
3536                     gen_op_load_fpr_DT0(DFPREG(rs1));
3537                     gen_op_load_fpr_DT1(DFPREG(rs2));
3538                     tcg_gen_helper_0_0(helper_fcmple32);
3539                     gen_op_store_DT0_fpr(DFPREG(rd));
3540                     break;
3541                 case 0x026: /* VIS I fcmpne32 */
3542                     gen_op_load_fpr_DT0(DFPREG(rs1));
3543                     gen_op_load_fpr_DT1(DFPREG(rs2));
3544                     tcg_gen_helper_0_0(helper_fcmpne32);
3545                     gen_op_store_DT0_fpr(DFPREG(rd));
3546                     break;
3547                 case 0x028: /* VIS I fcmpgt16 */
3548                     gen_op_load_fpr_DT0(DFPREG(rs1));
3549                     gen_op_load_fpr_DT1(DFPREG(rs2));
3550                     tcg_gen_helper_0_0(helper_fcmpgt16);
3551                     gen_op_store_DT0_fpr(DFPREG(rd));
3552                     break;
3553                 case 0x02a: /* VIS I fcmpeq16 */
3554                     gen_op_load_fpr_DT0(DFPREG(rs1));
3555                     gen_op_load_fpr_DT1(DFPREG(rs2));
3556                     tcg_gen_helper_0_0(helper_fcmpeq16);
3557                     gen_op_store_DT0_fpr(DFPREG(rd));
3558                     break;
3559                 case 0x02c: /* VIS I fcmpgt32 */
3560                     gen_op_load_fpr_DT0(DFPREG(rs1));
3561                     gen_op_load_fpr_DT1(DFPREG(rs2));
3562                     tcg_gen_helper_0_0(helper_fcmpgt32);
3563                     gen_op_store_DT0_fpr(DFPREG(rd));
3564                     break;
3565                 case 0x02e: /* VIS I fcmpeq32 */
3566                     gen_op_load_fpr_DT0(DFPREG(rs1));
3567                     gen_op_load_fpr_DT1(DFPREG(rs2));
3568                     tcg_gen_helper_0_0(helper_fcmpeq32);
3569                     gen_op_store_DT0_fpr(DFPREG(rd));
3570                     break;
3571                 case 0x031: /* VIS I fmul8x16 */
3572                     gen_op_load_fpr_DT0(DFPREG(rs1));
3573                     gen_op_load_fpr_DT1(DFPREG(rs2));
3574                     tcg_gen_helper_0_0(helper_fmul8x16);
3575                     gen_op_store_DT0_fpr(DFPREG(rd));
3576                     break;
3577                 case 0x033: /* VIS I fmul8x16au */
3578                     gen_op_load_fpr_DT0(DFPREG(rs1));
3579                     gen_op_load_fpr_DT1(DFPREG(rs2));
3580                     tcg_gen_helper_0_0(helper_fmul8x16au);
3581                     gen_op_store_DT0_fpr(DFPREG(rd));
3582                     break;
3583                 case 0x035: /* VIS I fmul8x16al */
3584                     gen_op_load_fpr_DT0(DFPREG(rs1));
3585                     gen_op_load_fpr_DT1(DFPREG(rs2));
3586                     tcg_gen_helper_0_0(helper_fmul8x16al);
3587                     gen_op_store_DT0_fpr(DFPREG(rd));
3588                     break;
3589                 case 0x036: /* VIS I fmul8sux16 */
3590                     gen_op_load_fpr_DT0(DFPREG(rs1));
3591                     gen_op_load_fpr_DT1(DFPREG(rs2));
3592                     tcg_gen_helper_0_0(helper_fmul8sux16);
3593                     gen_op_store_DT0_fpr(DFPREG(rd));
3594                     break;
3595                 case 0x037: /* VIS I fmul8ulx16 */
3596                     gen_op_load_fpr_DT0(DFPREG(rs1));
3597                     gen_op_load_fpr_DT1(DFPREG(rs2));
3598                     tcg_gen_helper_0_0(helper_fmul8ulx16);
3599                     gen_op_store_DT0_fpr(DFPREG(rd));
3600                     break;
3601                 case 0x038: /* VIS I fmuld8sux16 */
3602                     gen_op_load_fpr_DT0(DFPREG(rs1));
3603                     gen_op_load_fpr_DT1(DFPREG(rs2));
3604                     tcg_gen_helper_0_0(helper_fmuld8sux16);
3605                     gen_op_store_DT0_fpr(DFPREG(rd));
3606                     break;
3607                 case 0x039: /* VIS I fmuld8ulx16 */
3608                     gen_op_load_fpr_DT0(DFPREG(rs1));
3609                     gen_op_load_fpr_DT1(DFPREG(rs2));
3610                     tcg_gen_helper_0_0(helper_fmuld8ulx16);
3611                     gen_op_store_DT0_fpr(DFPREG(rd));
3612                     break;
3613                 case 0x03a: /* VIS I fpack32 */
3614                 case 0x03b: /* VIS I fpack16 */
3615                 case 0x03d: /* VIS I fpackfix */
3616                 case 0x03e: /* VIS I pdist */
3617                     // XXX
3618                     goto illegal_insn;
3619                 case 0x048: /* VIS I faligndata */
3620                     gen_op_load_fpr_DT0(DFPREG(rs1));
3621                     gen_op_load_fpr_DT1(DFPREG(rs2));
3622                     tcg_gen_helper_0_0(helper_faligndata);
3623                     gen_op_store_DT0_fpr(DFPREG(rd));
3624                     break;
3625                 case 0x04b: /* VIS I fpmerge */
3626                     gen_op_load_fpr_DT0(DFPREG(rs1));
3627                     gen_op_load_fpr_DT1(DFPREG(rs2));
3628                     tcg_gen_helper_0_0(helper_fpmerge);
3629                     gen_op_store_DT0_fpr(DFPREG(rd));
3630                     break;
3631                 case 0x04c: /* VIS II bshuffle */
3632                     // XXX
3633                     goto illegal_insn;
3634                 case 0x04d: /* VIS I fexpand */
3635                     gen_op_load_fpr_DT0(DFPREG(rs1));
3636                     gen_op_load_fpr_DT1(DFPREG(rs2));
3637                     tcg_gen_helper_0_0(helper_fexpand);
3638                     gen_op_store_DT0_fpr(DFPREG(rd));
3639                     break;
3640                 case 0x050: /* VIS I fpadd16 */
3641                     gen_op_load_fpr_DT0(DFPREG(rs1));
3642                     gen_op_load_fpr_DT1(DFPREG(rs2));
3643                     tcg_gen_helper_0_0(helper_fpadd16);
3644                     gen_op_store_DT0_fpr(DFPREG(rd));
3645                     break;
3646                 case 0x051: /* VIS I fpadd16s */
3647                     gen_op_load_fpr_FT0(rs1);
3648                     gen_op_load_fpr_FT1(rs2);
3649                     tcg_gen_helper_0_0(helper_fpadd16s);
3650                     gen_op_store_FT0_fpr(rd);
3651                     break;
3652                 case 0x052: /* VIS I fpadd32 */
3653                     gen_op_load_fpr_DT0(DFPREG(rs1));
3654                     gen_op_load_fpr_DT1(DFPREG(rs2));
3655                     tcg_gen_helper_0_0(helper_fpadd32);
3656                     gen_op_store_DT0_fpr(DFPREG(rd));
3657                     break;
3658                 case 0x053: /* VIS I fpadd32s */
3659                     gen_op_load_fpr_FT0(rs1);
3660                     gen_op_load_fpr_FT1(rs2);
3661                     tcg_gen_helper_0_0(helper_fpadd32s);
3662                     gen_op_store_FT0_fpr(rd);
3663                     break;
3664                 case 0x054: /* VIS I fpsub16 */
3665                     gen_op_load_fpr_DT0(DFPREG(rs1));
3666                     gen_op_load_fpr_DT1(DFPREG(rs2));
3667                     tcg_gen_helper_0_0(helper_fpsub16);
3668                     gen_op_store_DT0_fpr(DFPREG(rd));
3669                     break;
3670                 case 0x055: /* VIS I fpsub16s */
3671                     gen_op_load_fpr_FT0(rs1);
3672                     gen_op_load_fpr_FT1(rs2);
3673                     tcg_gen_helper_0_0(helper_fpsub16s);
3674                     gen_op_store_FT0_fpr(rd);
3675                     break;
3676                 case 0x056: /* VIS I fpsub32 */
3677                     gen_op_load_fpr_DT0(DFPREG(rs1));
3678                     gen_op_load_fpr_DT1(DFPREG(rs2));
3679                     tcg_gen_helper_0_0(helper_fpadd32);
3680                     gen_op_store_DT0_fpr(DFPREG(rd));
3681                     break;
3682                 case 0x057: /* VIS I fpsub32s */
3683                     gen_op_load_fpr_FT0(rs1);
3684                     gen_op_load_fpr_FT1(rs2);
3685                     tcg_gen_helper_0_0(helper_fpsub32s);
3686                     gen_op_store_FT0_fpr(rd);
3687                     break;
3688                 case 0x060: /* VIS I fzero */
3689                     tcg_gen_helper_0_0(helper_movl_DT0_0);
3690                     gen_op_store_DT0_fpr(DFPREG(rd));
3691                     break;
3692                 case 0x061: /* VIS I fzeros */
3693                     tcg_gen_helper_0_0(helper_movl_FT0_0);
3694                     gen_op_store_FT0_fpr(rd);
3695                     break;
3696                 case 0x062: /* VIS I fnor */
3697                     gen_op_load_fpr_DT0(DFPREG(rs1));
3698                     gen_op_load_fpr_DT1(DFPREG(rs2));
3699                     tcg_gen_helper_0_0(helper_fnor);
3700                     gen_op_store_DT0_fpr(DFPREG(rd));
3701                     break;
3702                 case 0x063: /* VIS I fnors */
3703                     gen_op_load_fpr_FT0(rs1);
3704                     gen_op_load_fpr_FT1(rs2);
3705                     tcg_gen_helper_0_0(helper_fnors);
3706                     gen_op_store_FT0_fpr(rd);
3707                     break;
3708                 case 0x064: /* VIS I fandnot2 */
3709                     gen_op_load_fpr_DT1(DFPREG(rs1));
3710                     gen_op_load_fpr_DT0(DFPREG(rs2));
3711                     tcg_gen_helper_0_0(helper_fandnot);
3712                     gen_op_store_DT0_fpr(DFPREG(rd));
3713                     break;
3714                 case 0x065: /* VIS I fandnot2s */
3715                     gen_op_load_fpr_FT1(rs1);
3716                     gen_op_load_fpr_FT0(rs2);
3717                     tcg_gen_helper_0_0(helper_fandnots);
3718                     gen_op_store_FT0_fpr(rd);
3719                     break;
3720                 case 0x066: /* VIS I fnot2 */
3721                     gen_op_load_fpr_DT1(DFPREG(rs2));
3722                     tcg_gen_helper_0_0(helper_fnot);
3723                     gen_op_store_DT0_fpr(DFPREG(rd));
3724                     break;
3725                 case 0x067: /* VIS I fnot2s */
3726                     gen_op_load_fpr_FT1(rs2);
3727                     tcg_gen_helper_0_0(helper_fnot);
3728                     gen_op_store_FT0_fpr(rd);
3729                     break;
3730                 case 0x068: /* VIS I fandnot1 */
3731                     gen_op_load_fpr_DT0(DFPREG(rs1));
3732                     gen_op_load_fpr_DT1(DFPREG(rs2));
3733                     tcg_gen_helper_0_0(helper_fandnot);
3734                     gen_op_store_DT0_fpr(DFPREG(rd));
3735                     break;
3736                 case 0x069: /* VIS I fandnot1s */
3737                     gen_op_load_fpr_FT0(rs1);
3738                     gen_op_load_fpr_FT1(rs2);
3739                     tcg_gen_helper_0_0(helper_fandnots);
3740                     gen_op_store_FT0_fpr(rd);
3741                     break;
3742                 case 0x06a: /* VIS I fnot1 */
3743                     gen_op_load_fpr_DT1(DFPREG(rs1));
3744                     tcg_gen_helper_0_0(helper_fnot);
3745                     gen_op_store_DT0_fpr(DFPREG(rd));
3746                     break;
3747                 case 0x06b: /* VIS I fnot1s */
3748                     gen_op_load_fpr_FT1(rs1);
3749                     tcg_gen_helper_0_0(helper_fnot);
3750                     gen_op_store_FT0_fpr(rd);
3751                     break;
3752                 case 0x06c: /* VIS I fxor */
3753                     gen_op_load_fpr_DT0(DFPREG(rs1));
3754                     gen_op_load_fpr_DT1(DFPREG(rs2));
3755                     tcg_gen_helper_0_0(helper_fxor);
3756                     gen_op_store_DT0_fpr(DFPREG(rd));
3757                     break;
3758                 case 0x06d: /* VIS I fxors */
3759                     gen_op_load_fpr_FT0(rs1);
3760                     gen_op_load_fpr_FT1(rs2);
3761                     tcg_gen_helper_0_0(helper_fxors);
3762                     gen_op_store_FT0_fpr(rd);
3763                     break;
3764                 case 0x06e: /* VIS I fnand */
3765                     gen_op_load_fpr_DT0(DFPREG(rs1));
3766                     gen_op_load_fpr_DT1(DFPREG(rs2));
3767                     tcg_gen_helper_0_0(helper_fnand);
3768                     gen_op_store_DT0_fpr(DFPREG(rd));
3769                     break;
3770                 case 0x06f: /* VIS I fnands */
3771                     gen_op_load_fpr_FT0(rs1);
3772                     gen_op_load_fpr_FT1(rs2);
3773                     tcg_gen_helper_0_0(helper_fnands);
3774                     gen_op_store_FT0_fpr(rd);
3775                     break;
3776                 case 0x070: /* VIS I fand */
3777                     gen_op_load_fpr_DT0(DFPREG(rs1));
3778                     gen_op_load_fpr_DT1(DFPREG(rs2));
3779                     tcg_gen_helper_0_0(helper_fand);
3780                     gen_op_store_DT0_fpr(DFPREG(rd));
3781                     break;
3782                 case 0x071: /* VIS I fands */
3783                     gen_op_load_fpr_FT0(rs1);
3784                     gen_op_load_fpr_FT1(rs2);
3785                     tcg_gen_helper_0_0(helper_fands);
3786                     gen_op_store_FT0_fpr(rd);
3787                     break;
3788                 case 0x072: /* VIS I fxnor */
3789                     gen_op_load_fpr_DT0(DFPREG(rs1));
3790                     gen_op_load_fpr_DT1(DFPREG(rs2));
3791                     tcg_gen_helper_0_0(helper_fxnor);
3792                     gen_op_store_DT0_fpr(DFPREG(rd));
3793                     break;
3794                 case 0x073: /* VIS I fxnors */
3795                     gen_op_load_fpr_FT0(rs1);
3796                     gen_op_load_fpr_FT1(rs2);
3797                     tcg_gen_helper_0_0(helper_fxnors);
3798                     gen_op_store_FT0_fpr(rd);
3799                     break;
3800                 case 0x074: /* VIS I fsrc1 */
3801                     gen_op_load_fpr_DT0(DFPREG(rs1));
3802                     gen_op_store_DT0_fpr(DFPREG(rd));
3803                     break;
3804                 case 0x075: /* VIS I fsrc1s */
3805                     gen_op_load_fpr_FT0(rs1);
3806                     gen_op_store_FT0_fpr(rd);
3807                     break;
3808                 case 0x076: /* VIS I fornot2 */
3809                     gen_op_load_fpr_DT1(DFPREG(rs1));
3810                     gen_op_load_fpr_DT0(DFPREG(rs2));
3811                     tcg_gen_helper_0_0(helper_fornot);
3812                     gen_op_store_DT0_fpr(DFPREG(rd));
3813                     break;
3814                 case 0x077: /* VIS I fornot2s */
3815                     gen_op_load_fpr_FT1(rs1);
3816                     gen_op_load_fpr_FT0(rs2);
3817                     tcg_gen_helper_0_0(helper_fornots);
3818                     gen_op_store_FT0_fpr(rd);
3819                     break;
3820                 case 0x078: /* VIS I fsrc2 */
3821                     gen_op_load_fpr_DT0(DFPREG(rs2));
3822                     gen_op_store_DT0_fpr(DFPREG(rd));
3823                     break;
3824                 case 0x079: /* VIS I fsrc2s */
3825                     gen_op_load_fpr_FT0(rs2);
3826                     gen_op_store_FT0_fpr(rd);
3827                     break;
3828                 case 0x07a: /* VIS I fornot1 */
3829                     gen_op_load_fpr_DT0(DFPREG(rs1));
3830                     gen_op_load_fpr_DT1(DFPREG(rs2));
3831                     tcg_gen_helper_0_0(helper_fornot);
3832                     gen_op_store_DT0_fpr(DFPREG(rd));
3833                     break;
3834                 case 0x07b: /* VIS I fornot1s */
3835                     gen_op_load_fpr_FT0(rs1);
3836                     gen_op_load_fpr_FT1(rs2);
3837                     tcg_gen_helper_0_0(helper_fornots);
3838                     gen_op_store_FT0_fpr(rd);
3839                     break;
3840                 case 0x07c: /* VIS I for */
3841                     gen_op_load_fpr_DT0(DFPREG(rs1));
3842                     gen_op_load_fpr_DT1(DFPREG(rs2));
3843                     tcg_gen_helper_0_0(helper_for);
3844                     gen_op_store_DT0_fpr(DFPREG(rd));
3845                     break;
3846                 case 0x07d: /* VIS I fors */
3847                     gen_op_load_fpr_FT0(rs1);
3848                     gen_op_load_fpr_FT1(rs2);
3849                     tcg_gen_helper_0_0(helper_fors);
3850                     gen_op_store_FT0_fpr(rd);
3851                     break;
3852                 case 0x07e: /* VIS I fone */
3853                     tcg_gen_helper_0_0(helper_movl_DT0_1);
3854                     gen_op_store_DT0_fpr(DFPREG(rd));
3855                     break;
3856                 case 0x07f: /* VIS I fones */
3857                     tcg_gen_helper_0_0(helper_movl_FT0_1);
3858                     gen_op_store_FT0_fpr(rd);
3859                     break;
3860                 case 0x080: /* VIS I shutdown */
3861                 case 0x081: /* VIS II siam */
3862                     // XXX
3863                     goto illegal_insn;
3864                 default:
3865                     goto illegal_insn;
3866                 }
3867 #else
3868                 goto ncp_insn;
3869 #endif
3870             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
3871 #ifdef TARGET_SPARC64
3872                 goto illegal_insn;
3873 #else
3874                 goto ncp_insn;
3875 #endif
3876 #ifdef TARGET_SPARC64
3877             } else if (xop == 0x39) { /* V9 return */
3878                 save_state(dc, cpu_cond);
3879                 cpu_src1 = get_src1(insn, cpu_src1);
3880                 if (IS_IMM) {   /* immediate */
3881                     rs2 = GET_FIELDs(insn, 19, 31);
3882                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3883                 } else {                /* register */
3884                     rs2 = GET_FIELD(insn, 27, 31);
3885                     if (rs2) {
3886                         gen_movl_reg_TN(rs2, cpu_src2);
3887                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3888                     }
3889                 }
3890                 tcg_gen_helper_0_0(helper_restore);
3891                 gen_mov_pc_npc(dc, cpu_cond);
3892                 tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3893                 tcg_gen_mov_tl(cpu_npc, cpu_dst);
3894                 dc->npc = DYNAMIC_PC;
3895                 goto jmp_insn;
3896 #endif
3897             } else {
3898                 cpu_src1 = get_src1(insn, cpu_src1);
3899                 if (IS_IMM) {   /* immediate */
3900                     rs2 = GET_FIELDs(insn, 19, 31);
3901                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3902                 } else {                /* register */
3903                     rs2 = GET_FIELD(insn, 27, 31);
3904                     if (rs2) {
3905                         gen_movl_reg_TN(rs2, cpu_src2);
3906                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3907                     }
3908                 }
3909                 switch (xop) {
3910                 case 0x38:      /* jmpl */
3911                     {
3912                         if (rd != 0) {
3913                             tcg_gen_movi_tl(cpu_tmp0, dc->pc);
3914                             gen_movl_TN_reg(rd, cpu_tmp0);
3915                         }
3916                         gen_mov_pc_npc(dc, cpu_cond);
3917                         tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3918                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
3919                         dc->npc = DYNAMIC_PC;
3920                     }
3921                     goto jmp_insn;
3922 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3923                 case 0x39:      /* rett, V9 return */
3924                     {
3925                         if (!supervisor(dc))
3926                             goto priv_insn;
3927                         gen_mov_pc_npc(dc, cpu_cond);
3928                         tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3929                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
3930                         dc->npc = DYNAMIC_PC;
3931                         tcg_gen_helper_0_0(helper_rett);
3932                     }
3933                     goto jmp_insn;
3934 #endif
3935                 case 0x3b: /* flush */
3936                     tcg_gen_helper_0_1(helper_flush, cpu_dst);
3937                     break;
3938                 case 0x3c:      /* save */
3939                     save_state(dc, cpu_cond);
3940                     tcg_gen_helper_0_0(helper_save);
3941                     gen_movl_TN_reg(rd, cpu_dst);
3942                     break;
3943                 case 0x3d:      /* restore */
3944                     save_state(dc, cpu_cond);
3945                     tcg_gen_helper_0_0(helper_restore);
3946                     gen_movl_TN_reg(rd, cpu_dst);
3947                     break;
3948 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
3949                 case 0x3e:      /* V9 done/retry */
3950                     {
3951                         switch (rd) {
3952                         case 0:
3953                             if (!supervisor(dc))
3954                                 goto priv_insn;
3955                             dc->npc = DYNAMIC_PC;
3956                             dc->pc = DYNAMIC_PC;
3957                             tcg_gen_helper_0_0(helper_done);
3958                             goto jmp_insn;
3959                         case 1:
3960                             if (!supervisor(dc))
3961                                 goto priv_insn;
3962                             dc->npc = DYNAMIC_PC;
3963                             dc->pc = DYNAMIC_PC;
3964                             tcg_gen_helper_0_0(helper_retry);
3965                             goto jmp_insn;
3966                         default:
3967                             goto illegal_insn;
3968                         }
3969                     }
3970                     break;
3971 #endif
3972                 default:
3973                     goto illegal_insn;
3974                 }
3975             }
3976             break;
3977         }
3978         break;
3979     case 3:                     /* load/store instructions */
3980         {
3981             unsigned int xop = GET_FIELD(insn, 7, 12);
3982
3983             save_state(dc, cpu_cond);
3984             cpu_src1 = get_src1(insn, cpu_src1);
3985             if (xop == 0x3c || xop == 0x3e)
3986             {
3987                 rs2 = GET_FIELD(insn, 27, 31);
3988                 gen_movl_reg_TN(rs2, cpu_src2);
3989             }
3990             else if (IS_IMM) {       /* immediate */
3991                 rs2 = GET_FIELDs(insn, 19, 31);
3992                 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
3993             } else {            /* register */
3994                 rs2 = GET_FIELD(insn, 27, 31);
3995                 if (rs2 != 0) {
3996                     gen_movl_reg_TN(rs2, cpu_src2);
3997                     tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
3998                 }
3999             }
4000             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4001                 (xop > 0x17 && xop <= 0x1d ) ||
4002                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4003                 switch (xop) {
4004                 case 0x0:       /* load unsigned word */
4005                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4006                     ABI32_MASK(cpu_addr);
4007                     tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4008                     break;
4009                 case 0x1:       /* load unsigned byte */
4010                     ABI32_MASK(cpu_addr);
4011                     tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4012                     break;
4013                 case 0x2:       /* load unsigned halfword */
4014                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4015                     ABI32_MASK(cpu_addr);
4016                     tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4017                     break;
4018                 case 0x3:       /* load double word */
4019                     if (rd & 1)
4020                         goto illegal_insn;
4021                     else {
4022                         tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4023                         ABI32_MASK(cpu_addr);
4024                         tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4025                         tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4026                         tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4027                         gen_movl_TN_reg(rd + 1, cpu_tmp0);
4028                         tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4029                         tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4030                         tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4031                     }
4032                     break;
4033                 case 0x9:       /* load signed byte */
4034                     ABI32_MASK(cpu_addr);
4035                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4036                     break;
4037                 case 0xa:       /* load signed halfword */
4038                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4039                     ABI32_MASK(cpu_addr);
4040                     tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4041                     break;
4042                 case 0xd:       /* ldstub -- XXX: should be atomically */
4043                     ABI32_MASK(cpu_addr);
4044                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4045                     tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, dc->mem_idx);
4046                     break;
4047                 case 0x0f:      /* swap register with memory. Also atomically */
4048                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4049                     gen_movl_reg_TN(rd, cpu_val);
4050                     ABI32_MASK(cpu_addr);
4051                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4052                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4053                     tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4054                     break;
4055 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4056                 case 0x10:      /* load word alternate */
4057 #ifndef TARGET_SPARC64
4058                     if (IS_IMM)
4059                         goto illegal_insn;
4060                     if (!supervisor(dc))
4061                         goto priv_insn;
4062 #endif
4063                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4064                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4065                     break;
4066                 case 0x11:      /* load unsigned byte alternate */
4067 #ifndef TARGET_SPARC64
4068                     if (IS_IMM)
4069                         goto illegal_insn;
4070                     if (!supervisor(dc))
4071                         goto priv_insn;
4072 #endif
4073                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4074                     break;
4075                 case 0x12:      /* load unsigned halfword alternate */
4076 #ifndef TARGET_SPARC64
4077                     if (IS_IMM)
4078                         goto illegal_insn;
4079                     if (!supervisor(dc))
4080                         goto priv_insn;
4081 #endif
4082                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4083                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4084                     break;
4085                 case 0x13:      /* load double word alternate */
4086 #ifndef TARGET_SPARC64
4087                     if (IS_IMM)
4088                         goto illegal_insn;
4089                     if (!supervisor(dc))
4090                         goto priv_insn;
4091 #endif
4092                     if (rd & 1)
4093                         goto illegal_insn;
4094                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4095                     gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4096                     gen_movl_TN_reg(rd + 1, cpu_tmp0);
4097                     break;
4098                 case 0x19:      /* load signed byte alternate */
4099 #ifndef TARGET_SPARC64
4100                     if (IS_IMM)
4101                         goto illegal_insn;
4102                     if (!supervisor(dc))
4103                         goto priv_insn;
4104 #endif
4105                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4106                     break;
4107                 case 0x1a:      /* load signed halfword alternate */
4108 #ifndef TARGET_SPARC64
4109                     if (IS_IMM)
4110                         goto illegal_insn;
4111                     if (!supervisor(dc))
4112                         goto priv_insn;
4113 #endif
4114                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4115                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4116                     break;
4117                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
4118 #ifndef TARGET_SPARC64
4119                     if (IS_IMM)
4120                         goto illegal_insn;
4121                     if (!supervisor(dc))
4122                         goto priv_insn;
4123 #endif
4124                     gen_ldstub_asi(cpu_val, cpu_addr, insn);
4125                     break;
4126                 case 0x1f:      /* swap reg with alt. memory. Also atomically */
4127 #ifndef TARGET_SPARC64
4128                     if (IS_IMM)
4129                         goto illegal_insn;
4130                     if (!supervisor(dc))
4131                         goto priv_insn;
4132 #endif
4133                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4134                     gen_movl_reg_TN(rd, cpu_val);
4135                     gen_swap_asi(cpu_val, cpu_addr, insn);
4136                     break;
4137
4138 #ifndef TARGET_SPARC64
4139                 case 0x30: /* ldc */
4140                 case 0x31: /* ldcsr */
4141                 case 0x33: /* lddc */
4142                     goto ncp_insn;
4143 #endif
4144 #endif
4145 #ifdef TARGET_SPARC64
4146                 case 0x08: /* V9 ldsw */
4147                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4148                     ABI32_MASK(cpu_addr);
4149                     tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4150                     break;
4151                 case 0x0b: /* V9 ldx */
4152                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4153                     ABI32_MASK(cpu_addr);
4154                     tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4155                     break;
4156                 case 0x18: /* V9 ldswa */
4157                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4158                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4159                     break;
4160                 case 0x1b: /* V9 ldxa */
4161                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4162                     gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4163                     break;
4164                 case 0x2d: /* V9 prefetch, no effect */
4165                     goto skip_move;
4166                 case 0x30: /* V9 ldfa */
4167                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4168                     gen_ldf_asi(cpu_addr, insn, 4, rd);
4169                     goto skip_move;
4170                 case 0x33: /* V9 lddfa */
4171                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4172                     gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4173                     goto skip_move;
4174                 case 0x3d: /* V9 prefetcha, no effect */
4175                     goto skip_move;
4176                 case 0x32: /* V9 ldqfa */
4177 #if defined(CONFIG_USER_ONLY)
4178                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4179                     gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4180                     goto skip_move;
4181 #else
4182                     goto nfpu_insn;
4183 #endif
4184 #endif
4185                 default:
4186                     goto illegal_insn;
4187                 }
4188                 gen_movl_TN_reg(rd, cpu_val);
4189 #ifdef TARGET_SPARC64
4190             skip_move: ;
4191 #endif
4192             } else if (xop >= 0x20 && xop < 0x24) {
4193                 if (gen_trap_ifnofpu(dc, cpu_cond))
4194                     goto jmp_insn;
4195                 switch (xop) {
4196                 case 0x20:      /* load fpreg */
4197                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4198                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4199                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4200                                    offsetof(CPUState, fpr[rd]));
4201                     break;
4202                 case 0x21:      /* load fsr */
4203                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4204                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4205                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4206                                    offsetof(CPUState, ft0));
4207                     tcg_gen_helper_0_0(helper_ldfsr);
4208                     break;
4209                 case 0x22:      /* load quad fpreg */
4210 #if defined(CONFIG_USER_ONLY)
4211                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4212                     gen_op_ldst(ldqf);
4213                     gen_op_store_QT0_fpr(QFPREG(rd));
4214                     break;
4215 #else
4216                     goto nfpu_insn;
4217 #endif
4218                 case 0x23:      /* load double fpreg */
4219                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4220                     gen_op_ldst(lddf);
4221                     gen_op_store_DT0_fpr(DFPREG(rd));
4222                     break;
4223                 default:
4224                     goto illegal_insn;
4225                 }
4226             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4227                        xop == 0xe || xop == 0x1e) {
4228                 gen_movl_reg_TN(rd, cpu_val);
4229                 switch (xop) {
4230                 case 0x4: /* store word */
4231                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4232                     ABI32_MASK(cpu_addr);
4233                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4234                     break;
4235                 case 0x5: /* store byte */
4236                     ABI32_MASK(cpu_addr);
4237                     tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4238                     break;
4239                 case 0x6: /* store halfword */
4240                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4241                     ABI32_MASK(cpu_addr);
4242                     tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4243                     break;
4244                 case 0x7: /* store double word */
4245                     if (rd & 1)
4246                         goto illegal_insn;
4247 #ifndef __i386__
4248                     else {
4249                         TCGv r_low;
4250
4251                         tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4252                         r_low = tcg_temp_new(TCG_TYPE_I32);
4253                         gen_movl_reg_TN(rd + 1, r_low);
4254                         tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4255                                            r_low);
4256                         tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4257                     }
4258 #else /* __i386__ */
4259                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4260                     flush_cond(dc, cpu_cond);
4261                     gen_movl_reg_TN(rd + 1, cpu_cond);
4262                     gen_op_ldst(std);
4263 #endif /* __i386__ */
4264                     break;
4265 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4266                 case 0x14: /* store word alternate */
4267 #ifndef TARGET_SPARC64
4268                     if (IS_IMM)
4269                         goto illegal_insn;
4270                     if (!supervisor(dc))
4271                         goto priv_insn;
4272 #endif
4273                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4274                     gen_st_asi(cpu_val, cpu_addr, insn, 4);
4275                     break;
4276                 case 0x15: /* store byte alternate */
4277 #ifndef TARGET_SPARC64
4278                     if (IS_IMM)
4279                         goto illegal_insn;
4280                     if (!supervisor(dc))
4281                         goto priv_insn;
4282 #endif
4283                     gen_st_asi(cpu_val, cpu_addr, insn, 1);
4284                     break;
4285                 case 0x16: /* store halfword alternate */
4286 #ifndef TARGET_SPARC64
4287                     if (IS_IMM)
4288                         goto illegal_insn;
4289                     if (!supervisor(dc))
4290                         goto priv_insn;
4291 #endif
4292                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4293                     gen_st_asi(cpu_val, cpu_addr, insn, 2);
4294                     break;
4295                 case 0x17: /* store double word alternate */
4296 #ifndef TARGET_SPARC64
4297                     if (IS_IMM)
4298                         goto illegal_insn;
4299                     if (!supervisor(dc))
4300                         goto priv_insn;
4301 #endif
4302                     if (rd & 1)
4303                         goto illegal_insn;
4304                     else {
4305                         tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4306                         gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4307                     }
4308                     break;
4309 #endif
4310 #ifdef TARGET_SPARC64
4311                 case 0x0e: /* V9 stx */
4312                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4313                     ABI32_MASK(cpu_addr);
4314                     tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4315                     break;
4316                 case 0x1e: /* V9 stxa */
4317                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4318                     gen_st_asi(cpu_val, cpu_addr, insn, 8);
4319                     break;
4320 #endif
4321                 default:
4322                     goto illegal_insn;
4323                 }
4324             } else if (xop > 0x23 && xop < 0x28) {
4325                 if (gen_trap_ifnofpu(dc, cpu_cond))
4326                     goto jmp_insn;
4327                 switch (xop) {
4328                 case 0x24: /* store fpreg */
4329                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4330                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4331                                    offsetof(CPUState, fpr[rd]));
4332                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4333                     break;
4334                 case 0x25: /* stfsr, V9 stxfsr */
4335 #ifdef CONFIG_USER_ONLY
4336                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4337 #endif
4338                     tcg_gen_helper_0_0(helper_stfsr);
4339                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4340                                    offsetof(CPUState, ft0));
4341                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4342                     break;
4343                 case 0x26:
4344 #ifdef TARGET_SPARC64
4345 #if defined(CONFIG_USER_ONLY)
4346                     /* V9 stqf, store quad fpreg */
4347                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4348                     gen_op_load_fpr_QT0(QFPREG(rd));
4349                     gen_op_ldst(stqf);
4350                     break;
4351 #else
4352                     goto nfpu_insn;
4353 #endif
4354 #else /* !TARGET_SPARC64 */
4355                     /* stdfq, store floating point queue */
4356 #if defined(CONFIG_USER_ONLY)
4357                     goto illegal_insn;
4358 #else
4359                     if (!supervisor(dc))
4360                         goto priv_insn;
4361                     if (gen_trap_ifnofpu(dc, cpu_cond))
4362                         goto jmp_insn;
4363                     goto nfq_insn;
4364 #endif
4365 #endif
4366                 case 0x27:
4367                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4368                     gen_op_load_fpr_DT0(DFPREG(rd));
4369                     gen_op_ldst(stdf);
4370                     break;
4371                 default:
4372                     goto illegal_insn;
4373                 }
4374             } else if (xop > 0x33 && xop < 0x3f) {
4375                 switch (xop) {
4376 #ifdef TARGET_SPARC64
4377                 case 0x34: /* V9 stfa */
4378                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4379                     gen_op_load_fpr_FT0(rd);
4380                     gen_stf_asi(cpu_addr, insn, 4, rd);
4381                     break;
4382                 case 0x36: /* V9 stqfa */
4383 #if defined(CONFIG_USER_ONLY)
4384                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4385                     gen_op_load_fpr_QT0(QFPREG(rd));
4386                     gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4387                     break;
4388 #else
4389                     goto nfpu_insn;
4390 #endif
4391                 case 0x37: /* V9 stdfa */
4392                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4393                     gen_op_load_fpr_DT0(DFPREG(rd));
4394                     gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4395                     break;
4396                 case 0x3c: /* V9 casa */
4397                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4398                     gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4399                     gen_movl_TN_reg(rd, cpu_val);
4400                     break;
4401                 case 0x3e: /* V9 casxa */
4402                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4403                     gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4404                     gen_movl_TN_reg(rd, cpu_val);
4405                     break;
4406 #else
4407                 case 0x34: /* stc */
4408                 case 0x35: /* stcsr */
4409                 case 0x36: /* stdcq */
4410                 case 0x37: /* stdc */
4411                     goto ncp_insn;
4412 #endif
4413                 default:
4414                     goto illegal_insn;
4415                 }
4416             }
4417             else
4418                 goto illegal_insn;
4419         }
4420         break;
4421     }
4422     /* default case for non jump instructions */
4423     if (dc->npc == DYNAMIC_PC) {
4424         dc->pc = DYNAMIC_PC;
4425         gen_op_next_insn();
4426     } else if (dc->npc == JUMP_PC) {
4427         /* we can do a static jump */
4428         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4429         dc->is_br = 1;
4430     } else {
4431         dc->pc = dc->npc;
4432         dc->npc = dc->npc + 4;
4433     }
4434  jmp_insn:
4435     return;
4436  illegal_insn:
4437     save_state(dc, cpu_cond);
4438     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
4439     dc->is_br = 1;
4440     return;
4441 #if !defined(CONFIG_USER_ONLY)
4442  priv_insn:
4443     save_state(dc, cpu_cond);
4444     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
4445     dc->is_br = 1;
4446     return;
4447  nfpu_insn:
4448     save_state(dc, cpu_cond);
4449     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4450     dc->is_br = 1;
4451     return;
4452 #ifndef TARGET_SPARC64
4453  nfq_insn:
4454     save_state(dc, cpu_cond);
4455     gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4456     dc->is_br = 1;
4457     return;
4458 #endif
4459 #endif
4460 #ifndef TARGET_SPARC64
4461  ncp_insn:
4462     save_state(dc, cpu_cond);
4463     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
4464     dc->is_br = 1;
4465     return;
4466 #endif
4467 }
4468
4469 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
4470 {
4471 }
4472
4473 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4474                                                  int spc, CPUSPARCState *env)
4475 {
4476     target_ulong pc_start, last_pc;
4477     uint16_t *gen_opc_end;
4478     DisasContext dc1, *dc = &dc1;
4479     int j, lj = -1;
4480
4481     memset(dc, 0, sizeof(DisasContext));
4482     dc->tb = tb;
4483     pc_start = tb->pc;
4484     dc->pc = pc_start;
4485     last_pc = dc->pc;
4486     dc->npc = (target_ulong) tb->cs_base;
4487     dc->mem_idx = cpu_mmu_index(env);
4488     dc->fpu_enabled = cpu_fpu_enabled(env);
4489     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4490
4491     cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4492     cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4493     cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4494
4495     cpu_cond = cpu_T[2];
4496
4497     do {
4498         if (env->nb_breakpoints > 0) {
4499             for(j = 0; j < env->nb_breakpoints; j++) {
4500                 if (env->breakpoints[j] == dc->pc) {
4501                     if (dc->pc != pc_start)
4502                         save_state(dc, cpu_cond);
4503                     tcg_gen_helper_0_0(helper_debug);
4504                     tcg_gen_exit_tb(0);
4505                     dc->is_br = 1;
4506                     goto exit_gen_loop;
4507                 }
4508             }
4509         }
4510         if (spc) {
4511             if (loglevel > 0)
4512                 fprintf(logfile, "Search PC...\n");
4513             j = gen_opc_ptr - gen_opc_buf;
4514             if (lj < j) {
4515                 lj++;
4516                 while (lj < j)
4517                     gen_opc_instr_start[lj++] = 0;
4518                 gen_opc_pc[lj] = dc->pc;
4519                 gen_opc_npc[lj] = dc->npc;
4520                 gen_opc_instr_start[lj] = 1;
4521             }
4522         }
4523         last_pc = dc->pc;
4524         disas_sparc_insn(dc);
4525
4526         if (dc->is_br)
4527             break;
4528         /* if the next PC is different, we abort now */
4529         if (dc->pc != (last_pc + 4))
4530             break;
4531         /* if we reach a page boundary, we stop generation so that the
4532            PC of a TT_TFAULT exception is always in the right page */
4533         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4534             break;
4535         /* if single step mode, we generate only one instruction and
4536            generate an exception */
4537         if (env->singlestep_enabled) {
4538             tcg_gen_movi_tl(cpu_pc, dc->pc);
4539             tcg_gen_exit_tb(0);
4540             break;
4541         }
4542     } while ((gen_opc_ptr < gen_opc_end) &&
4543              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4544
4545  exit_gen_loop:
4546     if (!dc->is_br) {
4547         if (dc->pc != DYNAMIC_PC &&
4548             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4549             /* static PC and NPC: we can use direct chaining */
4550             gen_goto_tb(dc, 0, dc->pc, dc->npc);
4551         } else {
4552             if (dc->pc != DYNAMIC_PC)
4553                 tcg_gen_movi_tl(cpu_pc, dc->pc);
4554             save_npc(dc, cpu_cond);
4555             tcg_gen_exit_tb(0);
4556         }
4557     }
4558     *gen_opc_ptr = INDEX_op_end;
4559     if (spc) {
4560         j = gen_opc_ptr - gen_opc_buf;
4561         lj++;
4562         while (lj <= j)
4563             gen_opc_instr_start[lj++] = 0;
4564 #if 0
4565         if (loglevel > 0) {
4566             page_dump(logfile);
4567         }
4568 #endif
4569         gen_opc_jump_pc[0] = dc->jump_pc[0];
4570         gen_opc_jump_pc[1] = dc->jump_pc[1];
4571     } else {
4572         tb->size = last_pc + 4 - pc_start;
4573     }
4574 #ifdef DEBUG_DISAS
4575     if (loglevel & CPU_LOG_TB_IN_ASM) {
4576         fprintf(logfile, "--------------\n");
4577         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4578         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4579         fprintf(logfile, "\n");
4580     }
4581 #endif
4582     return 0;
4583 }
4584
4585 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4586 {
4587     return gen_intermediate_code_internal(tb, 0, env);
4588 }
4589
4590 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4591 {
4592     return gen_intermediate_code_internal(tb, 1, env);
4593 }
4594
4595 void gen_intermediate_code_init(CPUSPARCState *env)
4596 {
4597     unsigned int i;
4598     static int inited;
4599     static const char * const gregnames[8] = {
4600         NULL, // g0 not used
4601         "g1",
4602         "g2",
4603         "g3",
4604         "g4",
4605         "g5",
4606         "g6",
4607         "g7",
4608     };
4609
4610     /* init various static tables */
4611     if (!inited) {
4612         inited = 1;
4613
4614         tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
4615         cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4616         cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4617                                          offsetof(CPUState, regwptr),
4618                                          "regwptr");
4619         //#if TARGET_LONG_BITS > HOST_LONG_BITS
4620 #ifdef TARGET_SPARC64
4621         cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4622                                       TCG_AREG0, offsetof(CPUState, t0), "T0");
4623         cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4624                                       TCG_AREG0, offsetof(CPUState, t1), "T1");
4625         cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4626                                       TCG_AREG0, offsetof(CPUState, t2), "T2");
4627         cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4628                                      TCG_AREG0, offsetof(CPUState, xcc),
4629                                      "xcc");
4630 #else
4631         cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4632         cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4633         cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4634 #endif
4635         cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4636                                         TCG_AREG0, offsetof(CPUState, cc_src),
4637                                         "cc_src");
4638         cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4639                                          offsetof(CPUState, cc_src2),
4640                                          "cc_src2");
4641         cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4642                                         TCG_AREG0, offsetof(CPUState, cc_dst),
4643                                         "cc_dst");
4644         cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4645                                      TCG_AREG0, offsetof(CPUState, psr),
4646                                      "psr");
4647         cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4648                                      TCG_AREG0, offsetof(CPUState, fsr),
4649                                      "fsr");
4650         cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4651                                     TCG_AREG0, offsetof(CPUState, pc),
4652                                     "pc");
4653         cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4654                                     TCG_AREG0, offsetof(CPUState, npc),
4655                                     "npc");
4656         for (i = 1; i < 8; i++)
4657             cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4658                                               offsetof(CPUState, gregs[i]),
4659                                               gregnames[i]);
4660     }
4661 }