git.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23    TODO-list:
  24
  25    Rest of V9 instructions, VIS instructions
  26    NPC/PC static optimisations (use JUMP_TB when possible)
  27    Optimize synthetic instructions
  28 */
  29
  30 #include <stdarg.h>
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <string.h>
  34 #include <inttypes.h>
  35
  36 #include "cpu.h"
  37 #include "exec-all.h"
  38 #include "disas.h"
  39 #include "helper.h"
  40 #include "tcg-op.h"
  41
  42 #define DEBUG_DISAS
  43
  44 #define DYNAMIC_PC  1 /* dynamic pc value */
  45 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  46                          according to jump_pc[T2] */
  47
  48 /* global register indexes */
  49 static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_dst;
  50 static TCGv cpu_psr, cpu_fsr, cpu_gregs[8];
  51 #ifdef TARGET_SPARC64
  52 static TCGv cpu_xcc;
  53 #endif
  54 /* local register indexes (only used inside old micro ops) */
  55 static TCGv cpu_tmp0;
  56
  57 typedef struct DisasContext {
  58     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  59     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  60     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  61     int is_br;
  62     int mem_idx;
  63     int fpu_enabled;
  64     struct TranslationBlock *tb;
  65 } DisasContext;
  66
  67 typedef struct sparc_def_t sparc_def_t;
  68
  69 struct sparc_def_t {
  70     const unsigned char *name;
  71     target_ulong iu_version;
  72     uint32_t fpu_version;
  73     uint32_t mmu_version;
  74     uint32_t mmu_bm;
  75     uint32_t mmu_ctpr_mask;
  76     uint32_t mmu_cxr_mask;
  77     uint32_t mmu_sfsr_mask;
  78     uint32_t mmu_trcr_mask;
  79 };
  80
  81 static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
  82
  83 extern FILE *logfile;
  84 extern int loglevel;
  85
  86 // This function uses non-native bit order
  87 #define GET_FIELD(X, FROM, TO) \
  88   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  89
  90 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  91 #define GET_FIELD_SP(X, FROM, TO) \
  92     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  93
  94 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  95 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
  96
  97 #ifdef TARGET_SPARC64
  98 #define FFPREG(r) (r)
  99 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
 100 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
 101 #else
 102 #define FFPREG(r) (r)
 103 #define DFPREG(r) (r & 0x1e)
 104 #define QFPREG(r) (r & 0x1c)
 105 #endif
 106
 107 static int sign_extend(int x, int len)
 108 {
 109     len = 32 - len;
 110     return (x << len) >> len;
 111 }
 112
 113 #define IS_IMM (insn & (1<<13))
 114
 115 static void disas_sparc_insn(DisasContext * dc);
 116
 117 #ifdef TARGET_SPARC64
 118 #define GEN32(func, NAME) \
 119 static GenOpFunc * const NAME ## _table [64] = {                              \
 120 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
 121 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
 122 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
 123 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
 124 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
 125 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
 126 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
 127 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
 128 NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0,                   \
 129 NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0,                   \
 130 NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0,                   \
 131 NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0,                   \
 132 };                                                                            \
 133 static inline void func(int n)                                                \
 134 {                                                                             \
 135     NAME ## _table[n]();                                                      \
 136 }
 137 #else
 138 #define GEN32(func, NAME) \
 139 static GenOpFunc *const NAME ## _table [32] = {                               \
 140 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
 141 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
 142 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
 143 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
 144 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
 145 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
 146 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
 147 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
 148 };                                                                            \
 149 static inline void func(int n)                                                \
 150 {                                                                             \
 151     NAME ## _table[n]();                                                      \
 152 }
 153 #endif
 154
 155 /* floating point registers moves */
 156 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
 157 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
 158 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
 159 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
 160
 161 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
 162 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
 163 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
 164 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
 165
 166 #if defined(CONFIG_USER_ONLY)
 167 GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);
 168 GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);
 169 GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);
 170 GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
 171 #endif
 172
 173 /* moves */
 174 #ifdef CONFIG_USER_ONLY
 175 #define supervisor(dc) 0
 176 #ifdef TARGET_SPARC64
 177 #define hypervisor(dc) 0
 178 #endif
 179 #define gen_op_ldst(name)        gen_op_##name##_raw()
 180 #else
 181 #define supervisor(dc) (dc->mem_idx >= 1)
 182 #ifdef TARGET_SPARC64
 183 #define hypervisor(dc) (dc->mem_idx == 2)
 184 #define OP_LD_TABLE(width)                                              \
 185     static GenOpFunc * const gen_op_##width[] = {                       \
 186         &gen_op_##width##_user,                                         \
 187         &gen_op_##width##_kernel,                                       \
 188         &gen_op_##width##_hypv,                                         \
 189     };
 190 #else
 191 #define OP_LD_TABLE(width)                                              \
 192     static GenOpFunc * const gen_op_##width[] = {                       \
 193         &gen_op_##width##_user,                                         \
 194         &gen_op_##width##_kernel,                                       \
 195     };
 196 #endif
 197 #define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
 198 #endif
 199
 200 #ifndef CONFIG_USER_ONLY
 201 #ifdef __i386__
 202 OP_LD_TABLE(std);
 203 #endif /* __i386__ */
 204 OP_LD_TABLE(stf);
 205 OP_LD_TABLE(stdf);
 206 OP_LD_TABLE(ldf);
 207 OP_LD_TABLE(lddf);
 208 #endif
 209
 210 #ifdef TARGET_ABI32
 211 #define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL);
 212 #else
 213 #define ABI32_MASK(addr)
 214 #endif
 215
 216 static inline void gen_movl_simm_T1(int32_t val)
 217 {
 218     tcg_gen_movi_tl(cpu_T[1], val);
 219 }
 220
 221 static inline void gen_movl_reg_TN(int reg, TCGv tn)
 222 {
 223     if (reg == 0)
 224         tcg_gen_movi_tl(tn, 0);
 225     else if (reg < 8)
 226         tcg_gen_mov_tl(tn, cpu_gregs[reg]);
 227     else {
 228         tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 229     }
 230 }
 231
 232 static inline void gen_movl_reg_T0(int reg)
 233 {
 234     gen_movl_reg_TN(reg, cpu_T[0]);
 235 }
 236
 237 static inline void gen_movl_reg_T1(int reg)
 238 {
 239     gen_movl_reg_TN(reg, cpu_T[1]);
 240 }
 241
 242 #ifdef __i386__
 243 static inline void gen_movl_reg_T2(int reg)
 244 {
 245     gen_movl_reg_TN(reg, cpu_T[2]);
 246 }
 247
 248 #endif /* __i386__ */
 249 static inline void gen_movl_TN_reg(int reg, TCGv tn)
 250 {
 251     if (reg == 0)
 252         return;
 253     else if (reg < 8)
 254         tcg_gen_mov_tl(cpu_gregs[reg], tn);
 255     else {
 256         tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 257     }
 258 }
 259
 260 static inline void gen_movl_T0_reg(int reg)
 261 {
 262     gen_movl_TN_reg(reg, cpu_T[0]);
 263 }
 264
 265 static inline void gen_movl_T1_reg(int reg)
 266 {
 267     gen_movl_TN_reg(reg, cpu_T[1]);
 268 }
 269
 270 static inline void gen_op_movl_T0_env(size_t offset)
 271 {
 272     tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
 273 }
 274
 275 static inline void gen_op_movl_env_T0(size_t offset)
 276 {
 277     tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
 278 }
 279
 280 static inline void gen_op_movtl_T0_env(size_t offset)
 281 {
 282     tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);
 283 }
 284
 285 static inline void gen_op_movtl_env_T0(size_t offset)
 286 {
 287     tcg_gen_st_tl(cpu_T[0], cpu_env, offset);
 288 }
 289
 290 static inline void gen_op_add_T1_T0(void)
 291 {
 292     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 293 }
 294
 295 static inline void gen_op_or_T1_T0(void)
 296 {
 297     tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 298 }
 299
 300 static inline void gen_op_xor_T1_T0(void)
 301 {
 302     tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 303 }
 304
 305 static inline void gen_jmp_im(target_ulong pc)
 306 {
 307     tcg_gen_movi_tl(cpu_tmp0, pc);
 308     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, pc));
 309 }
 310
 311 static inline void gen_movl_npc_im(target_ulong npc)
 312 {
 313     tcg_gen_movi_tl(cpu_tmp0, npc);
 314     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, npc));
 315 }
 316
 317 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 318                                target_ulong pc, target_ulong npc)
 319 {
 320     TranslationBlock *tb;
 321
 322     tb = s->tb;
 323     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 324         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 325         /* jump to same page: we can use a direct jump */
 326         tcg_gen_goto_tb(tb_num);
 327         gen_jmp_im(pc);
 328         gen_movl_npc_im(npc);
 329         tcg_gen_exit_tb((long)tb + tb_num);
 330     } else {
 331         /* jump to another page: currently not optimized */
 332         gen_jmp_im(pc);
 333         gen_movl_npc_im(npc);
 334         tcg_gen_exit_tb(0);
 335     }
 336 }
 337
 338 // XXX suboptimal
 339 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
 340 {
 341     tcg_gen_shri_i32(reg, src, 23);
 342     tcg_gen_andi_tl(reg, reg, 0x1);
 343 }
 344
 345 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
 346 {
 347     tcg_gen_shri_i32(reg, src, 22);
 348     tcg_gen_andi_tl(reg, reg, 0x1);
 349 }
 350
 351 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
 352 {
 353     tcg_gen_shri_i32(reg, src, 21);
 354     tcg_gen_andi_tl(reg, reg, 0x1);
 355 }
 356
 357 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
 358 {
 359     tcg_gen_shri_i32(reg, src, 20);
 360     tcg_gen_andi_tl(reg, reg, 0x1);
 361 }
 362
 363 static inline void gen_op_exception(int exception)
 364 {
 365     TCGv r_except;
 366
 367     r_except = tcg_temp_new(TCG_TYPE_I32);
 368     tcg_gen_movi_i32(r_except, exception);
 369     tcg_gen_helper_0_1(raise_exception, r_except);
 370 }
 371
 372 static inline void gen_cc_clear(void)
 373 {
 374     tcg_gen_movi_i32(cpu_psr, 0);
 375 #ifdef TARGET_SPARC64
 376     tcg_gen_movi_i32(cpu_xcc, 0);
 377 #endif
 378 }
 379
 380 /* old op:
 381     if (!T0)
 382         env->psr |= PSR_ZERO;
 383     if ((int32_t) T0 < 0)
 384         env->psr |= PSR_NEG;
 385 */
 386 static inline void gen_cc_NZ(TCGv dst)
 387 {
 388     int l1, l2;
 389     TCGv r_zero;
 390
 391     l1 = gen_new_label();
 392     l2 = gen_new_label();
 393     r_zero = tcg_const_tl(0);
 394     tcg_gen_brcond_i32(TCG_COND_NE, dst, r_zero, l1);
 395     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
 396     gen_set_label(l1);
 397     tcg_gen_brcond_i32(TCG_COND_GE, dst, r_zero, l2);
 398     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
 399     gen_set_label(l2);
 400 #ifdef TARGET_SPARC64
 401     {
 402         int l3, l4;
 403
 404         l3 = gen_new_label();
 405         l4 = gen_new_label();
 406         tcg_gen_brcond_tl(TCG_COND_NE, dst, r_zero, l3);
 407         tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
 408         gen_set_label(l3);
 409         tcg_gen_brcond_tl(TCG_COND_GE, dst, r_zero, l4);
 410         tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
 411         gen_set_label(l4);
 412     }
 413 #endif
 414 }
 415
 416 /* old op:
 417     if (T0 < src1)
 418         env->psr |= PSR_CARRY;
 419 */
 420 static inline void gen_cc_C_add(TCGv dst, TCGv src1)
 421 {
 422     int l1;
 423
 424     l1 = gen_new_label();
 425     tcg_gen_brcond_i32(TCG_COND_GEU, dst, src1, l1);
 426     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 427     gen_set_label(l1);
 428 #ifdef TARGET_SPARC64
 429     {
 430         int l2;
 431
 432         l2 = gen_new_label();
 433         tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2);
 434         tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 435         gen_set_label(l2);
 436     }
 437 #endif
 438 }
 439
 440 /* old op:
 441     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
 442         env->psr |= PSR_OVF;
 443 */
 444 static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2)
 445 {
 446     TCGv r_temp, r_temp2, r_temp3, r_zero;
 447     int l1;
 448
 449     l1 = gen_new_label();
 450
 451     r_temp = tcg_temp_new(TCG_TYPE_TL);
 452     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 453     r_temp3 = tcg_temp_new(TCG_TYPE_TL);
 454     r_zero = tcg_const_tl(0);
 455     tcg_gen_xor_tl(r_temp, src1, src2);
 456     tcg_gen_xori_tl(r_temp, r_temp, -1);
 457     tcg_gen_xor_tl(r_temp2, src1, dst);
 458     tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 459     tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
 460     tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
 461     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 462     gen_set_label(l1);
 463 #ifdef TARGET_SPARC64
 464     {
 465         int l2;
 466
 467         l2 = gen_new_label();
 468         tcg_gen_xor_tl(r_temp, src1, src2);
 469         tcg_gen_xori_tl(r_temp, r_temp, -1);
 470         tcg_gen_xor_tl(r_temp2, src1, dst);
 471         tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 472         tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
 473         tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
 474         tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
 475         gen_set_label(l2);
 476     }
 477 #endif
 478 }
 479
 480 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
 481 {
 482     TCGv r_temp, r_temp2, r_temp3, r_zero;
 483     int l1;
 484
 485     l1 = gen_new_label();
 486
 487     r_temp = tcg_temp_new(TCG_TYPE_TL);
 488     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 489     r_temp3 = tcg_temp_new(TCG_TYPE_TL);
 490     r_zero = tcg_const_tl(0);
 491     tcg_gen_xor_tl(r_temp, src1, src2);
 492     tcg_gen_xori_tl(r_temp, r_temp, -1);
 493     tcg_gen_xor_tl(r_temp2, src1, dst);
 494     tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 495     tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
 496     tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
 497     gen_op_exception(TT_TOVF);
 498     gen_set_label(l1);
 499 #ifdef TARGET_SPARC64
 500     {
 501         int l2;
 502
 503         l2 = gen_new_label();
 504         tcg_gen_xor_tl(r_temp, src1, src2);
 505         tcg_gen_xori_tl(r_temp, r_temp, -1);
 506         tcg_gen_xor_tl(r_temp2, src1, dst);
 507         tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 508         tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
 509         tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
 510         gen_op_exception(TT_TOVF);
 511         gen_set_label(l2);
 512     }
 513 #endif
 514 }
 515
 516 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
 517 {
 518     int l1;
 519     TCGv r_zero, r_temp;
 520
 521     l1 = gen_new_label();
 522     r_zero = tcg_const_tl(0);
 523     r_temp = tcg_temp_new(TCG_TYPE_TL);
 524     tcg_gen_or_tl(r_temp, src1, src2);
 525     tcg_gen_andi_tl(r_temp, r_temp, 0x3);
 526     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1);
 527     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 528     gen_set_label(l1);
 529 }
 530
 531 static inline void gen_tag_tv(TCGv src1, TCGv src2)
 532 {
 533     int l1;
 534     TCGv r_zero, r_temp;
 535
 536     l1 = gen_new_label();
 537     r_zero = tcg_const_tl(0);
 538     r_temp = tcg_temp_new(TCG_TYPE_TL);
 539     tcg_gen_or_tl(r_temp, src1, src2);
 540     tcg_gen_andi_tl(r_temp, r_temp, 0x3);
 541     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1);
 542     gen_op_exception(TT_TOVF);
 543     gen_set_label(l1);
 544 }
 545
 546 static inline void gen_op_add_T1_T0_cc(void)
 547 {
 548     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 549     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 550     gen_cc_clear();
 551     gen_cc_NZ(cpu_T[0]);
 552     gen_cc_C_add(cpu_T[0], cpu_cc_src);
 553     gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
 554 }
 555
 556 static inline void gen_op_addx_T1_T0_cc(void)
 557 {
 558     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 559     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 560     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
 561     gen_cc_clear();
 562     gen_cc_C_add(cpu_T[0], cpu_cc_src);
 563     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 564     gen_cc_C_add(cpu_T[0], cpu_cc_src);
 565     gen_cc_NZ(cpu_T[0]);
 566     gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
 567 }
 568
 569 static inline void gen_op_tadd_T1_T0_cc(void)
 570 {
 571     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 572     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 573     gen_cc_clear();
 574     gen_cc_NZ(cpu_T[0]);
 575     gen_cc_C_add(cpu_T[0], cpu_cc_src);
 576     gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
 577     gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
 578 }
 579
 580 static inline void gen_op_tadd_T1_T0_ccTV(void)
 581 {
 582     gen_tag_tv(cpu_T[0], cpu_T[1]);
 583     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 584     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 585     gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
 586     gen_cc_clear();
 587     gen_cc_NZ(cpu_T[0]);
 588     gen_cc_C_add(cpu_T[0], cpu_cc_src);
 589 }
 590
 591 /* old op:
 592     if (src1 < T1)
 593         env->psr |= PSR_CARRY;
 594 */
 595 static inline void gen_cc_C_sub(TCGv src1, TCGv src2)
 596 {
 597     int l1;
 598
 599     l1 = gen_new_label();
 600     tcg_gen_brcond_i32(TCG_COND_GEU, src1, src2, l1);
 601     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 602     gen_set_label(l1);
 603 #ifdef TARGET_SPARC64
 604     {
 605         int l2;
 606
 607         l2 = gen_new_label();
 608         tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2);
 609         tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 610         gen_set_label(l2);
 611     }
 612 #endif
 613 }
 614
 615 /* old op:
 616     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
 617         env->psr |= PSR_OVF;
 618 */
 619 static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2)
 620 {
 621     TCGv r_temp, r_temp2, r_temp3, r_zero;
 622     int l1;
 623
 624     l1 = gen_new_label();
 625
 626     r_temp = tcg_temp_new(TCG_TYPE_TL);
 627     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 628     r_temp3 = tcg_temp_new(TCG_TYPE_TL);
 629     r_zero = tcg_const_tl(0);
 630     tcg_gen_xor_tl(r_temp, src1, src2);
 631     tcg_gen_xor_tl(r_temp2, src1, dst);
 632     tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 633     tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
 634     tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
 635     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 636     gen_set_label(l1);
 637 #ifdef TARGET_SPARC64
 638     {
 639         int l2;
 640
 641         l2 = gen_new_label();
 642         tcg_gen_xor_tl(r_temp, src1, src2);
 643         tcg_gen_xor_tl(r_temp2, src1, dst);
 644         tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 645         tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
 646         tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
 647         tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
 648         gen_set_label(l2);
 649     }
 650 #endif
 651 }
 652
 653 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
 654 {
 655     TCGv r_temp, r_temp2, r_temp3, r_zero;
 656     int l1;
 657
 658     l1 = gen_new_label();
 659
 660     r_temp = tcg_temp_new(TCG_TYPE_TL);
 661     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 662     r_temp3 = tcg_temp_new(TCG_TYPE_TL);
 663     r_zero = tcg_const_tl(0);
 664     tcg_gen_xor_tl(r_temp, src1, src2);
 665     tcg_gen_xor_tl(r_temp2, src1, dst);
 666     tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 667     tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
 668     tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
 669     gen_op_exception(TT_TOVF);
 670     gen_set_label(l1);
 671 #ifdef TARGET_SPARC64
 672     {
 673         int l2;
 674
 675         l2 = gen_new_label();
 676         tcg_gen_xor_tl(r_temp, src1, src2);
 677         tcg_gen_xor_tl(r_temp2, src1, dst);
 678         tcg_gen_and_tl(r_temp, r_temp, r_temp2);
 679         tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
 680         tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
 681         gen_op_exception(TT_TOVF);
 682         gen_set_label(l2);
 683     }
 684 #endif
 685 }
 686
 687 static inline void gen_op_sub_T1_T0_cc(void)
 688 {
 689     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 690     tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 691     gen_cc_clear();
 692     gen_cc_NZ(cpu_T[0]);
 693     gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
 694     gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
 695 }
 696
 697 static inline void gen_op_subx_T1_T0_cc(void)
 698 {
 699     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 700     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 701     tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
 702     gen_cc_clear();
 703     gen_cc_C_sub(cpu_T[0], cpu_cc_src);
 704     tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 705     gen_cc_C_sub(cpu_T[0], cpu_cc_src);
 706     gen_cc_NZ(cpu_T[0]);
 707     gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
 708 }
 709
 710 static inline void gen_op_tsub_T1_T0_cc(void)
 711 {
 712     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 713     tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 714     gen_cc_clear();
 715     gen_cc_NZ(cpu_T[0]);
 716     gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
 717     gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
 718     gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
 719 }
 720
 721 static inline void gen_op_tsub_T1_T0_ccTV(void)
 722 {
 723     gen_tag_tv(cpu_T[0], cpu_T[1]);
 724     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
 725     tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
 726     gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
 727     gen_cc_clear();
 728     gen_cc_NZ(cpu_T[0]);
 729     gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
 730 }
 731
 732 #ifdef TARGET_SPARC64
 733 static inline void gen_trap_ifdivzero_i64(TCGv divisor)
 734 {
 735     int l1;
 736
 737     l1 = gen_new_label();
 738     tcg_gen_brcond_i64(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
 739     gen_op_exception(TT_DIV_ZERO);
 740     gen_set_label(l1);
 741 }
 742
 743 static inline void gen_op_sdivx_T1_T0(void)
 744 {
 745     int l1, l2;
 746
 747     l1 = gen_new_label();
 748     l2 = gen_new_label();
 749     gen_trap_ifdivzero_i64(cpu_T[1]);
 750     tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[0], tcg_const_i64(INT64_MIN), l1);
 751     tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[1], tcg_const_i64(-1), l1);
 752     tcg_gen_movi_i64(cpu_T[0], INT64_MIN);
 753     gen_op_jmp_label(l2);
 754     gen_set_label(l1);
 755     tcg_gen_div_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
 756     gen_set_label(l2);
 757 }
 758 #endif
 759
 760 static inline void gen_op_div_cc(void)
 761 {
 762     int l1;
 763     TCGv r_zero;
 764
 765     gen_cc_clear();
 766     gen_cc_NZ(cpu_T[0]);
 767     l1 = gen_new_label();
 768     r_zero = tcg_const_tl(0);
 769     tcg_gen_brcond_i32(TCG_COND_EQ, cpu_T[1], r_zero, l1);
 770     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 771     gen_set_label(l1);
 772 }
 773
 774 static inline void gen_op_logic_T0_cc(void)
 775 {
 776     gen_cc_clear();
 777     gen_cc_NZ(cpu_T[0]);
 778 }
 779
 780 // 1
 781 static inline void gen_op_eval_ba(TCGv dst)
 782 {
 783     tcg_gen_movi_tl(dst, 1);
 784 }
 785
 786 // Z
 787 static inline void gen_op_eval_be(TCGv dst, TCGv src)
 788 {
 789     gen_mov_reg_Z(dst, src);
 790 }
 791
 792 // Z | (N ^ V)
 793 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
 794 {
 795     TCGv r_flag;
 796
 797     r_flag = tcg_temp_new(TCG_TYPE_TL);
 798     gen_mov_reg_N(r_flag, src);
 799     gen_mov_reg_V(dst, src);
 800     tcg_gen_xor_tl(dst, dst, r_flag);
 801     gen_mov_reg_Z(r_flag, src);
 802     tcg_gen_or_tl(dst, dst, r_flag);
 803 }
 804
 805 // N ^ V
 806 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
 807 {
 808     TCGv r_V;
 809
 810     r_V = tcg_temp_new(TCG_TYPE_TL);
 811     gen_mov_reg_V(r_V, src);
 812     gen_mov_reg_N(dst, src);
 813     tcg_gen_xor_tl(dst, dst, r_V);
 814 }
 815
 816 // C | Z
 817 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
 818 {
 819     TCGv r_Z;
 820
 821     r_Z = tcg_temp_new(TCG_TYPE_TL);
 822     gen_mov_reg_Z(r_Z, src);
 823     gen_mov_reg_C(dst, src);
 824     tcg_gen_or_tl(dst, dst, r_Z);
 825 }
 826
 827 // C
 828 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
 829 {
 830     gen_mov_reg_C(dst, src);
 831 }
 832
 833 // V
 834 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
 835 {
 836     gen_mov_reg_V(dst, src);
 837 }
 838
 839 // 0
 840 static inline void gen_op_eval_bn(TCGv dst)
 841 {
 842     tcg_gen_movi_tl(dst, 0);
 843 }
 844
 845 // N
 846 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
 847 {
 848     gen_mov_reg_N(dst, src);
 849 }
 850
 851 // !Z
 852 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
 853 {
 854     gen_mov_reg_Z(dst, src);
 855     tcg_gen_xori_tl(dst, dst, 0x1);
 856 }
 857
 858 // !(Z | (N ^ V))
 859 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
 860 {
 861     TCGv r_flag;
 862
 863     r_flag = tcg_temp_new(TCG_TYPE_TL);
 864     gen_mov_reg_N(r_flag, src);
 865     gen_mov_reg_V(dst, src);
 866     tcg_gen_xor_tl(dst, dst, r_flag);
 867     gen_mov_reg_Z(r_flag, src);
 868     tcg_gen_or_tl(dst, dst, r_flag);
 869     tcg_gen_xori_tl(dst, dst, 0x1);
 870 }
 871
 872 // !(N ^ V)
 873 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
 874 {
 875     TCGv r_V;
 876
 877     r_V = tcg_temp_new(TCG_TYPE_TL);
 878     gen_mov_reg_V(r_V, src);
 879     gen_mov_reg_N(dst, src);
 880     tcg_gen_xor_tl(dst, dst, r_V);
 881     tcg_gen_xori_tl(dst, dst, 0x1);
 882 }
 883
 884 // !(C | Z)
 885 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
 886 {
 887     TCGv r_Z;
 888
 889     r_Z = tcg_temp_new(TCG_TYPE_TL);
 890     gen_mov_reg_Z(r_Z, src);
 891     gen_mov_reg_C(dst, src);
 892     tcg_gen_or_tl(dst, dst, r_Z);
 893     tcg_gen_xori_tl(dst, dst, 0x1);
 894 }
 895
 896 // !C
 897 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
 898 {
 899     gen_mov_reg_C(dst, src);
 900     tcg_gen_xori_tl(dst, dst, 0x1);
 901 }
 902
 903 // !N
 904 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
 905 {
 906     gen_mov_reg_N(dst, src);
 907     tcg_gen_xori_tl(dst, dst, 0x1);
 908 }
 909
 910 // !V
 911 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
 912 {
 913     gen_mov_reg_V(dst, src);
 914     tcg_gen_xori_tl(dst, dst, 0x1);
 915 }
 916
 917 /*
 918   FPSR bit field FCC1 | FCC0:
 919    0 =
 920    1 <
 921    2 >
 922    3 unordered
 923 */
 924 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
 925                                     unsigned int fcc_offset)
 926 {
 927     tcg_gen_shri_i32(reg, src, 10 + fcc_offset);
 928     tcg_gen_andi_tl(reg, reg, 0x1);
 929 }
 930
 931 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
 932                                     unsigned int fcc_offset)
 933 {
 934     tcg_gen_shri_i32(reg, src, 11 + fcc_offset);
 935     tcg_gen_andi_tl(reg, reg, 0x1);
 936 }
 937
 938 // !0: FCC0 | FCC1
 939 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
 940                                     unsigned int fcc_offset)
 941 {
 942     TCGv r_fcc1;
 943
 944     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
 945     gen_mov_reg_FCC0(dst, src, fcc_offset);
 946     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
 947     tcg_gen_or_tl(dst, dst, r_fcc1);
 948 }
 949
 950 // 1 or 2: FCC0 ^ FCC1
 951 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
 952                                     unsigned int fcc_offset)
 953 {
 954     TCGv r_fcc1;
 955
 956     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
 957     gen_mov_reg_FCC0(dst, src, fcc_offset);
 958     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
 959     tcg_gen_xor_tl(dst, dst, r_fcc1);
 960 }
 961
 962 // 1 or 3: FCC0
 963 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
 964                                     unsigned int fcc_offset)
 965 {
 966     gen_mov_reg_FCC0(dst, src, fcc_offset);
 967 }
 968
 969 // 1: FCC0 & !FCC1
 970 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
 971                                     unsigned int fcc_offset)
 972 {
 973     TCGv r_fcc1;
 974
 975     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
 976     gen_mov_reg_FCC0(dst, src, fcc_offset);
 977     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
 978     tcg_gen_xori_tl(r_fcc1, r_fcc1, 0x1);
 979     tcg_gen_and_tl(dst, dst, r_fcc1);
 980 }
 981
 982 // 2 or 3: FCC1
 983 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
 984                                     unsigned int fcc_offset)
 985 {
 986     gen_mov_reg_FCC1(dst, src, fcc_offset);
 987 }
 988
 989 // 2: !FCC0 & FCC1
 990 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
 991                                     unsigned int fcc_offset)
 992 {
 993     TCGv r_fcc1;
 994
 995     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
 996     gen_mov_reg_FCC0(dst, src, fcc_offset);
 997     tcg_gen_xori_tl(dst, dst, 0x1);
 998     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
 999     tcg_gen_and_tl(dst, dst, r_fcc1);
1000 }
1001
1002 // 3: FCC0 & FCC1
1003 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1004                                     unsigned int fcc_offset)
1005 {
1006     TCGv r_fcc1;
1007
1008     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1009     gen_mov_reg_FCC0(dst, src, fcc_offset);
1010     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1011     tcg_gen_and_tl(dst, dst, r_fcc1);
1012 }
1013
1014 // 0: !(FCC0 | FCC1)
1015 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1016                                     unsigned int fcc_offset)
1017 {
1018     TCGv r_fcc1;
1019
1020     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1021     gen_mov_reg_FCC0(dst, src, fcc_offset);
1022     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1023     tcg_gen_or_tl(dst, dst, r_fcc1);
1024     tcg_gen_xori_tl(dst, dst, 0x1);
1025 }
1026
1027 // 0 or 3: !(FCC0 ^ FCC1)
1028 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1029                                     unsigned int fcc_offset)
1030 {
1031     TCGv r_fcc1;
1032
1033     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1034     gen_mov_reg_FCC0(dst, src, fcc_offset);
1035     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1036     tcg_gen_xor_tl(dst, dst, r_fcc1);
1037     tcg_gen_xori_tl(dst, dst, 0x1);
1038 }
1039
1040 // 0 or 2: !FCC0
1041 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1042                                     unsigned int fcc_offset)
1043 {
1044     gen_mov_reg_FCC0(dst, src, fcc_offset);
1045     tcg_gen_xori_tl(dst, dst, 0x1);
1046 }
1047
1048 // !1: !(FCC0 & !FCC1)
1049 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1050                                     unsigned int fcc_offset)
1051 {
1052     TCGv r_fcc1;
1053
1054     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1055     gen_mov_reg_FCC0(dst, src, fcc_offset);
1056     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1057     tcg_gen_xori_tl(r_fcc1, r_fcc1, 0x1);
1058     tcg_gen_and_tl(dst, dst, r_fcc1);
1059     tcg_gen_xori_tl(dst, dst, 0x1);
1060 }
1061
1062 // 0 or 1: !FCC1
1063 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1064                                     unsigned int fcc_offset)
1065 {
1066     gen_mov_reg_FCC1(dst, src, fcc_offset);
1067     tcg_gen_xori_tl(dst, dst, 0x1);
1068 }
1069
1070 // !2: !(!FCC0 & FCC1)
1071 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1072                                     unsigned int fcc_offset)
1073 {
1074     TCGv r_fcc1;
1075
1076     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1077     gen_mov_reg_FCC0(dst, src, fcc_offset);
1078     tcg_gen_xori_tl(dst, dst, 0x1);
1079     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1080     tcg_gen_and_tl(dst, dst, r_fcc1);
1081     tcg_gen_xori_tl(dst, dst, 0x1);
1082 }
1083
1084 // !3: !(FCC0 & FCC1)
1085 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1086                                     unsigned int fcc_offset)
1087 {
1088     TCGv r_fcc1;
1089
1090     r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1091     gen_mov_reg_FCC0(dst, src, fcc_offset);
1092     gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1093     tcg_gen_and_tl(dst, dst, r_fcc1);
1094     tcg_gen_xori_tl(dst, dst, 0x1);
1095 }
1096
1097 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1098                                target_ulong pc2, TCGv r_cond)
1099 {
1100     TCGv r_zero;
1101     int l1;
1102
1103     l1 = gen_new_label();
1104     r_zero = tcg_const_tl(0);
1105
1106     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1);
1107
1108     gen_goto_tb(dc, 0, pc1, pc1 + 4);
1109
1110     gen_set_label(l1);
1111     gen_goto_tb(dc, 1, pc2, pc2 + 4);
1112 }
1113
1114 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1115                                 target_ulong pc2, TCGv r_cond)
1116 {
1117     TCGv r_zero;
1118     int l1;
1119
1120     l1 = gen_new_label();
1121     r_zero = tcg_const_tl(0);
1122
1123     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1);
1124
1125     gen_goto_tb(dc, 0, pc2, pc1);
1126
1127     gen_set_label(l1);
1128     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1129 }
1130
1131 static inline void gen_branch(DisasContext *dc, target_ulong pc,
1132                               target_ulong npc)
1133 {
1134     gen_goto_tb(dc, 0, pc, npc);
1135 }
1136
1137 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1138                                       TCGv r_cond)
1139 {
1140     TCGv r_zero;
1141     int l1, l2;
1142
1143     l1 = gen_new_label();
1144     l2 = gen_new_label();
1145     r_zero = tcg_const_tl(0);
1146
1147     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1);
1148
1149     gen_movl_npc_im(npc1);
1150     gen_op_jmp_label(l2);
1151
1152     gen_set_label(l1);
1153     gen_movl_npc_im(npc2);
1154     gen_set_label(l2);
1155 }
1156
1157 /* call this function before using T2 as it may have been set for a jump */
1158 static inline void flush_T2(DisasContext * dc)
1159 {
1160     if (dc->npc == JUMP_PC) {
1161         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
1162         dc->npc = DYNAMIC_PC;
1163     }
1164 }
1165
1166 static inline void save_npc(DisasContext * dc)
1167 {
1168     if (dc->npc == JUMP_PC) {
1169         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
1170         dc->npc = DYNAMIC_PC;
1171     } else if (dc->npc != DYNAMIC_PC) {
1172         gen_movl_npc_im(dc->npc);
1173     }
1174 }
1175
1176 static inline void save_state(DisasContext * dc)
1177 {
1178     gen_jmp_im(dc->pc);
1179     save_npc(dc);
1180 }
1181
1182 static inline void gen_mov_pc_npc(DisasContext * dc)
1183 {
1184     if (dc->npc == JUMP_PC) {
1185         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
1186         tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1187         tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
1188         dc->pc = DYNAMIC_PC;
1189     } else if (dc->npc == DYNAMIC_PC) {
1190         tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1191         tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
1192         dc->pc = DYNAMIC_PC;
1193     } else {
1194         dc->pc = dc->npc;
1195     }
1196 }
1197
1198 static inline void gen_op_next_insn(void)
1199 {
1200     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1201     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
1202     tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, 4);
1203     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1204 }
1205
1206 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1207 {
1208     TCGv r_src;
1209
1210 #ifdef TARGET_SPARC64
1211     if (cc)
1212         r_src = cpu_xcc;
1213     else
1214         r_src = cpu_psr;
1215 #else
1216     r_src = cpu_psr;
1217 #endif
1218     switch (cond) {
1219     case 0x0:
1220         gen_op_eval_bn(r_dst);
1221         break;
1222     case 0x1:
1223         gen_op_eval_be(r_dst, r_src);
1224         break;
1225     case 0x2:
1226         gen_op_eval_ble(r_dst, r_src);
1227         break;
1228     case 0x3:
1229         gen_op_eval_bl(r_dst, r_src);
1230         break;
1231     case 0x4:
1232         gen_op_eval_bleu(r_dst, r_src);
1233         break;
1234     case 0x5:
1235         gen_op_eval_bcs(r_dst, r_src);
1236         break;
1237     case 0x6:
1238         gen_op_eval_bneg(r_dst, r_src);
1239         break;
1240     case 0x7:
1241         gen_op_eval_bvs(r_dst, r_src);
1242         break;
1243     case 0x8:
1244         gen_op_eval_ba(r_dst);
1245         break;
1246     case 0x9:
1247         gen_op_eval_bne(r_dst, r_src);
1248         break;
1249     case 0xa:
1250         gen_op_eval_bg(r_dst, r_src);
1251         break;
1252     case 0xb:
1253         gen_op_eval_bge(r_dst, r_src);
1254         break;
1255     case 0xc:
1256         gen_op_eval_bgu(r_dst, r_src);
1257         break;
1258     case 0xd:
1259         gen_op_eval_bcc(r_dst, r_src);
1260         break;
1261     case 0xe:
1262         gen_op_eval_bpos(r_dst, r_src);
1263         break;
1264     case 0xf:
1265         gen_op_eval_bvc(r_dst, r_src);
1266         break;
1267     }
1268 }
1269
1270 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1271 {
1272     unsigned int offset;
1273
1274     switch (cc) {
1275     default:
1276     case 0x0:
1277         offset = 0;
1278         break;
1279     case 0x1:
1280         offset = 32 - 10;
1281         break;
1282     case 0x2:
1283         offset = 34 - 10;
1284         break;
1285     case 0x3:
1286         offset = 36 - 10;
1287         break;
1288     }
1289
1290     switch (cond) {
1291     case 0x0:
1292         gen_op_eval_bn(r_dst);
1293         break;
1294     case 0x1:
1295         gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1296         break;
1297     case 0x2:
1298         gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1299         break;
1300     case 0x3:
1301         gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1302         break;
1303     case 0x4:
1304         gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1305         break;
1306     case 0x5:
1307         gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1308         break;
1309     case 0x6:
1310         gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1311         break;
1312     case 0x7:
1313         gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1314         break;
1315     case 0x8:
1316         gen_op_eval_ba(r_dst);
1317         break;
1318     case 0x9:
1319         gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1320         break;
1321     case 0xa:
1322         gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1323         break;
1324     case 0xb:
1325         gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1326         break;
1327     case 0xc:
1328         gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1329         break;
1330     case 0xd:
1331         gen_op_eval_fble(r_dst, cpu_fsr, offset);
1332         break;
1333     case 0xe:
1334         gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1335         break;
1336     case 0xf:
1337         gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1338         break;
1339     }
1340 }
1341
1342 #ifdef TARGET_SPARC64
1343 // Inverted logic
1344 static const int gen_tcg_cond_reg[8] = {
1345     -1,
1346     TCG_COND_NE,
1347     TCG_COND_GT,
1348     TCG_COND_GE,
1349     -1,
1350     TCG_COND_EQ,
1351     TCG_COND_LE,
1352     TCG_COND_LT,
1353 };
1354
1355 static inline void gen_cond_reg(TCGv r_dst, int cond)
1356 {
1357     TCGv r_zero;
1358     int l1;
1359
1360     l1 = gen_new_label();
1361     r_zero = tcg_const_tl(0);
1362     tcg_gen_mov_tl(r_dst, r_zero);
1363     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
1364     tcg_gen_movi_tl(r_dst, 1);
1365     gen_set_label(l1);
1366 }
1367 #endif
1368
1369 /* XXX: potentially incorrect if dynamic npc */
1370 static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1371 {
1372     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1373     target_ulong target = dc->pc + offset;
1374
1375     if (cond == 0x0) {
1376         /* unconditional not taken */
1377         if (a) {
1378             dc->pc = dc->npc + 4;
1379             dc->npc = dc->pc + 4;
1380         } else {
1381             dc->pc = dc->npc;
1382             dc->npc = dc->pc + 4;
1383         }
1384     } else if (cond == 0x8) {
1385         /* unconditional taken */
1386         if (a) {
1387             dc->pc = target;
1388             dc->npc = dc->pc + 4;
1389         } else {
1390             dc->pc = dc->npc;
1391             dc->npc = target;
1392         }
1393     } else {
1394         flush_T2(dc);
1395         gen_cond(cpu_T[2], cc, cond);
1396         if (a) {
1397             gen_branch_a(dc, target, dc->npc, cpu_T[2]);
1398             dc->is_br = 1;
1399         } else {
1400             dc->pc = dc->npc;
1401             dc->jump_pc[0] = target;
1402             dc->jump_pc[1] = dc->npc + 4;
1403             dc->npc = JUMP_PC;
1404         }
1405     }
1406 }
1407
1408 /* XXX: potentially incorrect if dynamic npc */
1409 static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1410 {
1411     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1412     target_ulong target = dc->pc + offset;
1413
1414     if (cond == 0x0) {
1415         /* unconditional not taken */
1416         if (a) {
1417             dc->pc = dc->npc + 4;
1418             dc->npc = dc->pc + 4;
1419         } else {
1420             dc->pc = dc->npc;
1421             dc->npc = dc->pc + 4;
1422         }
1423     } else if (cond == 0x8) {
1424         /* unconditional taken */
1425         if (a) {
1426             dc->pc = target;
1427             dc->npc = dc->pc + 4;
1428         } else {
1429             dc->pc = dc->npc;
1430             dc->npc = target;
1431         }
1432     } else {
1433         flush_T2(dc);
1434         gen_fcond(cpu_T[2], cc, cond);
1435         if (a) {
1436             gen_branch_a(dc, target, dc->npc, cpu_T[2]);
1437             dc->is_br = 1;
1438         } else {
1439             dc->pc = dc->npc;
1440             dc->jump_pc[0] = target;
1441             dc->jump_pc[1] = dc->npc + 4;
1442             dc->npc = JUMP_PC;
1443         }
1444     }
1445 }
1446
1447 #ifdef TARGET_SPARC64
1448 /* XXX: potentially incorrect if dynamic npc */
1449 static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
1450 {
1451     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1452     target_ulong target = dc->pc + offset;
1453
1454     flush_T2(dc);
1455     gen_cond_reg(cpu_T[2], cond);
1456     if (a) {
1457         gen_branch_a(dc, target, dc->npc, cpu_T[2]);
1458         dc->is_br = 1;
1459     } else {
1460         dc->pc = dc->npc;
1461         dc->jump_pc[0] = target;
1462         dc->jump_pc[1] = dc->npc + 4;
1463         dc->npc = JUMP_PC;
1464     }
1465 }
1466
1467 static GenOpFunc * const gen_fcmps[4] = {
1468     helper_fcmps,
1469     helper_fcmps_fcc1,
1470     helper_fcmps_fcc2,
1471     helper_fcmps_fcc3,
1472 };
1473
1474 static GenOpFunc * const gen_fcmpd[4] = {
1475     helper_fcmpd,
1476     helper_fcmpd_fcc1,
1477     helper_fcmpd_fcc2,
1478     helper_fcmpd_fcc3,
1479 };
1480
1481 #if defined(CONFIG_USER_ONLY)
1482 static GenOpFunc * const gen_fcmpq[4] = {
1483     helper_fcmpq,
1484     helper_fcmpq_fcc1,
1485     helper_fcmpq_fcc2,
1486     helper_fcmpq_fcc3,
1487 };
1488 #endif
1489
1490 static GenOpFunc * const gen_fcmpes[4] = {
1491     helper_fcmpes,
1492     helper_fcmpes_fcc1,
1493     helper_fcmpes_fcc2,
1494     helper_fcmpes_fcc3,
1495 };
1496
1497 static GenOpFunc * const gen_fcmped[4] = {
1498     helper_fcmped,
1499     helper_fcmped_fcc1,
1500     helper_fcmped_fcc2,
1501     helper_fcmped_fcc3,
1502 };
1503
1504 #if defined(CONFIG_USER_ONLY)
1505 static GenOpFunc * const gen_fcmpeq[4] = {
1506     helper_fcmpeq,
1507     helper_fcmpeq_fcc1,
1508     helper_fcmpeq_fcc2,
1509     helper_fcmpeq_fcc3,
1510 };
1511 #endif
1512
1513 static inline void gen_op_fcmps(int fccno)
1514 {
1515     tcg_gen_helper_0_0(gen_fcmps[fccno]);
1516 }
1517
1518 static inline void gen_op_fcmpd(int fccno)
1519 {
1520     tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1521 }
1522
1523 #if defined(CONFIG_USER_ONLY)
1524 static inline void gen_op_fcmpq(int fccno)
1525 {
1526     tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1527 }
1528 #endif
1529
1530 static inline void gen_op_fcmpes(int fccno)
1531 {
1532     tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1533 }
1534
1535 static inline void gen_op_fcmped(int fccno)
1536 {
1537     tcg_gen_helper_0_0(gen_fcmped[fccno]);
1538 }
1539
1540 #if defined(CONFIG_USER_ONLY)
1541 static inline void gen_op_fcmpeq(int fccno)
1542 {
1543     tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1544 }
1545 #endif
1546
1547 #else
1548
1549 static inline void gen_op_fcmps(int fccno)
1550 {
1551     tcg_gen_helper_0_0(helper_fcmps);
1552 }
1553
1554 static inline void gen_op_fcmpd(int fccno)
1555 {
1556     tcg_gen_helper_0_0(helper_fcmpd);
1557 }
1558
1559 #if defined(CONFIG_USER_ONLY)
1560 static inline void gen_op_fcmpq(int fccno)
1561 {
1562     tcg_gen_helper_0_0(helper_fcmpq);
1563 }
1564 #endif
1565
1566 static inline void gen_op_fcmpes(int fccno)
1567 {
1568     tcg_gen_helper_0_0(helper_fcmpes);
1569 }
1570
1571 static inline void gen_op_fcmped(int fccno)
1572 {
1573     tcg_gen_helper_0_0(helper_fcmped);
1574 }
1575
1576 #if defined(CONFIG_USER_ONLY)
1577 static inline void gen_op_fcmpeq(int fccno)
1578 {
1579     tcg_gen_helper_0_0(helper_fcmpeq);
1580 }
1581 #endif
1582
1583 #endif
1584
1585 static inline void gen_op_fpexception_im(int fsr_flags)
1586 {
1587     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1588     tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1589     gen_op_exception(TT_FP_EXCP);
1590 }
1591
1592 static int gen_trap_ifnofpu(DisasContext * dc)
1593 {
1594 #if !defined(CONFIG_USER_ONLY)
1595     if (!dc->fpu_enabled) {
1596         save_state(dc);
1597         gen_op_exception(TT_NFPU_INSN);
1598         dc->is_br = 1;
1599         return 1;
1600     }
1601 #endif
1602     return 0;
1603 }
1604
1605 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1606 {
1607     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1608 }
1609
1610 static inline void gen_clear_float_exceptions(void)
1611 {
1612     tcg_gen_helper_0_0(helper_clear_float_exceptions);
1613 }
1614
1615 /* asi moves */
1616 #ifdef TARGET_SPARC64
1617 static inline void gen_ld_asi(int insn, int size, int sign)
1618 {
1619     int asi, offset;
1620     TCGv r_size, r_sign;
1621
1622     r_size = tcg_temp_new(TCG_TYPE_I32);
1623     r_sign = tcg_temp_new(TCG_TYPE_I32);
1624     tcg_gen_movi_i32(r_size, size);
1625     tcg_gen_movi_i32(r_sign, sign);
1626     if (IS_IMM) {
1627         offset = GET_FIELD(insn, 25, 31);
1628         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1629         tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
1630     } else {
1631         asi = GET_FIELD(insn, 19, 26);
1632         tcg_gen_movi_i32(cpu_T[1], asi);
1633     }
1634     tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], cpu_T[1], r_size,
1635                        r_sign);
1636 }
1637
1638 static inline void gen_st_asi(int insn, int size)
1639 {
1640     int asi, offset;
1641     TCGv r_asi, r_size;
1642
1643     r_asi = tcg_temp_new(TCG_TYPE_I32);
1644     r_size = tcg_temp_new(TCG_TYPE_I32);
1645     tcg_gen_movi_i32(r_size, size);
1646     if (IS_IMM) {
1647         offset = GET_FIELD(insn, 25, 31);
1648         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1649         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1650     } else {
1651         asi = GET_FIELD(insn, 19, 26);
1652         tcg_gen_movi_i32(r_asi, asi);
1653     }
1654     tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi, r_size);
1655 }
1656
1657 static inline void gen_ldf_asi(int insn, int size, int rd)
1658 {
1659     int asi, offset;
1660     TCGv r_asi, r_size, r_rd;
1661
1662     r_asi = tcg_temp_new(TCG_TYPE_I32);
1663     r_size = tcg_temp_new(TCG_TYPE_I32);
1664     r_rd = tcg_temp_new(TCG_TYPE_I32);
1665     tcg_gen_movi_i32(r_size, size);
1666     tcg_gen_movi_i32(r_rd, rd);
1667     if (IS_IMM) {
1668         offset = GET_FIELD(insn, 25, 31);
1669         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1670         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1671     } else {
1672         asi = GET_FIELD(insn, 19, 26);
1673         tcg_gen_movi_i32(r_asi, asi);
1674     }
1675     tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, r_size, r_rd);
1676 }
1677
1678 static inline void gen_stf_asi(int insn, int size, int rd)
1679 {
1680     int asi, offset;
1681     TCGv r_asi, r_size, r_rd;
1682
1683     r_asi = tcg_temp_new(TCG_TYPE_I32);
1684     r_size = tcg_temp_new(TCG_TYPE_I32);
1685     r_rd = tcg_temp_new(TCG_TYPE_I32);
1686     tcg_gen_movi_i32(r_size, size);
1687     tcg_gen_movi_i32(r_rd, rd);
1688     if (IS_IMM) {
1689         offset = GET_FIELD(insn, 25, 31);
1690         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1691         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1692     } else {
1693         asi = GET_FIELD(insn, 19, 26);
1694         tcg_gen_movi_i32(r_asi, asi);
1695     }
1696     tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, r_size, r_rd);
1697 }
1698
1699 static inline void gen_swap_asi(int insn)
1700 {
1701     int asi, offset;
1702     TCGv r_size, r_sign, r_temp;
1703
1704     r_size = tcg_temp_new(TCG_TYPE_I32);
1705     r_sign = tcg_temp_new(TCG_TYPE_I32);
1706     r_temp = tcg_temp_new(TCG_TYPE_I32);
1707     tcg_gen_movi_i32(r_size, 4);
1708     tcg_gen_movi_i32(r_sign, 0);
1709     if (IS_IMM) {
1710         offset = GET_FIELD(insn, 25, 31);
1711         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1712         tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
1713     } else {
1714         asi = GET_FIELD(insn, 19, 26);
1715         tcg_gen_movi_i32(cpu_T[1], asi);
1716     }
1717     tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
1718                        r_sign);
1719     tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
1720     tcg_gen_mov_i32(cpu_T[1], r_temp);
1721 }
1722
1723 static inline void gen_ldda_asi(int insn)
1724 {
1725     int asi, offset;
1726     TCGv r_size, r_sign, r_dword;
1727
1728     r_size = tcg_temp_new(TCG_TYPE_I32);
1729     r_sign = tcg_temp_new(TCG_TYPE_I32);
1730     r_dword = tcg_temp_new(TCG_TYPE_I64);
1731     tcg_gen_movi_i32(r_size, 8);
1732     tcg_gen_movi_i32(r_sign, 0);
1733     if (IS_IMM) {
1734         offset = GET_FIELD(insn, 25, 31);
1735         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1736         tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
1737     } else {
1738         asi = GET_FIELD(insn, 19, 26);
1739         tcg_gen_movi_i32(cpu_T[1], asi);
1740     }
1741     tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
1742                        r_sign);
1743     tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1744     tcg_gen_shri_i64(r_dword, r_dword, 32);
1745     tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1746 }
1747
1748 static inline void gen_cas_asi(int insn, int rd)
1749 {
1750     int asi, offset;
1751     TCGv r_val1, r_asi;
1752
1753     r_val1 = tcg_temp_new(TCG_TYPE_I32);
1754     r_asi = tcg_temp_new(TCG_TYPE_I32);
1755     gen_movl_reg_TN(rd, r_val1);
1756     if (IS_IMM) {
1757         offset = GET_FIELD(insn, 25, 31);
1758         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1759         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1760     } else {
1761         asi = GET_FIELD(insn, 19, 26);
1762         tcg_gen_movi_i32(r_asi, asi);
1763     }
1764     tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1765                        r_asi);
1766 }
1767
1768 static inline void gen_casx_asi(int insn, int rd)
1769 {
1770     int asi, offset;
1771     TCGv r_val1, r_asi;
1772
1773     r_val1 = tcg_temp_new(TCG_TYPE_I64);
1774     r_asi = tcg_temp_new(TCG_TYPE_I32);
1775     gen_movl_reg_TN(rd, r_val1);
1776     if (IS_IMM) {
1777         offset = GET_FIELD(insn, 25, 31);
1778         tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1779         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1780     } else {
1781         asi = GET_FIELD(insn, 19, 26);
1782         tcg_gen_movi_i32(r_asi, asi);
1783     }
1784     tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1785                        r_asi);
1786 }
1787
1788 #elif !defined(CONFIG_USER_ONLY)
1789
1790 static inline void gen_ld_asi(int insn, int size, int sign)
1791 {
1792     int asi;
1793     TCGv r_size, r_sign, r_dword;
1794
1795     r_size = tcg_temp_new(TCG_TYPE_I32);
1796     r_sign = tcg_temp_new(TCG_TYPE_I32);
1797     r_dword = tcg_temp_new(TCG_TYPE_I64);
1798     tcg_gen_movi_i32(r_size, size);
1799     tcg_gen_movi_i32(r_sign, sign);
1800     asi = GET_FIELD(insn, 19, 26);
1801     tcg_gen_movi_i32(cpu_T[1], asi);
1802     tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
1803                        r_sign);
1804     tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1805 }
1806
1807 static inline void gen_st_asi(int insn, int size)
1808 {
1809     int asi;
1810     TCGv r_dword, r_asi, r_size;
1811
1812     r_dword = tcg_temp_new(TCG_TYPE_I64);
1813     tcg_gen_extu_i32_i64(r_dword, cpu_T[1]);
1814     r_asi = tcg_temp_new(TCG_TYPE_I32);
1815     r_size = tcg_temp_new(TCG_TYPE_I32);
1816     asi = GET_FIELD(insn, 19, 26);
1817     tcg_gen_movi_i32(r_asi, asi);
1818     tcg_gen_movi_i32(r_size, size);
1819     tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
1820 }
1821
1822 static inline void gen_swap_asi(int insn)
1823 {
1824     int asi;
1825     TCGv r_size, r_sign, r_temp;
1826
1827     r_size = tcg_temp_new(TCG_TYPE_I32);
1828     r_sign = tcg_temp_new(TCG_TYPE_I32);
1829     r_temp = tcg_temp_new(TCG_TYPE_I32);
1830     tcg_gen_movi_i32(r_size, 4);
1831     tcg_gen_movi_i32(r_sign, 0);
1832     asi = GET_FIELD(insn, 19, 26);
1833     tcg_gen_movi_i32(cpu_T[1], asi);
1834     tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
1835                        r_sign);
1836     tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
1837     tcg_gen_mov_i32(cpu_T[1], r_temp);
1838 }
1839
1840 static inline void gen_ldda_asi(int insn)
1841 {
1842     int asi;
1843     TCGv r_size, r_sign, r_dword;
1844
1845     r_size = tcg_temp_new(TCG_TYPE_I32);
1846     r_sign = tcg_temp_new(TCG_TYPE_I32);
1847     r_dword = tcg_temp_new(TCG_TYPE_I64);
1848     tcg_gen_movi_i32(r_size, 8);
1849     tcg_gen_movi_i32(r_sign, 0);
1850     asi = GET_FIELD(insn, 19, 26);
1851     tcg_gen_movi_i32(cpu_T[1], asi);
1852     tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
1853                        r_sign);
1854     tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1855     tcg_gen_shri_i64(r_dword, r_dword, 32);
1856     tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1857 }
1858 #endif
1859
1860 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1861 static inline void gen_ldstub_asi(int insn)
1862 {
1863     int asi;
1864     TCGv r_dword, r_asi, r_size;
1865
1866     gen_ld_asi(insn, 1, 0);
1867
1868     r_dword = tcg_temp_new(TCG_TYPE_I64);
1869     r_asi = tcg_temp_new(TCG_TYPE_I32);
1870     r_size = tcg_temp_new(TCG_TYPE_I32);
1871     asi = GET_FIELD(insn, 19, 26);
1872     tcg_gen_movi_i32(r_dword, 0xff);
1873     tcg_gen_movi_i32(r_asi, asi);
1874     tcg_gen_movi_i32(r_size, 1);
1875     tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
1876 }
1877 #endif
1878
1879 /* before an instruction, dc->pc must be static */
1880 static void disas_sparc_insn(DisasContext * dc)
1881 {
1882     unsigned int insn, opc, rs1, rs2, rd;
1883
1884     insn = ldl_code(dc->pc);
1885     opc = GET_FIELD(insn, 0, 1);
1886
1887     rd = GET_FIELD(insn, 2, 6);
1888     switch (opc) {
1889     case 0:                     /* branches/sethi */
1890         {
1891             unsigned int xop = GET_FIELD(insn, 7, 9);
1892             int32_t target;
1893             switch (xop) {
1894 #ifdef TARGET_SPARC64
1895             case 0x1:           /* V9 BPcc */
1896                 {
1897                     int cc;
1898
1899                     target = GET_FIELD_SP(insn, 0, 18);
1900                     target = sign_extend(target, 18);
1901                     target <<= 2;
1902                     cc = GET_FIELD_SP(insn, 20, 21);
1903                     if (cc == 0)
1904                         do_branch(dc, target, insn, 0);
1905                     else if (cc == 2)
1906                         do_branch(dc, target, insn, 1);
1907                     else
1908                         goto illegal_insn;
1909                     goto jmp_insn;
1910                 }
1911             case 0x3:           /* V9 BPr */
1912                 {
1913                     target = GET_FIELD_SP(insn, 0, 13) |
1914                         (GET_FIELD_SP(insn, 20, 21) << 14);
1915                     target = sign_extend(target, 16);
1916                     target <<= 2;
1917                     rs1 = GET_FIELD(insn, 13, 17);
1918                     gen_movl_reg_T0(rs1);
1919                     do_branch_reg(dc, target, insn);
1920                     goto jmp_insn;
1921                 }
1922             case 0x5:           /* V9 FBPcc */
1923                 {
1924                     int cc = GET_FIELD_SP(insn, 20, 21);
1925                     if (gen_trap_ifnofpu(dc))
1926                         goto jmp_insn;
1927                     target = GET_FIELD_SP(insn, 0, 18);
1928                     target = sign_extend(target, 19);
1929                     target <<= 2;
1930                     do_fbranch(dc, target, insn, cc);
1931                     goto jmp_insn;
1932                 }
1933 #else
1934             case 0x7:           /* CBN+x */
1935                 {
1936                     goto ncp_insn;
1937                 }
1938 #endif
1939             case 0x2:           /* BN+x */
1940                 {
1941                     target = GET_FIELD(insn, 10, 31);
1942                     target = sign_extend(target, 22);
1943                     target <<= 2;
1944                     do_branch(dc, target, insn, 0);
1945                     goto jmp_insn;
1946                 }
1947             case 0x6:           /* FBN+x */
1948                 {
1949                     if (gen_trap_ifnofpu(dc))
1950                         goto jmp_insn;
1951                     target = GET_FIELD(insn, 10, 31);
1952                     target = sign_extend(target, 22);
1953                     target <<= 2;
1954                     do_fbranch(dc, target, insn, 0);
1955                     goto jmp_insn;
1956                 }
1957             case 0x4:           /* SETHI */
1958 #define OPTIM
1959 #if defined(OPTIM)
1960                 if (rd) { // nop
1961 #endif
1962                     uint32_t value = GET_FIELD(insn, 10, 31);
1963                     tcg_gen_movi_tl(cpu_T[0], value << 10);
1964                     gen_movl_T0_reg(rd);
1965 #if defined(OPTIM)
1966                 }
1967 #endif
1968                 break;
1969             case 0x0:           /* UNIMPL */
1970             default:
1971                 goto illegal_insn;
1972             }
1973             break;
1974         }
1975         break;
1976     case 1:
1977         /*CALL*/ {
1978             target_long target = GET_FIELDs(insn, 2, 31) << 2;
1979
1980             tcg_gen_movi_tl(cpu_T[0], dc->pc);
1981             gen_movl_T0_reg(15);
1982             target += dc->pc;
1983             gen_mov_pc_npc(dc);
1984             dc->npc = target;
1985         }
1986         goto jmp_insn;
1987     case 2:                     /* FPU & Logical Operations */
1988         {
1989             unsigned int xop = GET_FIELD(insn, 7, 12);
1990             if (xop == 0x3a) {  /* generate trap */
1991                 int cond;
1992
1993                 rs1 = GET_FIELD(insn, 13, 17);
1994                 gen_movl_reg_T0(rs1);
1995                 if (IS_IMM) {
1996                     rs2 = GET_FIELD(insn, 25, 31);
1997                     tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2);
1998                 } else {
1999                     rs2 = GET_FIELD(insn, 27, 31);
2000 #if defined(OPTIM)
2001                     if (rs2 != 0) {
2002 #endif
2003                         gen_movl_reg_T1(rs2);
2004                         gen_op_add_T1_T0();
2005 #if defined(OPTIM)
2006                     }
2007 #endif
2008                 }
2009                 cond = GET_FIELD(insn, 3, 6);
2010                 if (cond == 0x8) {
2011                     save_state(dc);
2012                     tcg_gen_helper_0_1(helper_trap, cpu_T[0]);
2013                 } else if (cond != 0) {
2014                     TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2015 #ifdef TARGET_SPARC64
2016                     /* V9 icc/xcc */
2017                     int cc = GET_FIELD_SP(insn, 11, 12);
2018
2019                     save_state(dc);
2020                     if (cc == 0)
2021                         gen_cond(r_cond, 0, cond);
2022                     else if (cc == 2)
2023                         gen_cond(r_cond, 1, cond);
2024                     else
2025                         goto illegal_insn;
2026 #else
2027                     save_state(dc);
2028                     gen_cond(r_cond, 0, cond);
2029 #endif
2030                     tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], r_cond);
2031                 }
2032                 gen_op_next_insn();
2033                 tcg_gen_exit_tb(0);
2034                 dc->is_br = 1;
2035                 goto jmp_insn;
2036             } else if (xop == 0x28) {
2037                 rs1 = GET_FIELD(insn, 13, 17);
2038                 switch(rs1) {
2039                 case 0: /* rdy */
2040 #ifndef TARGET_SPARC64
2041                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2042                                        manual, rdy on the microSPARC
2043                                        II */
2044                 case 0x0f:          /* stbar in the SPARCv8 manual,
2045                                        rdy on the microSPARC II */
2046                 case 0x10 ... 0x1f: /* implementation-dependent in the
2047                                        SPARCv8 manual, rdy on the
2048                                        microSPARC II */
2049 #endif
2050                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
2051                     gen_movl_T0_reg(rd);
2052                     break;
2053 #ifdef TARGET_SPARC64
2054                 case 0x2: /* V9 rdccr */
2055                     gen_op_rdccr();
2056                     gen_movl_T0_reg(rd);
2057                     break;
2058                 case 0x3: /* V9 rdasi */
2059                     gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
2060                     gen_movl_T0_reg(rd);
2061                     break;
2062                 case 0x4: /* V9 rdtick */
2063                     {
2064                         TCGv r_tickptr;
2065
2066                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2067                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2068                                        offsetof(CPUState, tick));
2069                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2070                                            r_tickptr);
2071                         gen_movl_T0_reg(rd);
2072                     }
2073                     break;
2074                 case 0x5: /* V9 rdpc */
2075                     tcg_gen_movi_tl(cpu_T[0], dc->pc);
2076                     gen_movl_T0_reg(rd);
2077                     break;
2078                 case 0x6: /* V9 rdfprs */
2079                     gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
2080                     gen_movl_T0_reg(rd);
2081                     break;
2082                 case 0xf: /* V9 membar */
2083                     break; /* no effect */
2084                 case 0x13: /* Graphics Status */
2085                     if (gen_trap_ifnofpu(dc))
2086                         goto jmp_insn;
2087                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
2088                     gen_movl_T0_reg(rd);
2089                     break;
2090                 case 0x17: /* Tick compare */
2091                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
2092                     gen_movl_T0_reg(rd);
2093                     break;
2094                 case 0x18: /* System tick */
2095                     {
2096                         TCGv r_tickptr;
2097
2098                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2099                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2100                                        offsetof(CPUState, stick));
2101                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2102                                            r_tickptr);
2103                         gen_movl_T0_reg(rd);
2104                     }
2105                     break;
2106                 case 0x19: /* System tick compare */
2107                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
2108                     gen_movl_T0_reg(rd);
2109                     break;
2110                 case 0x10: /* Performance Control */
2111                 case 0x11: /* Performance Instrumentation Counter */
2112                 case 0x12: /* Dispatch Control */
2113                 case 0x14: /* Softint set, WO */
2114                 case 0x15: /* Softint clear, WO */
2115                 case 0x16: /* Softint write */
2116 #endif
2117                 default:
2118                     goto illegal_insn;
2119                 }
2120 #if !defined(CONFIG_USER_ONLY)
2121             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2122 #ifndef TARGET_SPARC64
2123                 if (!supervisor(dc))
2124                     goto priv_insn;
2125                 tcg_gen_helper_1_0(helper_rdpsr, cpu_T[0]);
2126 #else
2127                 if (!hypervisor(dc))
2128                     goto priv_insn;
2129                 rs1 = GET_FIELD(insn, 13, 17);
2130                 switch (rs1) {
2131                 case 0: // hpstate
2132                     // gen_op_rdhpstate();
2133                     break;
2134                 case 1: // htstate
2135                     // gen_op_rdhtstate();
2136                     break;
2137                 case 3: // hintp
2138                     gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
2139                     break;
2140                 case 5: // htba
2141                     gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
2142                     break;
2143                 case 6: // hver
2144                     gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
2145                     break;
2146                 case 31: // hstick_cmpr
2147                     gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2148                     break;
2149                 default:
2150                     goto illegal_insn;
2151                 }
2152 #endif
2153                 gen_movl_T0_reg(rd);
2154                 break;
2155             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2156                 if (!supervisor(dc))
2157                     goto priv_insn;
2158 #ifdef TARGET_SPARC64
2159                 rs1 = GET_FIELD(insn, 13, 17);
2160                 switch (rs1) {
2161                 case 0: // tpc
2162                     {
2163                         TCGv r_tsptr;
2164
2165                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2166                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2167                                        offsetof(CPUState, tsptr));
2168                         tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2169                                       offsetof(trap_state, tpc));
2170                     }
2171                     break;
2172                 case 1: // tnpc
2173                     {
2174                         TCGv r_tsptr;
2175
2176                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2177                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2178                                        offsetof(CPUState, tsptr));
2179                         tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2180                                       offsetof(trap_state, tnpc));
2181                     }
2182                     break;
2183                 case 2: // tstate
2184                     {
2185                         TCGv r_tsptr;
2186
2187                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2188                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2189                                        offsetof(CPUState, tsptr));
2190                         tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2191                                       offsetof(trap_state, tstate));
2192                     }
2193                     break;
2194                 case 3: // tt
2195                     {
2196                         TCGv r_tsptr;
2197
2198                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2199                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2200                                        offsetof(CPUState, tsptr));
2201                         tcg_gen_ld_i32(cpu_T[0], r_tsptr,
2202                                        offsetof(trap_state, tt));
2203                     }
2204                     break;
2205                 case 4: // tick
2206                     {
2207                         TCGv r_tickptr;
2208
2209                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2210                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2211                                        offsetof(CPUState, tick));
2212                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2213                                            r_tickptr);
2214                         gen_movl_T0_reg(rd);
2215                     }
2216                     break;
2217                 case 5: // tba
2218                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
2219                     break;
2220                 case 6: // pstate
2221                     gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate));
2222                     break;
2223                 case 7: // tl
2224                     gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
2225                     break;
2226                 case 8: // pil
2227                     gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
2228                     break;
2229                 case 9: // cwp
2230                     gen_op_rdcwp();
2231                     break;
2232                 case 10: // cansave
2233                     gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
2234                     break;
2235                 case 11: // canrestore
2236                     gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
2237                     break;
2238                 case 12: // cleanwin
2239                     gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
2240                     break;
2241                 case 13: // otherwin
2242                     gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
2243                     break;
2244                 case 14: // wstate
2245                     gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
2246                     break;
2247                 case 16: // UA2005 gl
2248                     gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
2249                     break;
2250                 case 26: // UA2005 strand status
2251                     if (!hypervisor(dc))
2252                         goto priv_insn;
2253                     gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
2254                     break;
2255                 case 31: // ver
2256                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
2257                     break;
2258                 case 15: // fq
2259                 default:
2260                     goto illegal_insn;
2261                 }
2262 #else
2263                 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
2264 #endif
2265                 gen_movl_T0_reg(rd);
2266                 break;
2267             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2268 #ifdef TARGET_SPARC64
2269                 gen_op_flushw();
2270 #else
2271                 if (!supervisor(dc))
2272                     goto priv_insn;
2273                 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
2274                 gen_movl_T0_reg(rd);
2275 #endif
2276                 break;
2277 #endif
2278             } else if (xop == 0x34) {   /* FPU Operations */
2279                 if (gen_trap_ifnofpu(dc))
2280                     goto jmp_insn;
2281                 gen_op_clear_ieee_excp_and_FTT();
2282                 rs1 = GET_FIELD(insn, 13, 17);
2283                 rs2 = GET_FIELD(insn, 27, 31);
2284                 xop = GET_FIELD(insn, 18, 26);
2285                 switch (xop) {
2286                     case 0x1: /* fmovs */
2287                         gen_op_load_fpr_FT0(rs2);
2288                         gen_op_store_FT0_fpr(rd);
2289                         break;
2290                     case 0x5: /* fnegs */
2291                         gen_op_load_fpr_FT1(rs2);
2292                         gen_op_fnegs();
2293                         gen_op_store_FT0_fpr(rd);
2294                         break;
2295                     case 0x9: /* fabss */
2296                         gen_op_load_fpr_FT1(rs2);
2297                         tcg_gen_helper_0_0(helper_fabss);
2298                         gen_op_store_FT0_fpr(rd);
2299                         break;
2300                     case 0x29: /* fsqrts */
2301                         gen_op_load_fpr_FT1(rs2);
2302                         gen_clear_float_exceptions();
2303                         tcg_gen_helper_0_0(helper_fsqrts);
2304                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2305                         gen_op_store_FT0_fpr(rd);
2306                         break;
2307                     case 0x2a: /* fsqrtd */
2308                         gen_op_load_fpr_DT1(DFPREG(rs2));
2309                         gen_clear_float_exceptions();
2310                         tcg_gen_helper_0_0(helper_fsqrtd);
2311                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2312                         gen_op_store_DT0_fpr(DFPREG(rd));
2313                         break;
2314                     case 0x2b: /* fsqrtq */
2315 #if defined(CONFIG_USER_ONLY)
2316                         gen_op_load_fpr_QT1(QFPREG(rs2));
2317                         gen_clear_float_exceptions();
2318                         tcg_gen_helper_0_0(helper_fsqrtq);
2319                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2320                         gen_op_store_QT0_fpr(QFPREG(rd));
2321                         break;
2322 #else
2323                         goto nfpu_insn;
2324 #endif
2325                     case 0x41:
2326                         gen_op_load_fpr_FT0(rs1);
2327                         gen_op_load_fpr_FT1(rs2);
2328                         gen_clear_float_exceptions();
2329                         gen_op_fadds();
2330                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2331                         gen_op_store_FT0_fpr(rd);
2332                         break;
2333                     case 0x42:
2334                         gen_op_load_fpr_DT0(DFPREG(rs1));
2335                         gen_op_load_fpr_DT1(DFPREG(rs2));
2336                         gen_clear_float_exceptions();
2337                         gen_op_faddd();
2338                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2339                         gen_op_store_DT0_fpr(DFPREG(rd));
2340                         break;
2341                     case 0x43: /* faddq */
2342 #if defined(CONFIG_USER_ONLY)
2343                         gen_op_load_fpr_QT0(QFPREG(rs1));
2344                         gen_op_load_fpr_QT1(QFPREG(rs2));
2345                         gen_clear_float_exceptions();
2346                         gen_op_faddq();
2347                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2348                         gen_op_store_QT0_fpr(QFPREG(rd));
2349                         break;
2350 #else
2351                         goto nfpu_insn;
2352 #endif
2353                     case 0x45:
2354                         gen_op_load_fpr_FT0(rs1);
2355                         gen_op_load_fpr_FT1(rs2);
2356                         gen_clear_float_exceptions();
2357                         gen_op_fsubs();
2358                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2359                         gen_op_store_FT0_fpr(rd);
2360                         break;
2361                     case 0x46:
2362                         gen_op_load_fpr_DT0(DFPREG(rs1));
2363                         gen_op_load_fpr_DT1(DFPREG(rs2));
2364                         gen_clear_float_exceptions();
2365                         gen_op_fsubd();
2366                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2367                         gen_op_store_DT0_fpr(DFPREG(rd));
2368                         break;
2369                     case 0x47: /* fsubq */
2370 #if defined(CONFIG_USER_ONLY)
2371                         gen_op_load_fpr_QT0(QFPREG(rs1));
2372                         gen_op_load_fpr_QT1(QFPREG(rs2));
2373                         gen_clear_float_exceptions();
2374                         gen_op_fsubq();
2375                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2376                         gen_op_store_QT0_fpr(QFPREG(rd));
2377                         break;
2378 #else
2379                         goto nfpu_insn;
2380 #endif
2381                     case 0x49:
2382                         gen_op_load_fpr_FT0(rs1);
2383                         gen_op_load_fpr_FT1(rs2);
2384                         gen_clear_float_exceptions();
2385                         gen_op_fmuls();
2386                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2387                         gen_op_store_FT0_fpr(rd);
2388                         break;
2389                     case 0x4a:
2390                         gen_op_load_fpr_DT0(DFPREG(rs1));
2391                         gen_op_load_fpr_DT1(DFPREG(rs2));
2392                         gen_clear_float_exceptions();
2393                         gen_op_fmuld();
2394                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2395                         gen_op_store_DT0_fpr(DFPREG(rd));
2396                         break;
2397                     case 0x4b: /* fmulq */
2398 #if defined(CONFIG_USER_ONLY)
2399                         gen_op_load_fpr_QT0(QFPREG(rs1));
2400                         gen_op_load_fpr_QT1(QFPREG(rs2));
2401                         gen_clear_float_exceptions();
2402                         gen_op_fmulq();
2403                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2404                         gen_op_store_QT0_fpr(QFPREG(rd));
2405                         break;
2406 #else
2407                         goto nfpu_insn;
2408 #endif
2409                     case 0x4d:
2410                         gen_op_load_fpr_FT0(rs1);
2411                         gen_op_load_fpr_FT1(rs2);
2412                         gen_clear_float_exceptions();
2413                         gen_op_fdivs();
2414                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2415                         gen_op_store_FT0_fpr(rd);
2416                         break;
2417                     case 0x4e:
2418                         gen_op_load_fpr_DT0(DFPREG(rs1));
2419                         gen_op_load_fpr_DT1(DFPREG(rs2));
2420                         gen_clear_float_exceptions();
2421                         gen_op_fdivd();
2422                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2423                         gen_op_store_DT0_fpr(DFPREG(rd));
2424                         break;
2425                     case 0x4f: /* fdivq */
2426 #if defined(CONFIG_USER_ONLY)
2427                         gen_op_load_fpr_QT0(QFPREG(rs1));
2428                         gen_op_load_fpr_QT1(QFPREG(rs2));
2429                         gen_clear_float_exceptions();
2430                         gen_op_fdivq();
2431                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2432                         gen_op_store_QT0_fpr(QFPREG(rd));
2433                         break;
2434 #else
2435                         goto nfpu_insn;
2436 #endif
2437                     case 0x69:
2438                         gen_op_load_fpr_FT0(rs1);
2439                         gen_op_load_fpr_FT1(rs2);
2440                         gen_clear_float_exceptions();
2441                         gen_op_fsmuld();
2442                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2443                         gen_op_store_DT0_fpr(DFPREG(rd));
2444                         break;
2445                     case 0x6e: /* fdmulq */
2446 #if defined(CONFIG_USER_ONLY)
2447                         gen_op_load_fpr_DT0(DFPREG(rs1));
2448                         gen_op_load_fpr_DT1(DFPREG(rs2));
2449                         gen_clear_float_exceptions();
2450                         gen_op_fdmulq();
2451                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2452                         gen_op_store_QT0_fpr(QFPREG(rd));
2453                         break;
2454 #else
2455                         goto nfpu_insn;
2456 #endif
2457                     case 0xc4:
2458                         gen_op_load_fpr_FT1(rs2);
2459                         gen_clear_float_exceptions();
2460                         gen_op_fitos();
2461                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2462                         gen_op_store_FT0_fpr(rd);
2463                         break;
2464                     case 0xc6:
2465                         gen_op_load_fpr_DT1(DFPREG(rs2));
2466                         gen_clear_float_exceptions();
2467                         gen_op_fdtos();
2468                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2469                         gen_op_store_FT0_fpr(rd);
2470                         break;
2471                     case 0xc7: /* fqtos */
2472 #if defined(CONFIG_USER_ONLY)
2473                         gen_op_load_fpr_QT1(QFPREG(rs2));
2474                         gen_clear_float_exceptions();
2475                         gen_op_fqtos();
2476                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2477                         gen_op_store_FT0_fpr(rd);
2478                         break;
2479 #else
2480                         goto nfpu_insn;
2481 #endif
2482                     case 0xc8:
2483                         gen_op_load_fpr_FT1(rs2);
2484                         gen_op_fitod();
2485                         gen_op_store_DT0_fpr(DFPREG(rd));
2486                         break;
2487                     case 0xc9:
2488                         gen_op_load_fpr_FT1(rs2);
2489                         gen_op_fstod();
2490                         gen_op_store_DT0_fpr(DFPREG(rd));
2491                         break;
2492                     case 0xcb: /* fqtod */
2493 #if defined(CONFIG_USER_ONLY)
2494                         gen_op_load_fpr_QT1(QFPREG(rs2));
2495                         gen_clear_float_exceptions();
2496                         gen_op_fqtod();
2497                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2498                         gen_op_store_DT0_fpr(DFPREG(rd));
2499                         break;
2500 #else
2501                         goto nfpu_insn;
2502 #endif
2503                     case 0xcc: /* fitoq */
2504 #if defined(CONFIG_USER_ONLY)
2505                         gen_op_load_fpr_FT1(rs2);
2506                         gen_op_fitoq();
2507                         gen_op_store_QT0_fpr(QFPREG(rd));
2508                         break;
2509 #else
2510                         goto nfpu_insn;
2511 #endif
2512                     case 0xcd: /* fstoq */
2513 #if defined(CONFIG_USER_ONLY)
2514                         gen_op_load_fpr_FT1(rs2);
2515                         gen_op_fstoq();
2516                         gen_op_store_QT0_fpr(QFPREG(rd));
2517                         break;
2518 #else
2519                         goto nfpu_insn;
2520 #endif
2521                     case 0xce: /* fdtoq */
2522 #if defined(CONFIG_USER_ONLY)
2523                         gen_op_load_fpr_DT1(DFPREG(rs2));
2524                         gen_op_fdtoq();
2525                         gen_op_store_QT0_fpr(QFPREG(rd));
2526                         break;
2527 #else
2528                         goto nfpu_insn;
2529 #endif
2530                     case 0xd1:
2531                         gen_op_load_fpr_FT1(rs2);
2532                         gen_clear_float_exceptions();
2533                         gen_op_fstoi();
2534                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2535                         gen_op_store_FT0_fpr(rd);
2536                         break;
2537                     case 0xd2:
2538                         gen_op_load_fpr_DT1(DFPREG(rs2));
2539                         gen_clear_float_exceptions();
2540                         gen_op_fdtoi();
2541                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2542                         gen_op_store_FT0_fpr(rd);
2543                         break;
2544                     case 0xd3: /* fqtoi */
2545 #if defined(CONFIG_USER_ONLY)
2546                         gen_op_load_fpr_QT1(QFPREG(rs2));
2547                         gen_clear_float_exceptions();
2548                         gen_op_fqtoi();
2549                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2550                         gen_op_store_FT0_fpr(rd);
2551                         break;
2552 #else
2553                         goto nfpu_insn;
2554 #endif
2555 #ifdef TARGET_SPARC64
2556                     case 0x2: /* V9 fmovd */
2557                         gen_op_load_fpr_DT0(DFPREG(rs2));
2558                         gen_op_store_DT0_fpr(DFPREG(rd));
2559                         break;
2560                     case 0x3: /* V9 fmovq */
2561 #if defined(CONFIG_USER_ONLY)
2562                         gen_op_load_fpr_QT0(QFPREG(rs2));
2563                         gen_op_store_QT0_fpr(QFPREG(rd));
2564                         break;
2565 #else
2566                         goto nfpu_insn;
2567 #endif
2568                     case 0x6: /* V9 fnegd */
2569                         gen_op_load_fpr_DT1(DFPREG(rs2));
2570                         gen_op_fnegd();
2571                         gen_op_store_DT0_fpr(DFPREG(rd));
2572                         break;
2573                     case 0x7: /* V9 fnegq */
2574 #if defined(CONFIG_USER_ONLY)
2575                         gen_op_load_fpr_QT1(QFPREG(rs2));
2576                         gen_op_fnegq();
2577                         gen_op_store_QT0_fpr(QFPREG(rd));
2578                         break;
2579 #else
2580                         goto nfpu_insn;
2581 #endif
2582                     case 0xa: /* V9 fabsd */
2583                         gen_op_load_fpr_DT1(DFPREG(rs2));
2584                         tcg_gen_helper_0_0(helper_fabsd);
2585                         gen_op_store_DT0_fpr(DFPREG(rd));
2586                         break;
2587                     case 0xb: /* V9 fabsq */
2588 #if defined(CONFIG_USER_ONLY)
2589                         gen_op_load_fpr_QT1(QFPREG(rs2));
2590                         tcg_gen_helper_0_0(helper_fabsq);
2591                         gen_op_store_QT0_fpr(QFPREG(rd));
2592                         break;
2593 #else
2594                         goto nfpu_insn;
2595 #endif
2596                     case 0x81: /* V9 fstox */
2597                         gen_op_load_fpr_FT1(rs2);
2598                         gen_clear_float_exceptions();
2599                         gen_op_fstox();
2600                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2601                         gen_op_store_DT0_fpr(DFPREG(rd));
2602                         break;
2603                     case 0x82: /* V9 fdtox */
2604                         gen_op_load_fpr_DT1(DFPREG(rs2));
2605                         gen_clear_float_exceptions();
2606                         gen_op_fdtox();
2607                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2608                         gen_op_store_DT0_fpr(DFPREG(rd));
2609                         break;
2610                     case 0x83: /* V9 fqtox */
2611 #if defined(CONFIG_USER_ONLY)
2612                         gen_op_load_fpr_QT1(QFPREG(rs2));
2613                         gen_clear_float_exceptions();
2614                         gen_op_fqtox();
2615                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2616                         gen_op_store_DT0_fpr(DFPREG(rd));
2617                         break;
2618 #else
2619                         goto nfpu_insn;
2620 #endif
2621                     case 0x84: /* V9 fxtos */
2622                         gen_op_load_fpr_DT1(DFPREG(rs2));
2623                         gen_clear_float_exceptions();
2624                         gen_op_fxtos();
2625                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2626                         gen_op_store_FT0_fpr(rd);
2627                         break;
2628                     case 0x88: /* V9 fxtod */
2629                         gen_op_load_fpr_DT1(DFPREG(rs2));
2630                         gen_clear_float_exceptions();
2631                         gen_op_fxtod();
2632                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2633                         gen_op_store_DT0_fpr(DFPREG(rd));
2634                         break;
2635                     case 0x8c: /* V9 fxtoq */
2636 #if defined(CONFIG_USER_ONLY)
2637                         gen_op_load_fpr_DT1(DFPREG(rs2));
2638                         gen_clear_float_exceptions();
2639                         gen_op_fxtoq();
2640                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2641                         gen_op_store_QT0_fpr(QFPREG(rd));
2642                         break;
2643 #else
2644                         goto nfpu_insn;
2645 #endif
2646 #endif
2647                     default:
2648                         goto illegal_insn;
2649                 }
2650             } else if (xop == 0x35) {   /* FPU Operations */
2651 #ifdef TARGET_SPARC64
2652                 int cond;
2653 #endif
2654                 if (gen_trap_ifnofpu(dc))
2655                     goto jmp_insn;
2656                 gen_op_clear_ieee_excp_and_FTT();
2657                 rs1 = GET_FIELD(insn, 13, 17);
2658                 rs2 = GET_FIELD(insn, 27, 31);
2659                 xop = GET_FIELD(insn, 18, 26);
2660 #ifdef TARGET_SPARC64
2661                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2662                     TCGv r_zero;
2663                     int l1;
2664
2665                     l1 = gen_new_label();
2666                     r_zero = tcg_const_tl(0);
2667                     cond = GET_FIELD_SP(insn, 14, 17);
2668                     rs1 = GET_FIELD(insn, 13, 17);
2669                     gen_movl_reg_T0(rs1);
2670                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
2671                     gen_op_load_fpr_FT0(rs2);
2672                     gen_op_store_FT0_fpr(rd);
2673                     gen_set_label(l1);
2674                     break;
2675                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2676                     TCGv r_zero;
2677                     int l1;
2678
2679                     l1 = gen_new_label();
2680                     r_zero = tcg_const_tl(0);
2681                     cond = GET_FIELD_SP(insn, 14, 17);
2682                     rs1 = GET_FIELD(insn, 13, 17);
2683                     gen_movl_reg_T0(rs1);
2684                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
2685                     gen_op_load_fpr_DT0(DFPREG(rs2));
2686                     gen_op_store_DT0_fpr(DFPREG(rd));
2687                     gen_set_label(l1);
2688                     break;
2689                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2690 #if defined(CONFIG_USER_ONLY)
2691                     TCGv r_zero;
2692                     int l1;
2693
2694                     l1 = gen_new_label();
2695                     r_zero = tcg_const_tl(0);
2696                     cond = GET_FIELD_SP(insn, 14, 17);
2697                     rs1 = GET_FIELD(insn, 13, 17);
2698                     gen_movl_reg_T0(rs1);
2699                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
2700                     gen_op_load_fpr_QT0(QFPREG(rs2));
2701                     gen_op_store_QT0_fpr(QFPREG(rd));
2702                     gen_set_label(l1);
2703                     break;
2704 #else
2705                     goto nfpu_insn;
2706 #endif
2707                 }
2708 #endif
2709                 switch (xop) {
2710 #ifdef TARGET_SPARC64
2711 #define FMOVCC(size_FDQ, fcc)                                           \
2712                     {                                                   \
2713                         TCGv r_zero, r_cond;                            \
2714                         int l1;                                         \
2715                                                                         \
2716                         l1 = gen_new_label();                           \
2717                         r_zero = tcg_const_tl(0);                       \
2718                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2719                         cond = GET_FIELD_SP(insn, 14, 17);              \
2720                         gen_fcond(r_cond, fcc, cond);                   \
2721                         tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); \
2722                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2723                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2724                         gen_set_label(l1);                              \
2725                     }
2726                     case 0x001: /* V9 fmovscc %fcc0 */
2727                         FMOVCC(F, 0);
2728                         break;
2729                     case 0x002: /* V9 fmovdcc %fcc0 */
2730                         FMOVCC(D, 0);
2731                         break;
2732                     case 0x003: /* V9 fmovqcc %fcc0 */
2733 #if defined(CONFIG_USER_ONLY)
2734                         FMOVCC(Q, 0);
2735                         break;
2736 #else
2737                         goto nfpu_insn;
2738 #endif
2739                     case 0x041: /* V9 fmovscc %fcc1 */
2740                         FMOVCC(F, 1);
2741                         break;
2742                     case 0x042: /* V9 fmovdcc %fcc1 */
2743                         FMOVCC(D, 1);
2744                         break;
2745                     case 0x043: /* V9 fmovqcc %fcc1 */
2746 #if defined(CONFIG_USER_ONLY)
2747                         FMOVCC(Q, 1);
2748                         break;
2749 #else
2750                         goto nfpu_insn;
2751 #endif
2752                     case 0x081: /* V9 fmovscc %fcc2 */
2753                         FMOVCC(F, 2);
2754                         break;
2755                     case 0x082: /* V9 fmovdcc %fcc2 */
2756                         FMOVCC(D, 2);
2757                         break;
2758                     case 0x083: /* V9 fmovqcc %fcc2 */
2759 #if defined(CONFIG_USER_ONLY)
2760                         FMOVCC(Q, 2);
2761                         break;
2762 #else
2763                         goto nfpu_insn;
2764 #endif
2765                     case 0x0c1: /* V9 fmovscc %fcc3 */
2766                         FMOVCC(F, 3);
2767                         break;
2768                     case 0x0c2: /* V9 fmovdcc %fcc3 */
2769                         FMOVCC(D, 3);
2770                         break;
2771                     case 0x0c3: /* V9 fmovqcc %fcc3 */
2772 #if defined(CONFIG_USER_ONLY)
2773                         FMOVCC(Q, 3);
2774                         break;
2775 #else
2776                         goto nfpu_insn;
2777 #endif
2778 #undef FMOVCC
2779 #define FMOVCC(size_FDQ, icc)                                           \
2780                     {                                                   \
2781                         TCGv r_zero, r_cond;                            \
2782                         int l1;                                         \
2783                                                                         \
2784                         l1 = gen_new_label();                           \
2785                         r_zero = tcg_const_tl(0);                       \
2786                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2787                         cond = GET_FIELD_SP(insn, 14, 17);              \
2788                         gen_cond(r_cond, icc, cond);                    \
2789                         tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); \
2790                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2791                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2792                         gen_set_label(l1);                              \
2793                     }
2794
2795                     case 0x101: /* V9 fmovscc %icc */
2796                         FMOVCC(F, 0);
2797                         break;
2798                     case 0x102: /* V9 fmovdcc %icc */
2799                         FMOVCC(D, 0);
2800                     case 0x103: /* V9 fmovqcc %icc */
2801 #if defined(CONFIG_USER_ONLY)
2802                         FMOVCC(D, 0);
2803                         break;
2804 #else
2805                         goto nfpu_insn;
2806 #endif
2807                     case 0x181: /* V9 fmovscc %xcc */
2808                         FMOVCC(F, 1);
2809                         break;
2810                     case 0x182: /* V9 fmovdcc %xcc */
2811                         FMOVCC(D, 1);
2812                         break;
2813                     case 0x183: /* V9 fmovqcc %xcc */
2814 #if defined(CONFIG_USER_ONLY)
2815                         FMOVCC(Q, 1);
2816                         break;
2817 #else
2818                         goto nfpu_insn;
2819 #endif
2820 #undef FMOVCC
2821 #endif
2822                     case 0x51: /* fcmps, V9 %fcc */
2823                         gen_op_load_fpr_FT0(rs1);
2824                         gen_op_load_fpr_FT1(rs2);
2825                         gen_op_fcmps(rd & 3);
2826                         break;
2827                     case 0x52: /* fcmpd, V9 %fcc */
2828                         gen_op_load_fpr_DT0(DFPREG(rs1));
2829                         gen_op_load_fpr_DT1(DFPREG(rs2));
2830                         gen_op_fcmpd(rd & 3);
2831                         break;
2832                     case 0x53: /* fcmpq, V9 %fcc */
2833 #if defined(CONFIG_USER_ONLY)
2834                         gen_op_load_fpr_QT0(QFPREG(rs1));
2835                         gen_op_load_fpr_QT1(QFPREG(rs2));
2836                         gen_op_fcmpq(rd & 3);
2837                         break;
2838 #else /* !defined(CONFIG_USER_ONLY) */
2839                         goto nfpu_insn;
2840 #endif
2841                     case 0x55: /* fcmpes, V9 %fcc */
2842                         gen_op_load_fpr_FT0(rs1);
2843                         gen_op_load_fpr_FT1(rs2);
2844                         gen_op_fcmpes(rd & 3);
2845                         break;
2846                     case 0x56: /* fcmped, V9 %fcc */
2847                         gen_op_load_fpr_DT0(DFPREG(rs1));
2848                         gen_op_load_fpr_DT1(DFPREG(rs2));
2849                         gen_op_fcmped(rd & 3);
2850                         break;
2851                     case 0x57: /* fcmpeq, V9 %fcc */
2852 #if defined(CONFIG_USER_ONLY)
2853                         gen_op_load_fpr_QT0(QFPREG(rs1));
2854                         gen_op_load_fpr_QT1(QFPREG(rs2));
2855                         gen_op_fcmpeq(rd & 3);
2856                         break;
2857 #else/* !defined(CONFIG_USER_ONLY) */
2858                         goto nfpu_insn;
2859 #endif
2860                     default:
2861                         goto illegal_insn;
2862                 }
2863 #if defined(OPTIM)
2864             } else if (xop == 0x2) {
2865                 // clr/mov shortcut
2866
2867                 rs1 = GET_FIELD(insn, 13, 17);
2868                 if (rs1 == 0) {
2869                     // or %g0, x, y -> mov T0, x; mov y, T0
2870                     if (IS_IMM) {       /* immediate */
2871                         rs2 = GET_FIELDs(insn, 19, 31);
2872                         tcg_gen_movi_tl(cpu_T[0], (int)rs2);
2873                     } else {            /* register */
2874                         rs2 = GET_FIELD(insn, 27, 31);
2875                         gen_movl_reg_T0(rs2);
2876                     }
2877                 } else {
2878                     gen_movl_reg_T0(rs1);
2879                     if (IS_IMM) {       /* immediate */
2880                         rs2 = GET_FIELDs(insn, 19, 31);
2881                         tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2);
2882                     } else {            /* register */
2883                         // or x, %g0, y -> mov T1, x; mov y, T1
2884                         rs2 = GET_FIELD(insn, 27, 31);
2885                         if (rs2 != 0) {
2886                             gen_movl_reg_T1(rs2);
2887                             gen_op_or_T1_T0();
2888                         }
2889                     }
2890                 }
2891                 gen_movl_T0_reg(rd);
2892 #endif
2893 #ifdef TARGET_SPARC64
2894             } else if (xop == 0x25) { /* sll, V9 sllx */
2895                 rs1 = GET_FIELD(insn, 13, 17);
2896                 gen_movl_reg_T0(rs1);
2897                 if (IS_IMM) {   /* immediate */
2898                     rs2 = GET_FIELDs(insn, 20, 31);
2899                     if (insn & (1 << 12)) {
2900                         tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2901                     } else {
2902                         tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2903                         tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2904                     }
2905                 } else {                /* register */
2906                     rs2 = GET_FIELD(insn, 27, 31);
2907                     gen_movl_reg_T1(rs2);
2908                     if (insn & (1 << 12)) {
2909                         tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2910                         tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2911                     } else {
2912                         tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2913                         tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2914                         tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2915                     }
2916                 }
2917                 gen_movl_T0_reg(rd);
2918             } else if (xop == 0x26) { /* srl, V9 srlx */
2919                 rs1 = GET_FIELD(insn, 13, 17);
2920                 gen_movl_reg_T0(rs1);
2921                 if (IS_IMM) {   /* immediate */
2922                     rs2 = GET_FIELDs(insn, 20, 31);
2923                     if (insn & (1 << 12)) {
2924                         tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2925                     } else {
2926                         tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2927                         tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2928                     }
2929                 } else {                /* register */
2930                     rs2 = GET_FIELD(insn, 27, 31);
2931                     gen_movl_reg_T1(rs2);
2932                     if (insn & (1 << 12)) {
2933                         tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2934                         tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2935                     } else {
2936                         tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2937                         tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2938                         tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2939                     }
2940                 }
2941                 gen_movl_T0_reg(rd);
2942             } else if (xop == 0x27) { /* sra, V9 srax */
2943                 rs1 = GET_FIELD(insn, 13, 17);
2944                 gen_movl_reg_T0(rs1);
2945                 if (IS_IMM) {   /* immediate */
2946                     rs2 = GET_FIELDs(insn, 20, 31);
2947                     if (insn & (1 << 12)) {
2948                         tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2949                     } else {
2950                         tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2951                         tcg_gen_ext_i32_i64(cpu_T[0], cpu_T[0]);
2952                         tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2953                     }
2954                 } else {                /* register */
2955                     rs2 = GET_FIELD(insn, 27, 31);
2956                     gen_movl_reg_T1(rs2);
2957                     if (insn & (1 << 12)) {
2958                         tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2959                         tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2960                     } else {
2961                         tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2962                         tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2963                         tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2964                     }
2965                 }
2966                 gen_movl_T0_reg(rd);
2967 #endif
2968             } else if (xop < 0x36) {
2969                 rs1 = GET_FIELD(insn, 13, 17);
2970                 gen_movl_reg_T0(rs1);
2971                 if (IS_IMM) {   /* immediate */
2972                     rs2 = GET_FIELDs(insn, 19, 31);
2973                     gen_movl_simm_T1(rs2);
2974                 } else {                /* register */
2975                     rs2 = GET_FIELD(insn, 27, 31);
2976                     gen_movl_reg_T1(rs2);
2977                 }
2978                 if (xop < 0x20) {
2979                     switch (xop & ~0x10) {
2980                     case 0x0:
2981                         if (xop & 0x10)
2982                             gen_op_add_T1_T0_cc();
2983                         else
2984                             gen_op_add_T1_T0();
2985                         break;
2986                     case 0x1:
2987                         tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2988                         if (xop & 0x10)
2989                             gen_op_logic_T0_cc();
2990                         break;
2991                     case 0x2:
2992                         tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2993                         if (xop & 0x10)
2994                             gen_op_logic_T0_cc();
2995                         break;
2996                     case 0x3:
2997                         tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2998                         if (xop & 0x10)
2999                             gen_op_logic_T0_cc();
3000                         break;
3001                     case 0x4:
3002                         if (xop & 0x10)
3003                             gen_op_sub_T1_T0_cc();
3004                         else
3005                             tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3006                         break;
3007                     case 0x5:
3008                         tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3009                         tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3010                         if (xop & 0x10)
3011                             gen_op_logic_T0_cc();
3012                         break;
3013                     case 0x6:
3014                         tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3015                         tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3016                         if (xop & 0x10)
3017                             gen_op_logic_T0_cc();
3018                         break;
3019                     case 0x7:
3020                         tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3021                         tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3022                         if (xop & 0x10)
3023                             gen_op_logic_T0_cc();
3024                         break;
3025                     case 0x8:
3026                         if (xop & 0x10)
3027                             gen_op_addx_T1_T0_cc();
3028                         else {
3029                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3030                             tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
3031                             tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3032                         }
3033                         break;
3034 #ifdef TARGET_SPARC64
3035                     case 0x9: /* V9 mulx */
3036                         tcg_gen_mul_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
3037                         break;
3038 #endif
3039                     case 0xa:
3040                         gen_op_umul_T1_T0();
3041                         if (xop & 0x10)
3042                             gen_op_logic_T0_cc();
3043                         break;
3044                     case 0xb:
3045                         gen_op_smul_T1_T0();
3046                         if (xop & 0x10)
3047                             gen_op_logic_T0_cc();
3048                         break;
3049                     case 0xc:
3050                         if (xop & 0x10)
3051                             gen_op_subx_T1_T0_cc();
3052                         else {
3053                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3054                             tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
3055                             tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3056                         }
3057                         break;
3058 #ifdef TARGET_SPARC64
3059                     case 0xd: /* V9 udivx */
3060                         gen_trap_ifdivzero_i64(cpu_T[1]);
3061                         tcg_gen_divu_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
3062                         break;
3063 #endif
3064                     case 0xe:
3065                         gen_op_udiv_T1_T0();
3066                         if (xop & 0x10)
3067                             gen_op_div_cc();
3068                         break;
3069                     case 0xf:
3070                         gen_op_sdiv_T1_T0();
3071                         if (xop & 0x10)
3072                             gen_op_div_cc();
3073                         break;
3074                     default:
3075                         goto illegal_insn;
3076                     }
3077                     gen_movl_T0_reg(rd);
3078                 } else {
3079                     switch (xop) {
3080                     case 0x20: /* taddcc */
3081                         gen_op_tadd_T1_T0_cc();
3082                         gen_movl_T0_reg(rd);
3083                         break;
3084                     case 0x21: /* tsubcc */
3085                         gen_op_tsub_T1_T0_cc();
3086                         gen_movl_T0_reg(rd);
3087                         break;
3088                     case 0x22: /* taddcctv */
3089                         save_state(dc);
3090                         gen_op_tadd_T1_T0_ccTV();
3091                         gen_movl_T0_reg(rd);
3092                         break;
3093                     case 0x23: /* tsubcctv */
3094                         save_state(dc);
3095                         gen_op_tsub_T1_T0_ccTV();
3096                         gen_movl_T0_reg(rd);
3097                         break;
3098                     case 0x24: /* mulscc */
3099                         gen_op_mulscc_T1_T0();
3100                         gen_movl_T0_reg(rd);
3101                         break;
3102 #ifndef TARGET_SPARC64
3103                     case 0x25:  /* sll */
3104                         tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3105                         tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
3106                         gen_movl_T0_reg(rd);
3107                         break;
3108                     case 0x26:  /* srl */
3109                         tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3110                         tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
3111                         gen_movl_T0_reg(rd);
3112                         break;
3113                     case 0x27:  /* sra */
3114                         tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3115                         tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
3116                         gen_movl_T0_reg(rd);
3117                         break;
3118 #endif
3119                     case 0x30:
3120                         {
3121                             switch(rd) {
3122                             case 0: /* wry */
3123                                 gen_op_xor_T1_T0();
3124                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
3125                                 break;
3126 #ifndef TARGET_SPARC64
3127                             case 0x01 ... 0x0f: /* undefined in the
3128                                                    SPARCv8 manual, nop
3129                                                    on the microSPARC
3130                                                    II */
3131                             case 0x10 ... 0x1f: /* implementation-dependent
3132                                                    in the SPARCv8
3133                                                    manual, nop on the
3134                                                    microSPARC II */
3135                                 break;
3136 #else
3137                             case 0x2: /* V9 wrccr */
3138                                 gen_op_xor_T1_T0();
3139                                 gen_op_wrccr();
3140                                 break;
3141                             case 0x3: /* V9 wrasi */
3142                                 gen_op_xor_T1_T0();
3143                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
3144                                 break;
3145                             case 0x6: /* V9 wrfprs */
3146                                 gen_op_xor_T1_T0();
3147                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
3148                                 save_state(dc);
3149                                 gen_op_next_insn();
3150                                 tcg_gen_exit_tb(0);
3151                                 dc->is_br = 1;
3152                                 break;
3153                             case 0xf: /* V9 sir, nop if user */
3154 #if !defined(CONFIG_USER_ONLY)
3155                                 if (supervisor(dc))
3156                                     ; // XXX
3157 #endif
3158                                 break;
3159                             case 0x13: /* Graphics Status */
3160                                 if (gen_trap_ifnofpu(dc))
3161                                     goto jmp_insn;
3162                                 gen_op_xor_T1_T0();
3163                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
3164                                 break;
3165                             case 0x17: /* Tick compare */
3166 #if !defined(CONFIG_USER_ONLY)
3167                                 if (!supervisor(dc))
3168                                     goto illegal_insn;
3169 #endif
3170                                 {
3171                                     TCGv r_tickptr;
3172
3173                                     gen_op_xor_T1_T0();
3174                                     gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3175                                                                  tick_cmpr));
3176                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3177                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3178                                                    offsetof(CPUState, tick));
3179                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3180                                                        r_tickptr, cpu_T[0]);
3181                                 }
3182                                 break;
3183                             case 0x18: /* System tick */
3184 #if !defined(CONFIG_USER_ONLY)
3185                                 if (!supervisor(dc))
3186                                     goto illegal_insn;
3187 #endif
3188                                 {
3189                                     TCGv r_tickptr;
3190
3191                                     gen_op_xor_T1_T0();
3192                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3193                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3194                                                    offsetof(CPUState, stick));
3195                                     tcg_gen_helper_0_2(helper_tick_set_count,
3196                                                        r_tickptr, cpu_T[0]);
3197                                 }
3198                                 break;
3199                             case 0x19: /* System tick compare */
3200 #if !defined(CONFIG_USER_ONLY)
3201                                 if (!supervisor(dc))
3202                                     goto illegal_insn;
3203 #endif
3204                                 {
3205                                     TCGv r_tickptr;
3206
3207                                     gen_op_xor_T1_T0();
3208                                     gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3209                                                                  stick_cmpr));
3210                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3211                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3212                                                    offsetof(CPUState, stick));
3213                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3214                                                        r_tickptr, cpu_T[0]);
3215                                 }
3216                                 break;
3217
3218                             case 0x10: /* Performance Control */
3219                             case 0x11: /* Performance Instrumentation Counter */
3220                             case 0x12: /* Dispatch Control */
3221                             case 0x14: /* Softint set */
3222                             case 0x15: /* Softint clear */
3223                             case 0x16: /* Softint write */
3224 #endif
3225                             default:
3226                                 goto illegal_insn;
3227                             }
3228                         }
3229                         break;
3230 #if !defined(CONFIG_USER_ONLY)
3231                     case 0x31: /* wrpsr, V9 saved, restored */
3232                         {
3233                             if (!supervisor(dc))
3234                                 goto priv_insn;
3235 #ifdef TARGET_SPARC64
3236                             switch (rd) {
3237                             case 0:
3238                                 gen_op_saved();
3239                                 break;
3240                             case 1:
3241                                 gen_op_restored();
3242                                 break;
3243                             case 2: /* UA2005 allclean */
3244                             case 3: /* UA2005 otherw */
3245                             case 4: /* UA2005 normalw */
3246                             case 5: /* UA2005 invalw */
3247                                 // XXX
3248                             default:
3249                                 goto illegal_insn;
3250                             }
3251 #else
3252                             gen_op_xor_T1_T0();
3253                             tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
3254                             save_state(dc);
3255                             gen_op_next_insn();
3256                             tcg_gen_exit_tb(0);
3257                             dc->is_br = 1;
3258 #endif
3259                         }
3260                         break;
3261                     case 0x32: /* wrwim, V9 wrpr */
3262                         {
3263                             if (!supervisor(dc))
3264                                 goto priv_insn;
3265                             gen_op_xor_T1_T0();
3266 #ifdef TARGET_SPARC64
3267                             switch (rd) {
3268                             case 0: // tpc
3269                                 {
3270                                     TCGv r_tsptr;
3271
3272                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3273                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3274                                                    offsetof(CPUState, tsptr));
3275                                     tcg_gen_st_tl(cpu_T[0], r_tsptr,
3276                                                   offsetof(trap_state, tpc));
3277                                 }
3278                                 break;
3279                             case 1: // tnpc
3280                                 {
3281                                     TCGv r_tsptr;
3282
3283                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3284                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3285                                                    offsetof(CPUState, tsptr));
3286                                     tcg_gen_st_tl(cpu_T[0], r_tsptr,
3287                                                   offsetof(trap_state, tnpc));
3288                                 }
3289                                 break;
3290                             case 2: // tstate
3291                                 {
3292                                     TCGv r_tsptr;
3293
3294                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3295                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3296                                                    offsetof(CPUState, tsptr));
3297                                     tcg_gen_st_tl(cpu_T[0], r_tsptr,
3298                                                   offsetof(trap_state, tstate));
3299                                 }
3300                                 break;
3301                             case 3: // tt
3302                                 {
3303                                     TCGv r_tsptr;
3304
3305                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3306                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3307                                                    offsetof(CPUState, tsptr));
3308                                     tcg_gen_st_i32(cpu_T[0], r_tsptr,
3309                                                    offsetof(trap_state, tt));
3310                                 }
3311                                 break;
3312                             case 4: // tick
3313                                 {
3314                                     TCGv r_tickptr;
3315
3316                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3317                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3318                                                    offsetof(CPUState, tick));
3319                                     tcg_gen_helper_0_2(helper_tick_set_count,
3320                                                        r_tickptr, cpu_T[0]);
3321                                 }
3322                                 break;
3323                             case 5: // tba
3324                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3325                                 break;
3326                             case 6: // pstate
3327                                 save_state(dc);
3328                                 tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]);
3329                                 gen_op_next_insn();
3330                                 tcg_gen_exit_tb(0);
3331                                 dc->is_br = 1;
3332                                 break;
3333                             case 7: // tl
3334                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
3335                                 break;
3336                             case 8: // pil
3337                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
3338                                 break;
3339                             case 9: // cwp
3340                                 gen_op_wrcwp();
3341                                 break;
3342                             case 10: // cansave
3343                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
3344                                 break;
3345                             case 11: // canrestore
3346                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
3347                                 break;
3348                             case 12: // cleanwin
3349                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
3350                                 break;
3351                             case 13: // otherwin
3352                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
3353                                 break;
3354                             case 14: // wstate
3355                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
3356                                 break;
3357                             case 16: // UA2005 gl
3358                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
3359                                 break;
3360                             case 26: // UA2005 strand status
3361                                 if (!hypervisor(dc))
3362                                     goto priv_insn;
3363                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
3364                                 break;
3365                             default:
3366                                 goto illegal_insn;
3367                             }
3368 #else
3369                             tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
3370                             gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
3371 #endif
3372                         }
3373                         break;
3374                     case 0x33: /* wrtbr, UA2005 wrhpr */
3375                         {
3376 #ifndef TARGET_SPARC64
3377                             if (!supervisor(dc))
3378                                 goto priv_insn;
3379                             gen_op_xor_T1_T0();
3380                             gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3381 #else
3382                             if (!hypervisor(dc))
3383                                 goto priv_insn;
3384                             gen_op_xor_T1_T0();
3385                             switch (rd) {
3386                             case 0: // hpstate
3387                                 // XXX gen_op_wrhpstate();
3388                                 save_state(dc);
3389                                 gen_op_next_insn();
3390                                 tcg_gen_exit_tb(0);
3391                                 dc->is_br = 1;
3392                                 break;
3393                             case 1: // htstate
3394                                 // XXX gen_op_wrhtstate();
3395                                 break;
3396                             case 3: // hintp
3397                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
3398                                 break;
3399                             case 5: // htba
3400                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
3401                                 break;
3402                             case 31: // hstick_cmpr
3403                                 {
3404                                     TCGv r_tickptr;
3405
3406                                     gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3407                                                                  hstick_cmpr));
3408                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3409                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3410                                                    offsetof(CPUState, hstick));
3411                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3412                                                        r_tickptr, cpu_T[0]);
3413                                 }
3414                                 break;
3415                             case 6: // hver readonly
3416                             default:
3417                                 goto illegal_insn;
3418                             }
3419 #endif
3420                         }
3421                         break;
3422 #endif
3423 #ifdef TARGET_SPARC64
3424                     case 0x2c: /* V9 movcc */
3425                         {
3426                             int cc = GET_FIELD_SP(insn, 11, 12);
3427                             int cond = GET_FIELD_SP(insn, 14, 17);
3428                             TCGv r_cond;
3429                             int l1;
3430
3431                             r_cond = tcg_temp_new(TCG_TYPE_TL);
3432                             if (insn & (1 << 18)) {
3433                                 if (cc == 0)
3434                                     gen_cond(r_cond, 0, cond);
3435                                 else if (cc == 2)
3436                                     gen_cond(r_cond, 1, cond);
3437                                 else
3438                                     goto illegal_insn;
3439                             } else {
3440                                 gen_fcond(r_cond, cc, cond);
3441                             }
3442
3443                             l1 = gen_new_label();
3444
3445                             tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,
3446                                               tcg_const_tl(0), l1);
3447                             if (IS_IMM) {       /* immediate */
3448                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
3449                                 gen_movl_simm_T1(rs2);
3450                             } else {
3451                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3452                                 gen_movl_reg_T1(rs2);
3453                             }
3454                             gen_movl_T1_reg(rd);
3455                             gen_set_label(l1);
3456                             break;
3457                         }
3458                     case 0x2d: /* V9 sdivx */
3459                         gen_op_sdivx_T1_T0();
3460                         gen_movl_T0_reg(rd);
3461                         break;
3462                     case 0x2e: /* V9 popc */
3463                         {
3464                             if (IS_IMM) {       /* immediate */
3465                                 rs2 = GET_FIELD_SPs(insn, 0, 12);
3466                                 gen_movl_simm_T1(rs2);
3467                                 // XXX optimize: popc(constant)
3468                             }
3469                             else {
3470                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3471                                 gen_movl_reg_T1(rs2);
3472                             }
3473                             tcg_gen_helper_1_1(helper_popc, cpu_T[0],
3474                                                cpu_T[1]);
3475                             gen_movl_T0_reg(rd);
3476                         }
3477                     case 0x2f: /* V9 movr */
3478                         {
3479                             int cond = GET_FIELD_SP(insn, 10, 12);
3480                             TCGv r_zero;
3481                             int l1;
3482
3483                             rs1 = GET_FIELD(insn, 13, 17);
3484                             gen_movl_reg_T0(rs1);
3485
3486                             l1 = gen_new_label();
3487
3488                             r_zero = tcg_const_tl(0);
3489                             tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
3490                             if (IS_IMM) {       /* immediate */
3491                                 rs2 = GET_FIELD_SPs(insn, 0, 9);
3492                                 gen_movl_simm_T1(rs2);
3493                             } else {
3494                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3495                                 gen_movl_reg_T1(rs2);
3496                             }
3497                             gen_movl_T1_reg(rd);
3498                             gen_set_label(l1);
3499                             break;
3500                         }
3501 #endif
3502                     default:
3503                         goto illegal_insn;
3504                     }
3505                 }
3506             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3507 #ifdef TARGET_SPARC64
3508                 int opf = GET_FIELD_SP(insn, 5, 13);
3509                 rs1 = GET_FIELD(insn, 13, 17);
3510                 rs2 = GET_FIELD(insn, 27, 31);
3511                 if (gen_trap_ifnofpu(dc))
3512                     goto jmp_insn;
3513
3514                 switch (opf) {
3515                 case 0x000: /* VIS I edge8cc */
3516                 case 0x001: /* VIS II edge8n */
3517                 case 0x002: /* VIS I edge8lcc */
3518                 case 0x003: /* VIS II edge8ln */
3519                 case 0x004: /* VIS I edge16cc */
3520                 case 0x005: /* VIS II edge16n */
3521                 case 0x006: /* VIS I edge16lcc */
3522                 case 0x007: /* VIS II edge16ln */
3523                 case 0x008: /* VIS I edge32cc */
3524                 case 0x009: /* VIS II edge32n */
3525                 case 0x00a: /* VIS I edge32lcc */
3526                 case 0x00b: /* VIS II edge32ln */
3527                     // XXX
3528                     goto illegal_insn;
3529                 case 0x010: /* VIS I array8 */
3530                     gen_movl_reg_T0(rs1);
3531                     gen_movl_reg_T1(rs2);
3532                     gen_op_array8();
3533                     gen_movl_T0_reg(rd);
3534                     break;
3535                 case 0x012: /* VIS I array16 */
3536                     gen_movl_reg_T0(rs1);
3537                     gen_movl_reg_T1(rs2);
3538                     gen_op_array16();
3539                     gen_movl_T0_reg(rd);
3540                     break;
3541                 case 0x014: /* VIS I array32 */
3542                     gen_movl_reg_T0(rs1);
3543                     gen_movl_reg_T1(rs2);
3544                     gen_op_array32();
3545                     gen_movl_T0_reg(rd);
3546                     break;
3547                 case 0x018: /* VIS I alignaddr */
3548                     gen_movl_reg_T0(rs1);
3549                     gen_movl_reg_T1(rs2);
3550                     gen_op_alignaddr();
3551                     gen_movl_T0_reg(rd);
3552                     break;
3553                 case 0x019: /* VIS II bmask */
3554                 case 0x01a: /* VIS I alignaddrl */
3555                     // XXX
3556                     goto illegal_insn;
3557                 case 0x020: /* VIS I fcmple16 */
3558                     gen_op_load_fpr_DT0(DFPREG(rs1));
3559                     gen_op_load_fpr_DT1(DFPREG(rs2));
3560                     gen_op_fcmple16();
3561                     gen_op_store_DT0_fpr(DFPREG(rd));
3562                     break;
3563                 case 0x022: /* VIS I fcmpne16 */
3564                     gen_op_load_fpr_DT0(DFPREG(rs1));
3565                     gen_op_load_fpr_DT1(DFPREG(rs2));
3566                     gen_op_fcmpne16();
3567                     gen_op_store_DT0_fpr(DFPREG(rd));
3568                     break;
3569                 case 0x024: /* VIS I fcmple32 */
3570                     gen_op_load_fpr_DT0(DFPREG(rs1));
3571                     gen_op_load_fpr_DT1(DFPREG(rs2));
3572                     gen_op_fcmple32();
3573                     gen_op_store_DT0_fpr(DFPREG(rd));
3574                     break;
3575                 case 0x026: /* VIS I fcmpne32 */
3576                     gen_op_load_fpr_DT0(DFPREG(rs1));
3577                     gen_op_load_fpr_DT1(DFPREG(rs2));
3578                     gen_op_fcmpne32();
3579                     gen_op_store_DT0_fpr(DFPREG(rd));
3580                     break;
3581                 case 0x028: /* VIS I fcmpgt16 */
3582                     gen_op_load_fpr_DT0(DFPREG(rs1));
3583                     gen_op_load_fpr_DT1(DFPREG(rs2));
3584                     gen_op_fcmpgt16();
3585                     gen_op_store_DT0_fpr(DFPREG(rd));
3586                     break;
3587                 case 0x02a: /* VIS I fcmpeq16 */
3588                     gen_op_load_fpr_DT0(DFPREG(rs1));
3589                     gen_op_load_fpr_DT1(DFPREG(rs2));
3590                     gen_op_fcmpeq16();
3591                     gen_op_store_DT0_fpr(DFPREG(rd));
3592                     break;
3593                 case 0x02c: /* VIS I fcmpgt32 */
3594                     gen_op_load_fpr_DT0(DFPREG(rs1));
3595                     gen_op_load_fpr_DT1(DFPREG(rs2));
3596                     gen_op_fcmpgt32();
3597                     gen_op_store_DT0_fpr(DFPREG(rd));
3598                     break;
3599                 case 0x02e: /* VIS I fcmpeq32 */
3600                     gen_op_load_fpr_DT0(DFPREG(rs1));
3601                     gen_op_load_fpr_DT1(DFPREG(rs2));
3602                     gen_op_fcmpeq32();
3603                     gen_op_store_DT0_fpr(DFPREG(rd));
3604                     break;
3605                 case 0x031: /* VIS I fmul8x16 */
3606                     gen_op_load_fpr_DT0(DFPREG(rs1));
3607                     gen_op_load_fpr_DT1(DFPREG(rs2));
3608                     gen_op_fmul8x16();
3609                     gen_op_store_DT0_fpr(DFPREG(rd));
3610                     break;
3611                 case 0x033: /* VIS I fmul8x16au */
3612                     gen_op_load_fpr_DT0(DFPREG(rs1));
3613                     gen_op_load_fpr_DT1(DFPREG(rs2));
3614                     gen_op_fmul8x16au();
3615                     gen_op_store_DT0_fpr(DFPREG(rd));
3616                     break;
3617                 case 0x035: /* VIS I fmul8x16al */
3618                     gen_op_load_fpr_DT0(DFPREG(rs1));
3619                     gen_op_load_fpr_DT1(DFPREG(rs2));
3620                     gen_op_fmul8x16al();
3621                     gen_op_store_DT0_fpr(DFPREG(rd));
3622                     break;
3623                 case 0x036: /* VIS I fmul8sux16 */
3624                     gen_op_load_fpr_DT0(DFPREG(rs1));
3625                     gen_op_load_fpr_DT1(DFPREG(rs2));
3626                     gen_op_fmul8sux16();
3627                     gen_op_store_DT0_fpr(DFPREG(rd));
3628                     break;
3629                 case 0x037: /* VIS I fmul8ulx16 */
3630                     gen_op_load_fpr_DT0(DFPREG(rs1));
3631                     gen_op_load_fpr_DT1(DFPREG(rs2));
3632                     gen_op_fmul8ulx16();
3633                     gen_op_store_DT0_fpr(DFPREG(rd));
3634                     break;
3635                 case 0x038: /* VIS I fmuld8sux16 */
3636                     gen_op_load_fpr_DT0(DFPREG(rs1));
3637                     gen_op_load_fpr_DT1(DFPREG(rs2));
3638                     gen_op_fmuld8sux16();
3639                     gen_op_store_DT0_fpr(DFPREG(rd));
3640                     break;
3641                 case 0x039: /* VIS I fmuld8ulx16 */
3642                     gen_op_load_fpr_DT0(DFPREG(rs1));
3643                     gen_op_load_fpr_DT1(DFPREG(rs2));
3644                     gen_op_fmuld8ulx16();
3645                     gen_op_store_DT0_fpr(DFPREG(rd));
3646                     break;
3647                 case 0x03a: /* VIS I fpack32 */
3648                 case 0x03b: /* VIS I fpack16 */
3649                 case 0x03d: /* VIS I fpackfix */
3650                 case 0x03e: /* VIS I pdist */
3651                     // XXX
3652                     goto illegal_insn;
3653                 case 0x048: /* VIS I faligndata */
3654                     gen_op_load_fpr_DT0(DFPREG(rs1));
3655                     gen_op_load_fpr_DT1(DFPREG(rs2));
3656                     gen_op_faligndata();
3657                     gen_op_store_DT0_fpr(DFPREG(rd));
3658                     break;
3659                 case 0x04b: /* VIS I fpmerge */
3660                     gen_op_load_fpr_DT0(DFPREG(rs1));
3661                     gen_op_load_fpr_DT1(DFPREG(rs2));
3662                     gen_op_fpmerge();
3663                     gen_op_store_DT0_fpr(DFPREG(rd));
3664                     break;
3665                 case 0x04c: /* VIS II bshuffle */
3666                     // XXX
3667                     goto illegal_insn;
3668                 case 0x04d: /* VIS I fexpand */
3669                     gen_op_load_fpr_DT0(DFPREG(rs1));
3670                     gen_op_load_fpr_DT1(DFPREG(rs2));
3671                     gen_op_fexpand();
3672                     gen_op_store_DT0_fpr(DFPREG(rd));
3673                     break;
3674                 case 0x050: /* VIS I fpadd16 */
3675                     gen_op_load_fpr_DT0(DFPREG(rs1));
3676                     gen_op_load_fpr_DT1(DFPREG(rs2));
3677                     gen_op_fpadd16();
3678                     gen_op_store_DT0_fpr(DFPREG(rd));
3679                     break;
3680                 case 0x051: /* VIS I fpadd16s */
3681                     gen_op_load_fpr_FT0(rs1);
3682                     gen_op_load_fpr_FT1(rs2);
3683                     gen_op_fpadd16s();
3684                     gen_op_store_FT0_fpr(rd);
3685                     break;
3686                 case 0x052: /* VIS I fpadd32 */
3687                     gen_op_load_fpr_DT0(DFPREG(rs1));
3688                     gen_op_load_fpr_DT1(DFPREG(rs2));
3689                     gen_op_fpadd32();
3690                     gen_op_store_DT0_fpr(DFPREG(rd));
3691                     break;
3692                 case 0x053: /* VIS I fpadd32s */
3693                     gen_op_load_fpr_FT0(rs1);
3694                     gen_op_load_fpr_FT1(rs2);
3695                     gen_op_fpadd32s();
3696                     gen_op_store_FT0_fpr(rd);
3697                     break;
3698                 case 0x054: /* VIS I fpsub16 */
3699                     gen_op_load_fpr_DT0(DFPREG(rs1));
3700                     gen_op_load_fpr_DT1(DFPREG(rs2));
3701                     gen_op_fpsub16();
3702                     gen_op_store_DT0_fpr(DFPREG(rd));
3703                     break;
3704                 case 0x055: /* VIS I fpsub16s */
3705                     gen_op_load_fpr_FT0(rs1);
3706                     gen_op_load_fpr_FT1(rs2);
3707                     gen_op_fpsub16s();
3708                     gen_op_store_FT0_fpr(rd);
3709                     break;
3710                 case 0x056: /* VIS I fpsub32 */
3711                     gen_op_load_fpr_DT0(DFPREG(rs1));
3712                     gen_op_load_fpr_DT1(DFPREG(rs2));
3713                     gen_op_fpadd32();
3714                     gen_op_store_DT0_fpr(DFPREG(rd));
3715                     break;
3716                 case 0x057: /* VIS I fpsub32s */
3717                     gen_op_load_fpr_FT0(rs1);
3718                     gen_op_load_fpr_FT1(rs2);
3719                     gen_op_fpsub32s();
3720                     gen_op_store_FT0_fpr(rd);
3721                     break;
3722                 case 0x060: /* VIS I fzero */
3723                     gen_op_movl_DT0_0();
3724                     gen_op_store_DT0_fpr(DFPREG(rd));
3725                     break;
3726                 case 0x061: /* VIS I fzeros */
3727                     gen_op_movl_FT0_0();
3728                     gen_op_store_FT0_fpr(rd);
3729                     break;
3730                 case 0x062: /* VIS I fnor */
3731                     gen_op_load_fpr_DT0(DFPREG(rs1));
3732                     gen_op_load_fpr_DT1(DFPREG(rs2));
3733                     gen_op_fnor();
3734                     gen_op_store_DT0_fpr(DFPREG(rd));
3735                     break;
3736                 case 0x063: /* VIS I fnors */
3737                     gen_op_load_fpr_FT0(rs1);
3738                     gen_op_load_fpr_FT1(rs2);
3739                     gen_op_fnors();
3740                     gen_op_store_FT0_fpr(rd);
3741                     break;
3742                 case 0x064: /* VIS I fandnot2 */
3743                     gen_op_load_fpr_DT1(DFPREG(rs1));
3744                     gen_op_load_fpr_DT0(DFPREG(rs2));
3745                     gen_op_fandnot();
3746                     gen_op_store_DT0_fpr(DFPREG(rd));
3747                     break;
3748                 case 0x065: /* VIS I fandnot2s */
3749                     gen_op_load_fpr_FT1(rs1);
3750                     gen_op_load_fpr_FT0(rs2);
3751                     gen_op_fandnots();
3752                     gen_op_store_FT0_fpr(rd);
3753                     break;
3754                 case 0x066: /* VIS I fnot2 */
3755                     gen_op_load_fpr_DT1(DFPREG(rs2));
3756                     gen_op_fnot();
3757                     gen_op_store_DT0_fpr(DFPREG(rd));
3758                     break;
3759                 case 0x067: /* VIS I fnot2s */
3760                     gen_op_load_fpr_FT1(rs2);
3761                     gen_op_fnot();
3762                     gen_op_store_FT0_fpr(rd);
3763                     break;
3764                 case 0x068: /* VIS I fandnot1 */
3765                     gen_op_load_fpr_DT0(DFPREG(rs1));
3766                     gen_op_load_fpr_DT1(DFPREG(rs2));
3767                     gen_op_fandnot();
3768                     gen_op_store_DT0_fpr(DFPREG(rd));
3769                     break;
3770                 case 0x069: /* VIS I fandnot1s */
3771                     gen_op_load_fpr_FT0(rs1);
3772                     gen_op_load_fpr_FT1(rs2);
3773                     gen_op_fandnots();
3774                     gen_op_store_FT0_fpr(rd);
3775                     break;
3776                 case 0x06a: /* VIS I fnot1 */
3777                     gen_op_load_fpr_DT1(DFPREG(rs1));
3778                     gen_op_fnot();
3779                     gen_op_store_DT0_fpr(DFPREG(rd));
3780                     break;
3781                 case 0x06b: /* VIS I fnot1s */
3782                     gen_op_load_fpr_FT1(rs1);
3783                     gen_op_fnot();
3784                     gen_op_store_FT0_fpr(rd);
3785                     break;
3786                 case 0x06c: /* VIS I fxor */
3787                     gen_op_load_fpr_DT0(DFPREG(rs1));
3788                     gen_op_load_fpr_DT1(DFPREG(rs2));
3789                     gen_op_fxor();
3790                     gen_op_store_DT0_fpr(DFPREG(rd));
3791                     break;
3792                 case 0x06d: /* VIS I fxors */
3793                     gen_op_load_fpr_FT0(rs1);
3794                     gen_op_load_fpr_FT1(rs2);
3795                     gen_op_fxors();
3796                     gen_op_store_FT0_fpr(rd);
3797                     break;
3798                 case 0x06e: /* VIS I fnand */
3799                     gen_op_load_fpr_DT0(DFPREG(rs1));
3800                     gen_op_load_fpr_DT1(DFPREG(rs2));
3801                     gen_op_fnand();
3802                     gen_op_store_DT0_fpr(DFPREG(rd));
3803                     break;
3804                 case 0x06f: /* VIS I fnands */
3805                     gen_op_load_fpr_FT0(rs1);
3806                     gen_op_load_fpr_FT1(rs2);
3807                     gen_op_fnands();
3808                     gen_op_store_FT0_fpr(rd);
3809                     break;
3810                 case 0x070: /* VIS I fand */
3811                     gen_op_load_fpr_DT0(DFPREG(rs1));
3812                     gen_op_load_fpr_DT1(DFPREG(rs2));
3813                     gen_op_fand();
3814                     gen_op_store_DT0_fpr(DFPREG(rd));
3815                     break;
3816                 case 0x071: /* VIS I fands */
3817                     gen_op_load_fpr_FT0(rs1);
3818                     gen_op_load_fpr_FT1(rs2);
3819                     gen_op_fands();
3820                     gen_op_store_FT0_fpr(rd);
3821                     break;
3822                 case 0x072: /* VIS I fxnor */
3823                     gen_op_load_fpr_DT0(DFPREG(rs1));
3824                     gen_op_load_fpr_DT1(DFPREG(rs2));
3825                     gen_op_fxnor();
3826                     gen_op_store_DT0_fpr(DFPREG(rd));
3827                     break;
3828                 case 0x073: /* VIS I fxnors */
3829                     gen_op_load_fpr_FT0(rs1);
3830                     gen_op_load_fpr_FT1(rs2);
3831                     gen_op_fxnors();
3832                     gen_op_store_FT0_fpr(rd);
3833                     break;
3834                 case 0x074: /* VIS I fsrc1 */
3835                     gen_op_load_fpr_DT0(DFPREG(rs1));
3836                     gen_op_store_DT0_fpr(DFPREG(rd));
3837                     break;
3838                 case 0x075: /* VIS I fsrc1s */
3839                     gen_op_load_fpr_FT0(rs1);
3840                     gen_op_store_FT0_fpr(rd);
3841                     break;
3842                 case 0x076: /* VIS I fornot2 */
3843                     gen_op_load_fpr_DT1(DFPREG(rs1));
3844                     gen_op_load_fpr_DT0(DFPREG(rs2));
3845                     gen_op_fornot();
3846                     gen_op_store_DT0_fpr(DFPREG(rd));
3847                     break;
3848                 case 0x077: /* VIS I fornot2s */
3849                     gen_op_load_fpr_FT1(rs1);
3850                     gen_op_load_fpr_FT0(rs2);
3851                     gen_op_fornots();
3852                     gen_op_store_FT0_fpr(rd);
3853                     break;
3854                 case 0x078: /* VIS I fsrc2 */
3855                     gen_op_load_fpr_DT0(DFPREG(rs2));
3856                     gen_op_store_DT0_fpr(DFPREG(rd));
3857                     break;
3858                 case 0x079: /* VIS I fsrc2s */
3859                     gen_op_load_fpr_FT0(rs2);
3860                     gen_op_store_FT0_fpr(rd);
3861                     break;
3862                 case 0x07a: /* VIS I fornot1 */
3863                     gen_op_load_fpr_DT0(DFPREG(rs1));
3864                     gen_op_load_fpr_DT1(DFPREG(rs2));
3865                     gen_op_fornot();
3866                     gen_op_store_DT0_fpr(DFPREG(rd));
3867                     break;
3868                 case 0x07b: /* VIS I fornot1s */
3869                     gen_op_load_fpr_FT0(rs1);
3870                     gen_op_load_fpr_FT1(rs2);
3871                     gen_op_fornots();
3872                     gen_op_store_FT0_fpr(rd);
3873                     break;
3874                 case 0x07c: /* VIS I for */
3875                     gen_op_load_fpr_DT0(DFPREG(rs1));
3876                     gen_op_load_fpr_DT1(DFPREG(rs2));
3877                     gen_op_for();
3878                     gen_op_store_DT0_fpr(DFPREG(rd));
3879                     break;
3880                 case 0x07d: /* VIS I fors */
3881                     gen_op_load_fpr_FT0(rs1);
3882                     gen_op_load_fpr_FT1(rs2);
3883                     gen_op_fors();
3884                     gen_op_store_FT0_fpr(rd);
3885                     break;
3886                 case 0x07e: /* VIS I fone */
3887                     gen_op_movl_DT0_1();
3888                     gen_op_store_DT0_fpr(DFPREG(rd));
3889                     break;
3890                 case 0x07f: /* VIS I fones */
3891                     gen_op_movl_FT0_1();
3892                     gen_op_store_FT0_fpr(rd);
3893                     break;
3894                 case 0x080: /* VIS I shutdown */
3895                 case 0x081: /* VIS II siam */
3896                     // XXX
3897                     goto illegal_insn;
3898                 default:
3899                     goto illegal_insn;
3900                 }
3901 #else
3902                 goto ncp_insn;
3903 #endif
3904             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
3905 #ifdef TARGET_SPARC64
3906                 goto illegal_insn;
3907 #else
3908                 goto ncp_insn;
3909 #endif
3910 #ifdef TARGET_SPARC64
3911             } else if (xop == 0x39) { /* V9 return */
3912                 rs1 = GET_FIELD(insn, 13, 17);
3913                 save_state(dc);
3914                 gen_movl_reg_T0(rs1);
3915                 if (IS_IMM) {   /* immediate */
3916                     rs2 = GET_FIELDs(insn, 19, 31);
3917                     tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
3918                 } else {                /* register */
3919                     rs2 = GET_FIELD(insn, 27, 31);
3920 #if defined(OPTIM)
3921                     if (rs2) {
3922 #endif
3923                         gen_movl_reg_T1(rs2);
3924                         gen_op_add_T1_T0();
3925 #if defined(OPTIM)
3926                     }
3927 #endif
3928                 }
3929                 gen_op_restore();
3930                 gen_mov_pc_npc(dc);
3931                 gen_op_check_align_T0_3();
3932                 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
3933                 dc->npc = DYNAMIC_PC;
3934                 goto jmp_insn;
3935 #endif
3936             } else {
3937                 rs1 = GET_FIELD(insn, 13, 17);
3938                 gen_movl_reg_T0(rs1);
3939                 if (IS_IMM) {   /* immediate */
3940                     rs2 = GET_FIELDs(insn, 19, 31);
3941                     tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
3942                 } else {                /* register */
3943                     rs2 = GET_FIELD(insn, 27, 31);
3944 #if defined(OPTIM)
3945                     if (rs2) {
3946 #endif
3947                         gen_movl_reg_T1(rs2);
3948                         gen_op_add_T1_T0();
3949 #if defined(OPTIM)
3950                     }
3951 #endif
3952                 }
3953                 switch (xop) {
3954                 case 0x38:      /* jmpl */
3955                     {
3956                         if (rd != 0) {
3957                             tcg_gen_movi_tl(cpu_T[1], dc->pc);
3958                             gen_movl_T1_reg(rd);
3959                         }
3960                         gen_mov_pc_npc(dc);
3961                         gen_op_check_align_T0_3();
3962                         tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
3963                         dc->npc = DYNAMIC_PC;
3964                     }
3965                     goto jmp_insn;
3966 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3967                 case 0x39:      /* rett, V9 return */
3968                     {
3969                         if (!supervisor(dc))
3970                             goto priv_insn;
3971                         gen_mov_pc_npc(dc);
3972                         gen_op_check_align_T0_3();
3973                         tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
3974                         dc->npc = DYNAMIC_PC;
3975                         tcg_gen_helper_0_0(helper_rett);
3976                     }
3977                     goto jmp_insn;
3978 #endif
3979                 case 0x3b: /* flush */
3980                     tcg_gen_helper_0_1(helper_flush, cpu_T[0]);
3981                     break;
3982                 case 0x3c:      /* save */
3983                     save_state(dc);
3984                     gen_op_save();
3985                     gen_movl_T0_reg(rd);
3986                     break;
3987                 case 0x3d:      /* restore */
3988                     save_state(dc);
3989                     gen_op_restore();
3990                     gen_movl_T0_reg(rd);
3991                     break;
3992 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
3993                 case 0x3e:      /* V9 done/retry */
3994                     {
3995                         switch (rd) {
3996                         case 0:
3997                             if (!supervisor(dc))
3998                                 goto priv_insn;
3999                             dc->npc = DYNAMIC_PC;
4000                             dc->pc = DYNAMIC_PC;
4001                             tcg_gen_helper_0_0(helper_done);
4002                             goto jmp_insn;
4003                         case 1:
4004                             if (!supervisor(dc))
4005                                 goto priv_insn;
4006                             dc->npc = DYNAMIC_PC;
4007                             dc->pc = DYNAMIC_PC;
4008                             tcg_gen_helper_0_0(helper_retry);
4009                             goto jmp_insn;
4010                         default:
4011                             goto illegal_insn;
4012                         }
4013                     }
4014                     break;
4015 #endif
4016                 default:
4017                     goto illegal_insn;
4018                 }
4019             }
4020             break;
4021         }
4022         break;
4023     case 3:                     /* load/store instructions */
4024         {
4025             unsigned int xop = GET_FIELD(insn, 7, 12);
4026             rs1 = GET_FIELD(insn, 13, 17);
4027             save_state(dc);
4028             gen_movl_reg_T0(rs1);
4029             if (xop == 0x3c || xop == 0x3e)
4030             {
4031                 rs2 = GET_FIELD(insn, 27, 31);
4032                 gen_movl_reg_T1(rs2);
4033             }
4034             else if (IS_IMM) {       /* immediate */
4035                 rs2 = GET_FIELDs(insn, 19, 31);
4036                 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
4037             } else {            /* register */
4038                 rs2 = GET_FIELD(insn, 27, 31);
4039 #if defined(OPTIM)
4040                 if (rs2 != 0) {
4041 #endif
4042                     gen_movl_reg_T1(rs2);
4043                     gen_op_add_T1_T0();
4044 #if defined(OPTIM)
4045                 }
4046 #endif
4047             }
4048             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4049                 (xop > 0x17 && xop <= 0x1d ) ||
4050                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4051                 switch (xop) {
4052                 case 0x0:       /* load unsigned word */
4053                     gen_op_check_align_T0_3();
4054                     ABI32_MASK(cpu_T[0]);
4055                     tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx);
4056                     break;
4057                 case 0x1:       /* load unsigned byte */
4058                     ABI32_MASK(cpu_T[0]);
4059                     tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx);
4060                     break;
4061                 case 0x2:       /* load unsigned halfword */
4062                     gen_op_check_align_T0_1();
4063                     ABI32_MASK(cpu_T[0]);
4064                     tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx);
4065                     break;
4066                 case 0x3:       /* load double word */
4067                     if (rd & 1)
4068                         goto illegal_insn;
4069                     else {
4070                         TCGv r_dword;
4071
4072                         r_dword = tcg_temp_new(TCG_TYPE_I64);
4073                         gen_op_check_align_T0_7();
4074                         ABI32_MASK(cpu_T[0]);
4075                         tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx);
4076                         tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
4077                         gen_movl_T0_reg(rd + 1);
4078                         tcg_gen_shri_i64(r_dword, r_dword, 32);
4079                         tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
4080                     }
4081                     break;
4082                 case 0x9:       /* load signed byte */
4083                     ABI32_MASK(cpu_T[0]);
4084                     tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
4085                     break;
4086                 case 0xa:       /* load signed halfword */
4087                     gen_op_check_align_T0_1();
4088                     ABI32_MASK(cpu_T[0]);
4089                     tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx);
4090                     break;
4091                 case 0xd:       /* ldstub -- XXX: should be atomically */
4092                     tcg_gen_movi_i32(cpu_tmp0, 0xff);
4093                     ABI32_MASK(cpu_T[0]);
4094                     tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
4095                     tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx);
4096                     break;
4097                 case 0x0f:      /* swap register with memory. Also atomically */
4098                     gen_op_check_align_T0_3();
4099                     gen_movl_reg_T1(rd);
4100                     ABI32_MASK(cpu_T[0]);
4101                     tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx);
4102                     tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
4103                     tcg_gen_mov_i32(cpu_T[1], cpu_tmp0);
4104                     break;
4105 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4106                 case 0x10:      /* load word alternate */
4107 #ifndef TARGET_SPARC64
4108                     if (IS_IMM)
4109                         goto illegal_insn;
4110                     if (!supervisor(dc))
4111                         goto priv_insn;
4112 #endif
4113                     gen_op_check_align_T0_3();
4114                     gen_ld_asi(insn, 4, 0);
4115                     break;
4116                 case 0x11:      /* load unsigned byte alternate */
4117 #ifndef TARGET_SPARC64
4118                     if (IS_IMM)
4119                         goto illegal_insn;
4120                     if (!supervisor(dc))
4121                         goto priv_insn;
4122 #endif
4123                     gen_ld_asi(insn, 1, 0);
4124                     break;
4125                 case 0x12:      /* load unsigned halfword alternate */
4126 #ifndef TARGET_SPARC64
4127                     if (IS_IMM)
4128                         goto illegal_insn;
4129                     if (!supervisor(dc))
4130                         goto priv_insn;
4131 #endif
4132                     gen_op_check_align_T0_1();
4133                     gen_ld_asi(insn, 2, 0);
4134                     break;
4135                 case 0x13:      /* load double word alternate */
4136 #ifndef TARGET_SPARC64
4137                     if (IS_IMM)
4138                         goto illegal_insn;
4139                     if (!supervisor(dc))
4140                         goto priv_insn;
4141 #endif
4142                     if (rd & 1)
4143                         goto illegal_insn;
4144                     gen_op_check_align_T0_7();
4145                     gen_ldda_asi(insn);
4146                     gen_movl_T0_reg(rd + 1);
4147                     break;
4148                 case 0x19:      /* load signed byte alternate */
4149 #ifndef TARGET_SPARC64
4150                     if (IS_IMM)
4151                         goto illegal_insn;
4152                     if (!supervisor(dc))
4153                         goto priv_insn;
4154 #endif
4155                     gen_ld_asi(insn, 1, 1);
4156                     break;
4157                 case 0x1a:      /* load signed halfword alternate */
4158 #ifndef TARGET_SPARC64
4159                     if (IS_IMM)
4160                         goto illegal_insn;
4161                     if (!supervisor(dc))
4162                         goto priv_insn;
4163 #endif
4164                     gen_op_check_align_T0_1();
4165                     gen_ld_asi(insn, 2, 1);
4166                     break;
4167                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
4168 #ifndef TARGET_SPARC64
4169                     if (IS_IMM)
4170                         goto illegal_insn;
4171                     if (!supervisor(dc))
4172                         goto priv_insn;
4173 #endif
4174                     gen_ldstub_asi(insn);
4175                     break;
4176                 case 0x1f:      /* swap reg with alt. memory. Also atomically */
4177 #ifndef TARGET_SPARC64
4178                     if (IS_IMM)
4179                         goto illegal_insn;
4180                     if (!supervisor(dc))
4181                         goto priv_insn;
4182 #endif
4183                     gen_op_check_align_T0_3();
4184                     gen_movl_reg_T1(rd);
4185                     gen_swap_asi(insn);
4186                     break;
4187
4188 #ifndef TARGET_SPARC64
4189                 case 0x30: /* ldc */
4190                 case 0x31: /* ldcsr */
4191                 case 0x33: /* lddc */
4192                     goto ncp_insn;
4193 #endif
4194 #endif
4195 #ifdef TARGET_SPARC64
4196                 case 0x08: /* V9 ldsw */
4197                     gen_op_check_align_T0_3();
4198                     ABI32_MASK(cpu_T[0]);
4199                     tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx);
4200                     break;
4201                 case 0x0b: /* V9 ldx */
4202                     gen_op_check_align_T0_7();
4203                     ABI32_MASK(cpu_T[0]);
4204                     tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx);
4205                     break;
4206                 case 0x18: /* V9 ldswa */
4207                     gen_op_check_align_T0_3();
4208                     gen_ld_asi(insn, 4, 1);
4209                     break;
4210                 case 0x1b: /* V9 ldxa */
4211                     gen_op_check_align_T0_7();
4212                     gen_ld_asi(insn, 8, 0);
4213                     break;
4214                 case 0x2d: /* V9 prefetch, no effect */
4215                     goto skip_move;
4216                 case 0x30: /* V9 ldfa */
4217                     gen_op_check_align_T0_3();
4218                     gen_ldf_asi(insn, 4, rd);
4219                     goto skip_move;
4220                 case 0x33: /* V9 lddfa */
4221                     gen_op_check_align_T0_3();
4222                     gen_ldf_asi(insn, 8, DFPREG(rd));
4223                     goto skip_move;
4224                 case 0x3d: /* V9 prefetcha, no effect */
4225                     goto skip_move;
4226                 case 0x32: /* V9 ldqfa */
4227 #if defined(CONFIG_USER_ONLY)
4228                     gen_op_check_align_T0_3();
4229                     gen_ldf_asi(insn, 16, QFPREG(rd));
4230                     goto skip_move;
4231 #else
4232                     goto nfpu_insn;
4233 #endif
4234 #endif
4235                 default:
4236                     goto illegal_insn;
4237                 }
4238                 gen_movl_T1_reg(rd);
4239 #ifdef TARGET_SPARC64
4240             skip_move: ;
4241 #endif
4242             } else if (xop >= 0x20 && xop < 0x24) {
4243                 if (gen_trap_ifnofpu(dc))
4244                     goto jmp_insn;
4245                 switch (xop) {
4246                 case 0x20:      /* load fpreg */
4247                     gen_op_check_align_T0_3();
4248                     gen_op_ldst(ldf);
4249                     gen_op_store_FT0_fpr(rd);
4250                     break;
4251                 case 0x21:      /* load fsr */
4252                     gen_op_check_align_T0_3();
4253                     gen_op_ldst(ldf);
4254                     tcg_gen_helper_0_0(helper_ldfsr);
4255                     break;
4256                 case 0x22:      /* load quad fpreg */
4257 #if defined(CONFIG_USER_ONLY)
4258                     gen_op_check_align_T0_7();
4259                     gen_op_ldst(ldqf);
4260                     gen_op_store_QT0_fpr(QFPREG(rd));
4261                     break;
4262 #else
4263                     goto nfpu_insn;
4264 #endif
4265                 case 0x23:      /* load double fpreg */
4266                     gen_op_check_align_T0_7();
4267                     gen_op_ldst(lddf);
4268                     gen_op_store_DT0_fpr(DFPREG(rd));
4269                     break;
4270                 default:
4271                     goto illegal_insn;
4272                 }
4273             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4274                        xop == 0xe || xop == 0x1e) {
4275                 gen_movl_reg_T1(rd);
4276                 switch (xop) {
4277                 case 0x4: /* store word */
4278                     gen_op_check_align_T0_3();
4279                     ABI32_MASK(cpu_T[0]);
4280                     tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
4281                     break;
4282                 case 0x5: /* store byte */
4283                     ABI32_MASK(cpu_T[0]);
4284                     tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx);
4285                     break;
4286                 case 0x6: /* store halfword */
4287                     gen_op_check_align_T0_1();
4288                     ABI32_MASK(cpu_T[0]);
4289                     tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx);
4290                     break;
4291                 case 0x7: /* store double word */
4292                     if (rd & 1)
4293                         goto illegal_insn;
4294 #ifndef __i386__
4295                     else {
4296                         TCGv r_dword, r_low;
4297
4298                         gen_op_check_align_T0_7();
4299                         r_dword = tcg_temp_new(TCG_TYPE_I64);
4300                         r_low = tcg_temp_new(TCG_TYPE_I32);
4301                         gen_movl_reg_TN(rd + 1, r_low);
4302                         tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
4303                                            r_low);
4304                         tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx);
4305                     }
4306 #else /* __i386__ */
4307                     gen_op_check_align_T0_7();
4308                     flush_T2(dc);
4309                     gen_movl_reg_T2(rd + 1);
4310                     gen_op_ldst(std);
4311 #endif /* __i386__ */
4312                     break;
4313 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4314                 case 0x14: /* store word alternate */
4315 #ifndef TARGET_SPARC64
4316                     if (IS_IMM)
4317                         goto illegal_insn;
4318                     if (!supervisor(dc))
4319                         goto priv_insn;
4320 #endif
4321                     gen_op_check_align_T0_3();
4322                     gen_st_asi(insn, 4);
4323                     break;
4324                 case 0x15: /* store byte alternate */
4325 #ifndef TARGET_SPARC64
4326                     if (IS_IMM)
4327                         goto illegal_insn;
4328                     if (!supervisor(dc))
4329                         goto priv_insn;
4330 #endif
4331                     gen_st_asi(insn, 1);
4332                     break;
4333                 case 0x16: /* store halfword alternate */
4334 #ifndef TARGET_SPARC64
4335                     if (IS_IMM)
4336                         goto illegal_insn;
4337                     if (!supervisor(dc))
4338                         goto priv_insn;
4339 #endif
4340                     gen_op_check_align_T0_1();
4341                     gen_st_asi(insn, 2);
4342                     break;
4343                 case 0x17: /* store double word alternate */
4344 #ifndef TARGET_SPARC64
4345                     if (IS_IMM)
4346                         goto illegal_insn;
4347                     if (!supervisor(dc))
4348                         goto priv_insn;
4349 #endif
4350                     if (rd & 1)
4351                         goto illegal_insn;
4352                     else {
4353                         int asi;
4354                         TCGv r_dword, r_temp, r_size;
4355
4356                         gen_op_check_align_T0_7();
4357                         r_dword = tcg_temp_new(TCG_TYPE_I64);
4358                         r_temp = tcg_temp_new(TCG_TYPE_I32);
4359                         r_size = tcg_temp_new(TCG_TYPE_I32);
4360                         gen_movl_reg_TN(rd + 1, r_temp);
4361                         tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
4362                                            r_temp);
4363 #ifdef TARGET_SPARC64
4364                         if (IS_IMM) {
4365                             int offset;
4366
4367                             offset = GET_FIELD(insn, 25, 31);
4368                             tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
4369                             tcg_gen_ld_i32(r_dword, cpu_env, offsetof(CPUSPARCState, asi));
4370                         } else {
4371 #endif
4372                             asi = GET_FIELD(insn, 19, 26);
4373                             tcg_gen_movi_i32(r_temp, asi);
4374 #ifdef TARGET_SPARC64
4375                         }
4376 #endif
4377                         tcg_gen_movi_i32(r_size, 8);
4378                         tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_temp, r_size);
4379                     }
4380                     break;
4381 #endif
4382 #ifdef TARGET_SPARC64
4383                 case 0x0e: /* V9 stx */
4384                     gen_op_check_align_T0_7();
4385                     ABI32_MASK(cpu_T[0]);
4386                     tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx);
4387                     break;
4388                 case 0x1e: /* V9 stxa */
4389                     gen_op_check_align_T0_7();
4390                     gen_st_asi(insn, 8);
4391                     break;
4392 #endif
4393                 default:
4394                     goto illegal_insn;
4395                 }
4396             } else if (xop > 0x23 && xop < 0x28) {
4397                 if (gen_trap_ifnofpu(dc))
4398                     goto jmp_insn;
4399                 switch (xop) {
4400                 case 0x24:
4401                     gen_op_check_align_T0_3();
4402                     gen_op_load_fpr_FT0(rd);
4403                     gen_op_ldst(stf);
4404                     break;
4405                 case 0x25: /* stfsr, V9 stxfsr */
4406 #ifdef CONFIG_USER_ONLY
4407                     gen_op_check_align_T0_3();
4408 #endif
4409                     tcg_gen_helper_0_0(helper_stfsr);
4410                     gen_op_ldst(stf);
4411                     break;
4412                 case 0x26:
4413 #ifdef TARGET_SPARC64
4414 #if defined(CONFIG_USER_ONLY)
4415                     /* V9 stqf, store quad fpreg */
4416                     gen_op_check_align_T0_7();
4417                     gen_op_load_fpr_QT0(QFPREG(rd));
4418                     gen_op_ldst(stqf);
4419                     break;
4420 #else
4421                     goto nfpu_insn;
4422 #endif
4423 #else /* !TARGET_SPARC64 */
4424                     /* stdfq, store floating point queue */
4425 #if defined(CONFIG_USER_ONLY)
4426                     goto illegal_insn;
4427 #else
4428                     if (!supervisor(dc))
4429                         goto priv_insn;
4430                     if (gen_trap_ifnofpu(dc))
4431                         goto jmp_insn;
4432                     goto nfq_insn;
4433 #endif
4434 #endif
4435                 case 0x27:
4436                     gen_op_check_align_T0_7();
4437                     gen_op_load_fpr_DT0(DFPREG(rd));
4438                     gen_op_ldst(stdf);
4439                     break;
4440                 default:
4441                     goto illegal_insn;
4442                 }
4443             } else if (xop > 0x33 && xop < 0x3f) {
4444                 switch (xop) {
4445 #ifdef TARGET_SPARC64
4446                 case 0x34: /* V9 stfa */
4447                     gen_op_check_align_T0_3();
4448                     gen_op_load_fpr_FT0(rd);
4449                     gen_stf_asi(insn, 4, rd);
4450                     break;
4451                 case 0x36: /* V9 stqfa */
4452 #if defined(CONFIG_USER_ONLY)
4453                     gen_op_check_align_T0_7();
4454                     gen_op_load_fpr_QT0(QFPREG(rd));
4455                     gen_stf_asi(insn, 16, QFPREG(rd));
4456                     break;
4457 #else
4458                     goto nfpu_insn;
4459 #endif
4460                 case 0x37: /* V9 stdfa */
4461                     gen_op_check_align_T0_3();
4462                     gen_op_load_fpr_DT0(DFPREG(rd));
4463                     gen_stf_asi(insn, 8, DFPREG(rd));
4464                     break;
4465                 case 0x3c: /* V9 casa */
4466                     gen_op_check_align_T0_3();
4467                     gen_cas_asi(insn, rd);
4468                     gen_movl_T1_reg(rd);
4469                     break;
4470                 case 0x3e: /* V9 casxa */
4471                     gen_op_check_align_T0_7();
4472                     gen_casx_asi(insn, rd);
4473                     gen_movl_T1_reg(rd);
4474                     break;
4475 #else
4476                 case 0x34: /* stc */
4477                 case 0x35: /* stcsr */
4478                 case 0x36: /* stdcq */
4479                 case 0x37: /* stdc */
4480                     goto ncp_insn;
4481 #endif
4482                 default:
4483                     goto illegal_insn;
4484                 }
4485             }
4486             else
4487                 goto illegal_insn;
4488         }
4489         break;
4490     }
4491     /* default case for non jump instructions */
4492     if (dc->npc == DYNAMIC_PC) {
4493         dc->pc = DYNAMIC_PC;
4494         gen_op_next_insn();
4495     } else if (dc->npc == JUMP_PC) {
4496         /* we can do a static jump */
4497         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
4498         dc->is_br = 1;
4499     } else {
4500         dc->pc = dc->npc;
4501         dc->npc = dc->npc + 4;
4502     }
4503  jmp_insn:
4504     return;
4505  illegal_insn:
4506     save_state(dc);
4507     gen_op_exception(TT_ILL_INSN);
4508     dc->is_br = 1;
4509     return;
4510 #if !defined(CONFIG_USER_ONLY)
4511  priv_insn:
4512     save_state(dc);
4513     gen_op_exception(TT_PRIV_INSN);
4514     dc->is_br = 1;
4515     return;
4516  nfpu_insn:
4517     save_state(dc);
4518     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4519     dc->is_br = 1;
4520     return;
4521 #ifndef TARGET_SPARC64
4522  nfq_insn:
4523     save_state(dc);
4524     gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4525     dc->is_br = 1;
4526     return;
4527 #endif
4528 #endif
4529 #ifndef TARGET_SPARC64
4530  ncp_insn:
4531     save_state(dc);
4532     gen_op_exception(TT_NCP_INSN);
4533     dc->is_br = 1;
4534     return;
4535 #endif
4536 }
4537
4538 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
4539 {
4540 }
4541
4542 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4543                                                  int spc, CPUSPARCState *env)
4544 {
4545     target_ulong pc_start, last_pc;
4546     uint16_t *gen_opc_end;
4547     DisasContext dc1, *dc = &dc1;
4548     int j, lj = -1;
4549
4550     memset(dc, 0, sizeof(DisasContext));
4551     dc->tb = tb;
4552     pc_start = tb->pc;
4553     dc->pc = pc_start;
4554     last_pc = dc->pc;
4555     dc->npc = (target_ulong) tb->cs_base;
4556     dc->mem_idx = cpu_mmu_index(env);
4557     dc->fpu_enabled = cpu_fpu_enabled(env);
4558     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4559
4560     cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4561
4562     do {
4563         if (env->nb_breakpoints > 0) {
4564             for(j = 0; j < env->nb_breakpoints; j++) {
4565                 if (env->breakpoints[j] == dc->pc) {
4566                     if (dc->pc != pc_start)
4567                         save_state(dc);
4568                     tcg_gen_helper_0_0(helper_debug);
4569                     tcg_gen_exit_tb(0);
4570                     dc->is_br = 1;
4571                     goto exit_gen_loop;
4572                 }
4573             }
4574         }
4575         if (spc) {
4576             if (loglevel > 0)
4577                 fprintf(logfile, "Search PC...\n");
4578             j = gen_opc_ptr - gen_opc_buf;
4579             if (lj < j) {
4580                 lj++;
4581                 while (lj < j)
4582                     gen_opc_instr_start[lj++] = 0;
4583                 gen_opc_pc[lj] = dc->pc;
4584                 gen_opc_npc[lj] = dc->npc;
4585                 gen_opc_instr_start[lj] = 1;
4586             }
4587         }
4588         last_pc = dc->pc;
4589         disas_sparc_insn(dc);
4590
4591         if (dc->is_br)
4592             break;
4593         /* if the next PC is different, we abort now */
4594         if (dc->pc != (last_pc + 4))
4595             break;
4596         /* if we reach a page boundary, we stop generation so that the
4597            PC of a TT_TFAULT exception is always in the right page */
4598         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4599             break;
4600         /* if single step mode, we generate only one instruction and
4601            generate an exception */
4602         if (env->singlestep_enabled) {
4603             gen_jmp_im(dc->pc);
4604             tcg_gen_exit_tb(0);
4605             break;
4606         }
4607     } while ((gen_opc_ptr < gen_opc_end) &&
4608              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4609
4610  exit_gen_loop:
4611     if (!dc->is_br) {
4612         if (dc->pc != DYNAMIC_PC &&
4613             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4614             /* static PC and NPC: we can use direct chaining */
4615             gen_branch(dc, dc->pc, dc->npc);
4616         } else {
4617             if (dc->pc != DYNAMIC_PC)
4618                 gen_jmp_im(dc->pc);
4619             save_npc(dc);
4620             tcg_gen_exit_tb(0);
4621         }
4622     }
4623     *gen_opc_ptr = INDEX_op_end;
4624     if (spc) {
4625         j = gen_opc_ptr - gen_opc_buf;
4626         lj++;
4627         while (lj <= j)
4628             gen_opc_instr_start[lj++] = 0;
4629 #if 0
4630         if (loglevel > 0) {
4631             page_dump(logfile);
4632         }
4633 #endif
4634         gen_opc_jump_pc[0] = dc->jump_pc[0];
4635         gen_opc_jump_pc[1] = dc->jump_pc[1];
4636     } else {
4637         tb->size = last_pc + 4 - pc_start;
4638     }
4639 #ifdef DEBUG_DISAS
4640     if (loglevel & CPU_LOG_TB_IN_ASM) {
4641         fprintf(logfile, "--------------\n");
4642         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4643         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4644         fprintf(logfile, "\n");
4645     }
4646 #endif
4647     return 0;
4648 }
4649
4650 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4651 {
4652     return gen_intermediate_code_internal(tb, 0, env);
4653 }
4654
4655 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4656 {
4657     return gen_intermediate_code_internal(tb, 1, env);
4658 }
4659
4660 void cpu_reset(CPUSPARCState *env)
4661 {
4662     tlb_flush(env, 1);
4663     env->cwp = 0;
4664     env->wim = 1;
4665     env->regwptr = env->regbase + (env->cwp * 16);
4666 #if defined(CONFIG_USER_ONLY)
4667     env->user_mode_only = 1;
4668 #ifdef TARGET_SPARC64
4669     env->cleanwin = NWINDOWS - 2;
4670     env->cansave = NWINDOWS - 2;
4671     env->pstate = PS_RMO | PS_PEF | PS_IE;
4672     env->asi = 0x82; // Primary no-fault
4673 #endif
4674 #else
4675     env->psret = 0;
4676     env->psrs = 1;
4677     env->psrps = 1;
4678 #ifdef TARGET_SPARC64
4679     env->pstate = PS_PRIV;
4680     env->hpstate = HS_PRIV;
4681     env->pc = 0x1fff0000000ULL;
4682     env->tsptr = &env->ts[env->tl];
4683 #else
4684     env->pc = 0;
4685     env->mmuregs[0] &= ~(MMU_E | MMU_NF);
4686     env->mmuregs[0] |= env->mmu_bm;
4687 #endif
4688     env->npc = env->pc + 4;
4689 #endif
4690 }
4691
4692 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
4693 {
4694     CPUSPARCState *env;
4695     const sparc_def_t *def;
4696     static int inited;
4697     unsigned int i;
4698     static const char * const gregnames[8] = {
4699         NULL, // g0 not used
4700         "g1",
4701         "g2",
4702         "g3",
4703         "g4",
4704         "g5",
4705         "g6",
4706         "g7",
4707     };
4708
4709     def = cpu_sparc_find_by_name(cpu_model);
4710     if (!def)
4711         return NULL;
4712
4713     env = qemu_mallocz(sizeof(CPUSPARCState));
4714     if (!env)
4715         return NULL;
4716     cpu_exec_init(env);
4717     env->cpu_model_str = cpu_model;
4718     env->version = def->iu_version;
4719     env->fsr = def->fpu_version;
4720 #if !defined(TARGET_SPARC64)
4721     env->mmu_bm = def->mmu_bm;
4722     env->mmu_ctpr_mask = def->mmu_ctpr_mask;
4723     env->mmu_cxr_mask = def->mmu_cxr_mask;
4724     env->mmu_sfsr_mask = def->mmu_sfsr_mask;
4725     env->mmu_trcr_mask = def->mmu_trcr_mask;
4726     env->mmuregs[0] |= def->mmu_version;
4727     cpu_sparc_set_id(env, 0);
4728 #endif
4729
4730     /* init various static tables */
4731     if (!inited) {
4732         inited = 1;
4733
4734         tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
4735         cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4736         cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4737                                          offsetof(CPUState, regwptr),
4738                                          "regwptr");
4739         //#if TARGET_LONG_BITS > HOST_LONG_BITS
4740 #ifdef TARGET_SPARC64
4741         cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4742                                       TCG_AREG0, offsetof(CPUState, t0), "T0");
4743         cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4744                                       TCG_AREG0, offsetof(CPUState, t1), "T1");
4745         cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4746                                       TCG_AREG0, offsetof(CPUState, t2), "T2");
4747         cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4748                                      TCG_AREG0, offsetof(CPUState, xcc),
4749                                      "xcc");
4750 #else
4751         cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4752         cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4753         cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4754 #endif
4755         cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4756                                         TCG_AREG0, offsetof(CPUState, cc_src),
4757                                         "cc_src");
4758         cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4759                                         TCG_AREG0, offsetof(CPUState, cc_dst),
4760                                         "cc_dst");
4761         cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4762                                      TCG_AREG0, offsetof(CPUState, psr),
4763                                      "psr");
4764         cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4765                                      TCG_AREG0, offsetof(CPUState, fsr),
4766                                      "fsr");
4767         for (i = 1; i < 8; i++)
4768             cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4769                                               offsetof(CPUState, gregs[i]),
4770                                               gregnames[i]);
4771     }
4772
4773     cpu_reset(env);
4774
4775     return env;
4776 }
4777
4778 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
4779 {
4780 #if !defined(TARGET_SPARC64)
4781     env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
4782 #endif
4783 }
4784
4785 static const sparc_def_t sparc_defs[] = {
4786 #ifdef TARGET_SPARC64
4787     {
4788         .name = "Fujitsu Sparc64",
4789         .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
4790                        | (MAXTL << 8) | (NWINDOWS - 1)),
4791         .fpu_version = 0x00000000,
4792         .mmu_version = 0,
4793     },
4794     {
4795         .name = "Fujitsu Sparc64 III",
4796         .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
4797                        | (MAXTL << 8) | (NWINDOWS - 1)),
4798         .fpu_version = 0x00000000,
4799         .mmu_version = 0,
4800     },
4801     {
4802         .name = "Fujitsu Sparc64 IV",
4803         .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
4804                        | (MAXTL << 8) | (NWINDOWS - 1)),
4805         .fpu_version = 0x00000000,
4806         .mmu_version = 0,
4807     },
4808     {
4809         .name = "Fujitsu Sparc64 V",
4810         .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
4811                        | (MAXTL << 8) | (NWINDOWS - 1)),
4812         .fpu_version = 0x00000000,
4813         .mmu_version = 0,
4814     },
4815     {
4816         .name = "TI UltraSparc I",
4817         .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
4818                        | (MAXTL << 8) | (NWINDOWS - 1)),
4819         .fpu_version = 0x00000000,
4820         .mmu_version = 0,
4821     },
4822     {
4823         .name = "TI UltraSparc II",
4824         .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
4825                        | (MAXTL << 8) | (NWINDOWS - 1)),
4826         .fpu_version = 0x00000000,
4827         .mmu_version = 0,
4828     },
4829     {
4830         .name = "TI UltraSparc IIi",
4831         .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
4832                        | (MAXTL << 8) | (NWINDOWS - 1)),
4833         .fpu_version = 0x00000000,
4834         .mmu_version = 0,
4835     },
4836     {
4837         .name = "TI UltraSparc IIe",
4838         .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
4839                        | (MAXTL << 8) | (NWINDOWS - 1)),
4840         .fpu_version = 0x00000000,
4841         .mmu_version = 0,
4842     },
4843     {
4844         .name = "Sun UltraSparc III",
4845         .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
4846                        | (MAXTL << 8) | (NWINDOWS - 1)),
4847         .fpu_version = 0x00000000,
4848         .mmu_version = 0,
4849     },
4850     {
4851         .name = "Sun UltraSparc III Cu",
4852         .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
4853                        | (MAXTL << 8) | (NWINDOWS - 1)),
4854         .fpu_version = 0x00000000,
4855         .mmu_version = 0,
4856     },
4857     {
4858         .name = "Sun UltraSparc IIIi",
4859         .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
4860                        | (MAXTL << 8) | (NWINDOWS - 1)),
4861         .fpu_version = 0x00000000,
4862         .mmu_version = 0,
4863     },
4864     {
4865         .name = "Sun UltraSparc IV",
4866         .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
4867                        | (MAXTL << 8) | (NWINDOWS - 1)),
4868         .fpu_version = 0x00000000,
4869         .mmu_version = 0,
4870     },
4871     {
4872         .name = "Sun UltraSparc IV+",
4873         .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
4874                        | (MAXTL << 8) | (NWINDOWS - 1)),
4875         .fpu_version = 0x00000000,
4876         .mmu_version = 0,
4877     },
4878     {
4879         .name = "Sun UltraSparc IIIi+",
4880         .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
4881                        | (MAXTL << 8) | (NWINDOWS - 1)),
4882         .fpu_version = 0x00000000,
4883         .mmu_version = 0,
4884     },
4885     {
4886         .name = "NEC UltraSparc I",
4887         .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
4888                        | (MAXTL << 8) | (NWINDOWS - 1)),
4889         .fpu_version = 0x00000000,
4890         .mmu_version = 0,
4891     },
4892 #else
4893     {
4894         .name = "Fujitsu MB86900",
4895         .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
4896         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4897         .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
4898         .mmu_bm = 0x00004000,
4899         .mmu_ctpr_mask = 0x007ffff0,
4900         .mmu_cxr_mask = 0x0000003f,
4901         .mmu_sfsr_mask = 0xffffffff,
4902         .mmu_trcr_mask = 0xffffffff,
4903     },
4904     {
4905         .name = "Fujitsu MB86904",
4906         .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
4907         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4908         .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
4909         .mmu_bm = 0x00004000,
4910         .mmu_ctpr_mask = 0x00ffffc0,
4911         .mmu_cxr_mask = 0x000000ff,
4912         .mmu_sfsr_mask = 0x00016fff,
4913         .mmu_trcr_mask = 0x00ffffff,
4914     },
4915     {
4916         .name = "Fujitsu MB86907",
4917         .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
4918         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4919         .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
4920         .mmu_bm = 0x00004000,
4921         .mmu_ctpr_mask = 0xffffffc0,
4922         .mmu_cxr_mask = 0x000000ff,
4923         .mmu_sfsr_mask = 0x00016fff,
4924         .mmu_trcr_mask = 0xffffffff,
4925     },
4926     {
4927         .name = "LSI L64811",
4928         .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
4929         .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
4930         .mmu_version = 0x10 << 24,
4931         .mmu_bm = 0x00004000,
4932         .mmu_ctpr_mask = 0x007ffff0,
4933         .mmu_cxr_mask = 0x0000003f,
4934         .mmu_sfsr_mask = 0xffffffff,
4935         .mmu_trcr_mask = 0xffffffff,
4936     },
4937     {
4938         .name = "Cypress CY7C601",
4939         .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
4940         .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4941         .mmu_version = 0x10 << 24,
4942         .mmu_bm = 0x00004000,
4943         .mmu_ctpr_mask = 0x007ffff0,
4944         .mmu_cxr_mask = 0x0000003f,
4945         .mmu_sfsr_mask = 0xffffffff,
4946         .mmu_trcr_mask = 0xffffffff,
4947     },
4948     {
4949         .name = "Cypress CY7C611",
4950         .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
4951         .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4952         .mmu_version = 0x10 << 24,
4953         .mmu_bm = 0x00004000,
4954         .mmu_ctpr_mask = 0x007ffff0,
4955         .mmu_cxr_mask = 0x0000003f,
4956         .mmu_sfsr_mask = 0xffffffff,
4957         .mmu_trcr_mask = 0xffffffff,
4958     },
4959     {
4960         .name = "TI SuperSparc II",
4961         .iu_version = 0x40000000,
4962         .fpu_version = 0 << 17,
4963         .mmu_version = 0x04000000,
4964         .mmu_bm = 0x00002000,
4965         .mmu_ctpr_mask = 0xffffffc0,
4966         .mmu_cxr_mask = 0x0000ffff,
4967         .mmu_sfsr_mask = 0xffffffff,
4968         .mmu_trcr_mask = 0xffffffff,
4969     },
4970     {
4971         .name = "TI MicroSparc I",
4972         .iu_version = 0x41000000,
4973         .fpu_version = 4 << 17,
4974         .mmu_version = 0x41000000,
4975         .mmu_bm = 0x00004000,
4976         .mmu_ctpr_mask = 0x007ffff0,
4977         .mmu_cxr_mask = 0x0000003f,
4978         .mmu_sfsr_mask = 0x00016fff,
4979         .mmu_trcr_mask = 0x0000003f,
4980     },
4981     {
4982         .name = "TI MicroSparc II",
4983         .iu_version = 0x42000000,
4984         .fpu_version = 4 << 17,
4985         .mmu_version = 0x02000000,
4986         .mmu_bm = 0x00004000,
4987         .mmu_ctpr_mask = 0x00ffffc0,
4988         .mmu_cxr_mask = 0x000000ff,
4989         .mmu_sfsr_mask = 0x00016fff,
4990         .mmu_trcr_mask = 0x00ffffff,
4991     },
4992     {
4993         .name = "TI MicroSparc IIep",
4994         .iu_version = 0x42000000,
4995         .fpu_version = 4 << 17,
4996         .mmu_version = 0x04000000,
4997         .mmu_bm = 0x00004000,
4998         .mmu_ctpr_mask = 0x00ffffc0,
4999         .mmu_cxr_mask = 0x000000ff,
5000         .mmu_sfsr_mask = 0x00016bff,
5001         .mmu_trcr_mask = 0x00ffffff,
5002     },
5003     {
5004         .name = "TI SuperSparc 51",
5005         .iu_version = 0x43000000,
5006         .fpu_version = 0 << 17,
5007         .mmu_version = 0x04000000,
5008         .mmu_bm = 0x00002000,
5009         .mmu_ctpr_mask = 0xffffffc0,
5010         .mmu_cxr_mask = 0x0000ffff,
5011         .mmu_sfsr_mask = 0xffffffff,
5012         .mmu_trcr_mask = 0xffffffff,
5013     },
5014     {
5015         .name = "TI SuperSparc 61",
5016         .iu_version = 0x44000000,
5017         .fpu_version = 0 << 17,
5018         .mmu_version = 0x04000000,
5019         .mmu_bm = 0x00002000,
5020         .mmu_ctpr_mask = 0xffffffc0,
5021         .mmu_cxr_mask = 0x0000ffff,
5022         .mmu_sfsr_mask = 0xffffffff,
5023         .mmu_trcr_mask = 0xffffffff,
5024     },
5025     {
5026         .name = "Ross RT625",
5027         .iu_version = 0x1e000000,
5028         .fpu_version = 1 << 17,
5029         .mmu_version = 0x1e000000,
5030         .mmu_bm = 0x00004000,
5031         .mmu_ctpr_mask = 0x007ffff0,
5032         .mmu_cxr_mask = 0x0000003f,
5033         .mmu_sfsr_mask = 0xffffffff,
5034         .mmu_trcr_mask = 0xffffffff,
5035     },
5036     {
5037         .name = "Ross RT620",
5038         .iu_version = 0x1f000000,
5039         .fpu_version = 1 << 17,
5040         .mmu_version = 0x1f000000,
5041         .mmu_bm = 0x00004000,
5042         .mmu_ctpr_mask = 0x007ffff0,
5043         .mmu_cxr_mask = 0x0000003f,
5044         .mmu_sfsr_mask = 0xffffffff,
5045         .mmu_trcr_mask = 0xffffffff,
5046     },
5047     {
5048         .name = "BIT B5010",
5049         .iu_version = 0x20000000,
5050         .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
5051         .mmu_version = 0x20000000,
5052         .mmu_bm = 0x00004000,
5053         .mmu_ctpr_mask = 0x007ffff0,
5054         .mmu_cxr_mask = 0x0000003f,
5055         .mmu_sfsr_mask = 0xffffffff,
5056         .mmu_trcr_mask = 0xffffffff,
5057     },
5058     {
5059         .name = "Matsushita MN10501",
5060         .iu_version = 0x50000000,
5061         .fpu_version = 0 << 17,
5062         .mmu_version = 0x50000000,
5063         .mmu_bm = 0x00004000,
5064         .mmu_ctpr_mask = 0x007ffff0,
5065         .mmu_cxr_mask = 0x0000003f,
5066         .mmu_sfsr_mask = 0xffffffff,
5067         .mmu_trcr_mask = 0xffffffff,
5068     },
5069     {
5070         .name = "Weitek W8601",
5071         .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
5072         .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
5073         .mmu_version = 0x10 << 24,
5074         .mmu_bm = 0x00004000,
5075         .mmu_ctpr_mask = 0x007ffff0,
5076         .mmu_cxr_mask = 0x0000003f,
5077         .mmu_sfsr_mask = 0xffffffff,
5078         .mmu_trcr_mask = 0xffffffff,
5079     },
5080     {
5081         .name = "LEON2",
5082         .iu_version = 0xf2000000,
5083         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
5084         .mmu_version = 0xf2000000,
5085         .mmu_bm = 0x00004000,
5086         .mmu_ctpr_mask = 0x007ffff0,
5087         .mmu_cxr_mask = 0x0000003f,
5088         .mmu_sfsr_mask = 0xffffffff,
5089         .mmu_trcr_mask = 0xffffffff,
5090     },
5091     {
5092         .name = "LEON3",
5093         .iu_version = 0xf3000000,
5094         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
5095         .mmu_version = 0xf3000000,
5096         .mmu_bm = 0x00004000,
5097         .mmu_ctpr_mask = 0x007ffff0,
5098         .mmu_cxr_mask = 0x0000003f,
5099         .mmu_sfsr_mask = 0xffffffff,
5100         .mmu_trcr_mask = 0xffffffff,
5101     },
5102 #endif
5103 };
5104
5105 static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name)
5106 {
5107     unsigned int i;
5108
5109     for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
5110         if (strcasecmp(name, sparc_defs[i].name) == 0) {
5111             return &sparc_defs[i];
5112         }
5113     }
5114     return NULL;
5115 }
5116
5117 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
5118 {
5119     unsigned int i;
5120
5121     for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
5122         (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
5123                        sparc_defs[i].name,
5124                        sparc_defs[i].iu_version,
5125                        sparc_defs[i].fpu_version,
5126                        sparc_defs[i].mmu_version);
5127     }
5128 }
5129
5130 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
5131
5132 void cpu_dump_state(CPUState *env, FILE *f,
5133                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
5134                     int flags)
5135 {
5136     int i, x;
5137
5138     cpu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
5139     cpu_fprintf(f, "General Registers:\n");
5140     for (i = 0; i < 4; i++)
5141         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
5142     cpu_fprintf(f, "\n");
5143     for (; i < 8; i++)
5144         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
5145     cpu_fprintf(f, "\nCurrent Register Window:\n");
5146     for (x = 0; x < 3; x++) {
5147         for (i = 0; i < 4; i++)
5148             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
5149                     (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
5150                     env->regwptr[i + x * 8]);
5151         cpu_fprintf(f, "\n");
5152         for (; i < 8; i++)
5153             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
5154                     (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
5155                     env->regwptr[i + x * 8]);
5156         cpu_fprintf(f, "\n");
5157     }
5158     cpu_fprintf(f, "\nFloating Point Registers:\n");
5159     for (i = 0; i < 32; i++) {
5160         if ((i & 3) == 0)
5161             cpu_fprintf(f, "%%f%02d:", i);
5162         cpu_fprintf(f, " %016lf", env->fpr[i]);
5163         if ((i & 3) == 3)
5164             cpu_fprintf(f, "\n");
5165     }
5166 #ifdef TARGET_SPARC64
5167     cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
5168                 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
5169     cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
5170                 env->cansave, env->canrestore, env->otherwin, env->wstate,
5171                 env->cleanwin, NWINDOWS - 1 - env->cwp);
5172 #else
5173     cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
5174             GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
5175             GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
5176             env->psrs?'S':'-', env->psrps?'P':'-',
5177             env->psret?'E':'-', env->wim);
5178 #endif
5179     cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
5180 }
5181
5182 #if defined(CONFIG_USER_ONLY)
5183 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
5184 {
5185     return addr;
5186 }
5187
5188 #else
5189 extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
5190                                  int *access_index, target_ulong address, int rw,
5191                                  int mmu_idx);
5192
5193 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
5194 {
5195     target_phys_addr_t phys_addr;
5196     int prot, access_index;
5197
5198     if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
5199                              MMU_KERNEL_IDX) != 0)
5200         if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
5201                                  0, MMU_KERNEL_IDX) != 0)
5202             return -1;
5203     if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
5204         return -1;
5205     return phys_addr;
5206 }
5207 #endif
5208
5209 void helper_flush(target_ulong addr)
5210 {
5211     addr &= ~7;
5212     tb_invalidate_page_range(addr, addr + 8);
5213 }