git.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <stdarg.h>
  23 #include <stdlib.h>
  24 #include <stdio.h>
  25 #include <string.h>
  26 #include <inttypes.h>
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30 #include "disas.h"
  31 #include "helper.h"
  32 #include "tcg-op.h"
  33
  34 #define DEBUG_DISAS
  35
  36 #define DYNAMIC_PC  1 /* dynamic pc value */
  37 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  38                          according to jump_pc[T2] */
  39
  40 /* global register indexes */
  41 static TCGv cpu_env, cpu_T[2], cpu_regwptr;
  42 static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
  43 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
  44 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
  45 #ifdef TARGET_SPARC64
  46 static TCGv cpu_xcc;
  47 #endif
  48 /* local register indexes (only used inside old micro ops) */
  49 static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
  50
  51 typedef struct DisasContext {
  52     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  53     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  54     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  55     int is_br;
  56     int mem_idx;
  57     int fpu_enabled;
  58     struct TranslationBlock *tb;
  59     uint32_t features;
  60 } DisasContext;
  61
  62 // This function uses non-native bit order
  63 #define GET_FIELD(X, FROM, TO) \
  64   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  65
  66 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  67 #define GET_FIELD_SP(X, FROM, TO) \
  68     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  69
  70 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  71 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
  72
  73 #ifdef TARGET_SPARC64
  74 #define FFPREG(r) (r)
  75 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
  76 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
  77 #else
  78 #define FFPREG(r) (r)
  79 #define DFPREG(r) (r & 0x1e)
  80 #define QFPREG(r) (r & 0x1c)
  81 #endif
  82
  83 static int sign_extend(int x, int len)
  84 {
  85     len = 32 - len;
  86     return (x << len) >> len;
  87 }
  88
  89 #define IS_IMM (insn & (1<<13))
  90
  91 /* floating point registers moves */
  92 static void gen_op_load_fpr_FT0(unsigned int src)
  93 {
  94     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  95     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
  96 }
  97
  98 static void gen_op_load_fpr_FT1(unsigned int src)
  99 {
 100     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 101     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
 102 }
 103
 104 static void gen_op_store_FT0_fpr(unsigned int dst)
 105 {
 106     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
 107     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 108 }
 109
 110 static void gen_op_load_fpr_DT0(unsigned int src)
 111 {
 112     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 113     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 114                    offsetof(CPU_DoubleU, l.upper));
 115     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 116     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 117                    offsetof(CPU_DoubleU, l.lower));
 118 }
 119
 120 static void gen_op_load_fpr_DT1(unsigned int src)
 121 {
 122     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 123     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
 124                    offsetof(CPU_DoubleU, l.upper));
 125     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 126     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
 127                    offsetof(CPU_DoubleU, l.lower));
 128 }
 129
 130 static void gen_op_store_DT0_fpr(unsigned int dst)
 131 {
 132     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 133                    offsetof(CPU_DoubleU, l.upper));
 134     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 135     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 136                    offsetof(CPU_DoubleU, l.lower));
 137     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 138 }
 139
 140 static void gen_op_load_fpr_QT0(unsigned int src)
 141 {
 142     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 143     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 144                    offsetof(CPU_QuadU, l.upmost));
 145     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 146     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 147                    offsetof(CPU_QuadU, l.upper));
 148     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 149     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 150                    offsetof(CPU_QuadU, l.lower));
 151     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 152     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 153                    offsetof(CPU_QuadU, l.lowest));
 154 }
 155
 156 static void gen_op_load_fpr_QT1(unsigned int src)
 157 {
 158     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 159     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 160                    offsetof(CPU_QuadU, l.upmost));
 161     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 162     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 163                    offsetof(CPU_QuadU, l.upper));
 164     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 165     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 166                    offsetof(CPU_QuadU, l.lower));
 167     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 168     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 169                    offsetof(CPU_QuadU, l.lowest));
 170 }
 171
 172 static void gen_op_store_QT0_fpr(unsigned int dst)
 173 {
 174     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 175                    offsetof(CPU_QuadU, l.upmost));
 176     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 177     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 178                    offsetof(CPU_QuadU, l.upper));
 179     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 180     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 181                    offsetof(CPU_QuadU, l.lower));
 182     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
 183     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 184                    offsetof(CPU_QuadU, l.lowest));
 185     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
 186 }
 187
 188 /* moves */
 189 #ifdef CONFIG_USER_ONLY
 190 #define supervisor(dc) 0
 191 #ifdef TARGET_SPARC64
 192 #define hypervisor(dc) 0
 193 #endif
 194 #else
 195 #define supervisor(dc) (dc->mem_idx >= 1)
 196 #ifdef TARGET_SPARC64
 197 #define hypervisor(dc) (dc->mem_idx == 2)
 198 #else
 199 #endif
 200 #endif
 201
 202 #ifdef TARGET_ABI32
 203 #define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
 204 #else
 205 #define ABI32_MASK(addr)
 206 #endif
 207
 208 static inline void gen_movl_reg_TN(int reg, TCGv tn)
 209 {
 210     if (reg == 0)
 211         tcg_gen_movi_tl(tn, 0);
 212     else if (reg < 8)
 213         tcg_gen_mov_tl(tn, cpu_gregs[reg]);
 214     else {
 215         tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 216     }
 217 }
 218
 219 static inline void gen_movl_TN_reg(int reg, TCGv tn)
 220 {
 221     if (reg == 0)
 222         return;
 223     else if (reg < 8)
 224         tcg_gen_mov_tl(cpu_gregs[reg], tn);
 225     else {
 226         tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 227     }
 228 }
 229
 230 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 231                                target_ulong pc, target_ulong npc)
 232 {
 233     TranslationBlock *tb;
 234
 235     tb = s->tb;
 236     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 237         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 238         /* jump to same page: we can use a direct jump */
 239         tcg_gen_goto_tb(tb_num);
 240         tcg_gen_movi_tl(cpu_pc, pc);
 241         tcg_gen_movi_tl(cpu_npc, npc);
 242         tcg_gen_exit_tb((long)tb + tb_num);
 243     } else {
 244         /* jump to another page: currently not optimized */
 245         tcg_gen_movi_tl(cpu_pc, pc);
 246         tcg_gen_movi_tl(cpu_npc, npc);
 247         tcg_gen_exit_tb(0);
 248     }
 249 }
 250
 251 // XXX suboptimal
 252 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
 253 {
 254     tcg_gen_extu_i32_tl(reg, src);
 255     tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
 256     tcg_gen_andi_tl(reg, reg, 0x1);
 257 }
 258
 259 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
 260 {
 261     tcg_gen_extu_i32_tl(reg, src);
 262     tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
 263     tcg_gen_andi_tl(reg, reg, 0x1);
 264 }
 265
 266 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
 267 {
 268     tcg_gen_extu_i32_tl(reg, src);
 269     tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
 270     tcg_gen_andi_tl(reg, reg, 0x1);
 271 }
 272
 273 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
 274 {
 275     tcg_gen_extu_i32_tl(reg, src);
 276     tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
 277     tcg_gen_andi_tl(reg, reg, 0x1);
 278 }
 279
 280 static inline void gen_cc_clear_icc(void)
 281 {
 282     tcg_gen_movi_i32(cpu_psr, 0);
 283 }
 284
 285 #ifdef TARGET_SPARC64
 286 static inline void gen_cc_clear_xcc(void)
 287 {
 288     tcg_gen_movi_i32(cpu_xcc, 0);
 289 }
 290 #endif
 291
 292 /* old op:
 293     if (!T0)
 294         env->psr |= PSR_ZERO;
 295     if ((int32_t) T0 < 0)
 296         env->psr |= PSR_NEG;
 297 */
 298 static inline void gen_cc_NZ_icc(TCGv dst)
 299 {
 300     TCGv r_temp;
 301     int l1, l2;
 302
 303     l1 = gen_new_label();
 304     l2 = gen_new_label();
 305     r_temp = tcg_temp_new(TCG_TYPE_TL);
 306     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 307     tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
 308     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
 309     gen_set_label(l1);
 310     tcg_gen_ext_i32_tl(r_temp, dst);
 311     tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
 312     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
 313     gen_set_label(l2);
 314 }
 315
 316 #ifdef TARGET_SPARC64
 317 static inline void gen_cc_NZ_xcc(TCGv dst)
 318 {
 319     int l1, l2;
 320
 321     l1 = gen_new_label();
 322     l2 = gen_new_label();
 323     tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
 324     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
 325     gen_set_label(l1);
 326     tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
 327     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
 328     gen_set_label(l2);
 329 }
 330 #endif
 331
 332 /* old op:
 333     if (T0 < src1)
 334         env->psr |= PSR_CARRY;
 335 */
 336 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
 337 {
 338     TCGv r_temp;
 339     int l1;
 340
 341     l1 = gen_new_label();
 342     r_temp = tcg_temp_new(TCG_TYPE_TL);
 343     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 344     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 345     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 346     gen_set_label(l1);
 347 }
 348
 349 #ifdef TARGET_SPARC64
 350 static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
 351 {
 352     int l1;
 353
 354     l1 = gen_new_label();
 355     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 356     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 357     gen_set_label(l1);
 358 }
 359 #endif
 360
 361 /* old op:
 362     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
 363         env->psr |= PSR_OVF;
 364 */
 365 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
 366 {
 367     TCGv r_temp;
 368
 369     r_temp = tcg_temp_new(TCG_TYPE_TL);
 370     tcg_gen_xor_tl(r_temp, src1, src2);
 371     tcg_gen_xori_tl(r_temp, r_temp, -1);
 372     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 373     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 374     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 375     tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
 376     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 377     tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
 378 }
 379
 380 #ifdef TARGET_SPARC64
 381 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
 382 {
 383     TCGv r_temp;
 384
 385     r_temp = tcg_temp_new(TCG_TYPE_TL);
 386     tcg_gen_xor_tl(r_temp, src1, src2);
 387     tcg_gen_xori_tl(r_temp, r_temp, -1);
 388     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 389     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 390     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 391     tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
 392     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 393     tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
 394 }
 395 #endif
 396
 397 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
 398 {
 399     TCGv r_temp;
 400     int l1;
 401
 402     l1 = gen_new_label();
 403
 404     r_temp = tcg_temp_new(TCG_TYPE_TL);
 405     tcg_gen_xor_tl(r_temp, src1, src2);
 406     tcg_gen_xori_tl(r_temp, r_temp, -1);
 407     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 408     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 409     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 410     tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
 411     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 412     gen_set_label(l1);
 413 }
 414
 415 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
 416 {
 417     int l1;
 418
 419     l1 = gen_new_label();
 420     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 421     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 422     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
 423     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 424     gen_set_label(l1);
 425 }
 426
 427 static inline void gen_tag_tv(TCGv src1, TCGv src2)
 428 {
 429     int l1;
 430
 431     l1 = gen_new_label();
 432     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 433     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 434     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
 435     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 436     gen_set_label(l1);
 437 }
 438
 439 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
 440 {
 441     tcg_gen_mov_tl(cpu_cc_src, src1);
 442     tcg_gen_mov_tl(cpu_cc_src2, src2);
 443     tcg_gen_add_tl(dst, src1, src2);
 444     tcg_gen_mov_tl(cpu_cc_dst, dst);
 445     gen_cc_clear_icc();
 446     gen_cc_NZ_icc(cpu_cc_dst);
 447     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 448     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 449 #ifdef TARGET_SPARC64
 450     gen_cc_clear_xcc();
 451     gen_cc_NZ_xcc(cpu_cc_dst);
 452     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 453     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 454 #endif
 455 }
 456
 457 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
 458 {
 459     tcg_gen_mov_tl(cpu_cc_src, src1);
 460     tcg_gen_mov_tl(cpu_cc_src2, src2);
 461     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 462     tcg_gen_add_tl(dst, src1, cpu_tmp0);
 463     gen_cc_clear_icc();
 464     gen_cc_C_add_icc(dst, cpu_cc_src);
 465 #ifdef TARGET_SPARC64
 466     gen_cc_clear_xcc();
 467     gen_cc_C_add_xcc(dst, cpu_cc_src);
 468 #endif
 469     tcg_gen_add_tl(dst, dst, cpu_cc_src2);
 470     tcg_gen_mov_tl(cpu_cc_dst, dst);
 471     gen_cc_NZ_icc(cpu_cc_dst);
 472     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 473     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 474 #ifdef TARGET_SPARC64
 475     gen_cc_NZ_xcc(cpu_cc_dst);
 476     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 477     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 478 #endif
 479 }
 480
 481 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
 482 {
 483     tcg_gen_mov_tl(cpu_cc_src, src1);
 484     tcg_gen_mov_tl(cpu_cc_src2, src2);
 485     tcg_gen_add_tl(dst, src1, src2);
 486     tcg_gen_mov_tl(cpu_cc_dst, dst);
 487     gen_cc_clear_icc();
 488     gen_cc_NZ_icc(cpu_cc_dst);
 489     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 490     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 491     gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
 492 #ifdef TARGET_SPARC64
 493     gen_cc_clear_xcc();
 494     gen_cc_NZ_xcc(cpu_cc_dst);
 495     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 496     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 497 #endif
 498 }
 499
 500 static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
 501 {
 502     tcg_gen_mov_tl(cpu_cc_src, src1);
 503     tcg_gen_mov_tl(cpu_cc_src2, src2);
 504     gen_tag_tv(cpu_cc_src, cpu_cc_src2);
 505     tcg_gen_add_tl(dst, src1, src2);
 506     tcg_gen_mov_tl(cpu_cc_dst, dst);
 507     gen_add_tv(dst, cpu_cc_src, cpu_cc_src2);
 508     gen_cc_clear_icc();
 509     gen_cc_NZ_icc(cpu_cc_dst);
 510     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 511 #ifdef TARGET_SPARC64
 512     gen_cc_clear_xcc();
 513     gen_cc_NZ_xcc(cpu_cc_dst);
 514     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 515     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 516 #endif
 517 }
 518
 519 /* old op:
 520     if (src1 < T1)
 521         env->psr |= PSR_CARRY;
 522 */
 523 static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
 524 {
 525     TCGv r_temp1, r_temp2;
 526     int l1;
 527
 528     l1 = gen_new_label();
 529     r_temp1 = tcg_temp_new(TCG_TYPE_TL);
 530     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 531     tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
 532     tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
 533     tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
 534     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 535     gen_set_label(l1);
 536 }
 537
 538 #ifdef TARGET_SPARC64
 539 static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
 540 {
 541     int l1;
 542
 543     l1 = gen_new_label();
 544     tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
 545     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 546     gen_set_label(l1);
 547 }
 548 #endif
 549
 550 /* old op:
 551     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
 552         env->psr |= PSR_OVF;
 553 */
 554 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
 555 {
 556     TCGv r_temp;
 557
 558     r_temp = tcg_temp_new(TCG_TYPE_TL);
 559     tcg_gen_xor_tl(r_temp, src1, src2);
 560     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 561     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 562     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 563     tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
 564     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 565     tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
 566 }
 567
 568 #ifdef TARGET_SPARC64
 569 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
 570 {
 571     TCGv r_temp;
 572
 573     r_temp = tcg_temp_new(TCG_TYPE_TL);
 574     tcg_gen_xor_tl(r_temp, src1, src2);
 575     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 576     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 577     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 578     tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
 579     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 580     tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
 581 }
 582 #endif
 583
 584 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
 585 {
 586     TCGv r_temp;
 587     int l1;
 588
 589     l1 = gen_new_label();
 590
 591     r_temp = tcg_temp_new(TCG_TYPE_TL);
 592     tcg_gen_xor_tl(r_temp, src1, src2);
 593     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 594     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 595     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 596     tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
 597     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 598     gen_set_label(l1);
 599 }
 600
 601 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
 602 {
 603     tcg_gen_mov_tl(cpu_cc_src, src1);
 604     tcg_gen_mov_tl(cpu_cc_src2, src2);
 605     tcg_gen_sub_tl(dst, src1, src2);
 606     tcg_gen_mov_tl(cpu_cc_dst, dst);
 607     gen_cc_clear_icc();
 608     gen_cc_NZ_icc(cpu_cc_dst);
 609     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 610     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 611 #ifdef TARGET_SPARC64
 612     gen_cc_clear_xcc();
 613     gen_cc_NZ_xcc(cpu_cc_dst);
 614     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 615     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 616 #endif
 617 }
 618
 619 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
 620 {
 621     tcg_gen_mov_tl(cpu_cc_src, src1);
 622     tcg_gen_mov_tl(cpu_cc_src2, src2);
 623     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 624     tcg_gen_sub_tl(dst, src1, cpu_tmp0);
 625     gen_cc_clear_icc();
 626     gen_cc_C_sub_icc(dst, cpu_cc_src);
 627 #ifdef TARGET_SPARC64
 628     gen_cc_clear_xcc();
 629     gen_cc_C_sub_xcc(dst, cpu_cc_src);
 630 #endif
 631     tcg_gen_sub_tl(dst, dst, cpu_cc_src2);
 632     tcg_gen_mov_tl(cpu_cc_dst, dst);
 633     gen_cc_NZ_icc(cpu_cc_dst);
 634     gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
 635     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 636 #ifdef TARGET_SPARC64
 637     gen_cc_NZ_xcc(cpu_cc_dst);
 638     gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
 639     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 640 #endif
 641 }
 642
 643 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
 644 {
 645     tcg_gen_mov_tl(cpu_cc_src, src1);
 646     tcg_gen_mov_tl(cpu_cc_src2, src2);
 647     tcg_gen_sub_tl(dst, src1, src2);
 648     tcg_gen_mov_tl(cpu_cc_dst, dst);
 649     gen_cc_clear_icc();
 650     gen_cc_NZ_icc(cpu_cc_dst);
 651     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 652     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 653     gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
 654 #ifdef TARGET_SPARC64
 655     gen_cc_clear_xcc();
 656     gen_cc_NZ_xcc(cpu_cc_dst);
 657     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 658     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 659 #endif
 660 }
 661
 662 static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
 663 {
 664     tcg_gen_mov_tl(cpu_cc_src, src1);
 665     tcg_gen_mov_tl(cpu_cc_src2, src2);
 666     gen_tag_tv(cpu_cc_src, cpu_cc_src2);
 667     tcg_gen_sub_tl(dst, src1, src2);
 668     tcg_gen_mov_tl(cpu_cc_dst, dst);
 669     gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2);
 670     gen_cc_clear_icc();
 671     gen_cc_NZ_icc(cpu_cc_dst);
 672     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 673 #ifdef TARGET_SPARC64
 674     gen_cc_clear_xcc();
 675     gen_cc_NZ_xcc(cpu_cc_dst);
 676     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 677     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 678 #endif
 679 }
 680
 681 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
 682 {
 683     TCGv r_temp, r_temp2;
 684     int l1;
 685
 686     l1 = gen_new_label();
 687     r_temp = tcg_temp_new(TCG_TYPE_TL);
 688     r_temp2 = tcg_temp_new(TCG_TYPE_I32);
 689
 690     /* old op:
 691     if (!(env->y & 1))
 692         T1 = 0;
 693     */
 694     tcg_gen_mov_tl(cpu_cc_src, src1);
 695     tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 696     tcg_gen_trunc_tl_i32(r_temp2, r_temp);
 697     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 698     tcg_gen_mov_tl(cpu_cc_src2, src2);
 699     tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
 700     tcg_gen_movi_tl(cpu_cc_src2, 0);
 701     gen_set_label(l1);
 702
 703     // b2 = T0 & 1;
 704     // env->y = (b2 << 31) | (env->y >> 1);
 705     tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
 706     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 707     tcg_gen_shli_i32(r_temp2, r_temp2, 31);
 708     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 709     tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
 710     tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
 711     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 712
 713     // b1 = N ^ V;
 714     gen_mov_reg_N(cpu_tmp0, cpu_psr);
 715     gen_mov_reg_V(r_temp, cpu_psr);
 716     tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
 717
 718     // T0 = (b1 << 31) | (T0 >> 1);
 719     // src1 = T0;
 720     tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
 721     tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
 722     tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
 723
 724     /* do addition and update flags */
 725     tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
 726     tcg_gen_mov_tl(cpu_cc_dst, dst);
 727
 728     gen_cc_clear_icc();
 729     gen_cc_NZ_icc(cpu_cc_dst);
 730     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 731     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 732 }
 733
 734 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
 735 {
 736     TCGv r_temp, r_temp2;
 737
 738     r_temp = tcg_temp_new(TCG_TYPE_I64);
 739     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 740
 741     tcg_gen_extu_tl_i64(r_temp, src2);
 742     tcg_gen_extu_tl_i64(r_temp2, src1);
 743     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 744
 745     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 746     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 747     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 748 #ifdef TARGET_SPARC64
 749     tcg_gen_mov_i64(dst, r_temp2);
 750 #else
 751     tcg_gen_trunc_i64_tl(dst, r_temp2);
 752 #endif
 753 }
 754
 755 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
 756 {
 757     TCGv r_temp, r_temp2;
 758
 759     r_temp = tcg_temp_new(TCG_TYPE_I64);
 760     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 761
 762     tcg_gen_ext_tl_i64(r_temp, src2);
 763     tcg_gen_ext_tl_i64(r_temp2, src1);
 764     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 765
 766     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 767     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 768     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 769 #ifdef TARGET_SPARC64
 770     tcg_gen_mov_i64(dst, r_temp2);
 771 #else
 772     tcg_gen_trunc_i64_tl(dst, r_temp2);
 773 #endif
 774 }
 775
 776 #ifdef TARGET_SPARC64
 777 static inline void gen_trap_ifdivzero_tl(TCGv divisor)
 778 {
 779     int l1;
 780
 781     l1 = gen_new_label();
 782     tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
 783     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO));
 784     gen_set_label(l1);
 785 }
 786
 787 static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
 788 {
 789     int l1, l2;
 790
 791     l1 = gen_new_label();
 792     l2 = gen_new_label();
 793     tcg_gen_mov_tl(cpu_cc_src, src1);
 794     tcg_gen_mov_tl(cpu_cc_src2, src2);
 795     gen_trap_ifdivzero_tl(src2);
 796     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
 797     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
 798     tcg_gen_movi_i64(dst, INT64_MIN);
 799     tcg_gen_br(l2);
 800     gen_set_label(l1);
 801     tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
 802     gen_set_label(l2);
 803 }
 804 #endif
 805
 806 static inline void gen_op_div_cc(TCGv dst)
 807 {
 808     int l1;
 809
 810     tcg_gen_mov_tl(cpu_cc_dst, dst);
 811     gen_cc_clear_icc();
 812     gen_cc_NZ_icc(cpu_cc_dst);
 813     l1 = gen_new_label();
 814     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
 815     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
 816     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 817     gen_set_label(l1);
 818 }
 819
 820 static inline void gen_op_logic_cc(TCGv dst)
 821 {
 822     tcg_gen_mov_tl(cpu_cc_dst, dst);
 823
 824     gen_cc_clear_icc();
 825     gen_cc_NZ_icc(cpu_cc_dst);
 826 #ifdef TARGET_SPARC64
 827     gen_cc_clear_xcc();
 828     gen_cc_NZ_xcc(cpu_cc_dst);
 829 #endif
 830 }
 831
 832 // 1
 833 static inline void gen_op_eval_ba(TCGv dst)
 834 {
 835     tcg_gen_movi_tl(dst, 1);
 836 }
 837
 838 // Z
 839 static inline void gen_op_eval_be(TCGv dst, TCGv src)
 840 {
 841     gen_mov_reg_Z(dst, src);
 842 }
 843
 844 // Z | (N ^ V)
 845 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
 846 {
 847     gen_mov_reg_N(cpu_tmp0, src);
 848     gen_mov_reg_V(dst, src);
 849     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 850     gen_mov_reg_Z(cpu_tmp0, src);
 851     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 852 }
 853
 854 // N ^ V
 855 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
 856 {
 857     gen_mov_reg_V(cpu_tmp0, src);
 858     gen_mov_reg_N(dst, src);
 859     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 860 }
 861
 862 // C | Z
 863 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
 864 {
 865     gen_mov_reg_Z(cpu_tmp0, src);
 866     gen_mov_reg_C(dst, src);
 867     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 868 }
 869
 870 // C
 871 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
 872 {
 873     gen_mov_reg_C(dst, src);
 874 }
 875
 876 // V
 877 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
 878 {
 879     gen_mov_reg_V(dst, src);
 880 }
 881
 882 // 0
 883 static inline void gen_op_eval_bn(TCGv dst)
 884 {
 885     tcg_gen_movi_tl(dst, 0);
 886 }
 887
 888 // N
 889 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
 890 {
 891     gen_mov_reg_N(dst, src);
 892 }
 893
 894 // !Z
 895 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
 896 {
 897     gen_mov_reg_Z(dst, src);
 898     tcg_gen_xori_tl(dst, dst, 0x1);
 899 }
 900
 901 // !(Z | (N ^ V))
 902 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
 903 {
 904     gen_mov_reg_N(cpu_tmp0, src);
 905     gen_mov_reg_V(dst, src);
 906     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 907     gen_mov_reg_Z(cpu_tmp0, src);
 908     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 909     tcg_gen_xori_tl(dst, dst, 0x1);
 910 }
 911
 912 // !(N ^ V)
 913 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
 914 {
 915     gen_mov_reg_V(cpu_tmp0, src);
 916     gen_mov_reg_N(dst, src);
 917     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 918     tcg_gen_xori_tl(dst, dst, 0x1);
 919 }
 920
 921 // !(C | Z)
 922 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
 923 {
 924     gen_mov_reg_Z(cpu_tmp0, src);
 925     gen_mov_reg_C(dst, src);
 926     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 927     tcg_gen_xori_tl(dst, dst, 0x1);
 928 }
 929
 930 // !C
 931 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
 932 {
 933     gen_mov_reg_C(dst, src);
 934     tcg_gen_xori_tl(dst, dst, 0x1);
 935 }
 936
 937 // !N
 938 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
 939 {
 940     gen_mov_reg_N(dst, src);
 941     tcg_gen_xori_tl(dst, dst, 0x1);
 942 }
 943
 944 // !V
 945 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
 946 {
 947     gen_mov_reg_V(dst, src);
 948     tcg_gen_xori_tl(dst, dst, 0x1);
 949 }
 950
 951 /*
 952   FPSR bit field FCC1 | FCC0:
 953    0 =
 954    1 <
 955    2 >
 956    3 unordered
 957 */
 958 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
 959                                     unsigned int fcc_offset)
 960 {
 961     tcg_gen_extu_i32_tl(reg, src);
 962     tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
 963     tcg_gen_andi_tl(reg, reg, 0x1);
 964 }
 965
 966 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
 967                                     unsigned int fcc_offset)
 968 {
 969     tcg_gen_extu_i32_tl(reg, src);
 970     tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
 971     tcg_gen_andi_tl(reg, reg, 0x1);
 972 }
 973
 974 // !0: FCC0 | FCC1
 975 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
 976                                     unsigned int fcc_offset)
 977 {
 978     gen_mov_reg_FCC0(dst, src, fcc_offset);
 979     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
 980     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 981 }
 982
 983 // 1 or 2: FCC0 ^ FCC1
 984 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
 985                                     unsigned int fcc_offset)
 986 {
 987     gen_mov_reg_FCC0(dst, src, fcc_offset);
 988     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
 989     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 990 }
 991
 992 // 1 or 3: FCC0
 993 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
 994                                     unsigned int fcc_offset)
 995 {
 996     gen_mov_reg_FCC0(dst, src, fcc_offset);
 997 }
 998
 999 // 1: FCC0 & !FCC1
1000 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1001                                     unsigned int fcc_offset)
1002 {
1003     gen_mov_reg_FCC0(dst, src, fcc_offset);
1004     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1005     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1006     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1007 }
1008
1009 // 2 or 3: FCC1
1010 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1011                                     unsigned int fcc_offset)
1012 {
1013     gen_mov_reg_FCC1(dst, src, fcc_offset);
1014 }
1015
1016 // 2: !FCC0 & FCC1
1017 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1018                                     unsigned int fcc_offset)
1019 {
1020     gen_mov_reg_FCC0(dst, src, fcc_offset);
1021     tcg_gen_xori_tl(dst, dst, 0x1);
1022     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1023     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1024 }
1025
1026 // 3: FCC0 & FCC1
1027 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1028                                     unsigned int fcc_offset)
1029 {
1030     gen_mov_reg_FCC0(dst, src, fcc_offset);
1031     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1032     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1033 }
1034
1035 // 0: !(FCC0 | FCC1)
1036 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1037                                     unsigned int fcc_offset)
1038 {
1039     gen_mov_reg_FCC0(dst, src, fcc_offset);
1040     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1041     tcg_gen_or_tl(dst, dst, cpu_tmp0);
1042     tcg_gen_xori_tl(dst, dst, 0x1);
1043 }
1044
1045 // 0 or 3: !(FCC0 ^ FCC1)
1046 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1047                                     unsigned int fcc_offset)
1048 {
1049     gen_mov_reg_FCC0(dst, src, fcc_offset);
1050     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1051     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1052     tcg_gen_xori_tl(dst, dst, 0x1);
1053 }
1054
1055 // 0 or 2: !FCC0
1056 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1057                                     unsigned int fcc_offset)
1058 {
1059     gen_mov_reg_FCC0(dst, src, fcc_offset);
1060     tcg_gen_xori_tl(dst, dst, 0x1);
1061 }
1062
1063 // !1: !(FCC0 & !FCC1)
1064 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1065                                     unsigned int fcc_offset)
1066 {
1067     gen_mov_reg_FCC0(dst, src, fcc_offset);
1068     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1069     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1070     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1071     tcg_gen_xori_tl(dst, dst, 0x1);
1072 }
1073
1074 // 0 or 1: !FCC1
1075 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1076                                     unsigned int fcc_offset)
1077 {
1078     gen_mov_reg_FCC1(dst, src, fcc_offset);
1079     tcg_gen_xori_tl(dst, dst, 0x1);
1080 }
1081
1082 // !2: !(!FCC0 & FCC1)
1083 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1084                                     unsigned int fcc_offset)
1085 {
1086     gen_mov_reg_FCC0(dst, src, fcc_offset);
1087     tcg_gen_xori_tl(dst, dst, 0x1);
1088     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1089     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1090     tcg_gen_xori_tl(dst, dst, 0x1);
1091 }
1092
1093 // !3: !(FCC0 & FCC1)
1094 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1095                                     unsigned int fcc_offset)
1096 {
1097     gen_mov_reg_FCC0(dst, src, fcc_offset);
1098     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1099     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1100     tcg_gen_xori_tl(dst, dst, 0x1);
1101 }
1102
1103 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1104                                target_ulong pc2, TCGv r_cond)
1105 {
1106     int l1;
1107
1108     l1 = gen_new_label();
1109
1110     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1111
1112     gen_goto_tb(dc, 0, pc1, pc1 + 4);
1113
1114     gen_set_label(l1);
1115     gen_goto_tb(dc, 1, pc2, pc2 + 4);
1116 }
1117
1118 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1119                                 target_ulong pc2, TCGv r_cond)
1120 {
1121     int l1;
1122
1123     l1 = gen_new_label();
1124
1125     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1126
1127     gen_goto_tb(dc, 0, pc2, pc1);
1128
1129     gen_set_label(l1);
1130     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1131 }
1132
1133 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1134                                       TCGv r_cond)
1135 {
1136     int l1, l2;
1137
1138     l1 = gen_new_label();
1139     l2 = gen_new_label();
1140
1141     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1142
1143     tcg_gen_movi_tl(cpu_npc, npc1);
1144     tcg_gen_br(l2);
1145
1146     gen_set_label(l1);
1147     tcg_gen_movi_tl(cpu_npc, npc2);
1148     gen_set_label(l2);
1149 }
1150
1151 /* call this function before using the condition register as it may
1152    have been set for a jump */
1153 static inline void flush_cond(DisasContext *dc, TCGv cond)
1154 {
1155     if (dc->npc == JUMP_PC) {
1156         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1157         dc->npc = DYNAMIC_PC;
1158     }
1159 }
1160
1161 static inline void save_npc(DisasContext *dc, TCGv cond)
1162 {
1163     if (dc->npc == JUMP_PC) {
1164         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1165         dc->npc = DYNAMIC_PC;
1166     } else if (dc->npc != DYNAMIC_PC) {
1167         tcg_gen_movi_tl(cpu_npc, dc->npc);
1168     }
1169 }
1170
1171 static inline void save_state(DisasContext *dc, TCGv cond)
1172 {
1173     tcg_gen_movi_tl(cpu_pc, dc->pc);
1174     save_npc(dc, cond);
1175 }
1176
1177 static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1178 {
1179     if (dc->npc == JUMP_PC) {
1180         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1181         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1182         dc->pc = DYNAMIC_PC;
1183     } else if (dc->npc == DYNAMIC_PC) {
1184         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1185         dc->pc = DYNAMIC_PC;
1186     } else {
1187         dc->pc = dc->npc;
1188     }
1189 }
1190
1191 static inline void gen_op_next_insn(void)
1192 {
1193     tcg_gen_mov_tl(cpu_pc, cpu_npc);
1194     tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1195 }
1196
1197 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1198 {
1199     TCGv r_src;
1200
1201 #ifdef TARGET_SPARC64
1202     if (cc)
1203         r_src = cpu_xcc;
1204     else
1205         r_src = cpu_psr;
1206 #else
1207     r_src = cpu_psr;
1208 #endif
1209     switch (cond) {
1210     case 0x0:
1211         gen_op_eval_bn(r_dst);
1212         break;
1213     case 0x1:
1214         gen_op_eval_be(r_dst, r_src);
1215         break;
1216     case 0x2:
1217         gen_op_eval_ble(r_dst, r_src);
1218         break;
1219     case 0x3:
1220         gen_op_eval_bl(r_dst, r_src);
1221         break;
1222     case 0x4:
1223         gen_op_eval_bleu(r_dst, r_src);
1224         break;
1225     case 0x5:
1226         gen_op_eval_bcs(r_dst, r_src);
1227         break;
1228     case 0x6:
1229         gen_op_eval_bneg(r_dst, r_src);
1230         break;
1231     case 0x7:
1232         gen_op_eval_bvs(r_dst, r_src);
1233         break;
1234     case 0x8:
1235         gen_op_eval_ba(r_dst);
1236         break;
1237     case 0x9:
1238         gen_op_eval_bne(r_dst, r_src);
1239         break;
1240     case 0xa:
1241         gen_op_eval_bg(r_dst, r_src);
1242         break;
1243     case 0xb:
1244         gen_op_eval_bge(r_dst, r_src);
1245         break;
1246     case 0xc:
1247         gen_op_eval_bgu(r_dst, r_src);
1248         break;
1249     case 0xd:
1250         gen_op_eval_bcc(r_dst, r_src);
1251         break;
1252     case 0xe:
1253         gen_op_eval_bpos(r_dst, r_src);
1254         break;
1255     case 0xf:
1256         gen_op_eval_bvc(r_dst, r_src);
1257         break;
1258     }
1259 }
1260
1261 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1262 {
1263     unsigned int offset;
1264
1265     switch (cc) {
1266     default:
1267     case 0x0:
1268         offset = 0;
1269         break;
1270     case 0x1:
1271         offset = 32 - 10;
1272         break;
1273     case 0x2:
1274         offset = 34 - 10;
1275         break;
1276     case 0x3:
1277         offset = 36 - 10;
1278         break;
1279     }
1280
1281     switch (cond) {
1282     case 0x0:
1283         gen_op_eval_bn(r_dst);
1284         break;
1285     case 0x1:
1286         gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1287         break;
1288     case 0x2:
1289         gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1290         break;
1291     case 0x3:
1292         gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1293         break;
1294     case 0x4:
1295         gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1296         break;
1297     case 0x5:
1298         gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1299         break;
1300     case 0x6:
1301         gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1302         break;
1303     case 0x7:
1304         gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1305         break;
1306     case 0x8:
1307         gen_op_eval_ba(r_dst);
1308         break;
1309     case 0x9:
1310         gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1311         break;
1312     case 0xa:
1313         gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1314         break;
1315     case 0xb:
1316         gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1317         break;
1318     case 0xc:
1319         gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1320         break;
1321     case 0xd:
1322         gen_op_eval_fble(r_dst, cpu_fsr, offset);
1323         break;
1324     case 0xe:
1325         gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1326         break;
1327     case 0xf:
1328         gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1329         break;
1330     }
1331 }
1332
1333 #ifdef TARGET_SPARC64
1334 // Inverted logic
1335 static const int gen_tcg_cond_reg[8] = {
1336     -1,
1337     TCG_COND_NE,
1338     TCG_COND_GT,
1339     TCG_COND_GE,
1340     -1,
1341     TCG_COND_EQ,
1342     TCG_COND_LE,
1343     TCG_COND_LT,
1344 };
1345
1346 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1347 {
1348     int l1;
1349
1350     l1 = gen_new_label();
1351     tcg_gen_movi_tl(r_dst, 0);
1352     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1353     tcg_gen_movi_tl(r_dst, 1);
1354     gen_set_label(l1);
1355 }
1356 #endif
1357
1358 /* XXX: potentially incorrect if dynamic npc */
1359 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1360                       TCGv r_cond)
1361 {
1362     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1363     target_ulong target = dc->pc + offset;
1364
1365     if (cond == 0x0) {
1366         /* unconditional not taken */
1367         if (a) {
1368             dc->pc = dc->npc + 4;
1369             dc->npc = dc->pc + 4;
1370         } else {
1371             dc->pc = dc->npc;
1372             dc->npc = dc->pc + 4;
1373         }
1374     } else if (cond == 0x8) {
1375         /* unconditional taken */
1376         if (a) {
1377             dc->pc = target;
1378             dc->npc = dc->pc + 4;
1379         } else {
1380             dc->pc = dc->npc;
1381             dc->npc = target;
1382         }
1383     } else {
1384         flush_cond(dc, r_cond);
1385         gen_cond(r_cond, cc, cond);
1386         if (a) {
1387             gen_branch_a(dc, target, dc->npc, r_cond);
1388             dc->is_br = 1;
1389         } else {
1390             dc->pc = dc->npc;
1391             dc->jump_pc[0] = target;
1392             dc->jump_pc[1] = dc->npc + 4;
1393             dc->npc = JUMP_PC;
1394         }
1395     }
1396 }
1397
1398 /* XXX: potentially incorrect if dynamic npc */
1399 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1400                       TCGv r_cond)
1401 {
1402     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1403     target_ulong target = dc->pc + offset;
1404
1405     if (cond == 0x0) {
1406         /* unconditional not taken */
1407         if (a) {
1408             dc->pc = dc->npc + 4;
1409             dc->npc = dc->pc + 4;
1410         } else {
1411             dc->pc = dc->npc;
1412             dc->npc = dc->pc + 4;
1413         }
1414     } else if (cond == 0x8) {
1415         /* unconditional taken */
1416         if (a) {
1417             dc->pc = target;
1418             dc->npc = dc->pc + 4;
1419         } else {
1420             dc->pc = dc->npc;
1421             dc->npc = target;
1422         }
1423     } else {
1424         flush_cond(dc, r_cond);
1425         gen_fcond(r_cond, cc, cond);
1426         if (a) {
1427             gen_branch_a(dc, target, dc->npc, r_cond);
1428             dc->is_br = 1;
1429         } else {
1430             dc->pc = dc->npc;
1431             dc->jump_pc[0] = target;
1432             dc->jump_pc[1] = dc->npc + 4;
1433             dc->npc = JUMP_PC;
1434         }
1435     }
1436 }
1437
1438 #ifdef TARGET_SPARC64
1439 /* XXX: potentially incorrect if dynamic npc */
1440 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1441                           TCGv r_cond, TCGv r_reg)
1442 {
1443     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1444     target_ulong target = dc->pc + offset;
1445
1446     flush_cond(dc, r_cond);
1447     gen_cond_reg(r_cond, cond, r_reg);
1448     if (a) {
1449         gen_branch_a(dc, target, dc->npc, r_cond);
1450         dc->is_br = 1;
1451     } else {
1452         dc->pc = dc->npc;
1453         dc->jump_pc[0] = target;
1454         dc->jump_pc[1] = dc->npc + 4;
1455         dc->npc = JUMP_PC;
1456     }
1457 }
1458
1459 static GenOpFunc * const gen_fcmps[4] = {
1460     helper_fcmps,
1461     helper_fcmps_fcc1,
1462     helper_fcmps_fcc2,
1463     helper_fcmps_fcc3,
1464 };
1465
1466 static GenOpFunc * const gen_fcmpd[4] = {
1467     helper_fcmpd,
1468     helper_fcmpd_fcc1,
1469     helper_fcmpd_fcc2,
1470     helper_fcmpd_fcc3,
1471 };
1472
1473 static GenOpFunc * const gen_fcmpq[4] = {
1474     helper_fcmpq,
1475     helper_fcmpq_fcc1,
1476     helper_fcmpq_fcc2,
1477     helper_fcmpq_fcc3,
1478 };
1479
1480 static GenOpFunc * const gen_fcmpes[4] = {
1481     helper_fcmpes,
1482     helper_fcmpes_fcc1,
1483     helper_fcmpes_fcc2,
1484     helper_fcmpes_fcc3,
1485 };
1486
1487 static GenOpFunc * const gen_fcmped[4] = {
1488     helper_fcmped,
1489     helper_fcmped_fcc1,
1490     helper_fcmped_fcc2,
1491     helper_fcmped_fcc3,
1492 };
1493
1494 static GenOpFunc * const gen_fcmpeq[4] = {
1495     helper_fcmpeq,
1496     helper_fcmpeq_fcc1,
1497     helper_fcmpeq_fcc2,
1498     helper_fcmpeq_fcc3,
1499 };
1500
1501 static inline void gen_op_fcmps(int fccno)
1502 {
1503     tcg_gen_helper_0_0(gen_fcmps[fccno]);
1504 }
1505
1506 static inline void gen_op_fcmpd(int fccno)
1507 {
1508     tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1509 }
1510
1511 static inline void gen_op_fcmpq(int fccno)
1512 {
1513     tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1514 }
1515
1516 static inline void gen_op_fcmpes(int fccno)
1517 {
1518     tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1519 }
1520
1521 static inline void gen_op_fcmped(int fccno)
1522 {
1523     tcg_gen_helper_0_0(gen_fcmped[fccno]);
1524 }
1525
1526 static inline void gen_op_fcmpeq(int fccno)
1527 {
1528     tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1529 }
1530
1531 #else
1532
1533 static inline void gen_op_fcmps(int fccno)
1534 {
1535     tcg_gen_helper_0_0(helper_fcmps);
1536 }
1537
1538 static inline void gen_op_fcmpd(int fccno)
1539 {
1540     tcg_gen_helper_0_0(helper_fcmpd);
1541 }
1542
1543 static inline void gen_op_fcmpq(int fccno)
1544 {
1545     tcg_gen_helper_0_0(helper_fcmpq);
1546 }
1547
1548 static inline void gen_op_fcmpes(int fccno)
1549 {
1550     tcg_gen_helper_0_0(helper_fcmpes);
1551 }
1552
1553 static inline void gen_op_fcmped(int fccno)
1554 {
1555     tcg_gen_helper_0_0(helper_fcmped);
1556 }
1557
1558 static inline void gen_op_fcmpeq(int fccno)
1559 {
1560     tcg_gen_helper_0_0(helper_fcmpeq);
1561 }
1562 #endif
1563
1564 static inline void gen_op_fpexception_im(int fsr_flags)
1565 {
1566     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1567     tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1568     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
1569 }
1570
1571 static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1572 {
1573 #if !defined(CONFIG_USER_ONLY)
1574     if (!dc->fpu_enabled) {
1575         save_state(dc, r_cond);
1576         tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
1577         dc->is_br = 1;
1578         return 1;
1579     }
1580 #endif
1581     return 0;
1582 }
1583
1584 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1585 {
1586     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1587 }
1588
1589 static inline void gen_clear_float_exceptions(void)
1590 {
1591     tcg_gen_helper_0_0(helper_clear_float_exceptions);
1592 }
1593
1594 /* asi moves */
1595 #ifdef TARGET_SPARC64
1596 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1597 {
1598     int asi, offset;
1599     TCGv r_asi;
1600
1601     if (IS_IMM) {
1602         r_asi = tcg_temp_new(TCG_TYPE_I32);
1603         offset = GET_FIELD(insn, 25, 31);
1604         tcg_gen_addi_tl(r_addr, r_addr, offset);
1605         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1606     } else {
1607         asi = GET_FIELD(insn, 19, 26);
1608         r_asi = tcg_const_i32(asi);
1609     }
1610     return r_asi;
1611 }
1612
1613 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1614                               int sign)
1615 {
1616     TCGv r_asi;
1617
1618     r_asi = gen_get_asi(insn, addr);
1619     tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi,
1620                        tcg_const_i32(size), tcg_const_i32(sign));
1621 }
1622
1623 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1624 {
1625     TCGv r_asi;
1626
1627     r_asi = gen_get_asi(insn, addr);
1628     tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, tcg_const_i32(size));
1629 }
1630
1631 static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1632 {
1633     TCGv r_asi;
1634
1635     r_asi = gen_get_asi(insn, addr);
1636     tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, tcg_const_i32(size),
1637                        tcg_const_i32(rd));
1638 }
1639
1640 static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1641 {
1642     TCGv r_asi;
1643
1644     r_asi = gen_get_asi(insn, addr);
1645     tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, tcg_const_i32(size),
1646                        tcg_const_i32(rd));
1647 }
1648
1649 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1650 {
1651     TCGv r_asi;
1652
1653     r_asi = gen_get_asi(insn, addr);
1654     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi,
1655                        tcg_const_i32(4), tcg_const_i32(0));
1656     tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi,
1657                        tcg_const_i32(4));
1658     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1659 }
1660
1661 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1662 {
1663     TCGv r_asi;
1664
1665     r_asi = gen_get_asi(insn, addr);
1666     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi,
1667                        tcg_const_i32(8), tcg_const_i32(0));
1668     tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1669     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1670     tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1671 }
1672
1673 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1674 {
1675     TCGv r_temp, r_asi;
1676
1677     r_temp = tcg_temp_new(TCG_TYPE_TL);
1678     gen_movl_reg_TN(rd + 1, r_temp);
1679     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1680                        r_temp);
1681     r_asi = gen_get_asi(insn, addr);
1682     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi,
1683                        tcg_const_i32(8));
1684 }
1685
1686 static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1687                                int rd)
1688 {
1689     TCGv r_val1, r_asi;
1690
1691     r_val1 = tcg_temp_new(TCG_TYPE_TL);
1692     gen_movl_reg_TN(rd, r_val1);
1693     r_asi = gen_get_asi(insn, addr);
1694     tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1695 }
1696
1697 static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1698                                 int rd)
1699 {
1700     TCGv r_asi;
1701
1702     gen_movl_reg_TN(rd, cpu_tmp64);
1703     r_asi = gen_get_asi(insn, addr);
1704     tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1705 }
1706
1707 #elif !defined(CONFIG_USER_ONLY)
1708
1709 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1710                               int sign)
1711 {
1712     int asi;
1713
1714     asi = GET_FIELD(insn, 19, 26);
1715     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1716                        tcg_const_i32(size), tcg_const_i32(sign));
1717     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1718 }
1719
1720 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1721 {
1722     int asi;
1723
1724     tcg_gen_extu_tl_i64(cpu_tmp64, src);
1725     asi = GET_FIELD(insn, 19, 26);
1726     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1727                        tcg_const_i32(size));
1728 }
1729
1730 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1731 {
1732     int asi;
1733
1734     asi = GET_FIELD(insn, 19, 26);
1735     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1736                        tcg_const_i32(4), tcg_const_i32(0));
1737     tcg_gen_helper_0_4(helper_st_asi, addr, dst, tcg_const_i32(asi),
1738                        tcg_const_i32(4));
1739     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1740 }
1741
1742 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1743 {
1744     int asi;
1745
1746     asi = GET_FIELD(insn, 19, 26);
1747     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1748                        tcg_const_i32(8), tcg_const_i32(0));
1749     tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1750     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1751     tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1752 }
1753
1754 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1755 {
1756     int asi;
1757     TCGv r_temp;
1758
1759     r_temp = tcg_temp_new(TCG_TYPE_TL);
1760     gen_movl_reg_TN(rd + 1, r_temp);
1761     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1762     asi = GET_FIELD(insn, 19, 26);
1763     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1764                        tcg_const_i32(8));
1765 }
1766 #endif
1767
1768 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1769 static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1770 {
1771     int asi;
1772
1773     gen_ld_asi(dst, addr, insn, 1, 0);
1774
1775     asi = GET_FIELD(insn, 19, 26);
1776     tcg_gen_helper_0_4(helper_st_asi, addr, tcg_const_i64(0xffULL),
1777                        tcg_const_i32(asi), tcg_const_i32(1));
1778 }
1779 #endif
1780
1781 static inline TCGv get_src1(unsigned int insn, TCGv def)
1782 {
1783     TCGv r_rs1 = def;
1784     unsigned int rs1;
1785
1786     rs1 = GET_FIELD(insn, 13, 17);
1787     if (rs1 == 0)
1788         //r_rs1 = tcg_const_tl(0);
1789         tcg_gen_movi_tl(def, 0);
1790     else if (rs1 < 8)
1791         //r_rs1 = cpu_gregs[rs1];
1792         tcg_gen_mov_tl(def, cpu_gregs[rs1]);
1793     else
1794         tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1795     return r_rs1;
1796 }
1797
1798 static inline TCGv get_src2(unsigned int insn, TCGv def)
1799 {
1800     TCGv r_rs2 = def;
1801     unsigned int rs2;
1802
1803     if (IS_IMM) { /* immediate */
1804         rs2 = GET_FIELDs(insn, 19, 31);
1805         r_rs2 = tcg_const_tl((int)rs2);
1806     } else { /* register */
1807         rs2 = GET_FIELD(insn, 27, 31);
1808         if (rs2 == 0)
1809             r_rs2 = tcg_const_tl(0);
1810         else if (rs2 < 8)
1811             r_rs2 = cpu_gregs[rs2];
1812         else
1813             tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1814     }
1815     return r_rs2;
1816 }
1817
1818 #define CHECK_IU_FEATURE(dc, FEATURE)                      \
1819     if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1820         goto illegal_insn;
1821 #define CHECK_FPU_FEATURE(dc, FEATURE)                     \
1822     if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1823         goto nfpu_insn;
1824
1825 /* before an instruction, dc->pc must be static */
1826 static void disas_sparc_insn(DisasContext * dc)
1827 {
1828     unsigned int insn, opc, rs1, rs2, rd;
1829
1830     if (unlikely(loglevel & CPU_LOG_TB_OP))
1831         tcg_gen_debug_insn_start(dc->pc);
1832     insn = ldl_code(dc->pc);
1833     opc = GET_FIELD(insn, 0, 1);
1834
1835     rd = GET_FIELD(insn, 2, 6);
1836
1837     cpu_dst = cpu_T[0];
1838     cpu_src1 = cpu_T[0]; // const
1839     cpu_src2 = cpu_T[1]; // const
1840
1841     // loads and stores
1842     cpu_addr = cpu_T[0];
1843     cpu_val = cpu_T[1];
1844
1845     switch (opc) {
1846     case 0:                     /* branches/sethi */
1847         {
1848             unsigned int xop = GET_FIELD(insn, 7, 9);
1849             int32_t target;
1850             switch (xop) {
1851 #ifdef TARGET_SPARC64
1852             case 0x1:           /* V9 BPcc */
1853                 {
1854                     int cc;
1855
1856                     target = GET_FIELD_SP(insn, 0, 18);
1857                     target = sign_extend(target, 18);
1858                     target <<= 2;
1859                     cc = GET_FIELD_SP(insn, 20, 21);
1860                     if (cc == 0)
1861                         do_branch(dc, target, insn, 0, cpu_cond);
1862                     else if (cc == 2)
1863                         do_branch(dc, target, insn, 1, cpu_cond);
1864                     else
1865                         goto illegal_insn;
1866                     goto jmp_insn;
1867                 }
1868             case 0x3:           /* V9 BPr */
1869                 {
1870                     target = GET_FIELD_SP(insn, 0, 13) |
1871                         (GET_FIELD_SP(insn, 20, 21) << 14);
1872                     target = sign_extend(target, 16);
1873                     target <<= 2;
1874                     cpu_src1 = get_src1(insn, cpu_src1);
1875                     do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1876                     goto jmp_insn;
1877                 }
1878             case 0x5:           /* V9 FBPcc */
1879                 {
1880                     int cc = GET_FIELD_SP(insn, 20, 21);
1881                     if (gen_trap_ifnofpu(dc, cpu_cond))
1882                         goto jmp_insn;
1883                     target = GET_FIELD_SP(insn, 0, 18);
1884                     target = sign_extend(target, 19);
1885                     target <<= 2;
1886                     do_fbranch(dc, target, insn, cc, cpu_cond);
1887                     goto jmp_insn;
1888                 }
1889 #else
1890             case 0x7:           /* CBN+x */
1891                 {
1892                     goto ncp_insn;
1893                 }
1894 #endif
1895             case 0x2:           /* BN+x */
1896                 {
1897                     target = GET_FIELD(insn, 10, 31);
1898                     target = sign_extend(target, 22);
1899                     target <<= 2;
1900                     do_branch(dc, target, insn, 0, cpu_cond);
1901                     goto jmp_insn;
1902                 }
1903             case 0x6:           /* FBN+x */
1904                 {
1905                     if (gen_trap_ifnofpu(dc, cpu_cond))
1906                         goto jmp_insn;
1907                     target = GET_FIELD(insn, 10, 31);
1908                     target = sign_extend(target, 22);
1909                     target <<= 2;
1910                     do_fbranch(dc, target, insn, 0, cpu_cond);
1911                     goto jmp_insn;
1912                 }
1913             case 0x4:           /* SETHI */
1914                 if (rd) { // nop
1915                     uint32_t value = GET_FIELD(insn, 10, 31);
1916                     gen_movl_TN_reg(rd, tcg_const_tl(value << 10));
1917                 }
1918                 break;
1919             case 0x0:           /* UNIMPL */
1920             default:
1921                 goto illegal_insn;
1922             }
1923             break;
1924         }
1925         break;
1926     case 1:
1927         /*CALL*/ {
1928             target_long target = GET_FIELDs(insn, 2, 31) << 2;
1929
1930             gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
1931             target += dc->pc;
1932             gen_mov_pc_npc(dc, cpu_cond);
1933             dc->npc = target;
1934         }
1935         goto jmp_insn;
1936     case 2:                     /* FPU & Logical Operations */
1937         {
1938             unsigned int xop = GET_FIELD(insn, 7, 12);
1939             if (xop == 0x3a) {  /* generate trap */
1940                 int cond;
1941
1942                 cpu_src1 = get_src1(insn, cpu_src1);
1943                 if (IS_IMM) {
1944                     rs2 = GET_FIELD(insn, 25, 31);
1945                     tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
1946                 } else {
1947                     rs2 = GET_FIELD(insn, 27, 31);
1948                     if (rs2 != 0) {
1949                         gen_movl_reg_TN(rs2, cpu_src2);
1950                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
1951                     } else
1952                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
1953                 }
1954                 cond = GET_FIELD(insn, 3, 6);
1955                 if (cond == 0x8) {
1956                     save_state(dc, cpu_cond);
1957                     tcg_gen_helper_0_1(helper_trap, cpu_dst);
1958                 } else if (cond != 0) {
1959                     TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
1960 #ifdef TARGET_SPARC64
1961                     /* V9 icc/xcc */
1962                     int cc = GET_FIELD_SP(insn, 11, 12);
1963
1964                     save_state(dc, cpu_cond);
1965                     if (cc == 0)
1966                         gen_cond(r_cond, 0, cond);
1967                     else if (cc == 2)
1968                         gen_cond(r_cond, 1, cond);
1969                     else
1970                         goto illegal_insn;
1971 #else
1972                     save_state(dc, cpu_cond);
1973                     gen_cond(r_cond, 0, cond);
1974 #endif
1975                     tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
1976                 }
1977                 gen_op_next_insn();
1978                 tcg_gen_exit_tb(0);
1979                 dc->is_br = 1;
1980                 goto jmp_insn;
1981             } else if (xop == 0x28) {
1982                 rs1 = GET_FIELD(insn, 13, 17);
1983                 switch(rs1) {
1984                 case 0: /* rdy */
1985 #ifndef TARGET_SPARC64
1986                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1987                                        manual, rdy on the microSPARC
1988                                        II */
1989                 case 0x0f:          /* stbar in the SPARCv8 manual,
1990                                        rdy on the microSPARC II */
1991                 case 0x10 ... 0x1f: /* implementation-dependent in the
1992                                        SPARCv8 manual, rdy on the
1993                                        microSPARC II */
1994 #endif
1995                     tcg_gen_ld_tl(cpu_dst, cpu_env,
1996                                   offsetof(CPUSPARCState, y));
1997                     gen_movl_TN_reg(rd, cpu_dst);
1998                     break;
1999 #ifdef TARGET_SPARC64
2000                 case 0x2: /* V9 rdccr */
2001                     tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2002                     gen_movl_TN_reg(rd, cpu_dst);
2003                     break;
2004                 case 0x3: /* V9 rdasi */
2005                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2006                                    offsetof(CPUSPARCState, asi));
2007                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2008                     gen_movl_TN_reg(rd, cpu_dst);
2009                     break;
2010                 case 0x4: /* V9 rdtick */
2011                     {
2012                         TCGv r_tickptr;
2013
2014                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2015                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2016                                        offsetof(CPUState, tick));
2017                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2018                                            r_tickptr);
2019                         gen_movl_TN_reg(rd, cpu_dst);
2020                     }
2021                     break;
2022                 case 0x5: /* V9 rdpc */
2023                     gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
2024                     break;
2025                 case 0x6: /* V9 rdfprs */
2026                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2027                                    offsetof(CPUSPARCState, fprs));
2028                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2029                     gen_movl_TN_reg(rd, cpu_dst);
2030                     break;
2031                 case 0xf: /* V9 membar */
2032                     break; /* no effect */
2033                 case 0x13: /* Graphics Status */
2034                     if (gen_trap_ifnofpu(dc, cpu_cond))
2035                         goto jmp_insn;
2036                     tcg_gen_ld_tl(cpu_dst, cpu_env,
2037                                   offsetof(CPUSPARCState, gsr));
2038                     gen_movl_TN_reg(rd, cpu_dst);
2039                     break;
2040                 case 0x17: /* Tick compare */
2041                     tcg_gen_ld_tl(cpu_dst, cpu_env,
2042                                   offsetof(CPUSPARCState, tick_cmpr));
2043                     gen_movl_TN_reg(rd, cpu_dst);
2044                     break;
2045                 case 0x18: /* System tick */
2046                     {
2047                         TCGv r_tickptr;
2048
2049                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2050                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2051                                        offsetof(CPUState, stick));
2052                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2053                                            r_tickptr);
2054                         gen_movl_TN_reg(rd, cpu_dst);
2055                     }
2056                     break;
2057                 case 0x19: /* System tick compare */
2058                     tcg_gen_ld_tl(cpu_dst, cpu_env,
2059                                   offsetof(CPUSPARCState, stick_cmpr));
2060                     gen_movl_TN_reg(rd, cpu_dst);
2061                     break;
2062                 case 0x10: /* Performance Control */
2063                 case 0x11: /* Performance Instrumentation Counter */
2064                 case 0x12: /* Dispatch Control */
2065                 case 0x14: /* Softint set, WO */
2066                 case 0x15: /* Softint clear, WO */
2067                 case 0x16: /* Softint write */
2068 #endif
2069                 default:
2070                     goto illegal_insn;
2071                 }
2072 #if !defined(CONFIG_USER_ONLY)
2073             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2074 #ifndef TARGET_SPARC64
2075                 if (!supervisor(dc))
2076                     goto priv_insn;
2077                 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2078 #else
2079                 if (!hypervisor(dc))
2080                     goto priv_insn;
2081                 rs1 = GET_FIELD(insn, 13, 17);
2082                 switch (rs1) {
2083                 case 0: // hpstate
2084                     // gen_op_rdhpstate();
2085                     break;
2086                 case 1: // htstate
2087                     // gen_op_rdhtstate();
2088                     break;
2089                 case 3: // hintp
2090                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2091                                    offsetof(CPUSPARCState, hintp));
2092                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2093                     break;
2094                 case 5: // htba
2095                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2096                                    offsetof(CPUSPARCState, htba));
2097                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2098                     break;
2099                 case 6: // hver
2100                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2101                                    offsetof(CPUSPARCState, hver));
2102                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2103                     break;
2104                 case 31: // hstick_cmpr
2105                     tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2106                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
2107                                    offsetof(CPUSPARCState, hstick_cmpr));
2108                     break;
2109                 default:
2110                     goto illegal_insn;
2111                 }
2112 #endif
2113                 gen_movl_TN_reg(rd, cpu_dst);
2114                 break;
2115             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2116                 if (!supervisor(dc))
2117                     goto priv_insn;
2118 #ifdef TARGET_SPARC64
2119                 rs1 = GET_FIELD(insn, 13, 17);
2120                 switch (rs1) {
2121                 case 0: // tpc
2122                     {
2123                         TCGv r_tsptr;
2124
2125                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2126                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2127                                        offsetof(CPUState, tsptr));
2128                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2129                                       offsetof(trap_state, tpc));
2130                     }
2131                     break;
2132                 case 1: // tnpc
2133                     {
2134                         TCGv r_tsptr;
2135
2136                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2137                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2138                                        offsetof(CPUState, tsptr));
2139                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2140                                       offsetof(trap_state, tnpc));
2141                     }
2142                     break;
2143                 case 2: // tstate
2144                     {
2145                         TCGv r_tsptr;
2146
2147                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2148                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2149                                        offsetof(CPUState, tsptr));
2150                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2151                                       offsetof(trap_state, tstate));
2152                     }
2153                     break;
2154                 case 3: // tt
2155                     {
2156                         TCGv r_tsptr;
2157
2158                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2159                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2160                                        offsetof(CPUState, tsptr));
2161                         tcg_gen_ld_i32(cpu_dst, r_tsptr,
2162                                        offsetof(trap_state, tt));
2163                     }
2164                     break;
2165                 case 4: // tick
2166                     {
2167                         TCGv r_tickptr;
2168
2169                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2170                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2171                                        offsetof(CPUState, tick));
2172                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2173                                            r_tickptr);
2174                         gen_movl_TN_reg(rd, cpu_dst);
2175                     }
2176                     break;
2177                 case 5: // tba
2178                     tcg_gen_ld_tl(cpu_dst, cpu_env,
2179                                   offsetof(CPUSPARCState, tbr));
2180                     break;
2181                 case 6: // pstate
2182                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2183                                    offsetof(CPUSPARCState, pstate));
2184                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2185                     break;
2186                 case 7: // tl
2187                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2188                                    offsetof(CPUSPARCState, tl));
2189                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2190                     break;
2191                 case 8: // pil
2192                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2193                                    offsetof(CPUSPARCState, psrpil));
2194                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2195                     break;
2196                 case 9: // cwp
2197                     tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
2198                     break;
2199                 case 10: // cansave
2200                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2201                                    offsetof(CPUSPARCState, cansave));
2202                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2203                     break;
2204                 case 11: // canrestore
2205                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2206                                    offsetof(CPUSPARCState, canrestore));
2207                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2208                     break;
2209                 case 12: // cleanwin
2210                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2211                                    offsetof(CPUSPARCState, cleanwin));
2212                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2213                     break;
2214                 case 13: // otherwin
2215                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2216                                    offsetof(CPUSPARCState, otherwin));
2217                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2218                     break;
2219                 case 14: // wstate
2220                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2221                                    offsetof(CPUSPARCState, wstate));
2222                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2223                     break;
2224                 case 16: // UA2005 gl
2225                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2226                                    offsetof(CPUSPARCState, gl));
2227                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2228                     break;
2229                 case 26: // UA2005 strand status
2230                     if (!hypervisor(dc))
2231                         goto priv_insn;
2232                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2233                                    offsetof(CPUSPARCState, ssr));
2234                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2235                     break;
2236                 case 31: // ver
2237                     tcg_gen_ld_tl(cpu_dst, cpu_env,
2238                                   offsetof(CPUSPARCState, version));
2239                     break;
2240                 case 15: // fq
2241                 default:
2242                     goto illegal_insn;
2243                 }
2244 #else
2245                 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2246                                offsetof(CPUSPARCState, wim));
2247                 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2248 #endif
2249                 gen_movl_TN_reg(rd, cpu_dst);
2250                 break;
2251             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2252 #ifdef TARGET_SPARC64
2253                 tcg_gen_helper_0_0(helper_flushw);
2254 #else
2255                 if (!supervisor(dc))
2256                     goto priv_insn;
2257                 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2258                 gen_movl_TN_reg(rd, cpu_dst);
2259 #endif
2260                 break;
2261 #endif
2262             } else if (xop == 0x34) {   /* FPU Operations */
2263                 if (gen_trap_ifnofpu(dc, cpu_cond))
2264                     goto jmp_insn;
2265                 gen_op_clear_ieee_excp_and_FTT();
2266                 rs1 = GET_FIELD(insn, 13, 17);
2267                 rs2 = GET_FIELD(insn, 27, 31);
2268                 xop = GET_FIELD(insn, 18, 26);
2269                 switch (xop) {
2270                     case 0x1: /* fmovs */
2271                         gen_op_load_fpr_FT0(rs2);
2272                         gen_op_store_FT0_fpr(rd);
2273                         break;
2274                     case 0x5: /* fnegs */
2275                         gen_op_load_fpr_FT1(rs2);
2276                         tcg_gen_helper_0_0(helper_fnegs);
2277                         gen_op_store_FT0_fpr(rd);
2278                         break;
2279                     case 0x9: /* fabss */
2280                         gen_op_load_fpr_FT1(rs2);
2281                         tcg_gen_helper_0_0(helper_fabss);
2282                         gen_op_store_FT0_fpr(rd);
2283                         break;
2284                     case 0x29: /* fsqrts */
2285                         CHECK_FPU_FEATURE(dc, FSQRT);
2286                         gen_op_load_fpr_FT1(rs2);
2287                         gen_clear_float_exceptions();
2288                         tcg_gen_helper_0_0(helper_fsqrts);
2289                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2290                         gen_op_store_FT0_fpr(rd);
2291                         break;
2292                     case 0x2a: /* fsqrtd */
2293                         CHECK_FPU_FEATURE(dc, FSQRT);
2294                         gen_op_load_fpr_DT1(DFPREG(rs2));
2295                         gen_clear_float_exceptions();
2296                         tcg_gen_helper_0_0(helper_fsqrtd);
2297                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2298                         gen_op_store_DT0_fpr(DFPREG(rd));
2299                         break;
2300                     case 0x2b: /* fsqrtq */
2301                         CHECK_FPU_FEATURE(dc, FLOAT128);
2302                         gen_op_load_fpr_QT1(QFPREG(rs2));
2303                         gen_clear_float_exceptions();
2304                         tcg_gen_helper_0_0(helper_fsqrtq);
2305                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2306                         gen_op_store_QT0_fpr(QFPREG(rd));
2307                         break;
2308                     case 0x41:
2309                         gen_op_load_fpr_FT0(rs1);
2310                         gen_op_load_fpr_FT1(rs2);
2311                         gen_clear_float_exceptions();
2312                         tcg_gen_helper_0_0(helper_fadds);
2313                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2314                         gen_op_store_FT0_fpr(rd);
2315                         break;
2316                     case 0x42:
2317                         gen_op_load_fpr_DT0(DFPREG(rs1));
2318                         gen_op_load_fpr_DT1(DFPREG(rs2));
2319                         gen_clear_float_exceptions();
2320                         tcg_gen_helper_0_0(helper_faddd);
2321                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2322                         gen_op_store_DT0_fpr(DFPREG(rd));
2323                         break;
2324                     case 0x43: /* faddq */
2325                         CHECK_FPU_FEATURE(dc, FLOAT128);
2326                         gen_op_load_fpr_QT0(QFPREG(rs1));
2327                         gen_op_load_fpr_QT1(QFPREG(rs2));
2328                         gen_clear_float_exceptions();
2329                         tcg_gen_helper_0_0(helper_faddq);
2330                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2331                         gen_op_store_QT0_fpr(QFPREG(rd));
2332                         break;
2333                     case 0x45:
2334                         gen_op_load_fpr_FT0(rs1);
2335                         gen_op_load_fpr_FT1(rs2);
2336                         gen_clear_float_exceptions();
2337                         tcg_gen_helper_0_0(helper_fsubs);
2338                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2339                         gen_op_store_FT0_fpr(rd);
2340                         break;
2341                     case 0x46:
2342                         gen_op_load_fpr_DT0(DFPREG(rs1));
2343                         gen_op_load_fpr_DT1(DFPREG(rs2));
2344                         gen_clear_float_exceptions();
2345                         tcg_gen_helper_0_0(helper_fsubd);
2346                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2347                         gen_op_store_DT0_fpr(DFPREG(rd));
2348                         break;
2349                     case 0x47: /* fsubq */
2350                         CHECK_FPU_FEATURE(dc, FLOAT128);
2351                         gen_op_load_fpr_QT0(QFPREG(rs1));
2352                         gen_op_load_fpr_QT1(QFPREG(rs2));
2353                         gen_clear_float_exceptions();
2354                         tcg_gen_helper_0_0(helper_fsubq);
2355                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2356                         gen_op_store_QT0_fpr(QFPREG(rd));
2357                         break;
2358                     case 0x49: /* fmuls */
2359                         CHECK_FPU_FEATURE(dc, FMUL);
2360                         gen_op_load_fpr_FT0(rs1);
2361                         gen_op_load_fpr_FT1(rs2);
2362                         gen_clear_float_exceptions();
2363                         tcg_gen_helper_0_0(helper_fmuls);
2364                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2365                         gen_op_store_FT0_fpr(rd);
2366                         break;
2367                     case 0x4a: /* fmuld */
2368                         CHECK_FPU_FEATURE(dc, FMUL);
2369                         gen_op_load_fpr_DT0(DFPREG(rs1));
2370                         gen_op_load_fpr_DT1(DFPREG(rs2));
2371                         gen_clear_float_exceptions();
2372                         tcg_gen_helper_0_0(helper_fmuld);
2373                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2374                         gen_op_store_DT0_fpr(DFPREG(rd));
2375                         break;
2376                     case 0x4b: /* fmulq */
2377                         CHECK_FPU_FEATURE(dc, FLOAT128);
2378                         CHECK_FPU_FEATURE(dc, FMUL);
2379                         gen_op_load_fpr_QT0(QFPREG(rs1));
2380                         gen_op_load_fpr_QT1(QFPREG(rs2));
2381                         gen_clear_float_exceptions();
2382                         tcg_gen_helper_0_0(helper_fmulq);
2383                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2384                         gen_op_store_QT0_fpr(QFPREG(rd));
2385                         break;
2386                     case 0x4d:
2387                         gen_op_load_fpr_FT0(rs1);
2388                         gen_op_load_fpr_FT1(rs2);
2389                         gen_clear_float_exceptions();
2390                         tcg_gen_helper_0_0(helper_fdivs);
2391                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2392                         gen_op_store_FT0_fpr(rd);
2393                         break;
2394                     case 0x4e:
2395                         gen_op_load_fpr_DT0(DFPREG(rs1));
2396                         gen_op_load_fpr_DT1(DFPREG(rs2));
2397                         gen_clear_float_exceptions();
2398                         tcg_gen_helper_0_0(helper_fdivd);
2399                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2400                         gen_op_store_DT0_fpr(DFPREG(rd));
2401                         break;
2402                     case 0x4f: /* fdivq */
2403                         CHECK_FPU_FEATURE(dc, FLOAT128);
2404                         gen_op_load_fpr_QT0(QFPREG(rs1));
2405                         gen_op_load_fpr_QT1(QFPREG(rs2));
2406                         gen_clear_float_exceptions();
2407                         tcg_gen_helper_0_0(helper_fdivq);
2408                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2409                         gen_op_store_QT0_fpr(QFPREG(rd));
2410                         break;
2411                     case 0x69:
2412                         gen_op_load_fpr_FT0(rs1);
2413                         gen_op_load_fpr_FT1(rs2);
2414                         gen_clear_float_exceptions();
2415                         tcg_gen_helper_0_0(helper_fsmuld);
2416                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2417                         gen_op_store_DT0_fpr(DFPREG(rd));
2418                         break;
2419                     case 0x6e: /* fdmulq */
2420                         CHECK_FPU_FEATURE(dc, FLOAT128);
2421                         gen_op_load_fpr_DT0(DFPREG(rs1));
2422                         gen_op_load_fpr_DT1(DFPREG(rs2));
2423                         gen_clear_float_exceptions();
2424                         tcg_gen_helper_0_0(helper_fdmulq);
2425                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2426                         gen_op_store_QT0_fpr(QFPREG(rd));
2427                         break;
2428                     case 0xc4:
2429                         gen_op_load_fpr_FT1(rs2);
2430                         gen_clear_float_exceptions();
2431                         tcg_gen_helper_0_0(helper_fitos);
2432                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2433                         gen_op_store_FT0_fpr(rd);
2434                         break;
2435                     case 0xc6:
2436                         gen_op_load_fpr_DT1(DFPREG(rs2));
2437                         gen_clear_float_exceptions();
2438                         tcg_gen_helper_0_0(helper_fdtos);
2439                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2440                         gen_op_store_FT0_fpr(rd);
2441                         break;
2442                     case 0xc7: /* fqtos */
2443                         CHECK_FPU_FEATURE(dc, FLOAT128);
2444                         gen_op_load_fpr_QT1(QFPREG(rs2));
2445                         gen_clear_float_exceptions();
2446                         tcg_gen_helper_0_0(helper_fqtos);
2447                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2448                         gen_op_store_FT0_fpr(rd);
2449                         break;
2450                     case 0xc8:
2451                         gen_op_load_fpr_FT1(rs2);
2452                         tcg_gen_helper_0_0(helper_fitod);
2453                         gen_op_store_DT0_fpr(DFPREG(rd));
2454                         break;
2455                     case 0xc9:
2456                         gen_op_load_fpr_FT1(rs2);
2457                         tcg_gen_helper_0_0(helper_fstod);
2458                         gen_op_store_DT0_fpr(DFPREG(rd));
2459                         break;
2460                     case 0xcb: /* fqtod */
2461                         CHECK_FPU_FEATURE(dc, FLOAT128);
2462                         gen_op_load_fpr_QT1(QFPREG(rs2));
2463                         gen_clear_float_exceptions();
2464                         tcg_gen_helper_0_0(helper_fqtod);
2465                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2466                         gen_op_store_DT0_fpr(DFPREG(rd));
2467                         break;
2468                     case 0xcc: /* fitoq */
2469                         CHECK_FPU_FEATURE(dc, FLOAT128);
2470                         gen_op_load_fpr_FT1(rs2);
2471                         tcg_gen_helper_0_0(helper_fitoq);
2472                         gen_op_store_QT0_fpr(QFPREG(rd));
2473                         break;
2474                     case 0xcd: /* fstoq */
2475                         CHECK_FPU_FEATURE(dc, FLOAT128);
2476                         gen_op_load_fpr_FT1(rs2);
2477                         tcg_gen_helper_0_0(helper_fstoq);
2478                         gen_op_store_QT0_fpr(QFPREG(rd));
2479                         break;
2480                     case 0xce: /* fdtoq */
2481                         CHECK_FPU_FEATURE(dc, FLOAT128);
2482                         gen_op_load_fpr_DT1(DFPREG(rs2));
2483                         tcg_gen_helper_0_0(helper_fdtoq);
2484                         gen_op_store_QT0_fpr(QFPREG(rd));
2485                         break;
2486                     case 0xd1:
2487                         gen_op_load_fpr_FT1(rs2);
2488                         gen_clear_float_exceptions();
2489                         tcg_gen_helper_0_0(helper_fstoi);
2490                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2491                         gen_op_store_FT0_fpr(rd);
2492                         break;
2493                     case 0xd2:
2494                         gen_op_load_fpr_DT1(DFPREG(rs2));
2495                         gen_clear_float_exceptions();
2496                         tcg_gen_helper_0_0(helper_fdtoi);
2497                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2498                         gen_op_store_FT0_fpr(rd);
2499                         break;
2500                     case 0xd3: /* fqtoi */
2501                         CHECK_FPU_FEATURE(dc, FLOAT128);
2502                         gen_op_load_fpr_QT1(QFPREG(rs2));
2503                         gen_clear_float_exceptions();
2504                         tcg_gen_helper_0_0(helper_fqtoi);
2505                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2506                         gen_op_store_FT0_fpr(rd);
2507                         break;
2508 #ifdef TARGET_SPARC64
2509                     case 0x2: /* V9 fmovd */
2510                         gen_op_load_fpr_DT0(DFPREG(rs2));
2511                         gen_op_store_DT0_fpr(DFPREG(rd));
2512                         break;
2513                     case 0x3: /* V9 fmovq */
2514                         CHECK_FPU_FEATURE(dc, FLOAT128);
2515                         gen_op_load_fpr_QT0(QFPREG(rs2));
2516                         gen_op_store_QT0_fpr(QFPREG(rd));
2517                         break;
2518                     case 0x6: /* V9 fnegd */
2519                         gen_op_load_fpr_DT1(DFPREG(rs2));
2520                         tcg_gen_helper_0_0(helper_fnegd);
2521                         gen_op_store_DT0_fpr(DFPREG(rd));
2522                         break;
2523                     case 0x7: /* V9 fnegq */
2524                         CHECK_FPU_FEATURE(dc, FLOAT128);
2525                         gen_op_load_fpr_QT1(QFPREG(rs2));
2526                         tcg_gen_helper_0_0(helper_fnegq);
2527                         gen_op_store_QT0_fpr(QFPREG(rd));
2528                         break;
2529                     case 0xa: /* V9 fabsd */
2530                         gen_op_load_fpr_DT1(DFPREG(rs2));
2531                         tcg_gen_helper_0_0(helper_fabsd);
2532                         gen_op_store_DT0_fpr(DFPREG(rd));
2533                         break;
2534                     case 0xb: /* V9 fabsq */
2535                         CHECK_FPU_FEATURE(dc, FLOAT128);
2536                         gen_op_load_fpr_QT1(QFPREG(rs2));
2537                         tcg_gen_helper_0_0(helper_fabsq);
2538                         gen_op_store_QT0_fpr(QFPREG(rd));
2539                         break;
2540                     case 0x81: /* V9 fstox */
2541                         gen_op_load_fpr_FT1(rs2);
2542                         gen_clear_float_exceptions();
2543                         tcg_gen_helper_0_0(helper_fstox);
2544                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2545                         gen_op_store_DT0_fpr(DFPREG(rd));
2546                         break;
2547                     case 0x82: /* V9 fdtox */
2548                         gen_op_load_fpr_DT1(DFPREG(rs2));
2549                         gen_clear_float_exceptions();
2550                         tcg_gen_helper_0_0(helper_fdtox);
2551                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2552                         gen_op_store_DT0_fpr(DFPREG(rd));
2553                         break;
2554                     case 0x83: /* V9 fqtox */
2555                         CHECK_FPU_FEATURE(dc, FLOAT128);
2556                         gen_op_load_fpr_QT1(QFPREG(rs2));
2557                         gen_clear_float_exceptions();
2558                         tcg_gen_helper_0_0(helper_fqtox);
2559                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2560                         gen_op_store_DT0_fpr(DFPREG(rd));
2561                         break;
2562                     case 0x84: /* V9 fxtos */
2563                         gen_op_load_fpr_DT1(DFPREG(rs2));
2564                         gen_clear_float_exceptions();
2565                         tcg_gen_helper_0_0(helper_fxtos);
2566                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2567                         gen_op_store_FT0_fpr(rd);
2568                         break;
2569                     case 0x88: /* V9 fxtod */
2570                         gen_op_load_fpr_DT1(DFPREG(rs2));
2571                         gen_clear_float_exceptions();
2572                         tcg_gen_helper_0_0(helper_fxtod);
2573                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2574                         gen_op_store_DT0_fpr(DFPREG(rd));
2575                         break;
2576                     case 0x8c: /* V9 fxtoq */
2577                         CHECK_FPU_FEATURE(dc, FLOAT128);
2578                         gen_op_load_fpr_DT1(DFPREG(rs2));
2579                         gen_clear_float_exceptions();
2580                         tcg_gen_helper_0_0(helper_fxtoq);
2581                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2582                         gen_op_store_QT0_fpr(QFPREG(rd));
2583                         break;
2584 #endif
2585                     default:
2586                         goto illegal_insn;
2587                 }
2588             } else if (xop == 0x35) {   /* FPU Operations */
2589 #ifdef TARGET_SPARC64
2590                 int cond;
2591 #endif
2592                 if (gen_trap_ifnofpu(dc, cpu_cond))
2593                     goto jmp_insn;
2594                 gen_op_clear_ieee_excp_and_FTT();
2595                 rs1 = GET_FIELD(insn, 13, 17);
2596                 rs2 = GET_FIELD(insn, 27, 31);
2597                 xop = GET_FIELD(insn, 18, 26);
2598 #ifdef TARGET_SPARC64
2599                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2600                     int l1;
2601
2602                     l1 = gen_new_label();
2603                     cond = GET_FIELD_SP(insn, 14, 17);
2604                     cpu_src1 = get_src1(insn, cpu_src1);
2605                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2606                                        0, l1);
2607                     gen_op_load_fpr_FT0(rs2);
2608                     gen_op_store_FT0_fpr(rd);
2609                     gen_set_label(l1);
2610                     break;
2611                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2612                     int l1;
2613
2614                     l1 = gen_new_label();
2615                     cond = GET_FIELD_SP(insn, 14, 17);
2616                     cpu_src1 = get_src1(insn, cpu_src1);
2617                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2618                                        0, l1);
2619                     gen_op_load_fpr_DT0(DFPREG(rs2));
2620                     gen_op_store_DT0_fpr(DFPREG(rd));
2621                     gen_set_label(l1);
2622                     break;
2623                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2624                     int l1;
2625
2626                     CHECK_FPU_FEATURE(dc, FLOAT128);
2627                     l1 = gen_new_label();
2628                     cond = GET_FIELD_SP(insn, 14, 17);
2629                     cpu_src1 = get_src1(insn, cpu_src1);
2630                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2631                                        0, l1);
2632                     gen_op_load_fpr_QT0(QFPREG(rs2));
2633                     gen_op_store_QT0_fpr(QFPREG(rd));
2634                     gen_set_label(l1);
2635                     break;
2636                 }
2637 #endif
2638                 switch (xop) {
2639 #ifdef TARGET_SPARC64
2640 #define FMOVCC(size_FDQ, fcc)                                           \
2641                     {                                                   \
2642                         TCGv r_cond;                                    \
2643                         int l1;                                         \
2644                                                                         \
2645                         l1 = gen_new_label();                           \
2646                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2647                         cond = GET_FIELD_SP(insn, 14, 17);              \
2648                         gen_fcond(r_cond, fcc, cond);                   \
2649                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2650                                            0, l1);                      \
2651                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2652                             (glue(size_FDQ, FPREG(rs2)));               \
2653                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2654                             (glue(size_FDQ, FPREG(rd)));                \
2655                         gen_set_label(l1);                              \
2656                     }
2657                     case 0x001: /* V9 fmovscc %fcc0 */
2658                         FMOVCC(F, 0);
2659                         break;
2660                     case 0x002: /* V9 fmovdcc %fcc0 */
2661                         FMOVCC(D, 0);
2662                         break;
2663                     case 0x003: /* V9 fmovqcc %fcc0 */
2664                         CHECK_FPU_FEATURE(dc, FLOAT128);
2665                         FMOVCC(Q, 0);
2666                         break;
2667                     case 0x041: /* V9 fmovscc %fcc1 */
2668                         FMOVCC(F, 1);
2669                         break;
2670                     case 0x042: /* V9 fmovdcc %fcc1 */
2671                         FMOVCC(D, 1);
2672                         break;
2673                     case 0x043: /* V9 fmovqcc %fcc1 */
2674                         CHECK_FPU_FEATURE(dc, FLOAT128);
2675                         FMOVCC(Q, 1);
2676                         break;
2677                     case 0x081: /* V9 fmovscc %fcc2 */
2678                         FMOVCC(F, 2);
2679                         break;
2680                     case 0x082: /* V9 fmovdcc %fcc2 */
2681                         FMOVCC(D, 2);
2682                         break;
2683                     case 0x083: /* V9 fmovqcc %fcc2 */
2684                         CHECK_FPU_FEATURE(dc, FLOAT128);
2685                         FMOVCC(Q, 2);
2686                         break;
2687                     case 0x0c1: /* V9 fmovscc %fcc3 */
2688                         FMOVCC(F, 3);
2689                         break;
2690                     case 0x0c2: /* V9 fmovdcc %fcc3 */
2691                         FMOVCC(D, 3);
2692                         break;
2693                     case 0x0c3: /* V9 fmovqcc %fcc3 */
2694                         CHECK_FPU_FEATURE(dc, FLOAT128);
2695                         FMOVCC(Q, 3);
2696                         break;
2697 #undef FMOVCC
2698 #define FMOVCC(size_FDQ, icc)                                           \
2699                     {                                                   \
2700                         TCGv r_cond;                                    \
2701                         int l1;                                         \
2702                                                                         \
2703                         l1 = gen_new_label();                           \
2704                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2705                         cond = GET_FIELD_SP(insn, 14, 17);              \
2706                         gen_cond(r_cond, icc, cond);                    \
2707                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2708                                            0, l1);                      \
2709                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2710                             (glue(size_FDQ, FPREG(rs2)));               \
2711                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2712                             (glue(size_FDQ, FPREG(rd)));                \
2713                         gen_set_label(l1);                              \
2714                     }
2715
2716                     case 0x101: /* V9 fmovscc %icc */
2717                         FMOVCC(F, 0);
2718                         break;
2719                     case 0x102: /* V9 fmovdcc %icc */
2720                         FMOVCC(D, 0);
2721                     case 0x103: /* V9 fmovqcc %icc */
2722                         CHECK_FPU_FEATURE(dc, FLOAT128);
2723                         FMOVCC(Q, 0);
2724                         break;
2725                     case 0x181: /* V9 fmovscc %xcc */
2726                         FMOVCC(F, 1);
2727                         break;
2728                     case 0x182: /* V9 fmovdcc %xcc */
2729                         FMOVCC(D, 1);
2730                         break;
2731                     case 0x183: /* V9 fmovqcc %xcc */
2732                         CHECK_FPU_FEATURE(dc, FLOAT128);
2733                         FMOVCC(Q, 1);
2734                         break;
2735 #undef FMOVCC
2736 #endif
2737                     case 0x51: /* fcmps, V9 %fcc */
2738                         gen_op_load_fpr_FT0(rs1);
2739                         gen_op_load_fpr_FT1(rs2);
2740                         gen_op_fcmps(rd & 3);
2741                         break;
2742                     case 0x52: /* fcmpd, V9 %fcc */
2743                         gen_op_load_fpr_DT0(DFPREG(rs1));
2744                         gen_op_load_fpr_DT1(DFPREG(rs2));
2745                         gen_op_fcmpd(rd & 3);
2746                         break;
2747                     case 0x53: /* fcmpq, V9 %fcc */
2748                         CHECK_FPU_FEATURE(dc, FLOAT128);
2749                         gen_op_load_fpr_QT0(QFPREG(rs1));
2750                         gen_op_load_fpr_QT1(QFPREG(rs2));
2751                         gen_op_fcmpq(rd & 3);
2752                         break;
2753                     case 0x55: /* fcmpes, V9 %fcc */
2754                         gen_op_load_fpr_FT0(rs1);
2755                         gen_op_load_fpr_FT1(rs2);
2756                         gen_op_fcmpes(rd & 3);
2757                         break;
2758                     case 0x56: /* fcmped, V9 %fcc */
2759                         gen_op_load_fpr_DT0(DFPREG(rs1));
2760                         gen_op_load_fpr_DT1(DFPREG(rs2));
2761                         gen_op_fcmped(rd & 3);
2762                         break;
2763                     case 0x57: /* fcmpeq, V9 %fcc */
2764                         CHECK_FPU_FEATURE(dc, FLOAT128);
2765                         gen_op_load_fpr_QT0(QFPREG(rs1));
2766                         gen_op_load_fpr_QT1(QFPREG(rs2));
2767                         gen_op_fcmpeq(rd & 3);
2768                         break;
2769                     default:
2770                         goto illegal_insn;
2771                 }
2772             } else if (xop == 0x2) {
2773                 // clr/mov shortcut
2774
2775                 rs1 = GET_FIELD(insn, 13, 17);
2776                 if (rs1 == 0) {
2777                     // or %g0, x, y -> mov T0, x; mov y, T0
2778                     if (IS_IMM) {       /* immediate */
2779                         rs2 = GET_FIELDs(insn, 19, 31);
2780                         gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
2781                     } else {            /* register */
2782                         rs2 = GET_FIELD(insn, 27, 31);
2783                         gen_movl_reg_TN(rs2, cpu_dst);
2784                         gen_movl_TN_reg(rd, cpu_dst);
2785                     }
2786                 } else {
2787                     cpu_src1 = get_src1(insn, cpu_src1);
2788                     if (IS_IMM) {       /* immediate */
2789                         rs2 = GET_FIELDs(insn, 19, 31);
2790                         tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2791                         gen_movl_TN_reg(rd, cpu_dst);
2792                     } else {            /* register */
2793                         // or x, %g0, y -> mov T1, x; mov y, T1
2794                         rs2 = GET_FIELD(insn, 27, 31);
2795                         if (rs2 != 0) {
2796                             gen_movl_reg_TN(rs2, cpu_src2);
2797                             tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2798                             gen_movl_TN_reg(rd, cpu_dst);
2799                         } else
2800                             gen_movl_TN_reg(rd, cpu_src1);
2801                     }
2802                 }
2803 #ifdef TARGET_SPARC64
2804             } else if (xop == 0x25) { /* sll, V9 sllx */
2805                 cpu_src1 = get_src1(insn, cpu_src1);
2806                 if (IS_IMM) {   /* immediate */
2807                     rs2 = GET_FIELDs(insn, 20, 31);
2808                     if (insn & (1 << 12)) {
2809                         tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2810                     } else {
2811                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2812                         tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2813                     }
2814                 } else {                /* register */
2815                     rs2 = GET_FIELD(insn, 27, 31);
2816                     gen_movl_reg_TN(rs2, cpu_src2);
2817                     if (insn & (1 << 12)) {
2818                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2819                         tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2820                     } else {
2821                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2822                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2823                         tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2824                     }
2825                 }
2826                 gen_movl_TN_reg(rd, cpu_dst);
2827             } else if (xop == 0x26) { /* srl, V9 srlx */
2828                 cpu_src1 = get_src1(insn, cpu_src1);
2829                 if (IS_IMM) {   /* immediate */
2830                     rs2 = GET_FIELDs(insn, 20, 31);
2831                     if (insn & (1 << 12)) {
2832                         tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2833                     } else {
2834                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2835                         tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2836                     }
2837                 } else {                /* register */
2838                     rs2 = GET_FIELD(insn, 27, 31);
2839                     gen_movl_reg_TN(rs2, cpu_src2);
2840                     if (insn & (1 << 12)) {
2841                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2842                         tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2843                     } else {
2844                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2845                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2846                         tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2847                     }
2848                 }
2849                 gen_movl_TN_reg(rd, cpu_dst);
2850             } else if (xop == 0x27) { /* sra, V9 srax */
2851                 cpu_src1 = get_src1(insn, cpu_src1);
2852                 if (IS_IMM) {   /* immediate */
2853                     rs2 = GET_FIELDs(insn, 20, 31);
2854                     if (insn & (1 << 12)) {
2855                         tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2856                     } else {
2857                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2858                         tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2859                         tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2860                     }
2861                 } else {                /* register */
2862                     rs2 = GET_FIELD(insn, 27, 31);
2863                     gen_movl_reg_TN(rs2, cpu_src2);
2864                     if (insn & (1 << 12)) {
2865                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2866                         tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2867                     } else {
2868                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2869                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2870                         tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2871                     }
2872                 }
2873                 gen_movl_TN_reg(rd, cpu_dst);
2874 #endif
2875             } else if (xop < 0x36) {
2876                 cpu_src1 = get_src1(insn, cpu_src1);
2877                 cpu_src2 = get_src2(insn, cpu_src2);
2878                 if (xop < 0x20) {
2879                     switch (xop & ~0x10) {
2880                     case 0x0:
2881                         if (xop & 0x10)
2882                             gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2883                         else
2884                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2885                         break;
2886                     case 0x1:
2887                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2888                         if (xop & 0x10)
2889                             gen_op_logic_cc(cpu_dst);
2890                         break;
2891                     case 0x2:
2892                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2893                         if (xop & 0x10)
2894                             gen_op_logic_cc(cpu_dst);
2895                         break;
2896                     case 0x3:
2897                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
2898                         if (xop & 0x10)
2899                             gen_op_logic_cc(cpu_dst);
2900                         break;
2901                     case 0x4:
2902                         if (xop & 0x10)
2903                             gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
2904                         else
2905                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
2906                         break;
2907                     case 0x5:
2908                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2909                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
2910                         if (xop & 0x10)
2911                             gen_op_logic_cc(cpu_dst);
2912                         break;
2913                     case 0x6:
2914                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2915                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
2916                         if (xop & 0x10)
2917                             gen_op_logic_cc(cpu_dst);
2918                         break;
2919                     case 0x7:
2920                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2921                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
2922                         if (xop & 0x10)
2923                             gen_op_logic_cc(cpu_dst);
2924                         break;
2925                     case 0x8:
2926                         if (xop & 0x10)
2927                             gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
2928                         else {
2929                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
2930                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
2931                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
2932                         }
2933                         break;
2934 #ifdef TARGET_SPARC64
2935                     case 0x9: /* V9 mulx */
2936                         tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
2937                         break;
2938 #endif
2939                     case 0xa:
2940                         CHECK_IU_FEATURE(dc, MUL);
2941                         gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
2942                         if (xop & 0x10)
2943                             gen_op_logic_cc(cpu_dst);
2944                         break;
2945                     case 0xb:
2946                         CHECK_IU_FEATURE(dc, MUL);
2947                         gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
2948                         if (xop & 0x10)
2949                             gen_op_logic_cc(cpu_dst);
2950                         break;
2951                     case 0xc:
2952                         if (xop & 0x10)
2953                             gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
2954                         else {
2955                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
2956                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
2957                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
2958                         }
2959                         break;
2960 #ifdef TARGET_SPARC64
2961                     case 0xd: /* V9 udivx */
2962                         gen_trap_ifdivzero_tl(cpu_src2);
2963                         tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2);
2964                         break;
2965 #endif
2966                     case 0xe:
2967                         CHECK_IU_FEATURE(dc, DIV);
2968                         tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
2969                                            cpu_src2);
2970                         if (xop & 0x10)
2971                             gen_op_div_cc(cpu_dst);
2972                         break;
2973                     case 0xf:
2974                         CHECK_IU_FEATURE(dc, DIV);
2975                         tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
2976                                            cpu_src2);
2977                         if (xop & 0x10)
2978                             gen_op_div_cc(cpu_dst);
2979                         break;
2980                     default:
2981                         goto illegal_insn;
2982                     }
2983                     gen_movl_TN_reg(rd, cpu_dst);
2984                 } else {
2985                     switch (xop) {
2986                     case 0x20: /* taddcc */
2987                         gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
2988                         gen_movl_TN_reg(rd, cpu_dst);
2989                         break;
2990                     case 0x21: /* tsubcc */
2991                         gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
2992                         gen_movl_TN_reg(rd, cpu_dst);
2993                         break;
2994                     case 0x22: /* taddcctv */
2995                         save_state(dc, cpu_cond);
2996                         gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
2997                         gen_movl_TN_reg(rd, cpu_dst);
2998                         break;
2999                     case 0x23: /* tsubcctv */
3000                         save_state(dc, cpu_cond);
3001                         gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3002                         gen_movl_TN_reg(rd, cpu_dst);
3003                         break;
3004                     case 0x24: /* mulscc */
3005                         gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3006                         gen_movl_TN_reg(rd, cpu_dst);
3007                         break;
3008 #ifndef TARGET_SPARC64
3009                     case 0x25:  /* sll */
3010                         if (IS_IMM) { /* immediate */
3011                             rs2 = GET_FIELDs(insn, 20, 31);
3012                             tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3013                         } else { /* register */
3014                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3015                             tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3016                         }
3017                         gen_movl_TN_reg(rd, cpu_dst);
3018                         break;
3019                     case 0x26:  /* srl */
3020                         if (IS_IMM) { /* immediate */
3021                             rs2 = GET_FIELDs(insn, 20, 31);
3022                             tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3023                         } else { /* register */
3024                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3025                             tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3026                         }
3027                         gen_movl_TN_reg(rd, cpu_dst);
3028                         break;
3029                     case 0x27:  /* sra */
3030                         if (IS_IMM) { /* immediate */
3031                             rs2 = GET_FIELDs(insn, 20, 31);
3032                             tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3033                         } else { /* register */
3034                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3035                             tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3036                         }
3037                         gen_movl_TN_reg(rd, cpu_dst);
3038                         break;
3039 #endif
3040                     case 0x30:
3041                         {
3042                             switch(rd) {
3043                             case 0: /* wry */
3044                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3045                                 tcg_gen_st_tl(cpu_dst, cpu_env,
3046                                               offsetof(CPUSPARCState, y));
3047                                 break;
3048 #ifndef TARGET_SPARC64
3049                             case 0x01 ... 0x0f: /* undefined in the
3050                                                    SPARCv8 manual, nop
3051                                                    on the microSPARC
3052                                                    II */
3053                             case 0x10 ... 0x1f: /* implementation-dependent
3054                                                    in the SPARCv8
3055                                                    manual, nop on the
3056                                                    microSPARC II */
3057                                 break;
3058 #else
3059                             case 0x2: /* V9 wrccr */
3060                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3061                                 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3062                                 break;
3063                             case 0x3: /* V9 wrasi */
3064                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3065                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3066                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3067                                                offsetof(CPUSPARCState, asi));
3068                                 break;
3069                             case 0x6: /* V9 wrfprs */
3070                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3071                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3072                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3073                                                offsetof(CPUSPARCState, fprs));
3074                                 save_state(dc, cpu_cond);
3075                                 gen_op_next_insn();
3076                                 tcg_gen_exit_tb(0);
3077                                 dc->is_br = 1;
3078                                 break;
3079                             case 0xf: /* V9 sir, nop if user */
3080 #if !defined(CONFIG_USER_ONLY)
3081                                 if (supervisor(dc))
3082                                     ; // XXX
3083 #endif
3084                                 break;
3085                             case 0x13: /* Graphics Status */
3086                                 if (gen_trap_ifnofpu(dc, cpu_cond))
3087                                     goto jmp_insn;
3088                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3089                                 tcg_gen_st_tl(cpu_dst, cpu_env,
3090                                               offsetof(CPUSPARCState, gsr));
3091                                 break;
3092                             case 0x17: /* Tick compare */
3093 #if !defined(CONFIG_USER_ONLY)
3094                                 if (!supervisor(dc))
3095                                     goto illegal_insn;
3096 #endif
3097                                 {
3098                                     TCGv r_tickptr;
3099
3100                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3101                                                    cpu_src2);
3102                                     tcg_gen_st_tl(cpu_dst, cpu_env,
3103                                                   offsetof(CPUSPARCState,
3104                                                            tick_cmpr));
3105                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3106                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3107                                                    offsetof(CPUState, tick));
3108                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3109                                                        r_tickptr, cpu_dst);
3110                                 }
3111                                 break;
3112                             case 0x18: /* System tick */
3113 #if !defined(CONFIG_USER_ONLY)
3114                                 if (!supervisor(dc))
3115                                     goto illegal_insn;
3116 #endif
3117                                 {
3118                                     TCGv r_tickptr;
3119
3120                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3121                                                    cpu_src2);
3122                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3123                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3124                                                    offsetof(CPUState, stick));
3125                                     tcg_gen_helper_0_2(helper_tick_set_count,
3126                                                        r_tickptr, cpu_dst);
3127                                 }
3128                                 break;
3129                             case 0x19: /* System tick compare */
3130 #if !defined(CONFIG_USER_ONLY)
3131                                 if (!supervisor(dc))
3132                                     goto illegal_insn;
3133 #endif
3134                                 {
3135                                     TCGv r_tickptr;
3136
3137                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3138                                                    cpu_src2);
3139                                     tcg_gen_st_tl(cpu_dst, cpu_env,
3140                                                   offsetof(CPUSPARCState,
3141                                                            stick_cmpr));
3142                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3143                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3144                                                    offsetof(CPUState, stick));
3145                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3146                                                        r_tickptr, cpu_dst);
3147                                 }
3148                                 break;
3149
3150                             case 0x10: /* Performance Control */
3151                             case 0x11: /* Performance Instrumentation
3152                                           Counter */
3153                             case 0x12: /* Dispatch Control */
3154                             case 0x14: /* Softint set */
3155                             case 0x15: /* Softint clear */
3156                             case 0x16: /* Softint write */
3157 #endif
3158                             default:
3159                                 goto illegal_insn;
3160                             }
3161                         }
3162                         break;
3163 #if !defined(CONFIG_USER_ONLY)
3164                     case 0x31: /* wrpsr, V9 saved, restored */
3165                         {
3166                             if (!supervisor(dc))
3167                                 goto priv_insn;
3168 #ifdef TARGET_SPARC64
3169                             switch (rd) {
3170                             case 0:
3171                                 tcg_gen_helper_0_0(helper_saved);
3172                                 break;
3173                             case 1:
3174                                 tcg_gen_helper_0_0(helper_restored);
3175                                 break;
3176                             case 2: /* UA2005 allclean */
3177                             case 3: /* UA2005 otherw */
3178                             case 4: /* UA2005 normalw */
3179                             case 5: /* UA2005 invalw */
3180                                 // XXX
3181                             default:
3182                                 goto illegal_insn;
3183                             }
3184 #else
3185                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3186                             tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3187                             save_state(dc, cpu_cond);
3188                             gen_op_next_insn();
3189                             tcg_gen_exit_tb(0);
3190                             dc->is_br = 1;
3191 #endif
3192                         }
3193                         break;
3194                     case 0x32: /* wrwim, V9 wrpr */
3195                         {
3196                             if (!supervisor(dc))
3197                                 goto priv_insn;
3198                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3199 #ifdef TARGET_SPARC64
3200                             switch (rd) {
3201                             case 0: // tpc
3202                                 {
3203                                     TCGv r_tsptr;
3204
3205                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3206                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3207                                                    offsetof(CPUState, tsptr));
3208                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3209                                                   offsetof(trap_state, tpc));
3210                                 }
3211                                 break;
3212                             case 1: // tnpc
3213                                 {
3214                                     TCGv r_tsptr;
3215
3216                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3217                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3218                                                    offsetof(CPUState, tsptr));
3219                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3220                                                   offsetof(trap_state, tnpc));
3221                                 }
3222                                 break;
3223                             case 2: // tstate
3224                                 {
3225                                     TCGv r_tsptr;
3226
3227                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3228                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3229                                                    offsetof(CPUState, tsptr));
3230                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3231                                                   offsetof(trap_state,
3232                                                            tstate));
3233                                 }
3234                                 break;
3235                             case 3: // tt
3236                                 {
3237                                     TCGv r_tsptr;
3238
3239                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3240                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3241                                                    offsetof(CPUState, tsptr));
3242                                     tcg_gen_st_i32(cpu_dst, r_tsptr,
3243                                                    offsetof(trap_state, tt));
3244                                 }
3245                                 break;
3246                             case 4: // tick
3247                                 {
3248                                     TCGv r_tickptr;
3249
3250                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3251                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3252                                                    offsetof(CPUState, tick));
3253                                     tcg_gen_helper_0_2(helper_tick_set_count,
3254                                                        r_tickptr, cpu_dst);
3255                                 }
3256                                 break;
3257                             case 5: // tba
3258                                 tcg_gen_st_tl(cpu_dst, cpu_env,
3259                                               offsetof(CPUSPARCState, tbr));
3260                                 break;
3261                             case 6: // pstate
3262                                 save_state(dc, cpu_cond);
3263                                 tcg_gen_helper_0_1(helper_wrpstate, cpu_dst);
3264                                 gen_op_next_insn();
3265                                 tcg_gen_exit_tb(0);
3266                                 dc->is_br = 1;
3267                                 break;
3268                             case 7: // tl
3269                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3270                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3271                                                offsetof(CPUSPARCState, tl));
3272                                 break;
3273                             case 8: // pil
3274                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3275                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3276                                                offsetof(CPUSPARCState,
3277                                                         psrpil));
3278                                 break;
3279                             case 9: // cwp
3280                                 tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
3281                                 break;
3282                             case 10: // cansave
3283                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3284                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3285                                                offsetof(CPUSPARCState,
3286                                                         cansave));
3287                                 break;
3288                             case 11: // canrestore
3289                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3290                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3291                                                offsetof(CPUSPARCState,
3292                                                         canrestore));
3293                                 break;
3294                             case 12: // cleanwin
3295                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3296                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3297                                                offsetof(CPUSPARCState,
3298                                                         cleanwin));
3299                                 break;
3300                             case 13: // otherwin
3301                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3302                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3303                                                offsetof(CPUSPARCState,
3304                                                         otherwin));
3305                                 break;
3306                             case 14: // wstate
3307                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3308                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3309                                                offsetof(CPUSPARCState,
3310                                                         wstate));
3311                                 break;
3312                             case 16: // UA2005 gl
3313                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3314                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3315                                                offsetof(CPUSPARCState, gl));
3316                                 break;
3317                             case 26: // UA2005 strand status
3318                                 if (!hypervisor(dc))
3319                                     goto priv_insn;
3320                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3321                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3322                                                offsetof(CPUSPARCState, ssr));
3323                                 break;
3324                             default:
3325                                 goto illegal_insn;
3326                             }
3327 #else
3328                             tcg_gen_andi_tl(cpu_dst, cpu_dst,
3329                                             ((1 << NWINDOWS) - 1));
3330                             tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3331                             tcg_gen_st_i32(cpu_tmp32, cpu_env,
3332                                            offsetof(CPUSPARCState, wim));
3333 #endif
3334                         }
3335                         break;
3336                     case 0x33: /* wrtbr, UA2005 wrhpr */
3337                         {
3338 #ifndef TARGET_SPARC64
3339                             if (!supervisor(dc))
3340                                 goto priv_insn;
3341                             tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3342                             tcg_gen_st_tl(cpu_dst, cpu_env,
3343                                           offsetof(CPUSPARCState, tbr));
3344 #else
3345                             if (!hypervisor(dc))
3346                                 goto priv_insn;
3347                             tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3348                             switch (rd) {
3349                             case 0: // hpstate
3350                                 // XXX gen_op_wrhpstate();
3351                                 save_state(dc, cpu_cond);
3352                                 gen_op_next_insn();
3353                                 tcg_gen_exit_tb(0);
3354                                 dc->is_br = 1;
3355                                 break;
3356                             case 1: // htstate
3357                                 // XXX gen_op_wrhtstate();
3358                                 break;
3359                             case 3: // hintp
3360                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3361                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3362                                                offsetof(CPUSPARCState, hintp));
3363                                 break;
3364                             case 5: // htba
3365                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3366                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3367                                                offsetof(CPUSPARCState, htba));
3368                                 break;
3369                             case 31: // hstick_cmpr
3370                                 {
3371                                     TCGv r_tickptr;
3372
3373                                     tcg_gen_st_tl(cpu_dst, cpu_env,
3374                                                   offsetof(CPUSPARCState,
3375                                                            hstick_cmpr));
3376                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3377                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3378                                                    offsetof(CPUState, hstick));
3379                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3380                                                        r_tickptr, cpu_dst);
3381                                 }
3382                                 break;
3383                             case 6: // hver readonly
3384                             default:
3385                                 goto illegal_insn;
3386                             }
3387 #endif
3388                         }
3389                         break;
3390 #endif
3391 #ifdef TARGET_SPARC64
3392                     case 0x2c: /* V9 movcc */
3393                         {
3394                             int cc = GET_FIELD_SP(insn, 11, 12);
3395                             int cond = GET_FIELD_SP(insn, 14, 17);
3396                             TCGv r_cond;
3397                             int l1;
3398
3399                             r_cond = tcg_temp_new(TCG_TYPE_TL);
3400                             if (insn & (1 << 18)) {
3401                                 if (cc == 0)
3402                                     gen_cond(r_cond, 0, cond);
3403                                 else if (cc == 2)
3404                                     gen_cond(r_cond, 1, cond);
3405                                 else
3406                                     goto illegal_insn;
3407                             } else {
3408                                 gen_fcond(r_cond, cc, cond);
3409                             }
3410
3411                             l1 = gen_new_label();
3412
3413                             tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3414                             if (IS_IMM) {       /* immediate */
3415                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
3416                                 gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
3417                             } else {
3418                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3419                                 gen_movl_reg_TN(rs2, cpu_tmp0);
3420                                 gen_movl_TN_reg(rd, cpu_tmp0);
3421                             }
3422                             gen_set_label(l1);
3423                             break;
3424                         }
3425                     case 0x2d: /* V9 sdivx */
3426                         gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3427                         gen_movl_TN_reg(rd, cpu_dst);
3428                         break;
3429                     case 0x2e: /* V9 popc */
3430                         {
3431                             cpu_src2 = get_src2(insn, cpu_src2);
3432                             tcg_gen_helper_1_1(helper_popc, cpu_dst,
3433                                                cpu_src2);
3434                             gen_movl_TN_reg(rd, cpu_dst);
3435                         }
3436                     case 0x2f: /* V9 movr */
3437                         {
3438                             int cond = GET_FIELD_SP(insn, 10, 12);
3439                             int l1;
3440
3441                             cpu_src1 = get_src1(insn, cpu_src1);
3442
3443                             l1 = gen_new_label();
3444
3445                             tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3446                                               cpu_src1, 0, l1);
3447                             if (IS_IMM) {       /* immediate */
3448                                 rs2 = GET_FIELD_SPs(insn, 0, 9);
3449                                 gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
3450                             } else {
3451                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3452                                 gen_movl_reg_TN(rs2, cpu_tmp0);
3453                                 gen_movl_TN_reg(rd, cpu_tmp0);
3454                             }
3455                             gen_set_label(l1);
3456                             break;
3457                         }
3458 #endif
3459                     default:
3460                         goto illegal_insn;
3461                     }
3462                 }
3463             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3464 #ifdef TARGET_SPARC64
3465                 int opf = GET_FIELD_SP(insn, 5, 13);
3466                 rs1 = GET_FIELD(insn, 13, 17);
3467                 rs2 = GET_FIELD(insn, 27, 31);
3468                 if (gen_trap_ifnofpu(dc, cpu_cond))
3469                     goto jmp_insn;
3470
3471                 switch (opf) {
3472                 case 0x000: /* VIS I edge8cc */
3473                 case 0x001: /* VIS II edge8n */
3474                 case 0x002: /* VIS I edge8lcc */
3475                 case 0x003: /* VIS II edge8ln */
3476                 case 0x004: /* VIS I edge16cc */
3477                 case 0x005: /* VIS II edge16n */
3478                 case 0x006: /* VIS I edge16lcc */
3479                 case 0x007: /* VIS II edge16ln */
3480                 case 0x008: /* VIS I edge32cc */
3481                 case 0x009: /* VIS II edge32n */
3482                 case 0x00a: /* VIS I edge32lcc */
3483                 case 0x00b: /* VIS II edge32ln */
3484                     // XXX
3485                     goto illegal_insn;
3486                 case 0x010: /* VIS I array8 */
3487                     CHECK_FPU_FEATURE(dc, VIS1);
3488                     cpu_src1 = get_src1(insn, cpu_src1);
3489                     gen_movl_reg_TN(rs2, cpu_src2);
3490                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3491                                        cpu_src2);
3492                     gen_movl_TN_reg(rd, cpu_dst);
3493                     break;
3494                 case 0x012: /* VIS I array16 */
3495                     CHECK_FPU_FEATURE(dc, VIS1);
3496                     cpu_src1 = get_src1(insn, cpu_src1);
3497                     gen_movl_reg_TN(rs2, cpu_src2);
3498                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3499                                        cpu_src2);
3500                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3501                     gen_movl_TN_reg(rd, cpu_dst);
3502                     break;
3503                 case 0x014: /* VIS I array32 */
3504                     CHECK_FPU_FEATURE(dc, VIS1);
3505                     cpu_src1 = get_src1(insn, cpu_src1);
3506                     gen_movl_reg_TN(rs2, cpu_src2);
3507                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3508                                        cpu_src2);
3509                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3510                     gen_movl_TN_reg(rd, cpu_dst);
3511                     break;
3512                 case 0x018: /* VIS I alignaddr */
3513                     CHECK_FPU_FEATURE(dc, VIS1);
3514                     cpu_src1 = get_src1(insn, cpu_src1);
3515                     gen_movl_reg_TN(rs2, cpu_src2);
3516                     tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3517                                        cpu_src2);
3518                     gen_movl_TN_reg(rd, cpu_dst);
3519                     break;
3520                 case 0x019: /* VIS II bmask */
3521                 case 0x01a: /* VIS I alignaddrl */
3522                     // XXX
3523                     goto illegal_insn;
3524                 case 0x020: /* VIS I fcmple16 */
3525                     CHECK_FPU_FEATURE(dc, VIS1);
3526                     gen_op_load_fpr_DT0(DFPREG(rs1));
3527                     gen_op_load_fpr_DT1(DFPREG(rs2));
3528                     tcg_gen_helper_0_0(helper_fcmple16);
3529                     gen_op_store_DT0_fpr(DFPREG(rd));
3530                     break;
3531                 case 0x022: /* VIS I fcmpne16 */
3532                     CHECK_FPU_FEATURE(dc, VIS1);
3533                     gen_op_load_fpr_DT0(DFPREG(rs1));
3534                     gen_op_load_fpr_DT1(DFPREG(rs2));
3535                     tcg_gen_helper_0_0(helper_fcmpne16);
3536                     gen_op_store_DT0_fpr(DFPREG(rd));
3537                     break;
3538                 case 0x024: /* VIS I fcmple32 */
3539                     CHECK_FPU_FEATURE(dc, VIS1);
3540                     gen_op_load_fpr_DT0(DFPREG(rs1));
3541                     gen_op_load_fpr_DT1(DFPREG(rs2));
3542                     tcg_gen_helper_0_0(helper_fcmple32);
3543                     gen_op_store_DT0_fpr(DFPREG(rd));
3544                     break;
3545                 case 0x026: /* VIS I fcmpne32 */
3546                     CHECK_FPU_FEATURE(dc, VIS1);
3547                     gen_op_load_fpr_DT0(DFPREG(rs1));
3548                     gen_op_load_fpr_DT1(DFPREG(rs2));
3549                     tcg_gen_helper_0_0(helper_fcmpne32);
3550                     gen_op_store_DT0_fpr(DFPREG(rd));
3551                     break;
3552                 case 0x028: /* VIS I fcmpgt16 */
3553                     CHECK_FPU_FEATURE(dc, VIS1);
3554                     gen_op_load_fpr_DT0(DFPREG(rs1));
3555                     gen_op_load_fpr_DT1(DFPREG(rs2));
3556                     tcg_gen_helper_0_0(helper_fcmpgt16);
3557                     gen_op_store_DT0_fpr(DFPREG(rd));
3558                     break;
3559                 case 0x02a: /* VIS I fcmpeq16 */
3560                     CHECK_FPU_FEATURE(dc, VIS1);
3561                     gen_op_load_fpr_DT0(DFPREG(rs1));
3562                     gen_op_load_fpr_DT1(DFPREG(rs2));
3563                     tcg_gen_helper_0_0(helper_fcmpeq16);
3564                     gen_op_store_DT0_fpr(DFPREG(rd));
3565                     break;
3566                 case 0x02c: /* VIS I fcmpgt32 */
3567                     CHECK_FPU_FEATURE(dc, VIS1);
3568                     gen_op_load_fpr_DT0(DFPREG(rs1));
3569                     gen_op_load_fpr_DT1(DFPREG(rs2));
3570                     tcg_gen_helper_0_0(helper_fcmpgt32);
3571                     gen_op_store_DT0_fpr(DFPREG(rd));
3572                     break;
3573                 case 0x02e: /* VIS I fcmpeq32 */
3574                     CHECK_FPU_FEATURE(dc, VIS1);
3575                     gen_op_load_fpr_DT0(DFPREG(rs1));
3576                     gen_op_load_fpr_DT1(DFPREG(rs2));
3577                     tcg_gen_helper_0_0(helper_fcmpeq32);
3578                     gen_op_store_DT0_fpr(DFPREG(rd));
3579                     break;
3580                 case 0x031: /* VIS I fmul8x16 */
3581                     CHECK_FPU_FEATURE(dc, VIS1);
3582                     gen_op_load_fpr_DT0(DFPREG(rs1));
3583                     gen_op_load_fpr_DT1(DFPREG(rs2));
3584                     tcg_gen_helper_0_0(helper_fmul8x16);
3585                     gen_op_store_DT0_fpr(DFPREG(rd));
3586                     break;
3587                 case 0x033: /* VIS I fmul8x16au */
3588                     CHECK_FPU_FEATURE(dc, VIS1);
3589                     gen_op_load_fpr_DT0(DFPREG(rs1));
3590                     gen_op_load_fpr_DT1(DFPREG(rs2));
3591                     tcg_gen_helper_0_0(helper_fmul8x16au);
3592                     gen_op_store_DT0_fpr(DFPREG(rd));
3593                     break;
3594                 case 0x035: /* VIS I fmul8x16al */
3595                     CHECK_FPU_FEATURE(dc, VIS1);
3596                     gen_op_load_fpr_DT0(DFPREG(rs1));
3597                     gen_op_load_fpr_DT1(DFPREG(rs2));
3598                     tcg_gen_helper_0_0(helper_fmul8x16al);
3599                     gen_op_store_DT0_fpr(DFPREG(rd));
3600                     break;
3601                 case 0x036: /* VIS I fmul8sux16 */
3602                     CHECK_FPU_FEATURE(dc, VIS1);
3603                     gen_op_load_fpr_DT0(DFPREG(rs1));
3604                     gen_op_load_fpr_DT1(DFPREG(rs2));
3605                     tcg_gen_helper_0_0(helper_fmul8sux16);
3606                     gen_op_store_DT0_fpr(DFPREG(rd));
3607                     break;
3608                 case 0x037: /* VIS I fmul8ulx16 */
3609                     CHECK_FPU_FEATURE(dc, VIS1);
3610                     gen_op_load_fpr_DT0(DFPREG(rs1));
3611                     gen_op_load_fpr_DT1(DFPREG(rs2));
3612                     tcg_gen_helper_0_0(helper_fmul8ulx16);
3613                     gen_op_store_DT0_fpr(DFPREG(rd));
3614                     break;
3615                 case 0x038: /* VIS I fmuld8sux16 */
3616                     CHECK_FPU_FEATURE(dc, VIS1);
3617                     gen_op_load_fpr_DT0(DFPREG(rs1));
3618                     gen_op_load_fpr_DT1(DFPREG(rs2));
3619                     tcg_gen_helper_0_0(helper_fmuld8sux16);
3620                     gen_op_store_DT0_fpr(DFPREG(rd));
3621                     break;
3622                 case 0x039: /* VIS I fmuld8ulx16 */
3623                     CHECK_FPU_FEATURE(dc, VIS1);
3624                     gen_op_load_fpr_DT0(DFPREG(rs1));
3625                     gen_op_load_fpr_DT1(DFPREG(rs2));
3626                     tcg_gen_helper_0_0(helper_fmuld8ulx16);
3627                     gen_op_store_DT0_fpr(DFPREG(rd));
3628                     break;
3629                 case 0x03a: /* VIS I fpack32 */
3630                 case 0x03b: /* VIS I fpack16 */
3631                 case 0x03d: /* VIS I fpackfix */
3632                 case 0x03e: /* VIS I pdist */
3633                     // XXX
3634                     goto illegal_insn;
3635                 case 0x048: /* VIS I faligndata */
3636                     CHECK_FPU_FEATURE(dc, VIS1);
3637                     gen_op_load_fpr_DT0(DFPREG(rs1));
3638                     gen_op_load_fpr_DT1(DFPREG(rs2));
3639                     tcg_gen_helper_0_0(helper_faligndata);
3640                     gen_op_store_DT0_fpr(DFPREG(rd));
3641                     break;
3642                 case 0x04b: /* VIS I fpmerge */
3643                     CHECK_FPU_FEATURE(dc, VIS1);
3644                     gen_op_load_fpr_DT0(DFPREG(rs1));
3645                     gen_op_load_fpr_DT1(DFPREG(rs2));
3646                     tcg_gen_helper_0_0(helper_fpmerge);
3647                     gen_op_store_DT0_fpr(DFPREG(rd));
3648                     break;
3649                 case 0x04c: /* VIS II bshuffle */
3650                     // XXX
3651                     goto illegal_insn;
3652                 case 0x04d: /* VIS I fexpand */
3653                     CHECK_FPU_FEATURE(dc, VIS1);
3654                     gen_op_load_fpr_DT0(DFPREG(rs1));
3655                     gen_op_load_fpr_DT1(DFPREG(rs2));
3656                     tcg_gen_helper_0_0(helper_fexpand);
3657                     gen_op_store_DT0_fpr(DFPREG(rd));
3658                     break;
3659                 case 0x050: /* VIS I fpadd16 */
3660                     CHECK_FPU_FEATURE(dc, VIS1);
3661                     gen_op_load_fpr_DT0(DFPREG(rs1));
3662                     gen_op_load_fpr_DT1(DFPREG(rs2));
3663                     tcg_gen_helper_0_0(helper_fpadd16);
3664                     gen_op_store_DT0_fpr(DFPREG(rd));
3665                     break;
3666                 case 0x051: /* VIS I fpadd16s */
3667                     CHECK_FPU_FEATURE(dc, VIS1);
3668                     gen_op_load_fpr_FT0(rs1);
3669                     gen_op_load_fpr_FT1(rs2);
3670                     tcg_gen_helper_0_0(helper_fpadd16s);
3671                     gen_op_store_FT0_fpr(rd);
3672                     break;
3673                 case 0x052: /* VIS I fpadd32 */
3674                     CHECK_FPU_FEATURE(dc, VIS1);
3675                     gen_op_load_fpr_DT0(DFPREG(rs1));
3676                     gen_op_load_fpr_DT1(DFPREG(rs2));
3677                     tcg_gen_helper_0_0(helper_fpadd32);
3678                     gen_op_store_DT0_fpr(DFPREG(rd));
3679                     break;
3680                 case 0x053: /* VIS I fpadd32s */
3681                     CHECK_FPU_FEATURE(dc, VIS1);
3682                     gen_op_load_fpr_FT0(rs1);
3683                     gen_op_load_fpr_FT1(rs2);
3684                     tcg_gen_helper_0_0(helper_fpadd32s);
3685                     gen_op_store_FT0_fpr(rd);
3686                     break;
3687                 case 0x054: /* VIS I fpsub16 */
3688                     CHECK_FPU_FEATURE(dc, VIS1);
3689                     gen_op_load_fpr_DT0(DFPREG(rs1));
3690                     gen_op_load_fpr_DT1(DFPREG(rs2));
3691                     tcg_gen_helper_0_0(helper_fpsub16);
3692                     gen_op_store_DT0_fpr(DFPREG(rd));
3693                     break;
3694                 case 0x055: /* VIS I fpsub16s */
3695                     CHECK_FPU_FEATURE(dc, VIS1);
3696                     gen_op_load_fpr_FT0(rs1);
3697                     gen_op_load_fpr_FT1(rs2);
3698                     tcg_gen_helper_0_0(helper_fpsub16s);
3699                     gen_op_store_FT0_fpr(rd);
3700                     break;
3701                 case 0x056: /* VIS I fpsub32 */
3702                     CHECK_FPU_FEATURE(dc, VIS1);
3703                     gen_op_load_fpr_DT0(DFPREG(rs1));
3704                     gen_op_load_fpr_DT1(DFPREG(rs2));
3705                     tcg_gen_helper_0_0(helper_fpadd32);
3706                     gen_op_store_DT0_fpr(DFPREG(rd));
3707                     break;
3708                 case 0x057: /* VIS I fpsub32s */
3709                     CHECK_FPU_FEATURE(dc, VIS1);
3710                     gen_op_load_fpr_FT0(rs1);
3711                     gen_op_load_fpr_FT1(rs2);
3712                     tcg_gen_helper_0_0(helper_fpsub32s);
3713                     gen_op_store_FT0_fpr(rd);
3714                     break;
3715                 case 0x060: /* VIS I fzero */
3716                     CHECK_FPU_FEATURE(dc, VIS1);
3717                     tcg_gen_helper_0_0(helper_movl_DT0_0);
3718                     gen_op_store_DT0_fpr(DFPREG(rd));
3719                     break;
3720                 case 0x061: /* VIS I fzeros */
3721                     CHECK_FPU_FEATURE(dc, VIS1);
3722                     tcg_gen_helper_0_0(helper_movl_FT0_0);
3723                     gen_op_store_FT0_fpr(rd);
3724                     break;
3725                 case 0x062: /* VIS I fnor */
3726                     CHECK_FPU_FEATURE(dc, VIS1);
3727                     gen_op_load_fpr_DT0(DFPREG(rs1));
3728                     gen_op_load_fpr_DT1(DFPREG(rs2));
3729                     tcg_gen_helper_0_0(helper_fnor);
3730                     gen_op_store_DT0_fpr(DFPREG(rd));
3731                     break;
3732                 case 0x063: /* VIS I fnors */
3733                     CHECK_FPU_FEATURE(dc, VIS1);
3734                     gen_op_load_fpr_FT0(rs1);
3735                     gen_op_load_fpr_FT1(rs2);
3736                     tcg_gen_helper_0_0(helper_fnors);
3737                     gen_op_store_FT0_fpr(rd);
3738                     break;
3739                 case 0x064: /* VIS I fandnot2 */
3740                     CHECK_FPU_FEATURE(dc, VIS1);
3741                     gen_op_load_fpr_DT1(DFPREG(rs1));
3742                     gen_op_load_fpr_DT0(DFPREG(rs2));
3743                     tcg_gen_helper_0_0(helper_fandnot);
3744                     gen_op_store_DT0_fpr(DFPREG(rd));
3745                     break;
3746                 case 0x065: /* VIS I fandnot2s */
3747                     CHECK_FPU_FEATURE(dc, VIS1);
3748                     gen_op_load_fpr_FT1(rs1);
3749                     gen_op_load_fpr_FT0(rs2);
3750                     tcg_gen_helper_0_0(helper_fandnots);
3751                     gen_op_store_FT0_fpr(rd);
3752                     break;
3753                 case 0x066: /* VIS I fnot2 */
3754                     CHECK_FPU_FEATURE(dc, VIS1);
3755                     gen_op_load_fpr_DT1(DFPREG(rs2));
3756                     tcg_gen_helper_0_0(helper_fnot);
3757                     gen_op_store_DT0_fpr(DFPREG(rd));
3758                     break;
3759                 case 0x067: /* VIS I fnot2s */
3760                     CHECK_FPU_FEATURE(dc, VIS1);
3761                     gen_op_load_fpr_FT1(rs2);
3762                     tcg_gen_helper_0_0(helper_fnot);
3763                     gen_op_store_FT0_fpr(rd);
3764                     break;
3765                 case 0x068: /* VIS I fandnot1 */
3766                     CHECK_FPU_FEATURE(dc, VIS1);
3767                     gen_op_load_fpr_DT0(DFPREG(rs1));
3768                     gen_op_load_fpr_DT1(DFPREG(rs2));
3769                     tcg_gen_helper_0_0(helper_fandnot);
3770                     gen_op_store_DT0_fpr(DFPREG(rd));
3771                     break;
3772                 case 0x069: /* VIS I fandnot1s */
3773                     CHECK_FPU_FEATURE(dc, VIS1);
3774                     gen_op_load_fpr_FT0(rs1);
3775                     gen_op_load_fpr_FT1(rs2);
3776                     tcg_gen_helper_0_0(helper_fandnots);
3777                     gen_op_store_FT0_fpr(rd);
3778                     break;
3779                 case 0x06a: /* VIS I fnot1 */
3780                     CHECK_FPU_FEATURE(dc, VIS1);
3781                     gen_op_load_fpr_DT1(DFPREG(rs1));
3782                     tcg_gen_helper_0_0(helper_fnot);
3783                     gen_op_store_DT0_fpr(DFPREG(rd));
3784                     break;
3785                 case 0x06b: /* VIS I fnot1s */
3786                     CHECK_FPU_FEATURE(dc, VIS1);
3787                     gen_op_load_fpr_FT1(rs1);
3788                     tcg_gen_helper_0_0(helper_fnot);
3789                     gen_op_store_FT0_fpr(rd);
3790                     break;
3791                 case 0x06c: /* VIS I fxor */
3792                     CHECK_FPU_FEATURE(dc, VIS1);
3793                     gen_op_load_fpr_DT0(DFPREG(rs1));
3794                     gen_op_load_fpr_DT1(DFPREG(rs2));
3795                     tcg_gen_helper_0_0(helper_fxor);
3796                     gen_op_store_DT0_fpr(DFPREG(rd));
3797                     break;
3798                 case 0x06d: /* VIS I fxors */
3799                     CHECK_FPU_FEATURE(dc, VIS1);
3800                     gen_op_load_fpr_FT0(rs1);
3801                     gen_op_load_fpr_FT1(rs2);
3802                     tcg_gen_helper_0_0(helper_fxors);
3803                     gen_op_store_FT0_fpr(rd);
3804                     break;
3805                 case 0x06e: /* VIS I fnand */
3806                     CHECK_FPU_FEATURE(dc, VIS1);
3807                     gen_op_load_fpr_DT0(DFPREG(rs1));
3808                     gen_op_load_fpr_DT1(DFPREG(rs2));
3809                     tcg_gen_helper_0_0(helper_fnand);
3810                     gen_op_store_DT0_fpr(DFPREG(rd));
3811                     break;
3812                 case 0x06f: /* VIS I fnands */
3813                     CHECK_FPU_FEATURE(dc, VIS1);
3814                     gen_op_load_fpr_FT0(rs1);
3815                     gen_op_load_fpr_FT1(rs2);
3816                     tcg_gen_helper_0_0(helper_fnands);
3817                     gen_op_store_FT0_fpr(rd);
3818                     break;
3819                 case 0x070: /* VIS I fand */
3820                     CHECK_FPU_FEATURE(dc, VIS1);
3821                     gen_op_load_fpr_DT0(DFPREG(rs1));
3822                     gen_op_load_fpr_DT1(DFPREG(rs2));
3823                     tcg_gen_helper_0_0(helper_fand);
3824                     gen_op_store_DT0_fpr(DFPREG(rd));
3825                     break;
3826                 case 0x071: /* VIS I fands */
3827                     CHECK_FPU_FEATURE(dc, VIS1);
3828                     gen_op_load_fpr_FT0(rs1);
3829                     gen_op_load_fpr_FT1(rs2);
3830                     tcg_gen_helper_0_0(helper_fands);
3831                     gen_op_store_FT0_fpr(rd);
3832                     break;
3833                 case 0x072: /* VIS I fxnor */
3834                     CHECK_FPU_FEATURE(dc, VIS1);
3835                     gen_op_load_fpr_DT0(DFPREG(rs1));
3836                     gen_op_load_fpr_DT1(DFPREG(rs2));
3837                     tcg_gen_helper_0_0(helper_fxnor);
3838                     gen_op_store_DT0_fpr(DFPREG(rd));
3839                     break;
3840                 case 0x073: /* VIS I fxnors */
3841                     CHECK_FPU_FEATURE(dc, VIS1);
3842                     gen_op_load_fpr_FT0(rs1);
3843                     gen_op_load_fpr_FT1(rs2);
3844                     tcg_gen_helper_0_0(helper_fxnors);
3845                     gen_op_store_FT0_fpr(rd);
3846                     break;
3847                 case 0x074: /* VIS I fsrc1 */
3848                     CHECK_FPU_FEATURE(dc, VIS1);
3849                     gen_op_load_fpr_DT0(DFPREG(rs1));
3850                     gen_op_store_DT0_fpr(DFPREG(rd));
3851                     break;
3852                 case 0x075: /* VIS I fsrc1s */
3853                     CHECK_FPU_FEATURE(dc, VIS1);
3854                     gen_op_load_fpr_FT0(rs1);
3855                     gen_op_store_FT0_fpr(rd);
3856                     break;
3857                 case 0x076: /* VIS I fornot2 */
3858                     CHECK_FPU_FEATURE(dc, VIS1);
3859                     gen_op_load_fpr_DT1(DFPREG(rs1));
3860                     gen_op_load_fpr_DT0(DFPREG(rs2));
3861                     tcg_gen_helper_0_0(helper_fornot);
3862                     gen_op_store_DT0_fpr(DFPREG(rd));
3863                     break;
3864                 case 0x077: /* VIS I fornot2s */
3865                     CHECK_FPU_FEATURE(dc, VIS1);
3866                     gen_op_load_fpr_FT1(rs1);
3867                     gen_op_load_fpr_FT0(rs2);
3868                     tcg_gen_helper_0_0(helper_fornots);
3869                     gen_op_store_FT0_fpr(rd);
3870                     break;
3871                 case 0x078: /* VIS I fsrc2 */
3872                     CHECK_FPU_FEATURE(dc, VIS1);
3873                     gen_op_load_fpr_DT0(DFPREG(rs2));
3874                     gen_op_store_DT0_fpr(DFPREG(rd));
3875                     break;
3876                 case 0x079: /* VIS I fsrc2s */
3877                     CHECK_FPU_FEATURE(dc, VIS1);
3878                     gen_op_load_fpr_FT0(rs2);
3879                     gen_op_store_FT0_fpr(rd);
3880                     break;
3881                 case 0x07a: /* VIS I fornot1 */
3882                     CHECK_FPU_FEATURE(dc, VIS1);
3883                     gen_op_load_fpr_DT0(DFPREG(rs1));
3884                     gen_op_load_fpr_DT1(DFPREG(rs2));
3885                     tcg_gen_helper_0_0(helper_fornot);
3886                     gen_op_store_DT0_fpr(DFPREG(rd));
3887                     break;
3888                 case 0x07b: /* VIS I fornot1s */
3889                     CHECK_FPU_FEATURE(dc, VIS1);
3890                     gen_op_load_fpr_FT0(rs1);
3891                     gen_op_load_fpr_FT1(rs2);
3892                     tcg_gen_helper_0_0(helper_fornots);
3893                     gen_op_store_FT0_fpr(rd);
3894                     break;
3895                 case 0x07c: /* VIS I for */
3896                     CHECK_FPU_FEATURE(dc, VIS1);
3897                     gen_op_load_fpr_DT0(DFPREG(rs1));
3898                     gen_op_load_fpr_DT1(DFPREG(rs2));
3899                     tcg_gen_helper_0_0(helper_for);
3900                     gen_op_store_DT0_fpr(DFPREG(rd));
3901                     break;
3902                 case 0x07d: /* VIS I fors */
3903                     CHECK_FPU_FEATURE(dc, VIS1);
3904                     gen_op_load_fpr_FT0(rs1);
3905                     gen_op_load_fpr_FT1(rs2);
3906                     tcg_gen_helper_0_0(helper_fors);
3907                     gen_op_store_FT0_fpr(rd);
3908                     break;
3909                 case 0x07e: /* VIS I fone */
3910                     CHECK_FPU_FEATURE(dc, VIS1);
3911                     tcg_gen_helper_0_0(helper_movl_DT0_1);
3912                     gen_op_store_DT0_fpr(DFPREG(rd));
3913                     break;
3914                 case 0x07f: /* VIS I fones */
3915                     CHECK_FPU_FEATURE(dc, VIS1);
3916                     tcg_gen_helper_0_0(helper_movl_FT0_1);
3917                     gen_op_store_FT0_fpr(rd);
3918                     break;
3919                 case 0x080: /* VIS I shutdown */
3920                 case 0x081: /* VIS II siam */
3921                     // XXX
3922                     goto illegal_insn;
3923                 default:
3924                     goto illegal_insn;
3925                 }
3926 #else
3927                 goto ncp_insn;
3928 #endif
3929             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
3930 #ifdef TARGET_SPARC64
3931                 goto illegal_insn;
3932 #else
3933                 goto ncp_insn;
3934 #endif
3935 #ifdef TARGET_SPARC64
3936             } else if (xop == 0x39) { /* V9 return */
3937                 save_state(dc, cpu_cond);
3938                 cpu_src1 = get_src1(insn, cpu_src1);
3939                 if (IS_IMM) {   /* immediate */
3940                     rs2 = GET_FIELDs(insn, 19, 31);
3941                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3942                 } else {                /* register */
3943                     rs2 = GET_FIELD(insn, 27, 31);
3944                     if (rs2) {
3945                         gen_movl_reg_TN(rs2, cpu_src2);
3946                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3947                     } else
3948                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
3949                 }
3950                 tcg_gen_helper_0_0(helper_restore);
3951                 gen_mov_pc_npc(dc, cpu_cond);
3952                 tcg_gen_helper_0_2(helper_check_align, cpu_dst,
3953                                    tcg_const_i32(3));
3954                 tcg_gen_mov_tl(cpu_npc, cpu_dst);
3955                 dc->npc = DYNAMIC_PC;
3956                 goto jmp_insn;
3957 #endif
3958             } else {
3959                 cpu_src1 = get_src1(insn, cpu_src1);
3960                 if (IS_IMM) {   /* immediate */
3961                     rs2 = GET_FIELDs(insn, 19, 31);
3962                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3963                 } else {                /* register */
3964                     rs2 = GET_FIELD(insn, 27, 31);
3965                     if (rs2) {
3966                         gen_movl_reg_TN(rs2, cpu_src2);
3967                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3968                     } else
3969                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
3970                 }
3971                 switch (xop) {
3972                 case 0x38:      /* jmpl */
3973                     {
3974                         gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
3975                         gen_mov_pc_npc(dc, cpu_cond);
3976                         tcg_gen_helper_0_2(helper_check_align, cpu_dst,
3977                                            tcg_const_i32(3));
3978                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
3979                         dc->npc = DYNAMIC_PC;
3980                     }
3981                     goto jmp_insn;
3982 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3983                 case 0x39:      /* rett, V9 return */
3984                     {
3985                         if (!supervisor(dc))
3986                             goto priv_insn;
3987                         gen_mov_pc_npc(dc, cpu_cond);
3988                         tcg_gen_helper_0_2(helper_check_align, cpu_dst,
3989                                            tcg_const_i32(3));
3990                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
3991                         dc->npc = DYNAMIC_PC;
3992                         tcg_gen_helper_0_0(helper_rett);
3993                     }
3994                     goto jmp_insn;
3995 #endif
3996                 case 0x3b: /* flush */
3997                     if (!((dc)->features & CPU_FEATURE_FLUSH))
3998                         goto unimp_flush;
3999                     tcg_gen_helper_0_1(helper_flush, cpu_dst);
4000                     break;
4001                 case 0x3c:      /* save */
4002                     save_state(dc, cpu_cond);
4003                     tcg_gen_helper_0_0(helper_save);
4004                     gen_movl_TN_reg(rd, cpu_dst);
4005                     break;
4006                 case 0x3d:      /* restore */
4007                     save_state(dc, cpu_cond);
4008                     tcg_gen_helper_0_0(helper_restore);
4009                     gen_movl_TN_reg(rd, cpu_dst);
4010                     break;
4011 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4012                 case 0x3e:      /* V9 done/retry */
4013                     {
4014                         switch (rd) {
4015                         case 0:
4016                             if (!supervisor(dc))
4017                                 goto priv_insn;
4018                             dc->npc = DYNAMIC_PC;
4019                             dc->pc = DYNAMIC_PC;
4020                             tcg_gen_helper_0_0(helper_done);
4021                             goto jmp_insn;
4022                         case 1:
4023                             if (!supervisor(dc))
4024                                 goto priv_insn;
4025                             dc->npc = DYNAMIC_PC;
4026                             dc->pc = DYNAMIC_PC;
4027                             tcg_gen_helper_0_0(helper_retry);
4028                             goto jmp_insn;
4029                         default:
4030                             goto illegal_insn;
4031                         }
4032                     }
4033                     break;
4034 #endif
4035                 default:
4036                     goto illegal_insn;
4037                 }
4038             }
4039             break;
4040         }
4041         break;
4042     case 3:                     /* load/store instructions */
4043         {
4044             unsigned int xop = GET_FIELD(insn, 7, 12);
4045
4046             cpu_src1 = get_src1(insn, cpu_src1);
4047             if (xop == 0x3c || xop == 0x3e)
4048             {
4049                 rs2 = GET_FIELD(insn, 27, 31);
4050                 gen_movl_reg_TN(rs2, cpu_src2);
4051             }
4052             else if (IS_IMM) {       /* immediate */
4053                 rs2 = GET_FIELDs(insn, 19, 31);
4054                 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4055             } else {            /* register */
4056                 rs2 = GET_FIELD(insn, 27, 31);
4057                 if (rs2 != 0) {
4058                     gen_movl_reg_TN(rs2, cpu_src2);
4059                     tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4060                 } else
4061                     tcg_gen_mov_tl(cpu_addr, cpu_src1);
4062             }
4063             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4064                 (xop > 0x17 && xop <= 0x1d ) ||
4065                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4066                 switch (xop) {
4067                 case 0x0:       /* load unsigned word */
4068                     ABI32_MASK(cpu_addr);
4069                     tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4070                     break;
4071                 case 0x1:       /* load unsigned byte */
4072                     ABI32_MASK(cpu_addr);
4073                     tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4074                     break;
4075                 case 0x2:       /* load unsigned halfword */
4076                     ABI32_MASK(cpu_addr);
4077                     tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4078                     break;
4079                 case 0x3:       /* load double word */
4080                     if (rd & 1)
4081                         goto illegal_insn;
4082                     else {
4083                         save_state(dc, cpu_cond);
4084                         tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4085                                            tcg_const_i32(7)); // XXX remove
4086                         ABI32_MASK(cpu_addr);
4087                         tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4088                         tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4089                         tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4090                         gen_movl_TN_reg(rd + 1, cpu_tmp0);
4091                         tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4092                         tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4093                         tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4094                     }
4095                     break;
4096                 case 0x9:       /* load signed byte */
4097                     ABI32_MASK(cpu_addr);
4098                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4099                     break;
4100                 case 0xa:       /* load signed halfword */
4101                     ABI32_MASK(cpu_addr);
4102                     tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4103                     break;
4104                 case 0xd:       /* ldstub -- XXX: should be atomically */
4105                     ABI32_MASK(cpu_addr);
4106                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4107                     tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr,
4108                                      dc->mem_idx);
4109                     break;
4110                 case 0x0f:      /* swap register with memory. Also
4111                                    atomically */
4112                     CHECK_IU_FEATURE(dc, SWAP);
4113                     gen_movl_reg_TN(rd, cpu_val);
4114                     ABI32_MASK(cpu_addr);
4115                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4116                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4117                     tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4118                     break;
4119 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4120                 case 0x10:      /* load word alternate */
4121 #ifndef TARGET_SPARC64
4122                     if (IS_IMM)
4123                         goto illegal_insn;
4124                     if (!supervisor(dc))
4125                         goto priv_insn;
4126 #endif
4127                     save_state(dc, cpu_cond);
4128                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4129                     break;
4130                 case 0x11:      /* load unsigned byte alternate */
4131 #ifndef TARGET_SPARC64
4132                     if (IS_IMM)
4133                         goto illegal_insn;
4134                     if (!supervisor(dc))
4135                         goto priv_insn;
4136 #endif
4137                     save_state(dc, cpu_cond);
4138                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4139                     break;
4140                 case 0x12:      /* load unsigned halfword alternate */
4141 #ifndef TARGET_SPARC64
4142                     if (IS_IMM)
4143                         goto illegal_insn;
4144                     if (!supervisor(dc))
4145                         goto priv_insn;
4146 #endif
4147                     save_state(dc, cpu_cond);
4148                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4149                     break;
4150                 case 0x13:      /* load double word alternate */
4151 #ifndef TARGET_SPARC64
4152                     if (IS_IMM)
4153                         goto illegal_insn;
4154                     if (!supervisor(dc))
4155                         goto priv_insn;
4156 #endif
4157                     if (rd & 1)
4158                         goto illegal_insn;
4159                     save_state(dc, cpu_cond);
4160                     gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4161                     gen_movl_TN_reg(rd + 1, cpu_tmp0);
4162                     break;
4163                 case 0x19:      /* load signed byte alternate */
4164 #ifndef TARGET_SPARC64
4165                     if (IS_IMM)
4166                         goto illegal_insn;
4167                     if (!supervisor(dc))
4168                         goto priv_insn;
4169 #endif
4170                     save_state(dc, cpu_cond);
4171                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4172                     break;
4173                 case 0x1a:      /* load signed halfword alternate */
4174 #ifndef TARGET_SPARC64
4175                     if (IS_IMM)
4176                         goto illegal_insn;
4177                     if (!supervisor(dc))
4178                         goto priv_insn;
4179 #endif
4180                     save_state(dc, cpu_cond);
4181                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4182                     break;
4183                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
4184 #ifndef TARGET_SPARC64
4185                     if (IS_IMM)
4186                         goto illegal_insn;
4187                     if (!supervisor(dc))
4188                         goto priv_insn;
4189 #endif
4190                     save_state(dc, cpu_cond);
4191                     gen_ldstub_asi(cpu_val, cpu_addr, insn);
4192                     break;
4193                 case 0x1f:      /* swap reg with alt. memory. Also
4194                                    atomically */
4195                     CHECK_IU_FEATURE(dc, SWAP);
4196 #ifndef TARGET_SPARC64
4197                     if (IS_IMM)
4198                         goto illegal_insn;
4199                     if (!supervisor(dc))
4200                         goto priv_insn;
4201 #endif
4202                     save_state(dc, cpu_cond);
4203                     gen_movl_reg_TN(rd, cpu_val);
4204                     gen_swap_asi(cpu_val, cpu_addr, insn);
4205                     break;
4206
4207 #ifndef TARGET_SPARC64
4208                 case 0x30: /* ldc */
4209                 case 0x31: /* ldcsr */
4210                 case 0x33: /* lddc */
4211                     goto ncp_insn;
4212 #endif
4213 #endif
4214 #ifdef TARGET_SPARC64
4215                 case 0x08: /* V9 ldsw */
4216                     ABI32_MASK(cpu_addr);
4217                     tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4218                     break;
4219                 case 0x0b: /* V9 ldx */
4220                     ABI32_MASK(cpu_addr);
4221                     tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4222                     break;
4223                 case 0x18: /* V9 ldswa */
4224                     save_state(dc, cpu_cond);
4225                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4226                     break;
4227                 case 0x1b: /* V9 ldxa */
4228                     save_state(dc, cpu_cond);
4229                     gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4230                     break;
4231                 case 0x2d: /* V9 prefetch, no effect */
4232                     goto skip_move;
4233                 case 0x30: /* V9 ldfa */
4234                     save_state(dc, cpu_cond);
4235                     gen_ldf_asi(cpu_addr, insn, 4, rd);
4236                     goto skip_move;
4237                 case 0x33: /* V9 lddfa */
4238                     save_state(dc, cpu_cond);
4239                     gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4240                     goto skip_move;
4241                 case 0x3d: /* V9 prefetcha, no effect */
4242                     goto skip_move;
4243                 case 0x32: /* V9 ldqfa */
4244                     CHECK_FPU_FEATURE(dc, FLOAT128);
4245                     save_state(dc, cpu_cond);
4246                     gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4247                     goto skip_move;
4248 #endif
4249                 default:
4250                     goto illegal_insn;
4251                 }
4252                 gen_movl_TN_reg(rd, cpu_val);
4253 #ifdef TARGET_SPARC64
4254             skip_move: ;
4255 #endif
4256             } else if (xop >= 0x20 && xop < 0x24) {
4257                 if (gen_trap_ifnofpu(dc, cpu_cond))
4258                     goto jmp_insn;
4259                 save_state(dc, cpu_cond);
4260                 switch (xop) {
4261                 case 0x20:      /* load fpreg */
4262                     ABI32_MASK(cpu_addr);
4263                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4264                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4265                                    offsetof(CPUState, fpr[rd]));
4266                     break;
4267                 case 0x21:      /* load fsr */
4268                     ABI32_MASK(cpu_addr);
4269                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4270                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4271                                    offsetof(CPUState, ft0));
4272                     tcg_gen_helper_0_0(helper_ldfsr);
4273                     break;
4274                 case 0x22:      /* load quad fpreg */
4275                     CHECK_FPU_FEATURE(dc, FLOAT128);
4276                     tcg_gen_helper_0_2(helper_ldqf, cpu_addr,
4277                                        tcg_const_i32(dc->mem_idx));
4278                     gen_op_store_QT0_fpr(QFPREG(rd));
4279                     break;
4280                 case 0x23:      /* load double fpreg */
4281                     tcg_gen_helper_0_2(helper_lddf, cpu_addr,
4282                                        tcg_const_i32(dc->mem_idx));
4283                     gen_op_store_DT0_fpr(DFPREG(rd));
4284                     break;
4285                 default:
4286                     goto illegal_insn;
4287                 }
4288             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4289                        xop == 0xe || xop == 0x1e) {
4290                 gen_movl_reg_TN(rd, cpu_val);
4291                 switch (xop) {
4292                 case 0x4: /* store word */
4293                     ABI32_MASK(cpu_addr);
4294                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4295                     break;
4296                 case 0x5: /* store byte */
4297                     ABI32_MASK(cpu_addr);
4298                     tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4299                     break;
4300                 case 0x6: /* store halfword */
4301                     ABI32_MASK(cpu_addr);
4302                     tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4303                     break;
4304                 case 0x7: /* store double word */
4305                     if (rd & 1)
4306                         goto illegal_insn;
4307                     else {
4308                         TCGv r_low;
4309
4310                         save_state(dc, cpu_cond);
4311                         ABI32_MASK(cpu_addr);
4312                         tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4313                                            tcg_const_i32(7)); // XXX remove
4314                         r_low = tcg_temp_new(TCG_TYPE_TL);
4315                         gen_movl_reg_TN(rd + 1, r_low);
4316                         tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4317                                            r_low);
4318                         tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4319                     }
4320                     break;
4321 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4322                 case 0x14: /* store word alternate */
4323 #ifndef TARGET_SPARC64
4324                     if (IS_IMM)
4325                         goto illegal_insn;
4326                     if (!supervisor(dc))
4327                         goto priv_insn;
4328 #endif
4329                     save_state(dc, cpu_cond);
4330                     gen_st_asi(cpu_val, cpu_addr, insn, 4);
4331                     break;
4332                 case 0x15: /* store byte alternate */
4333 #ifndef TARGET_SPARC64
4334                     if (IS_IMM)
4335                         goto illegal_insn;
4336                     if (!supervisor(dc))
4337                         goto priv_insn;
4338 #endif
4339                     save_state(dc, cpu_cond);
4340                     gen_st_asi(cpu_val, cpu_addr, insn, 1);
4341                     break;
4342                 case 0x16: /* store halfword alternate */
4343 #ifndef TARGET_SPARC64
4344                     if (IS_IMM)
4345                         goto illegal_insn;
4346                     if (!supervisor(dc))
4347                         goto priv_insn;
4348 #endif
4349                     save_state(dc, cpu_cond);
4350                     gen_st_asi(cpu_val, cpu_addr, insn, 2);
4351                     break;
4352                 case 0x17: /* store double word alternate */
4353 #ifndef TARGET_SPARC64
4354                     if (IS_IMM)
4355                         goto illegal_insn;
4356                     if (!supervisor(dc))
4357                         goto priv_insn;
4358 #endif
4359                     if (rd & 1)
4360                         goto illegal_insn;
4361                     else {
4362                         save_state(dc, cpu_cond);
4363                         gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4364                     }
4365                     break;
4366 #endif
4367 #ifdef TARGET_SPARC64
4368                 case 0x0e: /* V9 stx */
4369                     ABI32_MASK(cpu_addr);
4370                     tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4371                     break;
4372                 case 0x1e: /* V9 stxa */
4373                     save_state(dc, cpu_cond);
4374                     gen_st_asi(cpu_val, cpu_addr, insn, 8);
4375                     break;
4376 #endif
4377                 default:
4378                     goto illegal_insn;
4379                 }
4380             } else if (xop > 0x23 && xop < 0x28) {
4381                 if (gen_trap_ifnofpu(dc, cpu_cond))
4382                     goto jmp_insn;
4383                 save_state(dc, cpu_cond);
4384                 switch (xop) {
4385                 case 0x24: /* store fpreg */
4386                     ABI32_MASK(cpu_addr);
4387                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4388                                    offsetof(CPUState, fpr[rd]));
4389                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4390                     break;
4391                 case 0x25: /* stfsr, V9 stxfsr */
4392                     ABI32_MASK(cpu_addr);
4393                     tcg_gen_helper_0_0(helper_stfsr);
4394                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4395                                    offsetof(CPUState, ft0));
4396                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4397                     break;
4398                 case 0x26:
4399 #ifdef TARGET_SPARC64
4400                     /* V9 stqf, store quad fpreg */
4401                     CHECK_FPU_FEATURE(dc, FLOAT128);
4402                     gen_op_load_fpr_QT0(QFPREG(rd));
4403                     tcg_gen_helper_0_2(helper_stqf, cpu_addr,
4404                                        tcg_const_i32(dc->mem_idx));
4405                     break;
4406 #else /* !TARGET_SPARC64 */
4407                     /* stdfq, store floating point queue */
4408 #if defined(CONFIG_USER_ONLY)
4409                     goto illegal_insn;
4410 #else
4411                     if (!supervisor(dc))
4412                         goto priv_insn;
4413                     if (gen_trap_ifnofpu(dc, cpu_cond))
4414                         goto jmp_insn;
4415                     goto nfq_insn;
4416 #endif
4417 #endif
4418                 case 0x27: /* store double fpreg */
4419                     gen_op_load_fpr_DT0(DFPREG(rd));
4420                     tcg_gen_helper_0_2(helper_stdf, cpu_addr,
4421                                        tcg_const_i32(dc->mem_idx));
4422                     break;
4423                 default:
4424                     goto illegal_insn;
4425                 }
4426             } else if (xop > 0x33 && xop < 0x3f) {
4427                 save_state(dc, cpu_cond);
4428                 switch (xop) {
4429 #ifdef TARGET_SPARC64
4430                 case 0x34: /* V9 stfa */
4431                     gen_op_load_fpr_FT0(rd);
4432                     gen_stf_asi(cpu_addr, insn, 4, rd);
4433                     break;
4434                 case 0x36: /* V9 stqfa */
4435                     CHECK_FPU_FEATURE(dc, FLOAT128);
4436                     tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4437                                        tcg_const_i32(7));
4438                     gen_op_load_fpr_QT0(QFPREG(rd));
4439                     gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4440                     break;
4441                 case 0x37: /* V9 stdfa */
4442                     gen_op_load_fpr_DT0(DFPREG(rd));
4443                     gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4444                     break;
4445                 case 0x3c: /* V9 casa */
4446                     gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4447                     gen_movl_TN_reg(rd, cpu_val);
4448                     break;
4449                 case 0x3e: /* V9 casxa */
4450                     gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4451                     gen_movl_TN_reg(rd, cpu_val);
4452                     break;
4453 #else
4454                 case 0x34: /* stc */
4455                 case 0x35: /* stcsr */
4456                 case 0x36: /* stdcq */
4457                 case 0x37: /* stdc */
4458                     goto ncp_insn;
4459 #endif
4460                 default:
4461                     goto illegal_insn;
4462                 }
4463             }
4464             else
4465                 goto illegal_insn;
4466         }
4467         break;
4468     }
4469     /* default case for non jump instructions */
4470     if (dc->npc == DYNAMIC_PC) {
4471         dc->pc = DYNAMIC_PC;
4472         gen_op_next_insn();
4473     } else if (dc->npc == JUMP_PC) {
4474         /* we can do a static jump */
4475         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4476         dc->is_br = 1;
4477     } else {
4478         dc->pc = dc->npc;
4479         dc->npc = dc->npc + 4;
4480     }
4481  jmp_insn:
4482     return;
4483  illegal_insn:
4484     save_state(dc, cpu_cond);
4485     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
4486     dc->is_br = 1;
4487     return;
4488  unimp_flush:
4489     save_state(dc, cpu_cond);
4490     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_UNIMP_FLUSH));
4491     dc->is_br = 1;
4492     return;
4493 #if !defined(CONFIG_USER_ONLY)
4494  priv_insn:
4495     save_state(dc, cpu_cond);
4496     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
4497     dc->is_br = 1;
4498     return;
4499 #endif
4500  nfpu_insn:
4501     save_state(dc, cpu_cond);
4502     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4503     dc->is_br = 1;
4504     return;
4505 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4506  nfq_insn:
4507     save_state(dc, cpu_cond);
4508     gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4509     dc->is_br = 1;
4510     return;
4511 #endif
4512 #ifndef TARGET_SPARC64
4513  ncp_insn:
4514     save_state(dc, cpu_cond);
4515     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
4516     dc->is_br = 1;
4517     return;
4518 #endif
4519 }
4520
4521 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4522                                                  int spc, CPUSPARCState *env)
4523 {
4524     target_ulong pc_start, last_pc;
4525     uint16_t *gen_opc_end;
4526     DisasContext dc1, *dc = &dc1;
4527     int j, lj = -1;
4528
4529     memset(dc, 0, sizeof(DisasContext));
4530     dc->tb = tb;
4531     pc_start = tb->pc;
4532     dc->pc = pc_start;
4533     last_pc = dc->pc;
4534     dc->npc = (target_ulong) tb->cs_base;
4535     dc->mem_idx = cpu_mmu_index(env);
4536     dc->features = env->features;
4537     if ((dc->features & CPU_FEATURE_FLOAT)) {
4538         dc->fpu_enabled = cpu_fpu_enabled(env);
4539 #if defined(CONFIG_USER_ONLY)
4540         dc->features |= CPU_FEATURE_FLOAT128;
4541 #endif
4542     } else
4543         dc->fpu_enabled = 0;
4544     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4545
4546     cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4547     cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4548     cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4549
4550     do {
4551         if (env->nb_breakpoints > 0) {
4552             for(j = 0; j < env->nb_breakpoints; j++) {
4553                 if (env->breakpoints[j] == dc->pc) {
4554                     if (dc->pc != pc_start)
4555                         save_state(dc, cpu_cond);
4556                     tcg_gen_helper_0_0(helper_debug);
4557                     tcg_gen_exit_tb(0);
4558                     dc->is_br = 1;
4559                     goto exit_gen_loop;
4560                 }
4561             }
4562         }
4563         if (spc) {
4564             if (loglevel > 0)
4565                 fprintf(logfile, "Search PC...\n");
4566             j = gen_opc_ptr - gen_opc_buf;
4567             if (lj < j) {
4568                 lj++;
4569                 while (lj < j)
4570                     gen_opc_instr_start[lj++] = 0;
4571                 gen_opc_pc[lj] = dc->pc;
4572                 gen_opc_npc[lj] = dc->npc;
4573                 gen_opc_instr_start[lj] = 1;
4574             }
4575         }
4576         last_pc = dc->pc;
4577         disas_sparc_insn(dc);
4578
4579         if (dc->is_br)
4580             break;
4581         /* if the next PC is different, we abort now */
4582         if (dc->pc != (last_pc + 4))
4583             break;
4584         /* if we reach a page boundary, we stop generation so that the
4585            PC of a TT_TFAULT exception is always in the right page */
4586         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4587             break;
4588         /* if single step mode, we generate only one instruction and
4589            generate an exception */
4590         if (env->singlestep_enabled) {
4591             tcg_gen_movi_tl(cpu_pc, dc->pc);
4592             tcg_gen_exit_tb(0);
4593             break;
4594         }
4595     } while ((gen_opc_ptr < gen_opc_end) &&
4596              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4597
4598  exit_gen_loop:
4599     if (!dc->is_br) {
4600         if (dc->pc != DYNAMIC_PC &&
4601             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4602             /* static PC and NPC: we can use direct chaining */
4603             gen_goto_tb(dc, 0, dc->pc, dc->npc);
4604         } else {
4605             if (dc->pc != DYNAMIC_PC)
4606                 tcg_gen_movi_tl(cpu_pc, dc->pc);
4607             save_npc(dc, cpu_cond);
4608             tcg_gen_exit_tb(0);
4609         }
4610     }
4611     *gen_opc_ptr = INDEX_op_end;
4612     if (spc) {
4613         j = gen_opc_ptr - gen_opc_buf;
4614         lj++;
4615         while (lj <= j)
4616             gen_opc_instr_start[lj++] = 0;
4617 #if 0
4618         if (loglevel > 0) {
4619             page_dump(logfile);
4620         }
4621 #endif
4622         gen_opc_jump_pc[0] = dc->jump_pc[0];
4623         gen_opc_jump_pc[1] = dc->jump_pc[1];
4624     } else {
4625         tb->size = last_pc + 4 - pc_start;
4626     }
4627 #ifdef DEBUG_DISAS
4628     if (loglevel & CPU_LOG_TB_IN_ASM) {
4629         fprintf(logfile, "--------------\n");
4630         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4631         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4632         fprintf(logfile, "\n");
4633     }
4634 #endif
4635     return 0;
4636 }
4637
4638 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4639 {
4640     return gen_intermediate_code_internal(tb, 0, env);
4641 }
4642
4643 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4644 {
4645     return gen_intermediate_code_internal(tb, 1, env);
4646 }
4647
4648 void gen_intermediate_code_init(CPUSPARCState *env)
4649 {
4650     unsigned int i;
4651     static int inited;
4652     static const char * const gregnames[8] = {
4653         NULL, // g0 not used
4654         "g1",
4655         "g2",
4656         "g3",
4657         "g4",
4658         "g5",
4659         "g6",
4660         "g7",
4661     };
4662
4663     /* init various static tables */
4664     if (!inited) {
4665         inited = 1;
4666
4667         cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4668         cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4669                                          offsetof(CPUState, regwptr),
4670                                          "regwptr");
4671 #ifdef TARGET_SPARC64
4672         cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4673                                      TCG_AREG0, offsetof(CPUState, xcc),
4674                                      "xcc");
4675 #endif
4676         /* XXX: T0 and T1 should be temporaries */
4677         cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4678                                       TCG_AREG0, offsetof(CPUState, t0), "T0");
4679         cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4680                                       TCG_AREG0, offsetof(CPUState, t1), "T1");
4681         cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4682                                       TCG_AREG0, offsetof(CPUState, cond),
4683                                       "cond");
4684         cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4685                                         TCG_AREG0, offsetof(CPUState, cc_src),
4686                                         "cc_src");
4687         cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4688                                          offsetof(CPUState, cc_src2),
4689                                          "cc_src2");
4690         cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4691                                         TCG_AREG0, offsetof(CPUState, cc_dst),
4692                                         "cc_dst");
4693         cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4694                                      TCG_AREG0, offsetof(CPUState, psr),
4695                                      "psr");
4696         cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4697                                      TCG_AREG0, offsetof(CPUState, fsr),
4698                                      "fsr");
4699         cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4700                                     TCG_AREG0, offsetof(CPUState, pc),
4701                                     "pc");
4702         cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4703                                     TCG_AREG0, offsetof(CPUState, npc),
4704                                     "npc");
4705         for (i = 1; i < 8; i++)
4706             cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4707                                               offsetof(CPUState, gregs[i]),
4708                                               gregnames[i]);
4709         /* register helpers */
4710
4711 #undef DEF_HELPER
4712 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4713 #include "helper.h"
4714     }
4715 }
4716
4717 void gen_pc_load(CPUState *env, TranslationBlock *tb,
4718                 unsigned long searched_pc, int pc_pos, void *puc)
4719 {
4720     target_ulong npc;
4721     env->pc = gen_opc_pc[pc_pos];
4722     npc = gen_opc_npc[pc_pos];
4723     if (npc == 1) {
4724         /* dynamic NPC: already stored */
4725     } else if (npc == 2) {
4726         target_ulong t2 = (target_ulong)(unsigned long)puc;
4727         /* jump PC: use T2 and the jump targets of the translation */
4728         if (t2)
4729             env->npc = gen_opc_jump_pc[0];
4730         else
4731             env->npc = gen_opc_jump_pc[1];
4732     } else {
4733         env->npc = npc;
4734     }
4735 }