git.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23    TODO-list:
  24
  25    Rest of V9 instructions, VIS instructions
  26    NPC/PC static optimisations (use JUMP_TB when possible)
  27    Optimize synthetic instructions
  28 */
  29
  30 #include <stdarg.h>
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <string.h>
  34 #include <inttypes.h>
  35
  36 #include "cpu.h"
  37 #include "exec-all.h"
  38 #include "disas.h"
  39 #include "helper.h"
  40 #include "tcg-op.h"
  41
  42 #define DEBUG_DISAS
  43
  44 #define DYNAMIC_PC  1 /* dynamic pc value */
  45 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  46                          according to jump_pc[T2] */
  47
  48 /* global register indexes */
  49 static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
  50 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
  51 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
  52 #ifdef TARGET_SPARC64
  53 static TCGv cpu_xcc;
  54 #endif
  55 /* local register indexes (only used inside old micro ops) */
  56 static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
  57
  58 typedef struct DisasContext {
  59     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  60     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  61     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  62     int is_br;
  63     int mem_idx;
  64     int fpu_enabled;
  65     struct TranslationBlock *tb;
  66 } DisasContext;
  67
  68 extern FILE *logfile;
  69 extern int loglevel;
  70
  71 // This function uses non-native bit order
  72 #define GET_FIELD(X, FROM, TO) \
  73   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  74
  75 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  76 #define GET_FIELD_SP(X, FROM, TO) \
  77     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  78
  79 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  80 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
  81
  82 #ifdef TARGET_SPARC64
  83 #define FFPREG(r) (r)
  84 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
  85 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
  86 #else
  87 #define FFPREG(r) (r)
  88 #define DFPREG(r) (r & 0x1e)
  89 #define QFPREG(r) (r & 0x1c)
  90 #endif
  91
  92 static int sign_extend(int x, int len)
  93 {
  94     len = 32 - len;
  95     return (x << len) >> len;
  96 }
  97
  98 #define IS_IMM (insn & (1<<13))
  99
 100 /* floating point registers moves */
 101 static void gen_op_load_fpr_FT0(unsigned int src)
 102 {
 103     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 104     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
 105 }
 106
 107 static void gen_op_load_fpr_FT1(unsigned int src)
 108 {
 109     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 110     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
 111 }
 112
 113 static void gen_op_store_FT0_fpr(unsigned int dst)
 114 {
 115     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
 116     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 117 }
 118
 119 static void gen_op_load_fpr_DT0(unsigned int src)
 120 {
 121     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 122     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
 123     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 124     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
 125 }
 126
 127 static void gen_op_load_fpr_DT1(unsigned int src)
 128 {
 129     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 130     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
 131     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 132     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
 133 }
 134
 135 static void gen_op_store_DT0_fpr(unsigned int dst)
 136 {
 137     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
 138     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 139     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
 140     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 141 }
 142
 143 #ifdef CONFIG_USER_ONLY
 144 static void gen_op_load_fpr_QT0(unsigned int src)
 145 {
 146     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 147     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
 148     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 149     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
 150     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 151     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
 152     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 153     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
 154 }
 155
 156 static void gen_op_load_fpr_QT1(unsigned int src)
 157 {
 158     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 159     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
 160     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 161     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
 162     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 163     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
 164     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 165     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
 166 }
 167
 168 static void gen_op_store_QT0_fpr(unsigned int dst)
 169 {
 170     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
 171     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 172     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
 173     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 174     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
 175     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
 176     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
 177     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
 178 }
 179 #endif
 180
 181 /* moves */
 182 #ifdef CONFIG_USER_ONLY
 183 #define supervisor(dc) 0
 184 #ifdef TARGET_SPARC64
 185 #define hypervisor(dc) 0
 186 #endif
 187 #define gen_op_ldst(name)        gen_op_##name##_raw()
 188 #else
 189 #define supervisor(dc) (dc->mem_idx >= 1)
 190 #ifdef TARGET_SPARC64
 191 #define hypervisor(dc) (dc->mem_idx == 2)
 192 #define OP_LD_TABLE(width)                                              \
 193     static GenOpFunc * const gen_op_##width[] = {                       \
 194         &gen_op_##width##_user,                                         \
 195         &gen_op_##width##_kernel,                                       \
 196         &gen_op_##width##_hypv,                                         \
 197     };
 198 #else
 199 #define OP_LD_TABLE(width)                                              \
 200     static GenOpFunc * const gen_op_##width[] = {                       \
 201         &gen_op_##width##_user,                                         \
 202         &gen_op_##width##_kernel,                                       \
 203     };
 204 #endif
 205 #define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
 206 #endif
 207
 208 #ifndef CONFIG_USER_ONLY
 209 #ifdef __i386__
 210 OP_LD_TABLE(std);
 211 #endif /* __i386__ */
 212 OP_LD_TABLE(stdf);
 213 OP_LD_TABLE(lddf);
 214 #endif
 215
 216 #ifdef TARGET_ABI32
 217 #define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
 218 #else
 219 #define ABI32_MASK(addr)
 220 #endif
 221
 222 static inline void gen_movl_reg_TN(int reg, TCGv tn)
 223 {
 224     if (reg == 0)
 225         tcg_gen_movi_tl(tn, 0);
 226     else if (reg < 8)
 227         tcg_gen_mov_tl(tn, cpu_gregs[reg]);
 228     else {
 229         tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 230     }
 231 }
 232
 233 static inline void gen_movl_TN_reg(int reg, TCGv tn)
 234 {
 235     if (reg == 0)
 236         return;
 237     else if (reg < 8)
 238         tcg_gen_mov_tl(cpu_gregs[reg], tn);
 239     else {
 240         tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 241     }
 242 }
 243
 244 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 245                                target_ulong pc, target_ulong npc)
 246 {
 247     TranslationBlock *tb;
 248
 249     tb = s->tb;
 250     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 251         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 252         /* jump to same page: we can use a direct jump */
 253         tcg_gen_goto_tb(tb_num);
 254         tcg_gen_movi_tl(cpu_pc, pc);
 255         tcg_gen_movi_tl(cpu_npc, npc);
 256         tcg_gen_exit_tb((long)tb + tb_num);
 257     } else {
 258         /* jump to another page: currently not optimized */
 259         tcg_gen_movi_tl(cpu_pc, pc);
 260         tcg_gen_movi_tl(cpu_npc, npc);
 261         tcg_gen_exit_tb(0);
 262     }
 263 }
 264
 265 // XXX suboptimal
 266 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
 267 {
 268     tcg_gen_extu_i32_tl(reg, src);
 269     tcg_gen_shri_tl(reg, reg, 23);
 270     tcg_gen_andi_tl(reg, reg, 0x1);
 271 }
 272
 273 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
 274 {
 275     tcg_gen_extu_i32_tl(reg, src);
 276     tcg_gen_shri_tl(reg, reg, 22);
 277     tcg_gen_andi_tl(reg, reg, 0x1);
 278 }
 279
 280 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
 281 {
 282     tcg_gen_extu_i32_tl(reg, src);
 283     tcg_gen_shri_tl(reg, reg, 21);
 284     tcg_gen_andi_tl(reg, reg, 0x1);
 285 }
 286
 287 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
 288 {
 289     tcg_gen_extu_i32_tl(reg, src);
 290     tcg_gen_shri_tl(reg, reg, 20);
 291     tcg_gen_andi_tl(reg, reg, 0x1);
 292 }
 293
 294 static inline void gen_cc_clear_icc(void)
 295 {
 296     tcg_gen_movi_i32(cpu_psr, 0);
 297 }
 298
 299 #ifdef TARGET_SPARC64
 300 static inline void gen_cc_clear_xcc(void)
 301 {
 302     tcg_gen_movi_i32(cpu_xcc, 0);
 303 }
 304 #endif
 305
 306 /* old op:
 307     if (!T0)
 308         env->psr |= PSR_ZERO;
 309     if ((int32_t) T0 < 0)
 310         env->psr |= PSR_NEG;
 311 */
 312 static inline void gen_cc_NZ_icc(TCGv dst)
 313 {
 314     TCGv r_temp;
 315     int l1, l2;
 316
 317     l1 = gen_new_label();
 318     l2 = gen_new_label();
 319     r_temp = tcg_temp_new(TCG_TYPE_TL);
 320     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 321     tcg_gen_brcond_tl(TCG_COND_NE, r_temp, tcg_const_tl(0), l1);
 322     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
 323     gen_set_label(l1);
 324     tcg_gen_ext_i32_tl(r_temp, dst);
 325     tcg_gen_brcond_tl(TCG_COND_GE, r_temp, tcg_const_tl(0), l2);
 326     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
 327     gen_set_label(l2);
 328 }
 329
 330 #ifdef TARGET_SPARC64
 331 static inline void gen_cc_NZ_xcc(TCGv dst)
 332 {
 333     int l1, l2;
 334
 335     l1 = gen_new_label();
 336     l2 = gen_new_label();
 337     tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l1);
 338     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
 339     gen_set_label(l1);
 340     tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l2);
 341     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
 342     gen_set_label(l2);
 343 }
 344 #endif
 345
 346 /* old op:
 347     if (T0 < src1)
 348         env->psr |= PSR_CARRY;
 349 */
 350 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
 351 {
 352     TCGv r_temp;
 353     int l1;
 354
 355     l1 = gen_new_label();
 356     r_temp = tcg_temp_new(TCG_TYPE_TL);
 357     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 358     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 359     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 360     gen_set_label(l1);
 361 }
 362
 363 #ifdef TARGET_SPARC64
 364 static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
 365 {
 366     int l1;
 367
 368     l1 = gen_new_label();
 369     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 370     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 371     gen_set_label(l1);
 372 }
 373 #endif
 374
 375 /* old op:
 376     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
 377         env->psr |= PSR_OVF;
 378 */
 379 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
 380 {
 381     TCGv r_temp;
 382     int l1;
 383
 384     l1 = gen_new_label();
 385
 386     r_temp = tcg_temp_new(TCG_TYPE_TL);
 387     tcg_gen_xor_tl(r_temp, src1, src2);
 388     tcg_gen_xori_tl(r_temp, r_temp, -1);
 389     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 390     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 391     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 392     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 393     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 394     gen_set_label(l1);
 395 }
 396
 397 #ifdef TARGET_SPARC64
 398 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
 399 {
 400     TCGv r_temp;
 401     int l1;
 402
 403     l1 = gen_new_label();
 404
 405     r_temp = tcg_temp_new(TCG_TYPE_TL);
 406     tcg_gen_xor_tl(r_temp, src1, src2);
 407     tcg_gen_xori_tl(r_temp, r_temp, -1);
 408     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 409     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 410     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 411     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 412     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
 413     gen_set_label(l1);
 414 }
 415 #endif
 416
 417 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
 418 {
 419     TCGv r_temp;
 420     int l1;
 421
 422     l1 = gen_new_label();
 423
 424     r_temp = tcg_temp_new(TCG_TYPE_TL);
 425     tcg_gen_xor_tl(r_temp, src1, src2);
 426     tcg_gen_xori_tl(r_temp, r_temp, -1);
 427     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 428     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 429     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 430     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 431     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 432     gen_set_label(l1);
 433 }
 434
 435 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
 436 {
 437     int l1;
 438
 439     l1 = gen_new_label();
 440     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 441     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 442     tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
 443     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 444     gen_set_label(l1);
 445 }
 446
 447 static inline void gen_tag_tv(TCGv src1, TCGv src2)
 448 {
 449     int l1;
 450
 451     l1 = gen_new_label();
 452     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 453     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 454     tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
 455     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 456     gen_set_label(l1);
 457 }
 458
 459 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
 460 {
 461     tcg_gen_mov_tl(cpu_cc_src, src1);
 462     tcg_gen_add_tl(dst, src1, src2);
 463     gen_cc_clear_icc();
 464     gen_cc_NZ_icc(dst);
 465     gen_cc_C_add_icc(dst, cpu_cc_src);
 466     gen_cc_V_add_icc(dst, cpu_cc_src, src2);
 467 #ifdef TARGET_SPARC64
 468     gen_cc_clear_xcc();
 469     gen_cc_NZ_xcc(dst);
 470     gen_cc_C_add_xcc(dst, cpu_cc_src);
 471     gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
 472 #endif
 473 }
 474
 475 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
 476 {
 477     tcg_gen_mov_tl(cpu_cc_src, src1);
 478     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 479     tcg_gen_add_tl(dst, src1, cpu_tmp0);
 480     gen_cc_clear_icc();
 481     gen_cc_C_add_icc(dst, cpu_cc_src);
 482 #ifdef TARGET_SPARC64
 483     gen_cc_clear_xcc();
 484     gen_cc_C_add_xcc(dst, cpu_cc_src);
 485 #endif
 486     tcg_gen_add_tl(dst, dst, src2);
 487     gen_cc_NZ_icc(dst);
 488     gen_cc_C_add_icc(dst, cpu_cc_src);
 489     gen_cc_V_add_icc(dst, cpu_cc_src, src2);
 490 #ifdef TARGET_SPARC64
 491     gen_cc_NZ_xcc(dst);
 492     gen_cc_C_add_xcc(dst, cpu_cc_src);
 493     gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
 494 #endif
 495 }
 496
 497 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
 498 {
 499     tcg_gen_mov_tl(cpu_cc_src, src1);
 500     tcg_gen_add_tl(dst, src1, src2);
 501     gen_cc_clear_icc();
 502     gen_cc_NZ_icc(dst);
 503     gen_cc_C_add_icc(dst, cpu_cc_src);
 504     gen_cc_V_add_icc(dst, cpu_cc_src, src2);
 505     gen_cc_V_tag(cpu_cc_src, src2);
 506 #ifdef TARGET_SPARC64
 507     gen_cc_clear_xcc();
 508     gen_cc_NZ_xcc(dst);
 509     gen_cc_C_add_xcc(dst, cpu_cc_src);
 510     gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
 511 #endif
 512 }
 513
 514 static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
 515 {
 516     gen_tag_tv(src1, src2);
 517     tcg_gen_mov_tl(cpu_cc_src, src1);
 518     tcg_gen_add_tl(dst, src1, src2);
 519     gen_add_tv(dst, cpu_cc_src, src2);
 520     gen_cc_clear_icc();
 521     gen_cc_NZ_icc(dst);
 522     gen_cc_C_add_icc(dst, cpu_cc_src);
 523 #ifdef TARGET_SPARC64
 524     gen_cc_clear_xcc();
 525     gen_cc_NZ_xcc(dst);
 526     gen_cc_C_add_xcc(dst, cpu_cc_src);
 527     gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
 528 #endif
 529 }
 530
 531 /* old op:
 532     if (src1 < T1)
 533         env->psr |= PSR_CARRY;
 534 */
 535 static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
 536 {
 537     TCGv r_temp1, r_temp2;
 538     int l1;
 539
 540     l1 = gen_new_label();
 541     r_temp1 = tcg_temp_new(TCG_TYPE_TL);
 542     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 543     tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
 544     tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
 545     tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
 546     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 547     gen_set_label(l1);
 548 }
 549
 550 #ifdef TARGET_SPARC64
 551 static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
 552 {
 553     int l1;
 554
 555     l1 = gen_new_label();
 556     tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
 557     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 558     gen_set_label(l1);
 559 }
 560 #endif
 561
 562 /* old op:
 563     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
 564         env->psr |= PSR_OVF;
 565 */
 566 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
 567 {
 568     TCGv r_temp;
 569     int l1;
 570
 571     l1 = gen_new_label();
 572
 573     r_temp = tcg_temp_new(TCG_TYPE_TL);
 574     tcg_gen_xor_tl(r_temp, src1, src2);
 575     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 576     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 577     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 578     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 579     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 580     gen_set_label(l1);
 581 }
 582
 583 #ifdef TARGET_SPARC64
 584 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
 585 {
 586     TCGv r_temp;
 587     int l1;
 588
 589     l1 = gen_new_label();
 590
 591     r_temp = tcg_temp_new(TCG_TYPE_TL);
 592     tcg_gen_xor_tl(r_temp, src1, src2);
 593     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 594     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 595     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 596     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 597     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
 598     gen_set_label(l1);
 599 }
 600 #endif
 601
 602 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
 603 {
 604     TCGv r_temp;
 605     int l1;
 606
 607     l1 = gen_new_label();
 608
 609     r_temp = tcg_temp_new(TCG_TYPE_TL);
 610     tcg_gen_xor_tl(r_temp, src1, src2);
 611     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 612     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 613     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 614     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 615     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 616     gen_set_label(l1);
 617     tcg_gen_discard_tl(r_temp);
 618 }
 619
 620 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
 621 {
 622     tcg_gen_mov_tl(cpu_cc_src, src1);
 623     tcg_gen_sub_tl(dst, src1, src2);
 624     gen_cc_clear_icc();
 625     gen_cc_NZ_icc(dst);
 626     gen_cc_C_sub_icc(cpu_cc_src, src2);
 627     gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
 628 #ifdef TARGET_SPARC64
 629     gen_cc_clear_xcc();
 630     gen_cc_NZ_xcc(dst);
 631     gen_cc_C_sub_xcc(cpu_cc_src, src2);
 632     gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
 633 #endif
 634 }
 635
 636 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
 637 {
 638     tcg_gen_mov_tl(cpu_cc_src, src1);
 639     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 640     tcg_gen_sub_tl(dst, src1, cpu_tmp0);
 641     gen_cc_clear_icc();
 642     gen_cc_C_sub_icc(dst, cpu_cc_src);
 643 #ifdef TARGET_SPARC64
 644     gen_cc_clear_xcc();
 645     gen_cc_C_sub_xcc(dst, cpu_cc_src);
 646 #endif
 647     tcg_gen_sub_tl(dst, dst, src2);
 648     gen_cc_NZ_icc(dst);
 649     gen_cc_C_sub_icc(dst, cpu_cc_src);
 650     gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
 651 #ifdef TARGET_SPARC64
 652     gen_cc_NZ_xcc(dst);
 653     gen_cc_C_sub_xcc(dst, cpu_cc_src);
 654     gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
 655 #endif
 656 }
 657
 658 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
 659 {
 660     tcg_gen_mov_tl(cpu_cc_src, src1);
 661     tcg_gen_sub_tl(dst, src1, src2);
 662     gen_cc_clear_icc();
 663     gen_cc_NZ_icc(dst);
 664     gen_cc_C_sub_icc(cpu_cc_src, src2);
 665     gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
 666     gen_cc_V_tag(cpu_cc_src, src2);
 667 #ifdef TARGET_SPARC64
 668     gen_cc_clear_xcc();
 669     gen_cc_NZ_xcc(dst);
 670     gen_cc_C_sub_xcc(cpu_cc_src, src2);
 671     gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
 672 #endif
 673 }
 674
 675 static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
 676 {
 677     gen_tag_tv(src1, src2);
 678     tcg_gen_mov_tl(cpu_cc_src, src1);
 679     tcg_gen_sub_tl(dst, src1, src2);
 680     gen_sub_tv(dst, cpu_cc_src, src2);
 681     gen_cc_clear_icc();
 682     gen_cc_NZ_icc(dst);
 683     gen_cc_C_sub_icc(cpu_cc_src, src2);
 684 #ifdef TARGET_SPARC64
 685     gen_cc_clear_xcc();
 686     gen_cc_NZ_xcc(dst);
 687     gen_cc_C_sub_xcc(cpu_cc_src, src2);
 688     gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
 689 #endif
 690 }
 691
 692 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
 693 {
 694     TCGv r_temp, r_temp2;
 695     int l1, l2;
 696
 697     l1 = gen_new_label();
 698     l2 = gen_new_label();
 699     r_temp = tcg_temp_new(TCG_TYPE_TL);
 700     r_temp2 = tcg_temp_new(TCG_TYPE_I32);
 701
 702     /* old op:
 703     if (!(env->y & 1))
 704         T1 = 0;
 705     */
 706     tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 707     tcg_gen_trunc_tl_i32(r_temp2, r_temp);
 708     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 709     tcg_gen_brcond_i32(TCG_COND_EQ, r_temp2, tcg_const_i32(0), l1);
 710     tcg_gen_mov_tl(cpu_cc_src2, src2);
 711     tcg_gen_br(l2);
 712     gen_set_label(l1);
 713     tcg_gen_movi_tl(cpu_cc_src2, 0);
 714     gen_set_label(l2);
 715
 716     // b2 = T0 & 1;
 717     // env->y = (b2 << 31) | (env->y >> 1);
 718     tcg_gen_trunc_tl_i32(r_temp2, src1);
 719     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 720     tcg_gen_shli_i32(r_temp2, r_temp2, 31);
 721     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 722     tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
 723     tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
 724     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 725
 726     // b1 = N ^ V;
 727     gen_mov_reg_N(cpu_tmp0, cpu_psr);
 728     gen_mov_reg_V(r_temp, cpu_psr);
 729     tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
 730
 731     // T0 = (b1 << 31) | (T0 >> 1);
 732     // src1 = T0;
 733     tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
 734     tcg_gen_shri_tl(cpu_cc_src, src1, 1);
 735     tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
 736
 737     /* do addition and update flags */
 738     tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
 739     tcg_gen_discard_tl(r_temp);
 740
 741     gen_cc_clear_icc();
 742     gen_cc_NZ_icc(dst);
 743     gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2);
 744     gen_cc_C_add_icc(dst, cpu_cc_src);
 745 }
 746
 747 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
 748 {
 749     TCGv r_temp, r_temp2;
 750
 751     r_temp = tcg_temp_new(TCG_TYPE_I64);
 752     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 753
 754     tcg_gen_extu_tl_i64(r_temp, src2);
 755     tcg_gen_extu_tl_i64(r_temp2, src1);
 756     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 757
 758     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 759     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 760     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 761 #ifdef TARGET_SPARC64
 762     tcg_gen_mov_i64(dst, r_temp2);
 763 #else
 764     tcg_gen_trunc_i64_tl(dst, r_temp2);
 765 #endif
 766
 767     tcg_gen_discard_i64(r_temp);
 768     tcg_gen_discard_i64(r_temp2);
 769 }
 770
 771 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
 772 {
 773     TCGv r_temp, r_temp2;
 774
 775     r_temp = tcg_temp_new(TCG_TYPE_I64);
 776     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 777
 778     tcg_gen_ext_tl_i64(r_temp, src2);
 779     tcg_gen_ext_tl_i64(r_temp2, src1);
 780     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 781
 782     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 783     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 784     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 785 #ifdef TARGET_SPARC64
 786     tcg_gen_mov_i64(dst, r_temp2);
 787 #else
 788     tcg_gen_trunc_i64_tl(dst, r_temp2);
 789 #endif
 790
 791     tcg_gen_discard_i64(r_temp);
 792     tcg_gen_discard_i64(r_temp2);
 793 }
 794
 795 #ifdef TARGET_SPARC64
 796 static inline void gen_trap_ifdivzero_tl(TCGv divisor)
 797 {
 798     int l1;
 799
 800     l1 = gen_new_label();
 801     tcg_gen_brcond_tl(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
 802     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO));
 803     gen_set_label(l1);
 804 }
 805
 806 static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
 807 {
 808     int l1, l2;
 809
 810     l1 = gen_new_label();
 811     l2 = gen_new_label();
 812     gen_trap_ifdivzero_tl(src2);
 813     tcg_gen_brcond_tl(TCG_COND_NE, src1, tcg_const_tl(INT64_MIN), l1);
 814     tcg_gen_brcond_tl(TCG_COND_NE, src2, tcg_const_tl(-1), l1);
 815     tcg_gen_movi_i64(dst, INT64_MIN);
 816     tcg_gen_br(l2);
 817     gen_set_label(l1);
 818     tcg_gen_div_i64(dst, src1, src2);
 819     gen_set_label(l2);
 820 }
 821 #endif
 822
 823 static inline void gen_op_div_cc(TCGv dst)
 824 {
 825     int l1;
 826
 827     gen_cc_clear_icc();
 828     gen_cc_NZ_icc(dst);
 829     l1 = gen_new_label();
 830     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
 831     tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
 832     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 833     gen_set_label(l1);
 834 }
 835
 836 static inline void gen_op_logic_cc(TCGv dst)
 837 {
 838     gen_cc_clear_icc();
 839     gen_cc_NZ_icc(dst);
 840 #ifdef TARGET_SPARC64
 841     gen_cc_clear_xcc();
 842     gen_cc_NZ_xcc(dst);
 843 #endif
 844 }
 845
 846 // 1
 847 static inline void gen_op_eval_ba(TCGv dst)
 848 {
 849     tcg_gen_movi_tl(dst, 1);
 850 }
 851
 852 // Z
 853 static inline void gen_op_eval_be(TCGv dst, TCGv src)
 854 {
 855     gen_mov_reg_Z(dst, src);
 856 }
 857
 858 // Z | (N ^ V)
 859 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
 860 {
 861     gen_mov_reg_N(cpu_tmp0, src);
 862     gen_mov_reg_V(dst, src);
 863     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 864     gen_mov_reg_Z(cpu_tmp0, src);
 865     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 866 }
 867
 868 // N ^ V
 869 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
 870 {
 871     gen_mov_reg_V(cpu_tmp0, src);
 872     gen_mov_reg_N(dst, src);
 873     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 874 }
 875
 876 // C | Z
 877 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
 878 {
 879     gen_mov_reg_Z(cpu_tmp0, src);
 880     gen_mov_reg_C(dst, src);
 881     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 882 }
 883
 884 // C
 885 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
 886 {
 887     gen_mov_reg_C(dst, src);
 888 }
 889
 890 // V
 891 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
 892 {
 893     gen_mov_reg_V(dst, src);
 894 }
 895
 896 // 0
 897 static inline void gen_op_eval_bn(TCGv dst)
 898 {
 899     tcg_gen_movi_tl(dst, 0);
 900 }
 901
 902 // N
 903 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
 904 {
 905     gen_mov_reg_N(dst, src);
 906 }
 907
 908 // !Z
 909 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
 910 {
 911     gen_mov_reg_Z(dst, src);
 912     tcg_gen_xori_tl(dst, dst, 0x1);
 913 }
 914
 915 // !(Z | (N ^ V))
 916 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
 917 {
 918     gen_mov_reg_N(cpu_tmp0, src);
 919     gen_mov_reg_V(dst, src);
 920     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 921     gen_mov_reg_Z(cpu_tmp0, src);
 922     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 923     tcg_gen_xori_tl(dst, dst, 0x1);
 924 }
 925
 926 // !(N ^ V)
 927 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
 928 {
 929     gen_mov_reg_V(cpu_tmp0, src);
 930     gen_mov_reg_N(dst, src);
 931     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 932     tcg_gen_xori_tl(dst, dst, 0x1);
 933 }
 934
 935 // !(C | Z)
 936 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
 937 {
 938     gen_mov_reg_Z(cpu_tmp0, src);
 939     gen_mov_reg_C(dst, src);
 940     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 941     tcg_gen_xori_tl(dst, dst, 0x1);
 942 }
 943
 944 // !C
 945 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
 946 {
 947     gen_mov_reg_C(dst, src);
 948     tcg_gen_xori_tl(dst, dst, 0x1);
 949 }
 950
 951 // !N
 952 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
 953 {
 954     gen_mov_reg_N(dst, src);
 955     tcg_gen_xori_tl(dst, dst, 0x1);
 956 }
 957
 958 // !V
 959 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
 960 {
 961     gen_mov_reg_V(dst, src);
 962     tcg_gen_xori_tl(dst, dst, 0x1);
 963 }
 964
 965 /*
 966   FPSR bit field FCC1 | FCC0:
 967    0 =
 968    1 <
 969    2 >
 970    3 unordered
 971 */
 972 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
 973                                     unsigned int fcc_offset)
 974 {
 975     tcg_gen_extu_i32_tl(reg, src);
 976     tcg_gen_shri_tl(reg, reg, 10 + fcc_offset);
 977     tcg_gen_andi_tl(reg, reg, 0x1);
 978 }
 979
 980 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
 981                                     unsigned int fcc_offset)
 982 {
 983     tcg_gen_extu_i32_tl(reg, src);
 984     tcg_gen_shri_tl(reg, reg, 11 + fcc_offset);
 985     tcg_gen_andi_tl(reg, reg, 0x1);
 986 }
 987
 988 // !0: FCC0 | FCC1
 989 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
 990                                     unsigned int fcc_offset)
 991 {
 992     gen_mov_reg_FCC0(dst, src, fcc_offset);
 993     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
 994     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 995 }
 996
 997 // 1 or 2: FCC0 ^ FCC1
 998 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
 999                                     unsigned int fcc_offset)
1000 {
1001     gen_mov_reg_FCC0(dst, src, fcc_offset);
1002     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1003     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1004 }
1005
1006 // 1 or 3: FCC0
1007 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1008                                     unsigned int fcc_offset)
1009 {
1010     gen_mov_reg_FCC0(dst, src, fcc_offset);
1011 }
1012
1013 // 1: FCC0 & !FCC1
1014 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1015                                     unsigned int fcc_offset)
1016 {
1017     gen_mov_reg_FCC0(dst, src, fcc_offset);
1018     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1019     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1020     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1021 }
1022
1023 // 2 or 3: FCC1
1024 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1025                                     unsigned int fcc_offset)
1026 {
1027     gen_mov_reg_FCC1(dst, src, fcc_offset);
1028 }
1029
1030 // 2: !FCC0 & FCC1
1031 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1032                                     unsigned int fcc_offset)
1033 {
1034     gen_mov_reg_FCC0(dst, src, fcc_offset);
1035     tcg_gen_xori_tl(dst, dst, 0x1);
1036     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1037     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1038 }
1039
1040 // 3: FCC0 & FCC1
1041 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1042                                     unsigned int fcc_offset)
1043 {
1044     gen_mov_reg_FCC0(dst, src, fcc_offset);
1045     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1046     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1047 }
1048
1049 // 0: !(FCC0 | FCC1)
1050 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1051                                     unsigned int fcc_offset)
1052 {
1053     gen_mov_reg_FCC0(dst, src, fcc_offset);
1054     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1055     tcg_gen_or_tl(dst, dst, cpu_tmp0);
1056     tcg_gen_xori_tl(dst, dst, 0x1);
1057 }
1058
1059 // 0 or 3: !(FCC0 ^ FCC1)
1060 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1061                                     unsigned int fcc_offset)
1062 {
1063     gen_mov_reg_FCC0(dst, src, fcc_offset);
1064     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1065     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1066     tcg_gen_xori_tl(dst, dst, 0x1);
1067 }
1068
1069 // 0 or 2: !FCC0
1070 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1071                                     unsigned int fcc_offset)
1072 {
1073     gen_mov_reg_FCC0(dst, src, fcc_offset);
1074     tcg_gen_xori_tl(dst, dst, 0x1);
1075 }
1076
1077 // !1: !(FCC0 & !FCC1)
1078 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1079                                     unsigned int fcc_offset)
1080 {
1081     gen_mov_reg_FCC0(dst, src, fcc_offset);
1082     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1083     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1084     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1085     tcg_gen_xori_tl(dst, dst, 0x1);
1086 }
1087
1088 // 0 or 1: !FCC1
1089 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1090                                     unsigned int fcc_offset)
1091 {
1092     gen_mov_reg_FCC1(dst, src, fcc_offset);
1093     tcg_gen_xori_tl(dst, dst, 0x1);
1094 }
1095
1096 // !2: !(!FCC0 & FCC1)
1097 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1098                                     unsigned int fcc_offset)
1099 {
1100     gen_mov_reg_FCC0(dst, src, fcc_offset);
1101     tcg_gen_xori_tl(dst, dst, 0x1);
1102     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1103     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1104     tcg_gen_xori_tl(dst, dst, 0x1);
1105 }
1106
1107 // !3: !(FCC0 & FCC1)
1108 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1109                                     unsigned int fcc_offset)
1110 {
1111     gen_mov_reg_FCC0(dst, src, fcc_offset);
1112     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1113     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1114     tcg_gen_xori_tl(dst, dst, 0x1);
1115 }
1116
1117 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1118                                target_ulong pc2, TCGv r_cond)
1119 {
1120     int l1;
1121
1122     l1 = gen_new_label();
1123
1124     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1125
1126     gen_goto_tb(dc, 0, pc1, pc1 + 4);
1127
1128     gen_set_label(l1);
1129     gen_goto_tb(dc, 1, pc2, pc2 + 4);
1130 }
1131
1132 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1133                                 target_ulong pc2, TCGv r_cond)
1134 {
1135     int l1;
1136
1137     l1 = gen_new_label();
1138
1139     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1140
1141     gen_goto_tb(dc, 0, pc2, pc1);
1142
1143     gen_set_label(l1);
1144     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1145 }
1146
1147 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1148                                       TCGv r_cond)
1149 {
1150     int l1, l2;
1151
1152     l1 = gen_new_label();
1153     l2 = gen_new_label();
1154
1155     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1156
1157     tcg_gen_movi_tl(cpu_npc, npc1);
1158     tcg_gen_br(l2);
1159
1160     gen_set_label(l1);
1161     tcg_gen_movi_tl(cpu_npc, npc2);
1162     gen_set_label(l2);
1163 }
1164
1165 /* call this function before using the condition register as it may
1166    have been set for a jump */
1167 static inline void flush_cond(DisasContext *dc, TCGv cond)
1168 {
1169     if (dc->npc == JUMP_PC) {
1170         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1171         dc->npc = DYNAMIC_PC;
1172     }
1173 }
1174
1175 static inline void save_npc(DisasContext *dc, TCGv cond)
1176 {
1177     if (dc->npc == JUMP_PC) {
1178         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1179         dc->npc = DYNAMIC_PC;
1180     } else if (dc->npc != DYNAMIC_PC) {
1181         tcg_gen_movi_tl(cpu_npc, dc->npc);
1182     }
1183 }
1184
1185 static inline void save_state(DisasContext *dc, TCGv cond)
1186 {
1187     tcg_gen_movi_tl(cpu_pc, dc->pc);
1188     save_npc(dc, cond);
1189 }
1190
1191 static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1192 {
1193     if (dc->npc == JUMP_PC) {
1194         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1195         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1196         dc->pc = DYNAMIC_PC;
1197     } else if (dc->npc == DYNAMIC_PC) {
1198         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1199         dc->pc = DYNAMIC_PC;
1200     } else {
1201         dc->pc = dc->npc;
1202     }
1203 }
1204
1205 static inline void gen_op_next_insn(void)
1206 {
1207     tcg_gen_mov_tl(cpu_pc, cpu_npc);
1208     tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1209 }
1210
1211 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1212 {
1213     TCGv r_src;
1214
1215 #ifdef TARGET_SPARC64
1216     if (cc)
1217         r_src = cpu_xcc;
1218     else
1219         r_src = cpu_psr;
1220 #else
1221     r_src = cpu_psr;
1222 #endif
1223     switch (cond) {
1224     case 0x0:
1225         gen_op_eval_bn(r_dst);
1226         break;
1227     case 0x1:
1228         gen_op_eval_be(r_dst, r_src);
1229         break;
1230     case 0x2:
1231         gen_op_eval_ble(r_dst, r_src);
1232         break;
1233     case 0x3:
1234         gen_op_eval_bl(r_dst, r_src);
1235         break;
1236     case 0x4:
1237         gen_op_eval_bleu(r_dst, r_src);
1238         break;
1239     case 0x5:
1240         gen_op_eval_bcs(r_dst, r_src);
1241         break;
1242     case 0x6:
1243         gen_op_eval_bneg(r_dst, r_src);
1244         break;
1245     case 0x7:
1246         gen_op_eval_bvs(r_dst, r_src);
1247         break;
1248     case 0x8:
1249         gen_op_eval_ba(r_dst);
1250         break;
1251     case 0x9:
1252         gen_op_eval_bne(r_dst, r_src);
1253         break;
1254     case 0xa:
1255         gen_op_eval_bg(r_dst, r_src);
1256         break;
1257     case 0xb:
1258         gen_op_eval_bge(r_dst, r_src);
1259         break;
1260     case 0xc:
1261         gen_op_eval_bgu(r_dst, r_src);
1262         break;
1263     case 0xd:
1264         gen_op_eval_bcc(r_dst, r_src);
1265         break;
1266     case 0xe:
1267         gen_op_eval_bpos(r_dst, r_src);
1268         break;
1269     case 0xf:
1270         gen_op_eval_bvc(r_dst, r_src);
1271         break;
1272     }
1273 }
1274
1275 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1276 {
1277     unsigned int offset;
1278
1279     switch (cc) {
1280     default:
1281     case 0x0:
1282         offset = 0;
1283         break;
1284     case 0x1:
1285         offset = 32 - 10;
1286         break;
1287     case 0x2:
1288         offset = 34 - 10;
1289         break;
1290     case 0x3:
1291         offset = 36 - 10;
1292         break;
1293     }
1294
1295     switch (cond) {
1296     case 0x0:
1297         gen_op_eval_bn(r_dst);
1298         break;
1299     case 0x1:
1300         gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1301         break;
1302     case 0x2:
1303         gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1304         break;
1305     case 0x3:
1306         gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1307         break;
1308     case 0x4:
1309         gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1310         break;
1311     case 0x5:
1312         gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1313         break;
1314     case 0x6:
1315         gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1316         break;
1317     case 0x7:
1318         gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1319         break;
1320     case 0x8:
1321         gen_op_eval_ba(r_dst);
1322         break;
1323     case 0x9:
1324         gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1325         break;
1326     case 0xa:
1327         gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1328         break;
1329     case 0xb:
1330         gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1331         break;
1332     case 0xc:
1333         gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1334         break;
1335     case 0xd:
1336         gen_op_eval_fble(r_dst, cpu_fsr, offset);
1337         break;
1338     case 0xe:
1339         gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1340         break;
1341     case 0xf:
1342         gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1343         break;
1344     }
1345 }
1346
1347 #ifdef TARGET_SPARC64
1348 // Inverted logic
1349 static const int gen_tcg_cond_reg[8] = {
1350     -1,
1351     TCG_COND_NE,
1352     TCG_COND_GT,
1353     TCG_COND_GE,
1354     -1,
1355     TCG_COND_EQ,
1356     TCG_COND_LE,
1357     TCG_COND_LT,
1358 };
1359
1360 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1361 {
1362     int l1;
1363
1364     l1 = gen_new_label();
1365     tcg_gen_movi_tl(r_dst, 0);
1366     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], r_src, tcg_const_tl(0), l1);
1367     tcg_gen_movi_tl(r_dst, 1);
1368     gen_set_label(l1);
1369 }
1370 #endif
1371
1372 /* XXX: potentially incorrect if dynamic npc */
1373 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1374                       TCGv r_cond)
1375 {
1376     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1377     target_ulong target = dc->pc + offset;
1378
1379     if (cond == 0x0) {
1380         /* unconditional not taken */
1381         if (a) {
1382             dc->pc = dc->npc + 4;
1383             dc->npc = dc->pc + 4;
1384         } else {
1385             dc->pc = dc->npc;
1386             dc->npc = dc->pc + 4;
1387         }
1388     } else if (cond == 0x8) {
1389         /* unconditional taken */
1390         if (a) {
1391             dc->pc = target;
1392             dc->npc = dc->pc + 4;
1393         } else {
1394             dc->pc = dc->npc;
1395             dc->npc = target;
1396         }
1397     } else {
1398         flush_cond(dc, r_cond);
1399         gen_cond(r_cond, cc, cond);
1400         if (a) {
1401             gen_branch_a(dc, target, dc->npc, r_cond);
1402             dc->is_br = 1;
1403         } else {
1404             dc->pc = dc->npc;
1405             dc->jump_pc[0] = target;
1406             dc->jump_pc[1] = dc->npc + 4;
1407             dc->npc = JUMP_PC;
1408         }
1409     }
1410 }
1411
1412 /* XXX: potentially incorrect if dynamic npc */
1413 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1414                       TCGv r_cond)
1415 {
1416     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1417     target_ulong target = dc->pc + offset;
1418
1419     if (cond == 0x0) {
1420         /* unconditional not taken */
1421         if (a) {
1422             dc->pc = dc->npc + 4;
1423             dc->npc = dc->pc + 4;
1424         } else {
1425             dc->pc = dc->npc;
1426             dc->npc = dc->pc + 4;
1427         }
1428     } else if (cond == 0x8) {
1429         /* unconditional taken */
1430         if (a) {
1431             dc->pc = target;
1432             dc->npc = dc->pc + 4;
1433         } else {
1434             dc->pc = dc->npc;
1435             dc->npc = target;
1436         }
1437     } else {
1438         flush_cond(dc, r_cond);
1439         gen_fcond(r_cond, cc, cond);
1440         if (a) {
1441             gen_branch_a(dc, target, dc->npc, r_cond);
1442             dc->is_br = 1;
1443         } else {
1444             dc->pc = dc->npc;
1445             dc->jump_pc[0] = target;
1446             dc->jump_pc[1] = dc->npc + 4;
1447             dc->npc = JUMP_PC;
1448         }
1449     }
1450 }
1451
1452 #ifdef TARGET_SPARC64
1453 /* XXX: potentially incorrect if dynamic npc */
1454 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1455                           TCGv r_cond, TCGv r_reg)
1456 {
1457     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1458     target_ulong target = dc->pc + offset;
1459
1460     flush_cond(dc, r_cond);
1461     gen_cond_reg(r_cond, cond, r_reg);
1462     if (a) {
1463         gen_branch_a(dc, target, dc->npc, r_cond);
1464         dc->is_br = 1;
1465     } else {
1466         dc->pc = dc->npc;
1467         dc->jump_pc[0] = target;
1468         dc->jump_pc[1] = dc->npc + 4;
1469         dc->npc = JUMP_PC;
1470     }
1471 }
1472
1473 static GenOpFunc * const gen_fcmps[4] = {
1474     helper_fcmps,
1475     helper_fcmps_fcc1,
1476     helper_fcmps_fcc2,
1477     helper_fcmps_fcc3,
1478 };
1479
1480 static GenOpFunc * const gen_fcmpd[4] = {
1481     helper_fcmpd,
1482     helper_fcmpd_fcc1,
1483     helper_fcmpd_fcc2,
1484     helper_fcmpd_fcc3,
1485 };
1486
1487 #if defined(CONFIG_USER_ONLY)
1488 static GenOpFunc * const gen_fcmpq[4] = {
1489     helper_fcmpq,
1490     helper_fcmpq_fcc1,
1491     helper_fcmpq_fcc2,
1492     helper_fcmpq_fcc3,
1493 };
1494 #endif
1495
1496 static GenOpFunc * const gen_fcmpes[4] = {
1497     helper_fcmpes,
1498     helper_fcmpes_fcc1,
1499     helper_fcmpes_fcc2,
1500     helper_fcmpes_fcc3,
1501 };
1502
1503 static GenOpFunc * const gen_fcmped[4] = {
1504     helper_fcmped,
1505     helper_fcmped_fcc1,
1506     helper_fcmped_fcc2,
1507     helper_fcmped_fcc3,
1508 };
1509
1510 #if defined(CONFIG_USER_ONLY)
1511 static GenOpFunc * const gen_fcmpeq[4] = {
1512     helper_fcmpeq,
1513     helper_fcmpeq_fcc1,
1514     helper_fcmpeq_fcc2,
1515     helper_fcmpeq_fcc3,
1516 };
1517 #endif
1518
1519 static inline void gen_op_fcmps(int fccno)
1520 {
1521     tcg_gen_helper_0_0(gen_fcmps[fccno]);
1522 }
1523
1524 static inline void gen_op_fcmpd(int fccno)
1525 {
1526     tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1527 }
1528
1529 #if defined(CONFIG_USER_ONLY)
1530 static inline void gen_op_fcmpq(int fccno)
1531 {
1532     tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1533 }
1534 #endif
1535
1536 static inline void gen_op_fcmpes(int fccno)
1537 {
1538     tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1539 }
1540
1541 static inline void gen_op_fcmped(int fccno)
1542 {
1543     tcg_gen_helper_0_0(gen_fcmped[fccno]);
1544 }
1545
1546 #if defined(CONFIG_USER_ONLY)
1547 static inline void gen_op_fcmpeq(int fccno)
1548 {
1549     tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1550 }
1551 #endif
1552
1553 #else
1554
1555 static inline void gen_op_fcmps(int fccno)
1556 {
1557     tcg_gen_helper_0_0(helper_fcmps);
1558 }
1559
1560 static inline void gen_op_fcmpd(int fccno)
1561 {
1562     tcg_gen_helper_0_0(helper_fcmpd);
1563 }
1564
1565 #if defined(CONFIG_USER_ONLY)
1566 static inline void gen_op_fcmpq(int fccno)
1567 {
1568     tcg_gen_helper_0_0(helper_fcmpq);
1569 }
1570 #endif
1571
1572 static inline void gen_op_fcmpes(int fccno)
1573 {
1574     tcg_gen_helper_0_0(helper_fcmpes);
1575 }
1576
1577 static inline void gen_op_fcmped(int fccno)
1578 {
1579     tcg_gen_helper_0_0(helper_fcmped);
1580 }
1581
1582 #if defined(CONFIG_USER_ONLY)
1583 static inline void gen_op_fcmpeq(int fccno)
1584 {
1585     tcg_gen_helper_0_0(helper_fcmpeq);
1586 }
1587 #endif
1588
1589 #endif
1590
1591 static inline void gen_op_fpexception_im(int fsr_flags)
1592 {
1593     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1594     tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1595     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
1596 }
1597
1598 static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1599 {
1600 #if !defined(CONFIG_USER_ONLY)
1601     if (!dc->fpu_enabled) {
1602         save_state(dc, r_cond);
1603         tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
1604         dc->is_br = 1;
1605         return 1;
1606     }
1607 #endif
1608     return 0;
1609 }
1610
1611 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1612 {
1613     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1614 }
1615
1616 static inline void gen_clear_float_exceptions(void)
1617 {
1618     tcg_gen_helper_0_0(helper_clear_float_exceptions);
1619 }
1620
1621 /* asi moves */
1622 #ifdef TARGET_SPARC64
1623 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1624 {
1625     int asi, offset;
1626     TCGv r_asi;
1627
1628     if (IS_IMM) {
1629         r_asi = tcg_temp_new(TCG_TYPE_I32);
1630         offset = GET_FIELD(insn, 25, 31);
1631         tcg_gen_addi_tl(r_addr, r_addr, offset);
1632         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1633     } else {
1634         asi = GET_FIELD(insn, 19, 26);
1635         r_asi = tcg_const_i32(asi);
1636     }
1637     return r_asi;
1638 }
1639
1640 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1641 {
1642     TCGv r_asi;
1643
1644     r_asi = gen_get_asi(insn, addr);
1645     tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi,
1646                        tcg_const_i32(size), tcg_const_i32(sign));
1647     tcg_gen_discard_i32(r_asi);
1648 }
1649
1650 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1651 {
1652     TCGv r_asi;
1653
1654     r_asi = gen_get_asi(insn, addr);
1655     tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, tcg_const_i32(size));
1656     tcg_gen_discard_i32(r_asi);
1657 }
1658
1659 static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1660 {
1661     TCGv r_asi;
1662
1663     r_asi = gen_get_asi(insn, addr);
1664     tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, tcg_const_i32(size),
1665                        tcg_const_i32(rd));
1666     tcg_gen_discard_i32(r_asi);
1667 }
1668
1669 static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1670 {
1671     TCGv r_asi;
1672
1673     r_asi = gen_get_asi(insn, addr);
1674     tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, tcg_const_i32(size),
1675                        tcg_const_i32(rd));
1676     tcg_gen_discard_i32(r_asi);
1677 }
1678
1679 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1680 {
1681     TCGv r_temp, r_asi;
1682
1683     r_temp = tcg_temp_new(TCG_TYPE_I32);
1684     r_asi = gen_get_asi(insn, addr);
1685     tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, r_asi,
1686                        tcg_const_i32(4), tcg_const_i32(0));
1687     tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi,
1688                        tcg_const_i32(4));
1689     tcg_gen_extu_i32_tl(dst, r_temp);
1690     tcg_gen_discard_i32(r_asi);
1691     tcg_gen_discard_i32(r_temp);
1692 }
1693
1694 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1695 {
1696     TCGv r_asi;
1697
1698     r_asi = gen_get_asi(insn, addr);
1699     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi,
1700                        tcg_const_i32(8), tcg_const_i32(0));
1701     tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1702     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1703     tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1704     tcg_gen_discard_i32(r_asi);
1705 }
1706
1707 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1708 {
1709     TCGv r_temp, r_asi;
1710
1711     r_temp = tcg_temp_new(TCG_TYPE_I32);
1712     gen_movl_reg_TN(rd + 1, r_temp);
1713     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1714                        r_temp);
1715     r_asi = gen_get_asi(insn, addr);
1716     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi,
1717                        tcg_const_i32(8));
1718     tcg_gen_discard_i32(r_asi);
1719     tcg_gen_discard_i32(r_temp);
1720 }
1721
1722 static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1723 {
1724     TCGv r_val1, r_asi;
1725
1726     r_val1 = tcg_temp_new(TCG_TYPE_I32);
1727     gen_movl_reg_TN(rd, r_val1);
1728     r_asi = gen_get_asi(insn, addr);
1729     tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1730     tcg_gen_discard_i32(r_asi);
1731     tcg_gen_discard_i32(r_val1);
1732 }
1733
1734 static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1735 {
1736     TCGv r_asi;
1737
1738     gen_movl_reg_TN(rd, cpu_tmp64);
1739     r_asi = gen_get_asi(insn, addr);
1740     tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1741     tcg_gen_discard_i32(r_asi);
1742 }
1743
1744 #elif !defined(CONFIG_USER_ONLY)
1745
1746 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1747 {
1748     int asi;
1749
1750     asi = GET_FIELD(insn, 19, 26);
1751     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1752                        tcg_const_i32(size), tcg_const_i32(sign));
1753     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1754 }
1755
1756 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1757 {
1758     int asi;
1759
1760     tcg_gen_extu_tl_i64(cpu_tmp64, src);
1761     asi = GET_FIELD(insn, 19, 26);
1762     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1763                        tcg_const_i32(size));
1764 }
1765
1766 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1767 {
1768     int asi;
1769     TCGv r_temp;
1770
1771     r_temp = tcg_temp_new(TCG_TYPE_I32);
1772     asi = GET_FIELD(insn, 19, 26);
1773     tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, tcg_const_i32(asi),
1774                        tcg_const_i32(4), tcg_const_i32(0));
1775     tcg_gen_helper_0_4(helper_st_asi, addr, dst, tcg_const_i32(asi),
1776                        tcg_const_i32(4));
1777     tcg_gen_extu_i32_tl(dst, r_temp);
1778     tcg_gen_discard_i32(r_temp);
1779 }
1780
1781 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1782 {
1783     int asi;
1784
1785     asi = GET_FIELD(insn, 19, 26);
1786     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1787                        tcg_const_i32(8), tcg_const_i32(0));
1788     tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1789     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1790     tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1791 }
1792
1793 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1794 {
1795     int asi;
1796     TCGv r_temp;
1797
1798     r_temp = tcg_temp_new(TCG_TYPE_I32);
1799     gen_movl_reg_TN(rd + 1, r_temp);
1800     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1801     asi = GET_FIELD(insn, 19, 26);
1802     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1803                        tcg_const_i32(8));
1804 }
1805 #endif
1806
1807 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1808 static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1809 {
1810     int asi;
1811
1812     gen_ld_asi(dst, addr, insn, 1, 0);
1813
1814     asi = GET_FIELD(insn, 19, 26);
1815     tcg_gen_helper_0_4(helper_st_asi, addr, tcg_const_i64(0xffULL),
1816                        tcg_const_i32(asi), tcg_const_i32(1));
1817 }
1818 #endif
1819
1820 static inline TCGv get_src1(unsigned int insn, TCGv def)
1821 {
1822     TCGv r_rs1 = def;
1823     unsigned int rs1;
1824
1825     rs1 = GET_FIELD(insn, 13, 17);
1826     if (rs1 == 0)
1827         //r_rs1 = tcg_const_tl(0);
1828         tcg_gen_movi_tl(def, 0);
1829     else if (rs1 < 8)
1830         //r_rs1 = cpu_gregs[rs1];
1831         tcg_gen_mov_tl(def, cpu_gregs[rs1]);
1832     else
1833         tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1834     return r_rs1;
1835 }
1836
1837 /* before an instruction, dc->pc must be static */
1838 static void disas_sparc_insn(DisasContext * dc)
1839 {
1840     unsigned int insn, opc, rs1, rs2, rd;
1841
1842     insn = ldl_code(dc->pc);
1843     opc = GET_FIELD(insn, 0, 1);
1844
1845     rd = GET_FIELD(insn, 2, 6);
1846
1847     cpu_dst = cpu_T[0];
1848     cpu_src1 = cpu_T[0]; // const
1849     cpu_src2 = cpu_T[1]; // const
1850
1851     // loads and stores
1852     cpu_addr = cpu_T[0];
1853     cpu_val = cpu_T[1];
1854
1855     switch (opc) {
1856     case 0:                     /* branches/sethi */
1857         {
1858             unsigned int xop = GET_FIELD(insn, 7, 9);
1859             int32_t target;
1860             switch (xop) {
1861 #ifdef TARGET_SPARC64
1862             case 0x1:           /* V9 BPcc */
1863                 {
1864                     int cc;
1865
1866                     target = GET_FIELD_SP(insn, 0, 18);
1867                     target = sign_extend(target, 18);
1868                     target <<= 2;
1869                     cc = GET_FIELD_SP(insn, 20, 21);
1870                     if (cc == 0)
1871                         do_branch(dc, target, insn, 0, cpu_cond);
1872                     else if (cc == 2)
1873                         do_branch(dc, target, insn, 1, cpu_cond);
1874                     else
1875                         goto illegal_insn;
1876                     goto jmp_insn;
1877                 }
1878             case 0x3:           /* V9 BPr */
1879                 {
1880                     target = GET_FIELD_SP(insn, 0, 13) |
1881                         (GET_FIELD_SP(insn, 20, 21) << 14);
1882                     target = sign_extend(target, 16);
1883                     target <<= 2;
1884                     cpu_src1 = get_src1(insn, cpu_src1);
1885                     do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1886                     goto jmp_insn;
1887                 }
1888             case 0x5:           /* V9 FBPcc */
1889                 {
1890                     int cc = GET_FIELD_SP(insn, 20, 21);
1891                     if (gen_trap_ifnofpu(dc, cpu_cond))
1892                         goto jmp_insn;
1893                     target = GET_FIELD_SP(insn, 0, 18);
1894                     target = sign_extend(target, 19);
1895                     target <<= 2;
1896                     do_fbranch(dc, target, insn, cc, cpu_cond);
1897                     goto jmp_insn;
1898                 }
1899 #else
1900             case 0x7:           /* CBN+x */
1901                 {
1902                     goto ncp_insn;
1903                 }
1904 #endif
1905             case 0x2:           /* BN+x */
1906                 {
1907                     target = GET_FIELD(insn, 10, 31);
1908                     target = sign_extend(target, 22);
1909                     target <<= 2;
1910                     do_branch(dc, target, insn, 0, cpu_cond);
1911                     goto jmp_insn;
1912                 }
1913             case 0x6:           /* FBN+x */
1914                 {
1915                     if (gen_trap_ifnofpu(dc, cpu_cond))
1916                         goto jmp_insn;
1917                     target = GET_FIELD(insn, 10, 31);
1918                     target = sign_extend(target, 22);
1919                     target <<= 2;
1920                     do_fbranch(dc, target, insn, 0, cpu_cond);
1921                     goto jmp_insn;
1922                 }
1923             case 0x4:           /* SETHI */
1924 #define OPTIM
1925 #if defined(OPTIM)
1926                 if (rd) { // nop
1927 #endif
1928                     uint32_t value = GET_FIELD(insn, 10, 31);
1929                     tcg_gen_movi_tl(cpu_dst, value << 10);
1930                     gen_movl_TN_reg(rd, cpu_dst);
1931 #if defined(OPTIM)
1932                 }
1933 #endif
1934                 break;
1935             case 0x0:           /* UNIMPL */
1936             default:
1937                 goto illegal_insn;
1938             }
1939             break;
1940         }
1941         break;
1942     case 1:
1943         /*CALL*/ {
1944             target_long target = GET_FIELDs(insn, 2, 31) << 2;
1945
1946             gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
1947             target += dc->pc;
1948             gen_mov_pc_npc(dc, cpu_cond);
1949             dc->npc = target;
1950         }
1951         goto jmp_insn;
1952     case 2:                     /* FPU & Logical Operations */
1953         {
1954             unsigned int xop = GET_FIELD(insn, 7, 12);
1955             if (xop == 0x3a) {  /* generate trap */
1956                 int cond;
1957
1958                 cpu_src1 = get_src1(insn, cpu_src1);
1959                 if (IS_IMM) {
1960                     rs2 = GET_FIELD(insn, 25, 31);
1961                     tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
1962                 } else {
1963                     rs2 = GET_FIELD(insn, 27, 31);
1964 #if defined(OPTIM)
1965                     if (rs2 != 0) {
1966 #endif
1967                         gen_movl_reg_TN(rs2, cpu_src2);
1968                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
1969 #if defined(OPTIM)
1970                     }
1971 #endif
1972                 }
1973                 cond = GET_FIELD(insn, 3, 6);
1974                 if (cond == 0x8) {
1975                     save_state(dc, cpu_cond);
1976                     tcg_gen_helper_0_1(helper_trap, cpu_dst);
1977                 } else if (cond != 0) {
1978                     TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
1979 #ifdef TARGET_SPARC64
1980                     /* V9 icc/xcc */
1981                     int cc = GET_FIELD_SP(insn, 11, 12);
1982
1983                     save_state(dc, cpu_cond);
1984                     if (cc == 0)
1985                         gen_cond(r_cond, 0, cond);
1986                     else if (cc == 2)
1987                         gen_cond(r_cond, 1, cond);
1988                     else
1989                         goto illegal_insn;
1990 #else
1991                     save_state(dc, cpu_cond);
1992                     gen_cond(r_cond, 0, cond);
1993 #endif
1994                     tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
1995                     tcg_gen_discard_tl(r_cond);
1996                 }
1997                 gen_op_next_insn();
1998                 tcg_gen_exit_tb(0);
1999                 dc->is_br = 1;
2000                 goto jmp_insn;
2001             } else if (xop == 0x28) {
2002                 rs1 = GET_FIELD(insn, 13, 17);
2003                 switch(rs1) {
2004                 case 0: /* rdy */
2005 #ifndef TARGET_SPARC64
2006                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2007                                        manual, rdy on the microSPARC
2008                                        II */
2009                 case 0x0f:          /* stbar in the SPARCv8 manual,
2010                                        rdy on the microSPARC II */
2011                 case 0x10 ... 0x1f: /* implementation-dependent in the
2012                                        SPARCv8 manual, rdy on the
2013                                        microSPARC II */
2014 #endif
2015                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
2016                     gen_movl_TN_reg(rd, cpu_dst);
2017                     break;
2018 #ifdef TARGET_SPARC64
2019                 case 0x2: /* V9 rdccr */
2020                     tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2021                     gen_movl_TN_reg(rd, cpu_dst);
2022                     break;
2023                 case 0x3: /* V9 rdasi */
2024                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
2025                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2026                     gen_movl_TN_reg(rd, cpu_dst);
2027                     break;
2028                 case 0x4: /* V9 rdtick */
2029                     {
2030                         TCGv r_tickptr;
2031
2032                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2033                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2034                                        offsetof(CPUState, tick));
2035                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2036                                            r_tickptr);
2037                         gen_movl_TN_reg(rd, cpu_dst);
2038                         tcg_gen_discard_ptr(r_tickptr);
2039                     }
2040                     break;
2041                 case 0x5: /* V9 rdpc */
2042                     tcg_gen_movi_tl(cpu_dst, dc->pc);
2043                     gen_movl_TN_reg(rd, cpu_dst);
2044                     break;
2045                 case 0x6: /* V9 rdfprs */
2046                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
2047                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2048                     gen_movl_TN_reg(rd, cpu_dst);
2049                     break;
2050                 case 0xf: /* V9 membar */
2051                     break; /* no effect */
2052                 case 0x13: /* Graphics Status */
2053                     if (gen_trap_ifnofpu(dc, cpu_cond))
2054                         goto jmp_insn;
2055                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
2056                     gen_movl_TN_reg(rd, cpu_dst);
2057                     break;
2058                 case 0x17: /* Tick compare */
2059                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tick_cmpr));
2060                     gen_movl_TN_reg(rd, cpu_dst);
2061                     break;
2062                 case 0x18: /* System tick */
2063                     {
2064                         TCGv r_tickptr;
2065
2066                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2067                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2068                                        offsetof(CPUState, stick));
2069                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2070                                            r_tickptr);
2071                         gen_movl_TN_reg(rd, cpu_dst);
2072                         tcg_gen_discard_ptr(r_tickptr);
2073                     }
2074                     break;
2075                 case 0x19: /* System tick compare */
2076                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, stick_cmpr));
2077                     gen_movl_TN_reg(rd, cpu_dst);
2078                     break;
2079                 case 0x10: /* Performance Control */
2080                 case 0x11: /* Performance Instrumentation Counter */
2081                 case 0x12: /* Dispatch Control */
2082                 case 0x14: /* Softint set, WO */
2083                 case 0x15: /* Softint clear, WO */
2084                 case 0x16: /* Softint write */
2085 #endif
2086                 default:
2087                     goto illegal_insn;
2088                 }
2089 #if !defined(CONFIG_USER_ONLY)
2090             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2091 #ifndef TARGET_SPARC64
2092                 if (!supervisor(dc))
2093                     goto priv_insn;
2094                 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2095 #else
2096                 if (!hypervisor(dc))
2097                     goto priv_insn;
2098                 rs1 = GET_FIELD(insn, 13, 17);
2099                 switch (rs1) {
2100                 case 0: // hpstate
2101                     // gen_op_rdhpstate();
2102                     break;
2103                 case 1: // htstate
2104                     // gen_op_rdhtstate();
2105                     break;
2106                 case 3: // hintp
2107                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
2108                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2109                     break;
2110                 case 5: // htba
2111                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
2112                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2113                     break;
2114                 case 6: // hver
2115                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver));
2116                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2117                     break;
2118                 case 31: // hstick_cmpr
2119                     tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2120                     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr));
2121                     break;
2122                 default:
2123                     goto illegal_insn;
2124                 }
2125 #endif
2126                 gen_movl_TN_reg(rd, cpu_dst);
2127                 break;
2128             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2129                 if (!supervisor(dc))
2130                     goto priv_insn;
2131 #ifdef TARGET_SPARC64
2132                 rs1 = GET_FIELD(insn, 13, 17);
2133                 switch (rs1) {
2134                 case 0: // tpc
2135                     {
2136                         TCGv r_tsptr;
2137
2138                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2139                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2140                                        offsetof(CPUState, tsptr));
2141                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2142                                       offsetof(trap_state, tpc));
2143                         tcg_gen_discard_ptr(r_tsptr);
2144                     }
2145                     break;
2146                 case 1: // tnpc
2147                     {
2148                         TCGv r_tsptr;
2149
2150                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2151                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2152                                        offsetof(CPUState, tsptr));
2153                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2154                                       offsetof(trap_state, tnpc));
2155                         tcg_gen_discard_ptr(r_tsptr);
2156                     }
2157                     break;
2158                 case 2: // tstate
2159                     {
2160                         TCGv r_tsptr;
2161
2162                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2163                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2164                                        offsetof(CPUState, tsptr));
2165                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2166                                       offsetof(trap_state, tstate));
2167                         tcg_gen_discard_ptr(r_tsptr);
2168                     }
2169                     break;
2170                 case 3: // tt
2171                     {
2172                         TCGv r_tsptr;
2173
2174                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2175                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2176                                        offsetof(CPUState, tsptr));
2177                         tcg_gen_ld_i32(cpu_dst, r_tsptr,
2178                                        offsetof(trap_state, tt));
2179                         tcg_gen_discard_ptr(r_tsptr);
2180                     }
2181                     break;
2182                 case 4: // tick
2183                     {
2184                         TCGv r_tickptr;
2185
2186                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2187                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2188                                        offsetof(CPUState, tick));
2189                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2190                                            r_tickptr);
2191                         gen_movl_TN_reg(rd, cpu_dst);
2192                         tcg_gen_discard_ptr(r_tickptr);
2193                     }
2194                     break;
2195                 case 5: // tba
2196                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2197                     break;
2198                 case 6: // pstate
2199                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate));
2200                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2201                     break;
2202                 case 7: // tl
2203                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
2204                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2205                     break;
2206                 case 8: // pil
2207                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
2208                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2209                     break;
2210                 case 9: // cwp
2211                     tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
2212                     break;
2213                 case 10: // cansave
2214                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
2215                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2216                     break;
2217                 case 11: // canrestore
2218                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
2219                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2220                     break;
2221                 case 12: // cleanwin
2222                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
2223                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2224                     break;
2225                 case 13: // otherwin
2226                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
2227                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2228                     break;
2229                 case 14: // wstate
2230                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
2231                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2232                     break;
2233                 case 16: // UA2005 gl
2234                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
2235                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2236                     break;
2237                 case 26: // UA2005 strand status
2238                     if (!hypervisor(dc))
2239                         goto priv_insn;
2240                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
2241                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2242                     break;
2243                 case 31: // ver
2244                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, version));
2245                     break;
2246                 case 15: // fq
2247                 default:
2248                     goto illegal_insn;
2249                 }
2250 #else
2251                 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
2252                 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2253 #endif
2254                 gen_movl_TN_reg(rd, cpu_dst);
2255                 break;
2256             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2257 #ifdef TARGET_SPARC64
2258                 tcg_gen_helper_0_0(helper_flushw);
2259 #else
2260                 if (!supervisor(dc))
2261                     goto priv_insn;
2262                 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2263                 gen_movl_TN_reg(rd, cpu_dst);
2264 #endif
2265                 break;
2266 #endif
2267             } else if (xop == 0x34) {   /* FPU Operations */
2268                 if (gen_trap_ifnofpu(dc, cpu_cond))
2269                     goto jmp_insn;
2270                 gen_op_clear_ieee_excp_and_FTT();
2271                 rs1 = GET_FIELD(insn, 13, 17);
2272                 rs2 = GET_FIELD(insn, 27, 31);
2273                 xop = GET_FIELD(insn, 18, 26);
2274                 switch (xop) {
2275                     case 0x1: /* fmovs */
2276                         gen_op_load_fpr_FT0(rs2);
2277                         gen_op_store_FT0_fpr(rd);
2278                         break;
2279                     case 0x5: /* fnegs */
2280                         gen_op_load_fpr_FT1(rs2);
2281                         tcg_gen_helper_0_0(helper_fnegs);
2282                         gen_op_store_FT0_fpr(rd);
2283                         break;
2284                     case 0x9: /* fabss */
2285                         gen_op_load_fpr_FT1(rs2);
2286                         tcg_gen_helper_0_0(helper_fabss);
2287                         gen_op_store_FT0_fpr(rd);
2288                         break;
2289                     case 0x29: /* fsqrts */
2290                         gen_op_load_fpr_FT1(rs2);
2291                         gen_clear_float_exceptions();
2292                         tcg_gen_helper_0_0(helper_fsqrts);
2293                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2294                         gen_op_store_FT0_fpr(rd);
2295                         break;
2296                     case 0x2a: /* fsqrtd */
2297                         gen_op_load_fpr_DT1(DFPREG(rs2));
2298                         gen_clear_float_exceptions();
2299                         tcg_gen_helper_0_0(helper_fsqrtd);
2300                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2301                         gen_op_store_DT0_fpr(DFPREG(rd));
2302                         break;
2303                     case 0x2b: /* fsqrtq */
2304 #if defined(CONFIG_USER_ONLY)
2305                         gen_op_load_fpr_QT1(QFPREG(rs2));
2306                         gen_clear_float_exceptions();
2307                         tcg_gen_helper_0_0(helper_fsqrtq);
2308                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2309                         gen_op_store_QT0_fpr(QFPREG(rd));
2310                         break;
2311 #else
2312                         goto nfpu_insn;
2313 #endif
2314                     case 0x41:
2315                         gen_op_load_fpr_FT0(rs1);
2316                         gen_op_load_fpr_FT1(rs2);
2317                         gen_clear_float_exceptions();
2318                         tcg_gen_helper_0_0(helper_fadds);
2319                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2320                         gen_op_store_FT0_fpr(rd);
2321                         break;
2322                     case 0x42:
2323                         gen_op_load_fpr_DT0(DFPREG(rs1));
2324                         gen_op_load_fpr_DT1(DFPREG(rs2));
2325                         gen_clear_float_exceptions();
2326                         tcg_gen_helper_0_0(helper_faddd);
2327                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2328                         gen_op_store_DT0_fpr(DFPREG(rd));
2329                         break;
2330                     case 0x43: /* faddq */
2331 #if defined(CONFIG_USER_ONLY)
2332                         gen_op_load_fpr_QT0(QFPREG(rs1));
2333                         gen_op_load_fpr_QT1(QFPREG(rs2));
2334                         gen_clear_float_exceptions();
2335                         tcg_gen_helper_0_0(helper_faddq);
2336                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2337                         gen_op_store_QT0_fpr(QFPREG(rd));
2338                         break;
2339 #else
2340                         goto nfpu_insn;
2341 #endif
2342                     case 0x45:
2343                         gen_op_load_fpr_FT0(rs1);
2344                         gen_op_load_fpr_FT1(rs2);
2345                         gen_clear_float_exceptions();
2346                         tcg_gen_helper_0_0(helper_fsubs);
2347                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2348                         gen_op_store_FT0_fpr(rd);
2349                         break;
2350                     case 0x46:
2351                         gen_op_load_fpr_DT0(DFPREG(rs1));
2352                         gen_op_load_fpr_DT1(DFPREG(rs2));
2353                         gen_clear_float_exceptions();
2354                         tcg_gen_helper_0_0(helper_fsubd);
2355                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2356                         gen_op_store_DT0_fpr(DFPREG(rd));
2357                         break;
2358                     case 0x47: /* fsubq */
2359 #if defined(CONFIG_USER_ONLY)
2360                         gen_op_load_fpr_QT0(QFPREG(rs1));
2361                         gen_op_load_fpr_QT1(QFPREG(rs2));
2362                         gen_clear_float_exceptions();
2363                         tcg_gen_helper_0_0(helper_fsubq);
2364                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2365                         gen_op_store_QT0_fpr(QFPREG(rd));
2366                         break;
2367 #else
2368                         goto nfpu_insn;
2369 #endif
2370                     case 0x49:
2371                         gen_op_load_fpr_FT0(rs1);
2372                         gen_op_load_fpr_FT1(rs2);
2373                         gen_clear_float_exceptions();
2374                         tcg_gen_helper_0_0(helper_fmuls);
2375                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2376                         gen_op_store_FT0_fpr(rd);
2377                         break;
2378                     case 0x4a:
2379                         gen_op_load_fpr_DT0(DFPREG(rs1));
2380                         gen_op_load_fpr_DT1(DFPREG(rs2));
2381                         gen_clear_float_exceptions();
2382                         tcg_gen_helper_0_0(helper_fmuld);
2383                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2384                         gen_op_store_DT0_fpr(DFPREG(rd));
2385                         break;
2386                     case 0x4b: /* fmulq */
2387 #if defined(CONFIG_USER_ONLY)
2388                         gen_op_load_fpr_QT0(QFPREG(rs1));
2389                         gen_op_load_fpr_QT1(QFPREG(rs2));
2390                         gen_clear_float_exceptions();
2391                         tcg_gen_helper_0_0(helper_fmulq);
2392                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2393                         gen_op_store_QT0_fpr(QFPREG(rd));
2394                         break;
2395 #else
2396                         goto nfpu_insn;
2397 #endif
2398                     case 0x4d:
2399                         gen_op_load_fpr_FT0(rs1);
2400                         gen_op_load_fpr_FT1(rs2);
2401                         gen_clear_float_exceptions();
2402                         tcg_gen_helper_0_0(helper_fdivs);
2403                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2404                         gen_op_store_FT0_fpr(rd);
2405                         break;
2406                     case 0x4e:
2407                         gen_op_load_fpr_DT0(DFPREG(rs1));
2408                         gen_op_load_fpr_DT1(DFPREG(rs2));
2409                         gen_clear_float_exceptions();
2410                         tcg_gen_helper_0_0(helper_fdivd);
2411                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2412                         gen_op_store_DT0_fpr(DFPREG(rd));
2413                         break;
2414                     case 0x4f: /* fdivq */
2415 #if defined(CONFIG_USER_ONLY)
2416                         gen_op_load_fpr_QT0(QFPREG(rs1));
2417                         gen_op_load_fpr_QT1(QFPREG(rs2));
2418                         gen_clear_float_exceptions();
2419                         tcg_gen_helper_0_0(helper_fdivq);
2420                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2421                         gen_op_store_QT0_fpr(QFPREG(rd));
2422                         break;
2423 #else
2424                         goto nfpu_insn;
2425 #endif
2426                     case 0x69:
2427                         gen_op_load_fpr_FT0(rs1);
2428                         gen_op_load_fpr_FT1(rs2);
2429                         gen_clear_float_exceptions();
2430                         tcg_gen_helper_0_0(helper_fsmuld);
2431                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2432                         gen_op_store_DT0_fpr(DFPREG(rd));
2433                         break;
2434                     case 0x6e: /* fdmulq */
2435 #if defined(CONFIG_USER_ONLY)
2436                         gen_op_load_fpr_DT0(DFPREG(rs1));
2437                         gen_op_load_fpr_DT1(DFPREG(rs2));
2438                         gen_clear_float_exceptions();
2439                         tcg_gen_helper_0_0(helper_fdmulq);
2440                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2441                         gen_op_store_QT0_fpr(QFPREG(rd));
2442                         break;
2443 #else
2444                         goto nfpu_insn;
2445 #endif
2446                     case 0xc4:
2447                         gen_op_load_fpr_FT1(rs2);
2448                         gen_clear_float_exceptions();
2449                         tcg_gen_helper_0_0(helper_fitos);
2450                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2451                         gen_op_store_FT0_fpr(rd);
2452                         break;
2453                     case 0xc6:
2454                         gen_op_load_fpr_DT1(DFPREG(rs2));
2455                         gen_clear_float_exceptions();
2456                         tcg_gen_helper_0_0(helper_fdtos);
2457                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2458                         gen_op_store_FT0_fpr(rd);
2459                         break;
2460                     case 0xc7: /* fqtos */
2461 #if defined(CONFIG_USER_ONLY)
2462                         gen_op_load_fpr_QT1(QFPREG(rs2));
2463                         gen_clear_float_exceptions();
2464                         tcg_gen_helper_0_0(helper_fqtos);
2465                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2466                         gen_op_store_FT0_fpr(rd);
2467                         break;
2468 #else
2469                         goto nfpu_insn;
2470 #endif
2471                     case 0xc8:
2472                         gen_op_load_fpr_FT1(rs2);
2473                         tcg_gen_helper_0_0(helper_fitod);
2474                         gen_op_store_DT0_fpr(DFPREG(rd));
2475                         break;
2476                     case 0xc9:
2477                         gen_op_load_fpr_FT1(rs2);
2478                         tcg_gen_helper_0_0(helper_fstod);
2479                         gen_op_store_DT0_fpr(DFPREG(rd));
2480                         break;
2481                     case 0xcb: /* fqtod */
2482 #if defined(CONFIG_USER_ONLY)
2483                         gen_op_load_fpr_QT1(QFPREG(rs2));
2484                         gen_clear_float_exceptions();
2485                         tcg_gen_helper_0_0(helper_fqtod);
2486                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2487                         gen_op_store_DT0_fpr(DFPREG(rd));
2488                         break;
2489 #else
2490                         goto nfpu_insn;
2491 #endif
2492                     case 0xcc: /* fitoq */
2493 #if defined(CONFIG_USER_ONLY)
2494                         gen_op_load_fpr_FT1(rs2);
2495                         tcg_gen_helper_0_0(helper_fitoq);
2496                         gen_op_store_QT0_fpr(QFPREG(rd));
2497                         break;
2498 #else
2499                         goto nfpu_insn;
2500 #endif
2501                     case 0xcd: /* fstoq */
2502 #if defined(CONFIG_USER_ONLY)
2503                         gen_op_load_fpr_FT1(rs2);
2504                         tcg_gen_helper_0_0(helper_fstoq);
2505                         gen_op_store_QT0_fpr(QFPREG(rd));
2506                         break;
2507 #else
2508                         goto nfpu_insn;
2509 #endif
2510                     case 0xce: /* fdtoq */
2511 #if defined(CONFIG_USER_ONLY)
2512                         gen_op_load_fpr_DT1(DFPREG(rs2));
2513                         tcg_gen_helper_0_0(helper_fdtoq);
2514                         gen_op_store_QT0_fpr(QFPREG(rd));
2515                         break;
2516 #else
2517                         goto nfpu_insn;
2518 #endif
2519                     case 0xd1:
2520                         gen_op_load_fpr_FT1(rs2);
2521                         gen_clear_float_exceptions();
2522                         tcg_gen_helper_0_0(helper_fstoi);
2523                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2524                         gen_op_store_FT0_fpr(rd);
2525                         break;
2526                     case 0xd2:
2527                         gen_op_load_fpr_DT1(DFPREG(rs2));
2528                         gen_clear_float_exceptions();
2529                         tcg_gen_helper_0_0(helper_fdtoi);
2530                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2531                         gen_op_store_FT0_fpr(rd);
2532                         break;
2533                     case 0xd3: /* fqtoi */
2534 #if defined(CONFIG_USER_ONLY)
2535                         gen_op_load_fpr_QT1(QFPREG(rs2));
2536                         gen_clear_float_exceptions();
2537                         tcg_gen_helper_0_0(helper_fqtoi);
2538                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2539                         gen_op_store_FT0_fpr(rd);
2540                         break;
2541 #else
2542                         goto nfpu_insn;
2543 #endif
2544 #ifdef TARGET_SPARC64
2545                     case 0x2: /* V9 fmovd */
2546                         gen_op_load_fpr_DT0(DFPREG(rs2));
2547                         gen_op_store_DT0_fpr(DFPREG(rd));
2548                         break;
2549                     case 0x3: /* V9 fmovq */
2550 #if defined(CONFIG_USER_ONLY)
2551                         gen_op_load_fpr_QT0(QFPREG(rs2));
2552                         gen_op_store_QT0_fpr(QFPREG(rd));
2553                         break;
2554 #else
2555                         goto nfpu_insn;
2556 #endif
2557                     case 0x6: /* V9 fnegd */
2558                         gen_op_load_fpr_DT1(DFPREG(rs2));
2559                         tcg_gen_helper_0_0(helper_fnegd);
2560                         gen_op_store_DT0_fpr(DFPREG(rd));
2561                         break;
2562                     case 0x7: /* V9 fnegq */
2563 #if defined(CONFIG_USER_ONLY)
2564                         gen_op_load_fpr_QT1(QFPREG(rs2));
2565                         tcg_gen_helper_0_0(helper_fnegq);
2566                         gen_op_store_QT0_fpr(QFPREG(rd));
2567                         break;
2568 #else
2569                         goto nfpu_insn;
2570 #endif
2571                     case 0xa: /* V9 fabsd */
2572                         gen_op_load_fpr_DT1(DFPREG(rs2));
2573                         tcg_gen_helper_0_0(helper_fabsd);
2574                         gen_op_store_DT0_fpr(DFPREG(rd));
2575                         break;
2576                     case 0xb: /* V9 fabsq */
2577 #if defined(CONFIG_USER_ONLY)
2578                         gen_op_load_fpr_QT1(QFPREG(rs2));
2579                         tcg_gen_helper_0_0(helper_fabsq);
2580                         gen_op_store_QT0_fpr(QFPREG(rd));
2581                         break;
2582 #else
2583                         goto nfpu_insn;
2584 #endif
2585                     case 0x81: /* V9 fstox */
2586                         gen_op_load_fpr_FT1(rs2);
2587                         gen_clear_float_exceptions();
2588                         tcg_gen_helper_0_0(helper_fstox);
2589                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2590                         gen_op_store_DT0_fpr(DFPREG(rd));
2591                         break;
2592                     case 0x82: /* V9 fdtox */
2593                         gen_op_load_fpr_DT1(DFPREG(rs2));
2594                         gen_clear_float_exceptions();
2595                         tcg_gen_helper_0_0(helper_fdtox);
2596                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2597                         gen_op_store_DT0_fpr(DFPREG(rd));
2598                         break;
2599                     case 0x83: /* V9 fqtox */
2600 #if defined(CONFIG_USER_ONLY)
2601                         gen_op_load_fpr_QT1(QFPREG(rs2));
2602                         gen_clear_float_exceptions();
2603                         tcg_gen_helper_0_0(helper_fqtox);
2604                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2605                         gen_op_store_DT0_fpr(DFPREG(rd));
2606                         break;
2607 #else
2608                         goto nfpu_insn;
2609 #endif
2610                     case 0x84: /* V9 fxtos */
2611                         gen_op_load_fpr_DT1(DFPREG(rs2));
2612                         gen_clear_float_exceptions();
2613                         tcg_gen_helper_0_0(helper_fxtos);
2614                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2615                         gen_op_store_FT0_fpr(rd);
2616                         break;
2617                     case 0x88: /* V9 fxtod */
2618                         gen_op_load_fpr_DT1(DFPREG(rs2));
2619                         gen_clear_float_exceptions();
2620                         tcg_gen_helper_0_0(helper_fxtod);
2621                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2622                         gen_op_store_DT0_fpr(DFPREG(rd));
2623                         break;
2624                     case 0x8c: /* V9 fxtoq */
2625 #if defined(CONFIG_USER_ONLY)
2626                         gen_op_load_fpr_DT1(DFPREG(rs2));
2627                         gen_clear_float_exceptions();
2628                         tcg_gen_helper_0_0(helper_fxtoq);
2629                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2630                         gen_op_store_QT0_fpr(QFPREG(rd));
2631                         break;
2632 #else
2633                         goto nfpu_insn;
2634 #endif
2635 #endif
2636                     default:
2637                         goto illegal_insn;
2638                 }
2639             } else if (xop == 0x35) {   /* FPU Operations */
2640 #ifdef TARGET_SPARC64
2641                 int cond;
2642 #endif
2643                 if (gen_trap_ifnofpu(dc, cpu_cond))
2644                     goto jmp_insn;
2645                 gen_op_clear_ieee_excp_and_FTT();
2646                 rs1 = GET_FIELD(insn, 13, 17);
2647                 rs2 = GET_FIELD(insn, 27, 31);
2648                 xop = GET_FIELD(insn, 18, 26);
2649 #ifdef TARGET_SPARC64
2650                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2651                     int l1;
2652
2653                     l1 = gen_new_label();
2654                     cond = GET_FIELD_SP(insn, 14, 17);
2655                     cpu_src1 = get_src1(insn, cpu_src1);
2656                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2657                                       tcg_const_tl(0), l1);
2658                     gen_op_load_fpr_FT0(rs2);
2659                     gen_op_store_FT0_fpr(rd);
2660                     gen_set_label(l1);
2661                     break;
2662                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2663                     int l1;
2664
2665                     l1 = gen_new_label();
2666                     cond = GET_FIELD_SP(insn, 14, 17);
2667                     cpu_src1 = get_src1(insn, cpu_src1);
2668                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2669                                       tcg_const_tl(0), l1);
2670                     gen_op_load_fpr_DT0(DFPREG(rs2));
2671                     gen_op_store_DT0_fpr(DFPREG(rd));
2672                     gen_set_label(l1);
2673                     break;
2674                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2675 #if defined(CONFIG_USER_ONLY)
2676                     int l1;
2677
2678                     l1 = gen_new_label();
2679                     cond = GET_FIELD_SP(insn, 14, 17);
2680                     cpu_src1 = get_src1(insn, cpu_src1);
2681                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2682                                       tcg_const_tl(0), l1);
2683                     gen_op_load_fpr_QT0(QFPREG(rs2));
2684                     gen_op_store_QT0_fpr(QFPREG(rd));
2685                     gen_set_label(l1);
2686                     break;
2687 #else
2688                     goto nfpu_insn;
2689 #endif
2690                 }
2691 #endif
2692                 switch (xop) {
2693 #ifdef TARGET_SPARC64
2694 #define FMOVCC(size_FDQ, fcc)                                           \
2695                     {                                                   \
2696                         TCGv r_cond;                                    \
2697                         int l1;                                         \
2698                                                                         \
2699                         l1 = gen_new_label();                           \
2700                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2701                         cond = GET_FIELD_SP(insn, 14, 17);              \
2702                         gen_fcond(r_cond, fcc, cond);                   \
2703                         tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,          \
2704                                           tcg_const_tl(0), l1);         \
2705                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2706                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2707                         gen_set_label(l1);                              \
2708                         tcg_gen_discard_tl(r_cond);                     \
2709                     }
2710                     case 0x001: /* V9 fmovscc %fcc0 */
2711                         FMOVCC(F, 0);
2712                         break;
2713                     case 0x002: /* V9 fmovdcc %fcc0 */
2714                         FMOVCC(D, 0);
2715                         break;
2716                     case 0x003: /* V9 fmovqcc %fcc0 */
2717 #if defined(CONFIG_USER_ONLY)
2718                         FMOVCC(Q, 0);
2719                         break;
2720 #else
2721                         goto nfpu_insn;
2722 #endif
2723                     case 0x041: /* V9 fmovscc %fcc1 */
2724                         FMOVCC(F, 1);
2725                         break;
2726                     case 0x042: /* V9 fmovdcc %fcc1 */
2727                         FMOVCC(D, 1);
2728                         break;
2729                     case 0x043: /* V9 fmovqcc %fcc1 */
2730 #if defined(CONFIG_USER_ONLY)
2731                         FMOVCC(Q, 1);
2732                         break;
2733 #else
2734                         goto nfpu_insn;
2735 #endif
2736                     case 0x081: /* V9 fmovscc %fcc2 */
2737                         FMOVCC(F, 2);
2738                         break;
2739                     case 0x082: /* V9 fmovdcc %fcc2 */
2740                         FMOVCC(D, 2);
2741                         break;
2742                     case 0x083: /* V9 fmovqcc %fcc2 */
2743 #if defined(CONFIG_USER_ONLY)
2744                         FMOVCC(Q, 2);
2745                         break;
2746 #else
2747                         goto nfpu_insn;
2748 #endif
2749                     case 0x0c1: /* V9 fmovscc %fcc3 */
2750                         FMOVCC(F, 3);
2751                         break;
2752                     case 0x0c2: /* V9 fmovdcc %fcc3 */
2753                         FMOVCC(D, 3);
2754                         break;
2755                     case 0x0c3: /* V9 fmovqcc %fcc3 */
2756 #if defined(CONFIG_USER_ONLY)
2757                         FMOVCC(Q, 3);
2758                         break;
2759 #else
2760                         goto nfpu_insn;
2761 #endif
2762 #undef FMOVCC
2763 #define FMOVCC(size_FDQ, icc)                                           \
2764                     {                                                   \
2765                         TCGv r_cond;                                    \
2766                         int l1;                                         \
2767                                                                         \
2768                         l1 = gen_new_label();                           \
2769                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2770                         cond = GET_FIELD_SP(insn, 14, 17);              \
2771                         gen_cond(r_cond, icc, cond);                    \
2772                         tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,          \
2773                                           tcg_const_tl(0), l1);         \
2774                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2775                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2776                         gen_set_label(l1);                              \
2777                         tcg_gen_discard_tl(r_cond);                     \
2778                     }
2779
2780                     case 0x101: /* V9 fmovscc %icc */
2781                         FMOVCC(F, 0);
2782                         break;
2783                     case 0x102: /* V9 fmovdcc %icc */
2784                         FMOVCC(D, 0);
2785                     case 0x103: /* V9 fmovqcc %icc */
2786 #if defined(CONFIG_USER_ONLY)
2787                         FMOVCC(D, 0);
2788                         break;
2789 #else
2790                         goto nfpu_insn;
2791 #endif
2792                     case 0x181: /* V9 fmovscc %xcc */
2793                         FMOVCC(F, 1);
2794                         break;
2795                     case 0x182: /* V9 fmovdcc %xcc */
2796                         FMOVCC(D, 1);
2797                         break;
2798                     case 0x183: /* V9 fmovqcc %xcc */
2799 #if defined(CONFIG_USER_ONLY)
2800                         FMOVCC(Q, 1);
2801                         break;
2802 #else
2803                         goto nfpu_insn;
2804 #endif
2805 #undef FMOVCC
2806 #endif
2807                     case 0x51: /* fcmps, V9 %fcc */
2808                         gen_op_load_fpr_FT0(rs1);
2809                         gen_op_load_fpr_FT1(rs2);
2810                         gen_op_fcmps(rd & 3);
2811                         break;
2812                     case 0x52: /* fcmpd, V9 %fcc */
2813                         gen_op_load_fpr_DT0(DFPREG(rs1));
2814                         gen_op_load_fpr_DT1(DFPREG(rs2));
2815                         gen_op_fcmpd(rd & 3);
2816                         break;
2817                     case 0x53: /* fcmpq, V9 %fcc */
2818 #if defined(CONFIG_USER_ONLY)
2819                         gen_op_load_fpr_QT0(QFPREG(rs1));
2820                         gen_op_load_fpr_QT1(QFPREG(rs2));
2821                         gen_op_fcmpq(rd & 3);
2822                         break;
2823 #else /* !defined(CONFIG_USER_ONLY) */
2824                         goto nfpu_insn;
2825 #endif
2826                     case 0x55: /* fcmpes, V9 %fcc */
2827                         gen_op_load_fpr_FT0(rs1);
2828                         gen_op_load_fpr_FT1(rs2);
2829                         gen_op_fcmpes(rd & 3);
2830                         break;
2831                     case 0x56: /* fcmped, V9 %fcc */
2832                         gen_op_load_fpr_DT0(DFPREG(rs1));
2833                         gen_op_load_fpr_DT1(DFPREG(rs2));
2834                         gen_op_fcmped(rd & 3);
2835                         break;
2836                     case 0x57: /* fcmpeq, V9 %fcc */
2837 #if defined(CONFIG_USER_ONLY)
2838                         gen_op_load_fpr_QT0(QFPREG(rs1));
2839                         gen_op_load_fpr_QT1(QFPREG(rs2));
2840                         gen_op_fcmpeq(rd & 3);
2841                         break;
2842 #else/* !defined(CONFIG_USER_ONLY) */
2843                         goto nfpu_insn;
2844 #endif
2845                     default:
2846                         goto illegal_insn;
2847                 }
2848 #if defined(OPTIM)
2849             } else if (xop == 0x2) {
2850                 // clr/mov shortcut
2851
2852                 rs1 = GET_FIELD(insn, 13, 17);
2853                 if (rs1 == 0) {
2854                     // or %g0, x, y -> mov T0, x; mov y, T0
2855                     if (IS_IMM) {       /* immediate */
2856                         rs2 = GET_FIELDs(insn, 19, 31);
2857                         tcg_gen_movi_tl(cpu_dst, (int)rs2);
2858                     } else {            /* register */
2859                         rs2 = GET_FIELD(insn, 27, 31);
2860                         gen_movl_reg_TN(rs2, cpu_dst);
2861                     }
2862                 } else {
2863                     cpu_src1 = get_src1(insn, cpu_src1);
2864                     if (IS_IMM) {       /* immediate */
2865                         rs2 = GET_FIELDs(insn, 19, 31);
2866                         tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2867                     } else {            /* register */
2868                         // or x, %g0, y -> mov T1, x; mov y, T1
2869                         rs2 = GET_FIELD(insn, 27, 31);
2870                         if (rs2 != 0) {
2871                             gen_movl_reg_TN(rs2, cpu_src2);
2872                             tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2873                         }
2874                     }
2875                 }
2876                 gen_movl_TN_reg(rd, cpu_dst);
2877 #endif
2878 #ifdef TARGET_SPARC64
2879             } else if (xop == 0x25) { /* sll, V9 sllx */
2880                 cpu_src1 = get_src1(insn, cpu_src1);
2881                 if (IS_IMM) {   /* immediate */
2882                     rs2 = GET_FIELDs(insn, 20, 31);
2883                     if (insn & (1 << 12)) {
2884                         tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2885                     } else {
2886                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2887                         tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2888                     }
2889                 } else {                /* register */
2890                     rs2 = GET_FIELD(insn, 27, 31);
2891                     gen_movl_reg_TN(rs2, cpu_src2);
2892                     if (insn & (1 << 12)) {
2893                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2894                         tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2895                     } else {
2896                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2897                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2898                         tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2899                     }
2900                 }
2901                 gen_movl_TN_reg(rd, cpu_dst);
2902             } else if (xop == 0x26) { /* srl, V9 srlx */
2903                 cpu_src1 = get_src1(insn, cpu_src1);
2904                 if (IS_IMM) {   /* immediate */
2905                     rs2 = GET_FIELDs(insn, 20, 31);
2906                     if (insn & (1 << 12)) {
2907                         tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2908                     } else {
2909                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2910                         tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2911                     }
2912                 } else {                /* register */
2913                     rs2 = GET_FIELD(insn, 27, 31);
2914                     gen_movl_reg_TN(rs2, cpu_src2);
2915                     if (insn & (1 << 12)) {
2916                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2917                         tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2918                     } else {
2919                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2920                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2921                         tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2922                     }
2923                 }
2924                 gen_movl_TN_reg(rd, cpu_dst);
2925             } else if (xop == 0x27) { /* sra, V9 srax */
2926                 cpu_src1 = get_src1(insn, cpu_src1);
2927                 if (IS_IMM) {   /* immediate */
2928                     rs2 = GET_FIELDs(insn, 20, 31);
2929                     if (insn & (1 << 12)) {
2930                         tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2931                     } else {
2932                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2933                         tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2934                         tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2935                     }
2936                 } else {                /* register */
2937                     rs2 = GET_FIELD(insn, 27, 31);
2938                     gen_movl_reg_TN(rs2, cpu_src2);
2939                     if (insn & (1 << 12)) {
2940                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2941                         tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2942                     } else {
2943                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2944                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2945                         tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2946                     }
2947                 }
2948                 gen_movl_TN_reg(rd, cpu_dst);
2949 #endif
2950             } else if (xop < 0x36) {
2951                 cpu_src1 = get_src1(insn, cpu_src1);
2952                 if (IS_IMM) {   /* immediate */
2953                     rs2 = GET_FIELDs(insn, 19, 31);
2954                     tcg_gen_movi_tl(cpu_src2, (int)rs2);
2955                 } else {                /* register */
2956                     rs2 = GET_FIELD(insn, 27, 31);
2957                     gen_movl_reg_TN(rs2, cpu_src2);
2958                 }
2959                 if (xop < 0x20) {
2960                     switch (xop & ~0x10) {
2961                     case 0x0:
2962                         if (xop & 0x10)
2963                             gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2964                         else
2965                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2966                         break;
2967                     case 0x1:
2968                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2969                         if (xop & 0x10)
2970                             gen_op_logic_cc(cpu_dst);
2971                         break;
2972                     case 0x2:
2973                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2974                         if (xop & 0x10)
2975                             gen_op_logic_cc(cpu_dst);
2976                         break;
2977                     case 0x3:
2978                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
2979                         if (xop & 0x10)
2980                             gen_op_logic_cc(cpu_dst);
2981                         break;
2982                     case 0x4:
2983                         if (xop & 0x10)
2984                             gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
2985                         else
2986                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
2987                         break;
2988                     case 0x5:
2989                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2990                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
2991                         if (xop & 0x10)
2992                             gen_op_logic_cc(cpu_dst);
2993                         break;
2994                     case 0x6:
2995                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2996                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
2997                         if (xop & 0x10)
2998                             gen_op_logic_cc(cpu_dst);
2999                         break;
3000                     case 0x7:
3001                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3002                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3003                         if (xop & 0x10)
3004                             gen_op_logic_cc(cpu_dst);
3005                         break;
3006                     case 0x8:
3007                         if (xop & 0x10)
3008                             gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3009                         else {
3010                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3011                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3012                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3013                         }
3014                         break;
3015 #ifdef TARGET_SPARC64
3016                     case 0x9: /* V9 mulx */
3017                         tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3018                         break;
3019 #endif
3020                     case 0xa:
3021                         gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3022                         if (xop & 0x10)
3023                             gen_op_logic_cc(cpu_dst);
3024                         break;
3025                     case 0xb:
3026                         gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3027                         if (xop & 0x10)
3028                             gen_op_logic_cc(cpu_dst);
3029                         break;
3030                     case 0xc:
3031                         if (xop & 0x10)
3032                             gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3033                         else {
3034                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3035                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3036                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3037                         }
3038                         break;
3039 #ifdef TARGET_SPARC64
3040                     case 0xd: /* V9 udivx */
3041                         gen_trap_ifdivzero_tl(cpu_src2);
3042                         tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2);
3043                         break;
3044 #endif
3045                     case 0xe:
3046                         tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, cpu_src2);
3047                         if (xop & 0x10)
3048                             gen_op_div_cc(cpu_dst);
3049                         break;
3050                     case 0xf:
3051                         tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, cpu_src2);
3052                         if (xop & 0x10)
3053                             gen_op_div_cc(cpu_dst);
3054                         break;
3055                     default:
3056                         goto illegal_insn;
3057                     }
3058                     gen_movl_TN_reg(rd, cpu_dst);
3059                 } else {
3060                     switch (xop) {
3061                     case 0x20: /* taddcc */
3062                         gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3063                         gen_movl_TN_reg(rd, cpu_dst);
3064                         break;
3065                     case 0x21: /* tsubcc */
3066                         gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3067                         gen_movl_TN_reg(rd, cpu_dst);
3068                         break;
3069                     case 0x22: /* taddcctv */
3070                         save_state(dc, cpu_cond);
3071                         gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3072                         gen_movl_TN_reg(rd, cpu_dst);
3073                         break;
3074                     case 0x23: /* tsubcctv */
3075                         save_state(dc, cpu_cond);
3076                         gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3077                         gen_movl_TN_reg(rd, cpu_dst);
3078                         break;
3079                     case 0x24: /* mulscc */
3080                         gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3081                         gen_movl_TN_reg(rd, cpu_dst);
3082                         break;
3083 #ifndef TARGET_SPARC64
3084                     case 0x25:  /* sll */
3085                         tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3086                         tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3087                         gen_movl_TN_reg(rd, cpu_dst);
3088                         break;
3089                     case 0x26:  /* srl */
3090                         tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3091                         tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3092                         gen_movl_TN_reg(rd, cpu_dst);
3093                         break;
3094                     case 0x27:  /* sra */
3095                         tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3096                         tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3097                         gen_movl_TN_reg(rd, cpu_dst);
3098                         break;
3099 #endif
3100                     case 0x30:
3101                         {
3102                             switch(rd) {
3103                             case 0: /* wry */
3104                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3105                                 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
3106                                 break;
3107 #ifndef TARGET_SPARC64
3108                             case 0x01 ... 0x0f: /* undefined in the
3109                                                    SPARCv8 manual, nop
3110                                                    on the microSPARC
3111                                                    II */
3112                             case 0x10 ... 0x1f: /* implementation-dependent
3113                                                    in the SPARCv8
3114                                                    manual, nop on the
3115                                                    microSPARC II */
3116                                 break;
3117 #else
3118                             case 0x2: /* V9 wrccr */
3119                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3120                                 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3121                                 break;
3122                             case 0x3: /* V9 wrasi */
3123                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3124                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3125                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
3126                                 break;
3127                             case 0x6: /* V9 wrfprs */
3128                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3129                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3130                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
3131                                 save_state(dc, cpu_cond);
3132                                 gen_op_next_insn();
3133                                 tcg_gen_exit_tb(0);
3134                                 dc->is_br = 1;
3135                                 break;
3136                             case 0xf: /* V9 sir, nop if user */
3137 #if !defined(CONFIG_USER_ONLY)
3138                                 if (supervisor(dc))
3139                                     ; // XXX
3140 #endif
3141                                 break;
3142                             case 0x13: /* Graphics Status */
3143                                 if (gen_trap_ifnofpu(dc, cpu_cond))
3144                                     goto jmp_insn;
3145                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3146                                 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
3147                                 break;
3148                             case 0x17: /* Tick compare */
3149 #if !defined(CONFIG_USER_ONLY)
3150                                 if (!supervisor(dc))
3151                                     goto illegal_insn;
3152 #endif
3153                                 {
3154                                     TCGv r_tickptr;
3155
3156                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3157                                                    cpu_src2);
3158                                     tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3159                                                                  tick_cmpr));
3160                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3161                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3162                                                    offsetof(CPUState, tick));
3163                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3164                                                        r_tickptr, cpu_dst);
3165                                     tcg_gen_discard_ptr(r_tickptr);
3166                                 }
3167                                 break;
3168                             case 0x18: /* System tick */
3169 #if !defined(CONFIG_USER_ONLY)
3170                                 if (!supervisor(dc))
3171                                     goto illegal_insn;
3172 #endif
3173                                 {
3174                                     TCGv r_tickptr;
3175
3176                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3177                                                    cpu_src2);
3178                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3179                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3180                                                    offsetof(CPUState, stick));
3181                                     tcg_gen_helper_0_2(helper_tick_set_count,
3182                                                        r_tickptr, cpu_dst);
3183                                     tcg_gen_discard_ptr(r_tickptr);
3184                                 }
3185                                 break;
3186                             case 0x19: /* System tick compare */
3187 #if !defined(CONFIG_USER_ONLY)
3188                                 if (!supervisor(dc))
3189                                     goto illegal_insn;
3190 #endif
3191                                 {
3192                                     TCGv r_tickptr;
3193
3194                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3195                                                    cpu_src2);
3196                                     tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3197                                                                  stick_cmpr));
3198                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3199                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3200                                                    offsetof(CPUState, stick));
3201                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3202                                                        r_tickptr, cpu_dst);
3203                                     tcg_gen_discard_ptr(r_tickptr);
3204                                 }
3205                                 break;
3206
3207                             case 0x10: /* Performance Control */
3208                             case 0x11: /* Performance Instrumentation Counter */
3209                             case 0x12: /* Dispatch Control */
3210                             case 0x14: /* Softint set */
3211                             case 0x15: /* Softint clear */
3212                             case 0x16: /* Softint write */
3213 #endif
3214                             default:
3215                                 goto illegal_insn;
3216                             }
3217                         }
3218                         break;
3219 #if !defined(CONFIG_USER_ONLY)
3220                     case 0x31: /* wrpsr, V9 saved, restored */
3221                         {
3222                             if (!supervisor(dc))
3223                                 goto priv_insn;
3224 #ifdef TARGET_SPARC64
3225                             switch (rd) {
3226                             case 0:
3227                                 tcg_gen_helper_0_0(helper_saved);
3228                                 break;
3229                             case 1:
3230                                 tcg_gen_helper_0_0(helper_restored);
3231                                 break;
3232                             case 2: /* UA2005 allclean */
3233                             case 3: /* UA2005 otherw */
3234                             case 4: /* UA2005 normalw */
3235                             case 5: /* UA2005 invalw */
3236                                 // XXX
3237                             default:
3238                                 goto illegal_insn;
3239                             }
3240 #else
3241                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3242                             tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3243                             save_state(dc, cpu_cond);
3244                             gen_op_next_insn();
3245                             tcg_gen_exit_tb(0);
3246                             dc->is_br = 1;
3247 #endif
3248                         }
3249                         break;
3250                     case 0x32: /* wrwim, V9 wrpr */
3251                         {
3252                             if (!supervisor(dc))
3253                                 goto priv_insn;
3254                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3255 #ifdef TARGET_SPARC64
3256                             switch (rd) {
3257                             case 0: // tpc
3258                                 {
3259                                     TCGv r_tsptr;
3260
3261                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3262                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3263                                                    offsetof(CPUState, tsptr));
3264                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3265                                                   offsetof(trap_state, tpc));
3266                                     tcg_gen_discard_ptr(r_tsptr);
3267                                 }
3268                                 break;
3269                             case 1: // tnpc
3270                                 {
3271                                     TCGv r_tsptr;
3272
3273                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3274                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3275                                                    offsetof(CPUState, tsptr));
3276                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3277                                                   offsetof(trap_state, tnpc));
3278                                     tcg_gen_discard_ptr(r_tsptr);
3279                                 }
3280                                 break;
3281                             case 2: // tstate
3282                                 {
3283                                     TCGv r_tsptr;
3284
3285                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3286                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3287                                                    offsetof(CPUState, tsptr));
3288                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3289                                                   offsetof(trap_state, tstate));
3290                                     tcg_gen_discard_ptr(r_tsptr);
3291                                 }
3292                                 break;
3293                             case 3: // tt
3294                                 {
3295                                     TCGv r_tsptr;
3296
3297                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3298                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3299                                                    offsetof(CPUState, tsptr));
3300                                     tcg_gen_st_i32(cpu_dst, r_tsptr,
3301                                                    offsetof(trap_state, tt));
3302                                     tcg_gen_discard_ptr(r_tsptr);
3303                                 }
3304                                 break;
3305                             case 4: // tick
3306                                 {
3307                                     TCGv r_tickptr;
3308
3309                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3310                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3311                                                    offsetof(CPUState, tick));
3312                                     tcg_gen_helper_0_2(helper_tick_set_count,
3313                                                        r_tickptr, cpu_dst);
3314                                     tcg_gen_discard_ptr(r_tickptr);
3315                                 }
3316                                 break;
3317                             case 5: // tba
3318                                 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
3319                                 break;
3320                             case 6: // pstate
3321                                 save_state(dc, cpu_cond);
3322                                 tcg_gen_helper_0_1(helper_wrpstate, cpu_dst);
3323                                 gen_op_next_insn();
3324                                 tcg_gen_exit_tb(0);
3325                                 dc->is_br = 1;
3326                                 break;
3327                             case 7: // tl
3328                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3329                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
3330                                 break;
3331                             case 8: // pil
3332                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3333                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
3334                                 break;
3335                             case 9: // cwp
3336                                 tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
3337                                 break;
3338                             case 10: // cansave
3339                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3340                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
3341                                 break;
3342                             case 11: // canrestore
3343                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3344                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
3345                                 break;
3346                             case 12: // cleanwin
3347                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3348                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
3349                                 break;
3350                             case 13: // otherwin
3351                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3352                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
3353                                 break;
3354                             case 14: // wstate
3355                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3356                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
3357                                 break;
3358                             case 16: // UA2005 gl
3359                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3360                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
3361                                 break;
3362                             case 26: // UA2005 strand status
3363                                 if (!hypervisor(dc))
3364                                     goto priv_insn;
3365                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3366                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
3367                                 break;
3368                             default:
3369                                 goto illegal_insn;
3370                             }
3371 #else
3372                             tcg_gen_andi_tl(cpu_dst, cpu_dst, ((1 << NWINDOWS) - 1));
3373                             tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3374                             tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
3375 #endif
3376                         }
3377                         break;
3378                     case 0x33: /* wrtbr, UA2005 wrhpr */
3379                         {
3380 #ifndef TARGET_SPARC64
3381                             if (!supervisor(dc))
3382                                 goto priv_insn;
3383                             tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3384                             tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
3385 #else
3386                             if (!hypervisor(dc))
3387                                 goto priv_insn;
3388                             tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3389                             switch (rd) {
3390                             case 0: // hpstate
3391                                 // XXX gen_op_wrhpstate();
3392                                 save_state(dc, cpu_cond);
3393                                 gen_op_next_insn();
3394                                 tcg_gen_exit_tb(0);
3395                                 dc->is_br = 1;
3396                                 break;
3397                             case 1: // htstate
3398                                 // XXX gen_op_wrhtstate();
3399                                 break;
3400                             case 3: // hintp
3401                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3402                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
3403                                 break;
3404                             case 5: // htba
3405                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3406                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
3407                                 break;
3408                             case 31: // hstick_cmpr
3409                                 {
3410                                     TCGv r_tickptr;
3411
3412                                     tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3413                                                                  hstick_cmpr));
3414                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3415                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3416                                                    offsetof(CPUState, hstick));
3417                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3418                                                        r_tickptr, cpu_dst);
3419                                     tcg_gen_discard_ptr(r_tickptr);
3420                                 }
3421                                 break;
3422                             case 6: // hver readonly
3423                             default:
3424                                 goto illegal_insn;
3425                             }
3426 #endif
3427                         }
3428                         break;
3429 #endif
3430 #ifdef TARGET_SPARC64
3431                     case 0x2c: /* V9 movcc */
3432                         {
3433                             int cc = GET_FIELD_SP(insn, 11, 12);
3434                             int cond = GET_FIELD_SP(insn, 14, 17);
3435                             TCGv r_cond;
3436                             int l1;
3437
3438                             r_cond = tcg_temp_new(TCG_TYPE_TL);
3439                             if (insn & (1 << 18)) {
3440                                 if (cc == 0)
3441                                     gen_cond(r_cond, 0, cond);
3442                                 else if (cc == 2)
3443                                     gen_cond(r_cond, 1, cond);
3444                                 else
3445                                     goto illegal_insn;
3446                             } else {
3447                                 gen_fcond(r_cond, cc, cond);
3448                             }
3449
3450                             l1 = gen_new_label();
3451
3452                             tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,
3453                                               tcg_const_tl(0), l1);
3454                             if (IS_IMM) {       /* immediate */
3455                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
3456                                 tcg_gen_movi_tl(cpu_dst, (int)rs2);
3457                             } else {
3458                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3459                                 gen_movl_reg_TN(rs2, cpu_dst);
3460                             }
3461                             gen_movl_TN_reg(rd, cpu_dst);
3462                             gen_set_label(l1);
3463                             tcg_gen_discard_tl(r_cond);
3464                             break;
3465                         }
3466                     case 0x2d: /* V9 sdivx */
3467                         gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3468                         gen_movl_TN_reg(rd, cpu_dst);
3469                         break;
3470                     case 0x2e: /* V9 popc */
3471                         {
3472                             if (IS_IMM) {       /* immediate */
3473                                 rs2 = GET_FIELD_SPs(insn, 0, 12);
3474                                 tcg_gen_movi_tl(cpu_src2, (int)rs2);
3475                                 // XXX optimize: popc(constant)
3476                             }
3477                             else {
3478                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3479                                 gen_movl_reg_TN(rs2, cpu_src2);
3480                             }
3481                             tcg_gen_helper_1_1(helper_popc, cpu_dst,
3482                                                cpu_src2);
3483                             gen_movl_TN_reg(rd, cpu_dst);
3484                         }
3485                     case 0x2f: /* V9 movr */
3486                         {
3487                             int cond = GET_FIELD_SP(insn, 10, 12);
3488                             int l1;
3489
3490                             cpu_src1 = get_src1(insn, cpu_src1);
3491
3492                             l1 = gen_new_label();
3493
3494                             tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
3495                                               tcg_const_tl(0), l1);
3496                             if (IS_IMM) {       /* immediate */
3497                                 rs2 = GET_FIELD_SPs(insn, 0, 9);
3498                                 tcg_gen_movi_tl(cpu_dst, (int)rs2);
3499                             } else {
3500                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3501                                 gen_movl_reg_TN(rs2, cpu_dst);
3502                             }
3503                             gen_movl_TN_reg(rd, cpu_dst);
3504                             gen_set_label(l1);
3505                             break;
3506                         }
3507 #endif
3508                     default:
3509                         goto illegal_insn;
3510                     }
3511                 }
3512             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3513 #ifdef TARGET_SPARC64
3514                 int opf = GET_FIELD_SP(insn, 5, 13);
3515                 rs1 = GET_FIELD(insn, 13, 17);
3516                 rs2 = GET_FIELD(insn, 27, 31);
3517                 if (gen_trap_ifnofpu(dc, cpu_cond))
3518                     goto jmp_insn;
3519
3520                 switch (opf) {
3521                 case 0x000: /* VIS I edge8cc */
3522                 case 0x001: /* VIS II edge8n */
3523                 case 0x002: /* VIS I edge8lcc */
3524                 case 0x003: /* VIS II edge8ln */
3525                 case 0x004: /* VIS I edge16cc */
3526                 case 0x005: /* VIS II edge16n */
3527                 case 0x006: /* VIS I edge16lcc */
3528                 case 0x007: /* VIS II edge16ln */
3529                 case 0x008: /* VIS I edge32cc */
3530                 case 0x009: /* VIS II edge32n */
3531                 case 0x00a: /* VIS I edge32lcc */
3532                 case 0x00b: /* VIS II edge32ln */
3533                     // XXX
3534                     goto illegal_insn;
3535                 case 0x010: /* VIS I array8 */
3536                     cpu_src1 = get_src1(insn, cpu_src1);
3537                     gen_movl_reg_TN(rs2, cpu_src2);
3538                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3539                                        cpu_src2);
3540                     gen_movl_TN_reg(rd, cpu_dst);
3541                     break;
3542                 case 0x012: /* VIS I array16 */
3543                     cpu_src1 = get_src1(insn, cpu_src1);
3544                     gen_movl_reg_TN(rs2, cpu_src2);
3545                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3546                                        cpu_src2);
3547                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3548                     gen_movl_TN_reg(rd, cpu_dst);
3549                     break;
3550                 case 0x014: /* VIS I array32 */
3551                     cpu_src1 = get_src1(insn, cpu_src1);
3552                     gen_movl_reg_TN(rs2, cpu_src2);
3553                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3554                                        cpu_src2);
3555                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3556                     gen_movl_TN_reg(rd, cpu_dst);
3557                     break;
3558                 case 0x018: /* VIS I alignaddr */
3559                     cpu_src1 = get_src1(insn, cpu_src1);
3560                     gen_movl_reg_TN(rs2, cpu_src2);
3561                     tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3562                                        cpu_src2);
3563                     gen_movl_TN_reg(rd, cpu_dst);
3564                     break;
3565                 case 0x019: /* VIS II bmask */
3566                 case 0x01a: /* VIS I alignaddrl */
3567                     // XXX
3568                     goto illegal_insn;
3569                 case 0x020: /* VIS I fcmple16 */
3570                     gen_op_load_fpr_DT0(DFPREG(rs1));
3571                     gen_op_load_fpr_DT1(DFPREG(rs2));
3572                     tcg_gen_helper_0_0(helper_fcmple16);
3573                     gen_op_store_DT0_fpr(DFPREG(rd));
3574                     break;
3575                 case 0x022: /* VIS I fcmpne16 */
3576                     gen_op_load_fpr_DT0(DFPREG(rs1));
3577                     gen_op_load_fpr_DT1(DFPREG(rs2));
3578                     tcg_gen_helper_0_0(helper_fcmpne16);
3579                     gen_op_store_DT0_fpr(DFPREG(rd));
3580                     break;
3581                 case 0x024: /* VIS I fcmple32 */
3582                     gen_op_load_fpr_DT0(DFPREG(rs1));
3583                     gen_op_load_fpr_DT1(DFPREG(rs2));
3584                     tcg_gen_helper_0_0(helper_fcmple32);
3585                     gen_op_store_DT0_fpr(DFPREG(rd));
3586                     break;
3587                 case 0x026: /* VIS I fcmpne32 */
3588                     gen_op_load_fpr_DT0(DFPREG(rs1));
3589                     gen_op_load_fpr_DT1(DFPREG(rs2));
3590                     tcg_gen_helper_0_0(helper_fcmpne32);
3591                     gen_op_store_DT0_fpr(DFPREG(rd));
3592                     break;
3593                 case 0x028: /* VIS I fcmpgt16 */
3594                     gen_op_load_fpr_DT0(DFPREG(rs1));
3595                     gen_op_load_fpr_DT1(DFPREG(rs2));
3596                     tcg_gen_helper_0_0(helper_fcmpgt16);
3597                     gen_op_store_DT0_fpr(DFPREG(rd));
3598                     break;
3599                 case 0x02a: /* VIS I fcmpeq16 */
3600                     gen_op_load_fpr_DT0(DFPREG(rs1));
3601                     gen_op_load_fpr_DT1(DFPREG(rs2));
3602                     tcg_gen_helper_0_0(helper_fcmpeq16);
3603                     gen_op_store_DT0_fpr(DFPREG(rd));
3604                     break;
3605                 case 0x02c: /* VIS I fcmpgt32 */
3606                     gen_op_load_fpr_DT0(DFPREG(rs1));
3607                     gen_op_load_fpr_DT1(DFPREG(rs2));
3608                     tcg_gen_helper_0_0(helper_fcmpgt32);
3609                     gen_op_store_DT0_fpr(DFPREG(rd));
3610                     break;
3611                 case 0x02e: /* VIS I fcmpeq32 */
3612                     gen_op_load_fpr_DT0(DFPREG(rs1));
3613                     gen_op_load_fpr_DT1(DFPREG(rs2));
3614                     tcg_gen_helper_0_0(helper_fcmpeq32);
3615                     gen_op_store_DT0_fpr(DFPREG(rd));
3616                     break;
3617                 case 0x031: /* VIS I fmul8x16 */
3618                     gen_op_load_fpr_DT0(DFPREG(rs1));
3619                     gen_op_load_fpr_DT1(DFPREG(rs2));
3620                     tcg_gen_helper_0_0(helper_fmul8x16);
3621                     gen_op_store_DT0_fpr(DFPREG(rd));
3622                     break;
3623                 case 0x033: /* VIS I fmul8x16au */
3624                     gen_op_load_fpr_DT0(DFPREG(rs1));
3625                     gen_op_load_fpr_DT1(DFPREG(rs2));
3626                     tcg_gen_helper_0_0(helper_fmul8x16au);
3627                     gen_op_store_DT0_fpr(DFPREG(rd));
3628                     break;
3629                 case 0x035: /* VIS I fmul8x16al */
3630                     gen_op_load_fpr_DT0(DFPREG(rs1));
3631                     gen_op_load_fpr_DT1(DFPREG(rs2));
3632                     tcg_gen_helper_0_0(helper_fmul8x16al);
3633                     gen_op_store_DT0_fpr(DFPREG(rd));
3634                     break;
3635                 case 0x036: /* VIS I fmul8sux16 */
3636                     gen_op_load_fpr_DT0(DFPREG(rs1));
3637                     gen_op_load_fpr_DT1(DFPREG(rs2));
3638                     tcg_gen_helper_0_0(helper_fmul8sux16);
3639                     gen_op_store_DT0_fpr(DFPREG(rd));
3640                     break;
3641                 case 0x037: /* VIS I fmul8ulx16 */
3642                     gen_op_load_fpr_DT0(DFPREG(rs1));
3643                     gen_op_load_fpr_DT1(DFPREG(rs2));
3644                     tcg_gen_helper_0_0(helper_fmul8ulx16);
3645                     gen_op_store_DT0_fpr(DFPREG(rd));
3646                     break;
3647                 case 0x038: /* VIS I fmuld8sux16 */
3648                     gen_op_load_fpr_DT0(DFPREG(rs1));
3649                     gen_op_load_fpr_DT1(DFPREG(rs2));
3650                     tcg_gen_helper_0_0(helper_fmuld8sux16);
3651                     gen_op_store_DT0_fpr(DFPREG(rd));
3652                     break;
3653                 case 0x039: /* VIS I fmuld8ulx16 */
3654                     gen_op_load_fpr_DT0(DFPREG(rs1));
3655                     gen_op_load_fpr_DT1(DFPREG(rs2));
3656                     tcg_gen_helper_0_0(helper_fmuld8ulx16);
3657                     gen_op_store_DT0_fpr(DFPREG(rd));
3658                     break;
3659                 case 0x03a: /* VIS I fpack32 */
3660                 case 0x03b: /* VIS I fpack16 */
3661                 case 0x03d: /* VIS I fpackfix */
3662                 case 0x03e: /* VIS I pdist */
3663                     // XXX
3664                     goto illegal_insn;
3665                 case 0x048: /* VIS I faligndata */
3666                     gen_op_load_fpr_DT0(DFPREG(rs1));
3667                     gen_op_load_fpr_DT1(DFPREG(rs2));
3668                     tcg_gen_helper_0_0(helper_faligndata);
3669                     gen_op_store_DT0_fpr(DFPREG(rd));
3670                     break;
3671                 case 0x04b: /* VIS I fpmerge */
3672                     gen_op_load_fpr_DT0(DFPREG(rs1));
3673                     gen_op_load_fpr_DT1(DFPREG(rs2));
3674                     tcg_gen_helper_0_0(helper_fpmerge);
3675                     gen_op_store_DT0_fpr(DFPREG(rd));
3676                     break;
3677                 case 0x04c: /* VIS II bshuffle */
3678                     // XXX
3679                     goto illegal_insn;
3680                 case 0x04d: /* VIS I fexpand */
3681                     gen_op_load_fpr_DT0(DFPREG(rs1));
3682                     gen_op_load_fpr_DT1(DFPREG(rs2));
3683                     tcg_gen_helper_0_0(helper_fexpand);
3684                     gen_op_store_DT0_fpr(DFPREG(rd));
3685                     break;
3686                 case 0x050: /* VIS I fpadd16 */
3687                     gen_op_load_fpr_DT0(DFPREG(rs1));
3688                     gen_op_load_fpr_DT1(DFPREG(rs2));
3689                     tcg_gen_helper_0_0(helper_fpadd16);
3690                     gen_op_store_DT0_fpr(DFPREG(rd));
3691                     break;
3692                 case 0x051: /* VIS I fpadd16s */
3693                     gen_op_load_fpr_FT0(rs1);
3694                     gen_op_load_fpr_FT1(rs2);
3695                     tcg_gen_helper_0_0(helper_fpadd16s);
3696                     gen_op_store_FT0_fpr(rd);
3697                     break;
3698                 case 0x052: /* VIS I fpadd32 */
3699                     gen_op_load_fpr_DT0(DFPREG(rs1));
3700                     gen_op_load_fpr_DT1(DFPREG(rs2));
3701                     tcg_gen_helper_0_0(helper_fpadd32);
3702                     gen_op_store_DT0_fpr(DFPREG(rd));
3703                     break;
3704                 case 0x053: /* VIS I fpadd32s */
3705                     gen_op_load_fpr_FT0(rs1);
3706                     gen_op_load_fpr_FT1(rs2);
3707                     tcg_gen_helper_0_0(helper_fpadd32s);
3708                     gen_op_store_FT0_fpr(rd);
3709                     break;
3710                 case 0x054: /* VIS I fpsub16 */
3711                     gen_op_load_fpr_DT0(DFPREG(rs1));
3712                     gen_op_load_fpr_DT1(DFPREG(rs2));
3713                     tcg_gen_helper_0_0(helper_fpsub16);
3714                     gen_op_store_DT0_fpr(DFPREG(rd));
3715                     break;
3716                 case 0x055: /* VIS I fpsub16s */
3717                     gen_op_load_fpr_FT0(rs1);
3718                     gen_op_load_fpr_FT1(rs2);
3719                     tcg_gen_helper_0_0(helper_fpsub16s);
3720                     gen_op_store_FT0_fpr(rd);
3721                     break;
3722                 case 0x056: /* VIS I fpsub32 */
3723                     gen_op_load_fpr_DT0(DFPREG(rs1));
3724                     gen_op_load_fpr_DT1(DFPREG(rs2));
3725                     tcg_gen_helper_0_0(helper_fpadd32);
3726                     gen_op_store_DT0_fpr(DFPREG(rd));
3727                     break;
3728                 case 0x057: /* VIS I fpsub32s */
3729                     gen_op_load_fpr_FT0(rs1);
3730                     gen_op_load_fpr_FT1(rs2);
3731                     tcg_gen_helper_0_0(helper_fpsub32s);
3732                     gen_op_store_FT0_fpr(rd);
3733                     break;
3734                 case 0x060: /* VIS I fzero */
3735                     tcg_gen_helper_0_0(helper_movl_DT0_0);
3736                     gen_op_store_DT0_fpr(DFPREG(rd));
3737                     break;
3738                 case 0x061: /* VIS I fzeros */
3739                     tcg_gen_helper_0_0(helper_movl_FT0_0);
3740                     gen_op_store_FT0_fpr(rd);
3741                     break;
3742                 case 0x062: /* VIS I fnor */
3743                     gen_op_load_fpr_DT0(DFPREG(rs1));
3744                     gen_op_load_fpr_DT1(DFPREG(rs2));
3745                     tcg_gen_helper_0_0(helper_fnor);
3746                     gen_op_store_DT0_fpr(DFPREG(rd));
3747                     break;
3748                 case 0x063: /* VIS I fnors */
3749                     gen_op_load_fpr_FT0(rs1);
3750                     gen_op_load_fpr_FT1(rs2);
3751                     tcg_gen_helper_0_0(helper_fnors);
3752                     gen_op_store_FT0_fpr(rd);
3753                     break;
3754                 case 0x064: /* VIS I fandnot2 */
3755                     gen_op_load_fpr_DT1(DFPREG(rs1));
3756                     gen_op_load_fpr_DT0(DFPREG(rs2));
3757                     tcg_gen_helper_0_0(helper_fandnot);
3758                     gen_op_store_DT0_fpr(DFPREG(rd));
3759                     break;
3760                 case 0x065: /* VIS I fandnot2s */
3761                     gen_op_load_fpr_FT1(rs1);
3762                     gen_op_load_fpr_FT0(rs2);
3763                     tcg_gen_helper_0_0(helper_fandnots);
3764                     gen_op_store_FT0_fpr(rd);
3765                     break;
3766                 case 0x066: /* VIS I fnot2 */
3767                     gen_op_load_fpr_DT1(DFPREG(rs2));
3768                     tcg_gen_helper_0_0(helper_fnot);
3769                     gen_op_store_DT0_fpr(DFPREG(rd));
3770                     break;
3771                 case 0x067: /* VIS I fnot2s */
3772                     gen_op_load_fpr_FT1(rs2);
3773                     tcg_gen_helper_0_0(helper_fnot);
3774                     gen_op_store_FT0_fpr(rd);
3775                     break;
3776                 case 0x068: /* VIS I fandnot1 */
3777                     gen_op_load_fpr_DT0(DFPREG(rs1));
3778                     gen_op_load_fpr_DT1(DFPREG(rs2));
3779                     tcg_gen_helper_0_0(helper_fandnot);
3780                     gen_op_store_DT0_fpr(DFPREG(rd));
3781                     break;
3782                 case 0x069: /* VIS I fandnot1s */
3783                     gen_op_load_fpr_FT0(rs1);
3784                     gen_op_load_fpr_FT1(rs2);
3785                     tcg_gen_helper_0_0(helper_fandnots);
3786                     gen_op_store_FT0_fpr(rd);
3787                     break;
3788                 case 0x06a: /* VIS I fnot1 */
3789                     gen_op_load_fpr_DT1(DFPREG(rs1));
3790                     tcg_gen_helper_0_0(helper_fnot);
3791                     gen_op_store_DT0_fpr(DFPREG(rd));
3792                     break;
3793                 case 0x06b: /* VIS I fnot1s */
3794                     gen_op_load_fpr_FT1(rs1);
3795                     tcg_gen_helper_0_0(helper_fnot);
3796                     gen_op_store_FT0_fpr(rd);
3797                     break;
3798                 case 0x06c: /* VIS I fxor */
3799                     gen_op_load_fpr_DT0(DFPREG(rs1));
3800                     gen_op_load_fpr_DT1(DFPREG(rs2));
3801                     tcg_gen_helper_0_0(helper_fxor);
3802                     gen_op_store_DT0_fpr(DFPREG(rd));
3803                     break;
3804                 case 0x06d: /* VIS I fxors */
3805                     gen_op_load_fpr_FT0(rs1);
3806                     gen_op_load_fpr_FT1(rs2);
3807                     tcg_gen_helper_0_0(helper_fxors);
3808                     gen_op_store_FT0_fpr(rd);
3809                     break;
3810                 case 0x06e: /* VIS I fnand */
3811                     gen_op_load_fpr_DT0(DFPREG(rs1));
3812                     gen_op_load_fpr_DT1(DFPREG(rs2));
3813                     tcg_gen_helper_0_0(helper_fnand);
3814                     gen_op_store_DT0_fpr(DFPREG(rd));
3815                     break;
3816                 case 0x06f: /* VIS I fnands */
3817                     gen_op_load_fpr_FT0(rs1);
3818                     gen_op_load_fpr_FT1(rs2);
3819                     tcg_gen_helper_0_0(helper_fnands);
3820                     gen_op_store_FT0_fpr(rd);
3821                     break;
3822                 case 0x070: /* VIS I fand */
3823                     gen_op_load_fpr_DT0(DFPREG(rs1));
3824                     gen_op_load_fpr_DT1(DFPREG(rs2));
3825                     tcg_gen_helper_0_0(helper_fand);
3826                     gen_op_store_DT0_fpr(DFPREG(rd));
3827                     break;
3828                 case 0x071: /* VIS I fands */
3829                     gen_op_load_fpr_FT0(rs1);
3830                     gen_op_load_fpr_FT1(rs2);
3831                     tcg_gen_helper_0_0(helper_fands);
3832                     gen_op_store_FT0_fpr(rd);
3833                     break;
3834                 case 0x072: /* VIS I fxnor */
3835                     gen_op_load_fpr_DT0(DFPREG(rs1));
3836                     gen_op_load_fpr_DT1(DFPREG(rs2));
3837                     tcg_gen_helper_0_0(helper_fxnor);
3838                     gen_op_store_DT0_fpr(DFPREG(rd));
3839                     break;
3840                 case 0x073: /* VIS I fxnors */
3841                     gen_op_load_fpr_FT0(rs1);
3842                     gen_op_load_fpr_FT1(rs2);
3843                     tcg_gen_helper_0_0(helper_fxnors);
3844                     gen_op_store_FT0_fpr(rd);
3845                     break;
3846                 case 0x074: /* VIS I fsrc1 */
3847                     gen_op_load_fpr_DT0(DFPREG(rs1));
3848                     gen_op_store_DT0_fpr(DFPREG(rd));
3849                     break;
3850                 case 0x075: /* VIS I fsrc1s */
3851                     gen_op_load_fpr_FT0(rs1);
3852                     gen_op_store_FT0_fpr(rd);
3853                     break;
3854                 case 0x076: /* VIS I fornot2 */
3855                     gen_op_load_fpr_DT1(DFPREG(rs1));
3856                     gen_op_load_fpr_DT0(DFPREG(rs2));
3857                     tcg_gen_helper_0_0(helper_fornot);
3858                     gen_op_store_DT0_fpr(DFPREG(rd));
3859                     break;
3860                 case 0x077: /* VIS I fornot2s */
3861                     gen_op_load_fpr_FT1(rs1);
3862                     gen_op_load_fpr_FT0(rs2);
3863                     tcg_gen_helper_0_0(helper_fornots);
3864                     gen_op_store_FT0_fpr(rd);
3865                     break;
3866                 case 0x078: /* VIS I fsrc2 */
3867                     gen_op_load_fpr_DT0(DFPREG(rs2));
3868                     gen_op_store_DT0_fpr(DFPREG(rd));
3869                     break;
3870                 case 0x079: /* VIS I fsrc2s */
3871                     gen_op_load_fpr_FT0(rs2);
3872                     gen_op_store_FT0_fpr(rd);
3873                     break;
3874                 case 0x07a: /* VIS I fornot1 */
3875                     gen_op_load_fpr_DT0(DFPREG(rs1));
3876                     gen_op_load_fpr_DT1(DFPREG(rs2));
3877                     tcg_gen_helper_0_0(helper_fornot);
3878                     gen_op_store_DT0_fpr(DFPREG(rd));
3879                     break;
3880                 case 0x07b: /* VIS I fornot1s */
3881                     gen_op_load_fpr_FT0(rs1);
3882                     gen_op_load_fpr_FT1(rs2);
3883                     tcg_gen_helper_0_0(helper_fornots);
3884                     gen_op_store_FT0_fpr(rd);
3885                     break;
3886                 case 0x07c: /* VIS I for */
3887                     gen_op_load_fpr_DT0(DFPREG(rs1));
3888                     gen_op_load_fpr_DT1(DFPREG(rs2));
3889                     tcg_gen_helper_0_0(helper_for);
3890                     gen_op_store_DT0_fpr(DFPREG(rd));
3891                     break;
3892                 case 0x07d: /* VIS I fors */
3893                     gen_op_load_fpr_FT0(rs1);
3894                     gen_op_load_fpr_FT1(rs2);
3895                     tcg_gen_helper_0_0(helper_fors);
3896                     gen_op_store_FT0_fpr(rd);
3897                     break;
3898                 case 0x07e: /* VIS I fone */
3899                     tcg_gen_helper_0_0(helper_movl_DT0_1);
3900                     gen_op_store_DT0_fpr(DFPREG(rd));
3901                     break;
3902                 case 0x07f: /* VIS I fones */
3903                     tcg_gen_helper_0_0(helper_movl_FT0_1);
3904                     gen_op_store_FT0_fpr(rd);
3905                     break;
3906                 case 0x080: /* VIS I shutdown */
3907                 case 0x081: /* VIS II siam */
3908                     // XXX
3909                     goto illegal_insn;
3910                 default:
3911                     goto illegal_insn;
3912                 }
3913 #else
3914                 goto ncp_insn;
3915 #endif
3916             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
3917 #ifdef TARGET_SPARC64
3918                 goto illegal_insn;
3919 #else
3920                 goto ncp_insn;
3921 #endif
3922 #ifdef TARGET_SPARC64
3923             } else if (xop == 0x39) { /* V9 return */
3924                 save_state(dc, cpu_cond);
3925                 cpu_src1 = get_src1(insn, cpu_src1);
3926                 if (IS_IMM) {   /* immediate */
3927                     rs2 = GET_FIELDs(insn, 19, 31);
3928                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3929                 } else {                /* register */
3930                     rs2 = GET_FIELD(insn, 27, 31);
3931 #if defined(OPTIM)
3932                     if (rs2) {
3933 #endif
3934                         gen_movl_reg_TN(rs2, cpu_src2);
3935                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3936 #if defined(OPTIM)
3937                     }
3938 #endif
3939                 }
3940                 tcg_gen_helper_0_0(helper_restore);
3941                 gen_mov_pc_npc(dc, cpu_cond);
3942                 tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3943                 tcg_gen_mov_tl(cpu_npc, cpu_dst);
3944                 dc->npc = DYNAMIC_PC;
3945                 goto jmp_insn;
3946 #endif
3947             } else {
3948                 cpu_src1 = get_src1(insn, cpu_src1);
3949                 if (IS_IMM) {   /* immediate */
3950                     rs2 = GET_FIELDs(insn, 19, 31);
3951                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3952                 } else {                /* register */
3953                     rs2 = GET_FIELD(insn, 27, 31);
3954 #if defined(OPTIM)
3955                     if (rs2) {
3956 #endif
3957                         gen_movl_reg_TN(rs2, cpu_src2);
3958                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3959 #if defined(OPTIM)
3960                     }
3961 #endif
3962                 }
3963                 switch (xop) {
3964                 case 0x38:      /* jmpl */
3965                     {
3966                         if (rd != 0) {
3967                             tcg_gen_movi_tl(cpu_tmp0, dc->pc);
3968                             gen_movl_TN_reg(rd, cpu_tmp0);
3969                         }
3970                         gen_mov_pc_npc(dc, cpu_cond);
3971                         tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3972                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
3973                         dc->npc = DYNAMIC_PC;
3974                     }
3975                     goto jmp_insn;
3976 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3977                 case 0x39:      /* rett, V9 return */
3978                     {
3979                         if (!supervisor(dc))
3980                             goto priv_insn;
3981                         gen_mov_pc_npc(dc, cpu_cond);
3982                         tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3983                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
3984                         dc->npc = DYNAMIC_PC;
3985                         tcg_gen_helper_0_0(helper_rett);
3986                     }
3987                     goto jmp_insn;
3988 #endif
3989                 case 0x3b: /* flush */
3990                     tcg_gen_helper_0_1(helper_flush, cpu_dst);
3991                     break;
3992                 case 0x3c:      /* save */
3993                     save_state(dc, cpu_cond);
3994                     tcg_gen_helper_0_0(helper_save);
3995                     gen_movl_TN_reg(rd, cpu_dst);
3996                     break;
3997                 case 0x3d:      /* restore */
3998                     save_state(dc, cpu_cond);
3999                     tcg_gen_helper_0_0(helper_restore);
4000                     gen_movl_TN_reg(rd, cpu_dst);
4001                     break;
4002 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4003                 case 0x3e:      /* V9 done/retry */
4004                     {
4005                         switch (rd) {
4006                         case 0:
4007                             if (!supervisor(dc))
4008                                 goto priv_insn;
4009                             dc->npc = DYNAMIC_PC;
4010                             dc->pc = DYNAMIC_PC;
4011                             tcg_gen_helper_0_0(helper_done);
4012                             goto jmp_insn;
4013                         case 1:
4014                             if (!supervisor(dc))
4015                                 goto priv_insn;
4016                             dc->npc = DYNAMIC_PC;
4017                             dc->pc = DYNAMIC_PC;
4018                             tcg_gen_helper_0_0(helper_retry);
4019                             goto jmp_insn;
4020                         default:
4021                             goto illegal_insn;
4022                         }
4023                     }
4024                     break;
4025 #endif
4026                 default:
4027                     goto illegal_insn;
4028                 }
4029             }
4030             break;
4031         }
4032         break;
4033     case 3:                     /* load/store instructions */
4034         {
4035             unsigned int xop = GET_FIELD(insn, 7, 12);
4036
4037             save_state(dc, cpu_cond);
4038             cpu_src1 = get_src1(insn, cpu_src1);
4039             if (xop == 0x3c || xop == 0x3e)
4040             {
4041                 rs2 = GET_FIELD(insn, 27, 31);
4042                 gen_movl_reg_TN(rs2, cpu_src2);
4043             }
4044             else if (IS_IMM) {       /* immediate */
4045                 rs2 = GET_FIELDs(insn, 19, 31);
4046                 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4047             } else {            /* register */
4048                 rs2 = GET_FIELD(insn, 27, 31);
4049 #if defined(OPTIM)
4050                 if (rs2 != 0) {
4051 #endif
4052                     gen_movl_reg_TN(rs2, cpu_src2);
4053                     tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4054 #if defined(OPTIM)
4055                 }
4056 #endif
4057             }
4058             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4059                 (xop > 0x17 && xop <= 0x1d ) ||
4060                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4061                 switch (xop) {
4062                 case 0x0:       /* load unsigned word */
4063                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4064                     ABI32_MASK(cpu_addr);
4065                     tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4066                     break;
4067                 case 0x1:       /* load unsigned byte */
4068                     ABI32_MASK(cpu_addr);
4069                     tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4070                     break;
4071                 case 0x2:       /* load unsigned halfword */
4072                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4073                     ABI32_MASK(cpu_addr);
4074                     tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4075                     break;
4076                 case 0x3:       /* load double word */
4077                     if (rd & 1)
4078                         goto illegal_insn;
4079                     else {
4080                         tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4081                         ABI32_MASK(cpu_addr);
4082                         tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4083                         tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4084                         tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4085                         gen_movl_TN_reg(rd + 1, cpu_tmp0);
4086                         tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4087                         tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4088                         tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4089                     }
4090                     break;
4091                 case 0x9:       /* load signed byte */
4092                     ABI32_MASK(cpu_addr);
4093                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4094                     break;
4095                 case 0xa:       /* load signed halfword */
4096                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4097                     ABI32_MASK(cpu_addr);
4098                     tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4099                     break;
4100                 case 0xd:       /* ldstub -- XXX: should be atomically */
4101                     ABI32_MASK(cpu_addr);
4102                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4103                     tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, dc->mem_idx);
4104                     break;
4105                 case 0x0f:      /* swap register with memory. Also atomically */
4106                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4107                     gen_movl_reg_TN(rd, cpu_val);
4108                     ABI32_MASK(cpu_addr);
4109                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4110                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4111                     tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4112                     break;
4113 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4114                 case 0x10:      /* load word alternate */
4115 #ifndef TARGET_SPARC64
4116                     if (IS_IMM)
4117                         goto illegal_insn;
4118                     if (!supervisor(dc))
4119                         goto priv_insn;
4120 #endif
4121                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4122                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4123                     break;
4124                 case 0x11:      /* load unsigned byte alternate */
4125 #ifndef TARGET_SPARC64
4126                     if (IS_IMM)
4127                         goto illegal_insn;
4128                     if (!supervisor(dc))
4129                         goto priv_insn;
4130 #endif
4131                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4132                     break;
4133                 case 0x12:      /* load unsigned halfword alternate */
4134 #ifndef TARGET_SPARC64
4135                     if (IS_IMM)
4136                         goto illegal_insn;
4137                     if (!supervisor(dc))
4138                         goto priv_insn;
4139 #endif
4140                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4141                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4142                     break;
4143                 case 0x13:      /* load double word alternate */
4144 #ifndef TARGET_SPARC64
4145                     if (IS_IMM)
4146                         goto illegal_insn;
4147                     if (!supervisor(dc))
4148                         goto priv_insn;
4149 #endif
4150                     if (rd & 1)
4151                         goto illegal_insn;
4152                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4153                     gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4154                     gen_movl_TN_reg(rd + 1, cpu_tmp0);
4155                     break;
4156                 case 0x19:      /* load signed byte alternate */
4157 #ifndef TARGET_SPARC64
4158                     if (IS_IMM)
4159                         goto illegal_insn;
4160                     if (!supervisor(dc))
4161                         goto priv_insn;
4162 #endif
4163                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4164                     break;
4165                 case 0x1a:      /* load signed halfword alternate */
4166 #ifndef TARGET_SPARC64
4167                     if (IS_IMM)
4168                         goto illegal_insn;
4169                     if (!supervisor(dc))
4170                         goto priv_insn;
4171 #endif
4172                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4173                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4174                     break;
4175                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
4176 #ifndef TARGET_SPARC64
4177                     if (IS_IMM)
4178                         goto illegal_insn;
4179                     if (!supervisor(dc))
4180                         goto priv_insn;
4181 #endif
4182                     gen_ldstub_asi(cpu_val, cpu_addr, insn);
4183                     break;
4184                 case 0x1f:      /* swap reg with alt. memory. Also atomically */
4185 #ifndef TARGET_SPARC64
4186                     if (IS_IMM)
4187                         goto illegal_insn;
4188                     if (!supervisor(dc))
4189                         goto priv_insn;
4190 #endif
4191                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4192                     gen_movl_reg_TN(rd, cpu_val);
4193                     gen_swap_asi(cpu_val, cpu_addr, insn);
4194                     break;
4195
4196 #ifndef TARGET_SPARC64
4197                 case 0x30: /* ldc */
4198                 case 0x31: /* ldcsr */
4199                 case 0x33: /* lddc */
4200                     goto ncp_insn;
4201 #endif
4202 #endif
4203 #ifdef TARGET_SPARC64
4204                 case 0x08: /* V9 ldsw */
4205                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4206                     ABI32_MASK(cpu_addr);
4207                     tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4208                     break;
4209                 case 0x0b: /* V9 ldx */
4210                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4211                     ABI32_MASK(cpu_addr);
4212                     tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4213                     break;
4214                 case 0x18: /* V9 ldswa */
4215                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4216                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4217                     break;
4218                 case 0x1b: /* V9 ldxa */
4219                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4220                     gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4221                     break;
4222                 case 0x2d: /* V9 prefetch, no effect */
4223                     goto skip_move;
4224                 case 0x30: /* V9 ldfa */
4225                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4226                     gen_ldf_asi(cpu_addr, insn, 4, rd);
4227                     goto skip_move;
4228                 case 0x33: /* V9 lddfa */
4229                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4230                     gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4231                     goto skip_move;
4232                 case 0x3d: /* V9 prefetcha, no effect */
4233                     goto skip_move;
4234                 case 0x32: /* V9 ldqfa */
4235 #if defined(CONFIG_USER_ONLY)
4236                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4237                     gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4238                     goto skip_move;
4239 #else
4240                     goto nfpu_insn;
4241 #endif
4242 #endif
4243                 default:
4244                     goto illegal_insn;
4245                 }
4246                 gen_movl_TN_reg(rd, cpu_val);
4247 #ifdef TARGET_SPARC64
4248             skip_move: ;
4249 #endif
4250             } else if (xop >= 0x20 && xop < 0x24) {
4251                 if (gen_trap_ifnofpu(dc, cpu_cond))
4252                     goto jmp_insn;
4253                 switch (xop) {
4254                 case 0x20:      /* load fpreg */
4255                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4256                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4257                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4258                                    offsetof(CPUState, fpr[rd]));
4259                     break;
4260                 case 0x21:      /* load fsr */
4261                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4262                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4263                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4264                                    offsetof(CPUState, ft0));
4265                     tcg_gen_helper_0_0(helper_ldfsr);
4266                     break;
4267                 case 0x22:      /* load quad fpreg */
4268 #if defined(CONFIG_USER_ONLY)
4269                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4270                     gen_op_ldst(ldqf);
4271                     gen_op_store_QT0_fpr(QFPREG(rd));
4272                     break;
4273 #else
4274                     goto nfpu_insn;
4275 #endif
4276                 case 0x23:      /* load double fpreg */
4277                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4278                     gen_op_ldst(lddf);
4279                     gen_op_store_DT0_fpr(DFPREG(rd));
4280                     break;
4281                 default:
4282                     goto illegal_insn;
4283                 }
4284             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4285                        xop == 0xe || xop == 0x1e) {
4286                 gen_movl_reg_TN(rd, cpu_val);
4287                 switch (xop) {
4288                 case 0x4: /* store word */
4289                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4290                     ABI32_MASK(cpu_addr);
4291                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4292                     break;
4293                 case 0x5: /* store byte */
4294                     ABI32_MASK(cpu_addr);
4295                     tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4296                     break;
4297                 case 0x6: /* store halfword */
4298                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4299                     ABI32_MASK(cpu_addr);
4300                     tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4301                     break;
4302                 case 0x7: /* store double word */
4303                     if (rd & 1)
4304                         goto illegal_insn;
4305 #ifndef __i386__
4306                     else {
4307                         TCGv r_low;
4308
4309                         tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4310                         r_low = tcg_temp_new(TCG_TYPE_I32);
4311                         gen_movl_reg_TN(rd + 1, r_low);
4312                         tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4313                                            r_low);
4314                         tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4315                     }
4316 #else /* __i386__ */
4317                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4318                     flush_cond(dc, cpu_cond);
4319                     gen_movl_reg_TN(rd + 1, cpu_cond);
4320                     gen_op_ldst(std);
4321 #endif /* __i386__ */
4322                     break;
4323 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4324                 case 0x14: /* store word alternate */
4325 #ifndef TARGET_SPARC64
4326                     if (IS_IMM)
4327                         goto illegal_insn;
4328                     if (!supervisor(dc))
4329                         goto priv_insn;
4330 #endif
4331                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4332                     gen_st_asi(cpu_val, cpu_addr, insn, 4);
4333                     break;
4334                 case 0x15: /* store byte alternate */
4335 #ifndef TARGET_SPARC64
4336                     if (IS_IMM)
4337                         goto illegal_insn;
4338                     if (!supervisor(dc))
4339                         goto priv_insn;
4340 #endif
4341                     gen_st_asi(cpu_val, cpu_addr, insn, 1);
4342                     break;
4343                 case 0x16: /* store halfword alternate */
4344 #ifndef TARGET_SPARC64
4345                     if (IS_IMM)
4346                         goto illegal_insn;
4347                     if (!supervisor(dc))
4348                         goto priv_insn;
4349 #endif
4350                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4351                     gen_st_asi(cpu_val, cpu_addr, insn, 2);
4352                     break;
4353                 case 0x17: /* store double word alternate */
4354 #ifndef TARGET_SPARC64
4355                     if (IS_IMM)
4356                         goto illegal_insn;
4357                     if (!supervisor(dc))
4358                         goto priv_insn;
4359 #endif
4360                     if (rd & 1)
4361                         goto illegal_insn;
4362                     else {
4363                         tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4364                         gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4365                     }
4366                     break;
4367 #endif
4368 #ifdef TARGET_SPARC64
4369                 case 0x0e: /* V9 stx */
4370                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4371                     ABI32_MASK(cpu_addr);
4372                     tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4373                     break;
4374                 case 0x1e: /* V9 stxa */
4375                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4376                     gen_st_asi(cpu_val, cpu_addr, insn, 8);
4377                     break;
4378 #endif
4379                 default:
4380                     goto illegal_insn;
4381                 }
4382             } else if (xop > 0x23 && xop < 0x28) {
4383                 if (gen_trap_ifnofpu(dc, cpu_cond))
4384                     goto jmp_insn;
4385                 switch (xop) {
4386                 case 0x24: /* store fpreg */
4387                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4388                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4389                                    offsetof(CPUState, fpr[rd]));
4390                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4391                     break;
4392                 case 0x25: /* stfsr, V9 stxfsr */
4393 #ifdef CONFIG_USER_ONLY
4394                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4395 #endif
4396                     tcg_gen_helper_0_0(helper_stfsr);
4397                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4398                                    offsetof(CPUState, ft0));
4399                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4400                     break;
4401                 case 0x26:
4402 #ifdef TARGET_SPARC64
4403 #if defined(CONFIG_USER_ONLY)
4404                     /* V9 stqf, store quad fpreg */
4405                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4406                     gen_op_load_fpr_QT0(QFPREG(rd));
4407                     gen_op_ldst(stqf);
4408                     break;
4409 #else
4410                     goto nfpu_insn;
4411 #endif
4412 #else /* !TARGET_SPARC64 */
4413                     /* stdfq, store floating point queue */
4414 #if defined(CONFIG_USER_ONLY)
4415                     goto illegal_insn;
4416 #else
4417                     if (!supervisor(dc))
4418                         goto priv_insn;
4419                     if (gen_trap_ifnofpu(dc, cpu_cond))
4420                         goto jmp_insn;
4421                     goto nfq_insn;
4422 #endif
4423 #endif
4424                 case 0x27:
4425                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4426                     gen_op_load_fpr_DT0(DFPREG(rd));
4427                     gen_op_ldst(stdf);
4428                     break;
4429                 default:
4430                     goto illegal_insn;
4431                 }
4432             } else if (xop > 0x33 && xop < 0x3f) {
4433                 switch (xop) {
4434 #ifdef TARGET_SPARC64
4435                 case 0x34: /* V9 stfa */
4436                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4437                     gen_op_load_fpr_FT0(rd);
4438                     gen_stf_asi(cpu_addr, insn, 4, rd);
4439                     break;
4440                 case 0x36: /* V9 stqfa */
4441 #if defined(CONFIG_USER_ONLY)
4442                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4443                     gen_op_load_fpr_QT0(QFPREG(rd));
4444                     gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4445                     break;
4446 #else
4447                     goto nfpu_insn;
4448 #endif
4449                 case 0x37: /* V9 stdfa */
4450                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4451                     gen_op_load_fpr_DT0(DFPREG(rd));
4452                     gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4453                     break;
4454                 case 0x3c: /* V9 casa */
4455                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4456                     gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4457                     gen_movl_TN_reg(rd, cpu_val);
4458                     break;
4459                 case 0x3e: /* V9 casxa */
4460                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4461                     gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4462                     gen_movl_TN_reg(rd, cpu_val);
4463                     break;
4464 #else
4465                 case 0x34: /* stc */
4466                 case 0x35: /* stcsr */
4467                 case 0x36: /* stdcq */
4468                 case 0x37: /* stdc */
4469                     goto ncp_insn;
4470 #endif
4471                 default:
4472                     goto illegal_insn;
4473                 }
4474             }
4475             else
4476                 goto illegal_insn;
4477         }
4478         break;
4479     }
4480     /* default case for non jump instructions */
4481     if (dc->npc == DYNAMIC_PC) {
4482         dc->pc = DYNAMIC_PC;
4483         gen_op_next_insn();
4484     } else if (dc->npc == JUMP_PC) {
4485         /* we can do a static jump */
4486         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4487         dc->is_br = 1;
4488     } else {
4489         dc->pc = dc->npc;
4490         dc->npc = dc->npc + 4;
4491     }
4492  jmp_insn:
4493     return;
4494  illegal_insn:
4495     save_state(dc, cpu_cond);
4496     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
4497     dc->is_br = 1;
4498     return;
4499 #if !defined(CONFIG_USER_ONLY)
4500  priv_insn:
4501     save_state(dc, cpu_cond);
4502     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
4503     dc->is_br = 1;
4504     return;
4505  nfpu_insn:
4506     save_state(dc, cpu_cond);
4507     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4508     dc->is_br = 1;
4509     return;
4510 #ifndef TARGET_SPARC64
4511  nfq_insn:
4512     save_state(dc, cpu_cond);
4513     gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4514     dc->is_br = 1;
4515     return;
4516 #endif
4517 #endif
4518 #ifndef TARGET_SPARC64
4519  ncp_insn:
4520     save_state(dc, cpu_cond);
4521     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
4522     dc->is_br = 1;
4523     return;
4524 #endif
4525 }
4526
4527 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
4528 {
4529 }
4530
4531 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4532                                                  int spc, CPUSPARCState *env)
4533 {
4534     target_ulong pc_start, last_pc;
4535     uint16_t *gen_opc_end;
4536     DisasContext dc1, *dc = &dc1;
4537     int j, lj = -1;
4538
4539     memset(dc, 0, sizeof(DisasContext));
4540     dc->tb = tb;
4541     pc_start = tb->pc;
4542     dc->pc = pc_start;
4543     last_pc = dc->pc;
4544     dc->npc = (target_ulong) tb->cs_base;
4545     dc->mem_idx = cpu_mmu_index(env);
4546     dc->fpu_enabled = cpu_fpu_enabled(env);
4547     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4548
4549     cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4550     cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4551     cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4552
4553     cpu_cond = cpu_T[2];
4554
4555     do {
4556         if (env->nb_breakpoints > 0) {
4557             for(j = 0; j < env->nb_breakpoints; j++) {
4558                 if (env->breakpoints[j] == dc->pc) {
4559                     if (dc->pc != pc_start)
4560                         save_state(dc, cpu_cond);
4561                     tcg_gen_helper_0_0(helper_debug);
4562                     tcg_gen_exit_tb(0);
4563                     dc->is_br = 1;
4564                     goto exit_gen_loop;
4565                 }
4566             }
4567         }
4568         if (spc) {
4569             if (loglevel > 0)
4570                 fprintf(logfile, "Search PC...\n");
4571             j = gen_opc_ptr - gen_opc_buf;
4572             if (lj < j) {
4573                 lj++;
4574                 while (lj < j)
4575                     gen_opc_instr_start[lj++] = 0;
4576                 gen_opc_pc[lj] = dc->pc;
4577                 gen_opc_npc[lj] = dc->npc;
4578                 gen_opc_instr_start[lj] = 1;
4579             }
4580         }
4581         last_pc = dc->pc;
4582         disas_sparc_insn(dc);
4583
4584         if (dc->is_br)
4585             break;
4586         /* if the next PC is different, we abort now */
4587         if (dc->pc != (last_pc + 4))
4588             break;
4589         /* if we reach a page boundary, we stop generation so that the
4590            PC of a TT_TFAULT exception is always in the right page */
4591         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4592             break;
4593         /* if single step mode, we generate only one instruction and
4594            generate an exception */
4595         if (env->singlestep_enabled) {
4596             tcg_gen_movi_tl(cpu_pc, dc->pc);
4597             tcg_gen_exit_tb(0);
4598             break;
4599         }
4600     } while ((gen_opc_ptr < gen_opc_end) &&
4601              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4602
4603  exit_gen_loop:
4604     if (!dc->is_br) {
4605         if (dc->pc != DYNAMIC_PC &&
4606             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4607             /* static PC and NPC: we can use direct chaining */
4608             gen_goto_tb(dc, 0, dc->pc, dc->npc);
4609         } else {
4610             if (dc->pc != DYNAMIC_PC)
4611                 tcg_gen_movi_tl(cpu_pc, dc->pc);
4612             save_npc(dc, cpu_cond);
4613             tcg_gen_exit_tb(0);
4614         }
4615     }
4616     *gen_opc_ptr = INDEX_op_end;
4617     if (spc) {
4618         j = gen_opc_ptr - gen_opc_buf;
4619         lj++;
4620         while (lj <= j)
4621             gen_opc_instr_start[lj++] = 0;
4622 #if 0
4623         if (loglevel > 0) {
4624             page_dump(logfile);
4625         }
4626 #endif
4627         gen_opc_jump_pc[0] = dc->jump_pc[0];
4628         gen_opc_jump_pc[1] = dc->jump_pc[1];
4629     } else {
4630         tb->size = last_pc + 4 - pc_start;
4631     }
4632 #ifdef DEBUG_DISAS
4633     if (loglevel & CPU_LOG_TB_IN_ASM) {
4634         fprintf(logfile, "--------------\n");
4635         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4636         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4637         fprintf(logfile, "\n");
4638     }
4639 #endif
4640     return 0;
4641 }
4642
4643 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4644 {
4645     return gen_intermediate_code_internal(tb, 0, env);
4646 }
4647
4648 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4649 {
4650     return gen_intermediate_code_internal(tb, 1, env);
4651 }
4652
4653 void gen_intermediate_code_init(CPUSPARCState *env)
4654 {
4655     unsigned int i;
4656     static int inited;
4657     static const char * const gregnames[8] = {
4658         NULL, // g0 not used
4659         "g1",
4660         "g2",
4661         "g3",
4662         "g4",
4663         "g5",
4664         "g6",
4665         "g7",
4666     };
4667
4668     /* init various static tables */
4669     if (!inited) {
4670         inited = 1;
4671
4672         tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
4673         cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4674         cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4675                                          offsetof(CPUState, regwptr),
4676                                          "regwptr");
4677         //#if TARGET_LONG_BITS > HOST_LONG_BITS
4678 #ifdef TARGET_SPARC64
4679         cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4680                                       TCG_AREG0, offsetof(CPUState, t0), "T0");
4681         cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4682                                       TCG_AREG0, offsetof(CPUState, t1), "T1");
4683         cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4684                                       TCG_AREG0, offsetof(CPUState, t2), "T2");
4685         cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4686                                      TCG_AREG0, offsetof(CPUState, xcc),
4687                                      "xcc");
4688 #else
4689         cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4690         cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4691         cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4692 #endif
4693         cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4694                                         TCG_AREG0, offsetof(CPUState, cc_src),
4695                                         "cc_src");
4696         cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4697                                          offsetof(CPUState, cc_src2),
4698                                          "cc_src2");
4699         cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4700                                         TCG_AREG0, offsetof(CPUState, cc_dst),
4701                                         "cc_dst");
4702         cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4703                                      TCG_AREG0, offsetof(CPUState, psr),
4704                                      "psr");
4705         cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4706                                      TCG_AREG0, offsetof(CPUState, fsr),
4707                                      "fsr");
4708         cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4709                                     TCG_AREG0, offsetof(CPUState, pc),
4710                                     "pc");
4711         cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4712                                     TCG_AREG0, offsetof(CPUState, npc),
4713                                     "npc");
4714         for (i = 1; i < 8; i++)
4715             cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4716                                               offsetof(CPUState, gregs[i]),
4717                                               gregnames[i]);
4718     }
4719 }