git.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23    TODO-list:
  24
  25    NPC/PC static optimisations (use JUMP_TB when possible)
  26    FPU-Instructions
  27    Privileged instructions
  28    Coprocessor-Instructions
  29    Optimize synthetic instructions
  30    Optional alignment and privileged instruction check
  31 */
  32
  33 #include <stdarg.h>
  34 #include <stdlib.h>
  35 #include <stdio.h>
  36 #include <string.h>
  37 #include <inttypes.h>
  38
  39 #include "cpu.h"
  40 #include "exec-all.h"
  41 #include "disas.h"
  42
  43 #define DEBUG_DISAS
  44
  45 #define DYNAMIC_PC  1 /* dynamic pc value */
  46 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  47                          according to jump_pc[T2] */
  48
  49 typedef struct DisasContext {
  50     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  51     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  52     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  53     int is_br;
  54     int mem_idx;
  55     struct TranslationBlock *tb;
  56 } DisasContext;
  57
  58 static uint16_t *gen_opc_ptr;
  59 static uint32_t *gen_opparam_ptr;
  60 extern FILE *logfile;
  61 extern int loglevel;
  62
  63 enum {
  64 #define DEF(s,n,copy_size) INDEX_op_ ## s,
  65 #include "opc.h"
  66 #undef DEF
  67     NB_OPS
  68 };
  69
  70 #include "gen-op.h"
  71
  72 #define GET_FIELD(X, FROM, TO) \
  73   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  74
  75 #define IS_IMM (insn & (1<<13))
  76
  77 static void disas_sparc_insn(DisasContext * dc);
  78
  79 static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
  80     {
  81      gen_op_movl_g0_T0,
  82      gen_op_movl_g1_T0,
  83      gen_op_movl_g2_T0,
  84      gen_op_movl_g3_T0,
  85      gen_op_movl_g4_T0,
  86      gen_op_movl_g5_T0,
  87      gen_op_movl_g6_T0,
  88      gen_op_movl_g7_T0,
  89      gen_op_movl_o0_T0,
  90      gen_op_movl_o1_T0,
  91      gen_op_movl_o2_T0,
  92      gen_op_movl_o3_T0,
  93      gen_op_movl_o4_T0,
  94      gen_op_movl_o5_T0,
  95      gen_op_movl_o6_T0,
  96      gen_op_movl_o7_T0,
  97      gen_op_movl_l0_T0,
  98      gen_op_movl_l1_T0,
  99      gen_op_movl_l2_T0,
 100      gen_op_movl_l3_T0,
 101      gen_op_movl_l4_T0,
 102      gen_op_movl_l5_T0,
 103      gen_op_movl_l6_T0,
 104      gen_op_movl_l7_T0,
 105      gen_op_movl_i0_T0,
 106      gen_op_movl_i1_T0,
 107      gen_op_movl_i2_T0,
 108      gen_op_movl_i3_T0,
 109      gen_op_movl_i4_T0,
 110      gen_op_movl_i5_T0,
 111      gen_op_movl_i6_T0,
 112      gen_op_movl_i7_T0,
 113      },
 114     {
 115      gen_op_movl_g0_T1,
 116      gen_op_movl_g1_T1,
 117      gen_op_movl_g2_T1,
 118      gen_op_movl_g3_T1,
 119      gen_op_movl_g4_T1,
 120      gen_op_movl_g5_T1,
 121      gen_op_movl_g6_T1,
 122      gen_op_movl_g7_T1,
 123      gen_op_movl_o0_T1,
 124      gen_op_movl_o1_T1,
 125      gen_op_movl_o2_T1,
 126      gen_op_movl_o3_T1,
 127      gen_op_movl_o4_T1,
 128      gen_op_movl_o5_T1,
 129      gen_op_movl_o6_T1,
 130      gen_op_movl_o7_T1,
 131      gen_op_movl_l0_T1,
 132      gen_op_movl_l1_T1,
 133      gen_op_movl_l2_T1,
 134      gen_op_movl_l3_T1,
 135      gen_op_movl_l4_T1,
 136      gen_op_movl_l5_T1,
 137      gen_op_movl_l6_T1,
 138      gen_op_movl_l7_T1,
 139      gen_op_movl_i0_T1,
 140      gen_op_movl_i1_T1,
 141      gen_op_movl_i2_T1,
 142      gen_op_movl_i3_T1,
 143      gen_op_movl_i4_T1,
 144      gen_op_movl_i5_T1,
 145      gen_op_movl_i6_T1,
 146      gen_op_movl_i7_T1,
 147      }
 148 };
 149
 150 static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
 151     {
 152      gen_op_movl_T0_g0,
 153      gen_op_movl_T0_g1,
 154      gen_op_movl_T0_g2,
 155      gen_op_movl_T0_g3,
 156      gen_op_movl_T0_g4,
 157      gen_op_movl_T0_g5,
 158      gen_op_movl_T0_g6,
 159      gen_op_movl_T0_g7,
 160      gen_op_movl_T0_o0,
 161      gen_op_movl_T0_o1,
 162      gen_op_movl_T0_o2,
 163      gen_op_movl_T0_o3,
 164      gen_op_movl_T0_o4,
 165      gen_op_movl_T0_o5,
 166      gen_op_movl_T0_o6,
 167      gen_op_movl_T0_o7,
 168      gen_op_movl_T0_l0,
 169      gen_op_movl_T0_l1,
 170      gen_op_movl_T0_l2,
 171      gen_op_movl_T0_l3,
 172      gen_op_movl_T0_l4,
 173      gen_op_movl_T0_l5,
 174      gen_op_movl_T0_l6,
 175      gen_op_movl_T0_l7,
 176      gen_op_movl_T0_i0,
 177      gen_op_movl_T0_i1,
 178      gen_op_movl_T0_i2,
 179      gen_op_movl_T0_i3,
 180      gen_op_movl_T0_i4,
 181      gen_op_movl_T0_i5,
 182      gen_op_movl_T0_i6,
 183      gen_op_movl_T0_i7,
 184      },
 185     {
 186      gen_op_movl_T1_g0,
 187      gen_op_movl_T1_g1,
 188      gen_op_movl_T1_g2,
 189      gen_op_movl_T1_g3,
 190      gen_op_movl_T1_g4,
 191      gen_op_movl_T1_g5,
 192      gen_op_movl_T1_g6,
 193      gen_op_movl_T1_g7,
 194      gen_op_movl_T1_o0,
 195      gen_op_movl_T1_o1,
 196      gen_op_movl_T1_o2,
 197      gen_op_movl_T1_o3,
 198      gen_op_movl_T1_o4,
 199      gen_op_movl_T1_o5,
 200      gen_op_movl_T1_o6,
 201      gen_op_movl_T1_o7,
 202      gen_op_movl_T1_l0,
 203      gen_op_movl_T1_l1,
 204      gen_op_movl_T1_l2,
 205      gen_op_movl_T1_l3,
 206      gen_op_movl_T1_l4,
 207      gen_op_movl_T1_l5,
 208      gen_op_movl_T1_l6,
 209      gen_op_movl_T1_l7,
 210      gen_op_movl_T1_i0,
 211      gen_op_movl_T1_i1,
 212      gen_op_movl_T1_i2,
 213      gen_op_movl_T1_i3,
 214      gen_op_movl_T1_i4,
 215      gen_op_movl_T1_i5,
 216      gen_op_movl_T1_i6,
 217      gen_op_movl_T1_i7,
 218      },
 219     {
 220      gen_op_movl_T2_g0,
 221      gen_op_movl_T2_g1,
 222      gen_op_movl_T2_g2,
 223      gen_op_movl_T2_g3,
 224      gen_op_movl_T2_g4,
 225      gen_op_movl_T2_g5,
 226      gen_op_movl_T2_g6,
 227      gen_op_movl_T2_g7,
 228      gen_op_movl_T2_o0,
 229      gen_op_movl_T2_o1,
 230      gen_op_movl_T2_o2,
 231      gen_op_movl_T2_o3,
 232      gen_op_movl_T2_o4,
 233      gen_op_movl_T2_o5,
 234      gen_op_movl_T2_o6,
 235      gen_op_movl_T2_o7,
 236      gen_op_movl_T2_l0,
 237      gen_op_movl_T2_l1,
 238      gen_op_movl_T2_l2,
 239      gen_op_movl_T2_l3,
 240      gen_op_movl_T2_l4,
 241      gen_op_movl_T2_l5,
 242      gen_op_movl_T2_l6,
 243      gen_op_movl_T2_l7,
 244      gen_op_movl_T2_i0,
 245      gen_op_movl_T2_i1,
 246      gen_op_movl_T2_i2,
 247      gen_op_movl_T2_i3,
 248      gen_op_movl_T2_i4,
 249      gen_op_movl_T2_i5,
 250      gen_op_movl_T2_i6,
 251      gen_op_movl_T2_i7,
 252      }
 253 };
 254
 255 static GenOpFunc1 *gen_op_movl_TN_im[3] = {
 256     gen_op_movl_T0_im,
 257     gen_op_movl_T1_im,
 258     gen_op_movl_T2_im
 259 };
 260
 261 #define GEN32(func, NAME) \
 262 static GenOpFunc *NAME ## _table [32] = {                                     \
 263 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
 264 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
 265 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
 266 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
 267 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
 268 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
 269 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
 270 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
 271 };                                                                            \
 272 static inline void func(int n)                                                \
 273 {                                                                             \
 274     NAME ## _table[n]();                                                      \
 275 }
 276
 277 /* floating point registers moves */
 278 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
 279 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
 280 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fprf);
 281 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
 282 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
 283 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fprf);
 284
 285 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
 286 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
 287 GEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fprf);
 288 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
 289 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
 290 GEN32(gen_op_store_DT2_fpr, gen_op_store_DT2_fpr_fprf);
 291
 292 #if defined(CONFIG_USER_ONLY)
 293 #define gen_op_ldst(name)        gen_op_##name##_raw()
 294 #define OP_LD_TABLE(width)
 295 #define supervisor(dc) 0
 296 #else
 297 #define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
 298 #define OP_LD_TABLE(width)                                                    \
 299 static GenOpFunc *gen_op_##width[] = {                                        \
 300     &gen_op_##width##_user,                                                   \
 301     &gen_op_##width##_kernel,                                                 \
 302 };                                                                            \
 303                                                                               \
 304 static void gen_op_##width##a(int insn, int is_ld, int size, int sign)        \
 305 {                                                                             \
 306     int asi;                                                                  \
 307                                                                               \
 308     asi = GET_FIELD(insn, 19, 26);                                            \
 309     switch (asi) {                                                            \
 310         case 10: /* User data access */                                       \
 311             gen_op_##width##_user();                                          \
 312             break;                                                            \
 313         case 11: /* Supervisor data access */                                 \
 314             gen_op_##width##_kernel();                                        \
 315             break;                                                            \
 316         case 0x20 ... 0x2f: /* MMU passthrough */                             \
 317             if (is_ld)                                                        \
 318                 gen_op_ld_asi(asi, size, sign);                               \
 319             else                                                              \
 320                 gen_op_st_asi(asi, size, sign);                               \
 321             break;                                                            \
 322         default:                                                              \
 323             if (is_ld)                                                        \
 324                 gen_op_ld_asi(asi, size, sign);                               \
 325             else                                                              \
 326                 gen_op_st_asi(asi, size, sign);                               \
 327             break;                                                            \
 328     }                                                                         \
 329 }
 330
 331 #define supervisor(dc) (dc->mem_idx == 1)
 332 #endif
 333
 334 OP_LD_TABLE(ld);
 335 OP_LD_TABLE(st);
 336 OP_LD_TABLE(ldub);
 337 OP_LD_TABLE(lduh);
 338 OP_LD_TABLE(ldsb);
 339 OP_LD_TABLE(ldsh);
 340 OP_LD_TABLE(stb);
 341 OP_LD_TABLE(sth);
 342 OP_LD_TABLE(std);
 343 OP_LD_TABLE(ldstub);
 344 OP_LD_TABLE(swap);
 345 OP_LD_TABLE(ldd);
 346 OP_LD_TABLE(stf);
 347 OP_LD_TABLE(stdf);
 348 OP_LD_TABLE(ldf);
 349 OP_LD_TABLE(lddf);
 350
 351 static inline void gen_movl_imm_TN(int reg, int imm)
 352 {
 353     gen_op_movl_TN_im[reg] (imm);
 354 }
 355
 356 static inline void gen_movl_imm_T1(int val)
 357 {
 358     gen_movl_imm_TN(1, val);
 359 }
 360
 361 static inline void gen_movl_imm_T0(int val)
 362 {
 363     gen_movl_imm_TN(0, val);
 364 }
 365
 366 static inline void gen_movl_reg_TN(int reg, int t)
 367 {
 368     if (reg)
 369         gen_op_movl_reg_TN[t][reg] ();
 370     else
 371         gen_movl_imm_TN(t, 0);
 372 }
 373
 374 static inline void gen_movl_reg_T0(int reg)
 375 {
 376     gen_movl_reg_TN(reg, 0);
 377 }
 378
 379 static inline void gen_movl_reg_T1(int reg)
 380 {
 381     gen_movl_reg_TN(reg, 1);
 382 }
 383
 384 static inline void gen_movl_reg_T2(int reg)
 385 {
 386     gen_movl_reg_TN(reg, 2);
 387 }
 388
 389 static inline void gen_movl_TN_reg(int reg, int t)
 390 {
 391     if (reg)
 392         gen_op_movl_TN_reg[t][reg] ();
 393 }
 394
 395 static inline void gen_movl_T0_reg(int reg)
 396 {
 397     gen_movl_TN_reg(reg, 0);
 398 }
 399
 400 static inline void gen_movl_T1_reg(int reg)
 401 {
 402     gen_movl_TN_reg(reg, 1);
 403 }
 404
 405 /* call this function before using T2 as it may have been set for a jump */
 406 static inline void flush_T2(DisasContext * dc)
 407 {
 408     if (dc->npc == JUMP_PC) {
 409         gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
 410         dc->npc = DYNAMIC_PC;
 411     }
 412 }
 413
 414 static inline void save_npc(DisasContext * dc)
 415 {
 416     if (dc->npc == JUMP_PC) {
 417         gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
 418         dc->npc = DYNAMIC_PC;
 419     } else if (dc->npc != DYNAMIC_PC) {
 420         gen_op_movl_npc_im(dc->npc);
 421     }
 422 }
 423
 424 static inline void save_state(DisasContext * dc)
 425 {
 426     gen_op_jmp_im(dc->pc);
 427     save_npc(dc);
 428 }
 429
 430 static void gen_cond(int cond)
 431 {
 432         switch (cond) {
 433         case 0x1:
 434             gen_op_eval_be();
 435             break;
 436         case 0x2:
 437             gen_op_eval_ble();
 438             break;
 439         case 0x3:
 440             gen_op_eval_bl();
 441             break;
 442         case 0x4:
 443             gen_op_eval_bleu();
 444             break;
 445         case 0x5:
 446             gen_op_eval_bcs();
 447             break;
 448         case 0x6:
 449             gen_op_eval_bneg();
 450             break;
 451         case 0x7:
 452             gen_op_eval_bvs();
 453             break;
 454         case 0x9:
 455             gen_op_eval_bne();
 456             break;
 457         case 0xa:
 458             gen_op_eval_bg();
 459             break;
 460         case 0xb:
 461             gen_op_eval_bge();
 462             break;
 463         case 0xc:
 464             gen_op_eval_bgu();
 465             break;
 466         case 0xd:
 467             gen_op_eval_bcc();
 468             break;
 469         case 0xe:
 470             gen_op_eval_bpos();
 471             break;
 472         default:
 473         case 0xf:
 474             gen_op_eval_bvc();
 475             break;
 476         }
 477 }
 478
 479 static void gen_fcond(int cond)
 480 {
 481         switch (cond) {
 482         case 0x1:
 483             gen_op_eval_fbne();
 484             break;
 485         case 0x2:
 486             gen_op_eval_fblg();
 487             break;
 488         case 0x3:
 489             gen_op_eval_fbul();
 490             break;
 491         case 0x4:
 492             gen_op_eval_fbl();
 493             break;
 494         case 0x5:
 495             gen_op_eval_fbug();
 496             break;
 497         case 0x6:
 498             gen_op_eval_fbg();
 499             break;
 500         case 0x7:
 501             gen_op_eval_fbu();
 502             break;
 503         case 0x9:
 504             gen_op_eval_fbe();
 505             break;
 506         case 0xa:
 507             gen_op_eval_fbue();
 508             break;
 509         case 0xb:
 510             gen_op_eval_fbge();
 511             break;
 512         case 0xc:
 513             gen_op_eval_fbuge();
 514             break;
 515         case 0xd:
 516             gen_op_eval_fble();
 517             break;
 518         case 0xe:
 519             gen_op_eval_fbule();
 520             break;
 521         default:
 522         case 0xf:
 523             gen_op_eval_fbo();
 524             break;
 525         }
 526 }
 527
 528 static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn)
 529 {
 530     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
 531     target_ulong target = dc->pc + offset;
 532
 533     if (cond == 0x0) {
 534         /* unconditional not taken */
 535         if (a) {
 536             dc->pc = dc->npc + 4;
 537             dc->npc = dc->pc + 4;
 538         } else {
 539             dc->pc = dc->npc;
 540             dc->npc = dc->pc + 4;
 541         }
 542     } else if (cond == 0x8) {
 543         /* unconditional taken */
 544         if (a) {
 545             dc->pc = target;
 546             dc->npc = dc->pc + 4;
 547         } else {
 548             dc->pc = dc->npc;
 549             dc->npc = target;
 550         }
 551     } else {
 552         flush_T2(dc);
 553         gen_cond(cond);
 554         if (a) {
 555             gen_op_branch_a((long)dc->tb, target, dc->npc);
 556             dc->is_br = 1;
 557         } else {
 558             dc->pc = dc->npc;
 559             dc->jump_pc[0] = target;
 560             dc->jump_pc[1] = dc->npc + 4;
 561             dc->npc = JUMP_PC;
 562         }
 563     }
 564 }
 565
 566 static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn)
 567 {
 568     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
 569     target_ulong target = dc->pc + offset;
 570
 571     if (cond == 0x0) {
 572         /* unconditional not taken */
 573         if (a) {
 574             dc->pc = dc->npc + 4;
 575             dc->npc = dc->pc + 4;
 576         } else {
 577             dc->pc = dc->npc;
 578             dc->npc = dc->pc + 4;
 579         }
 580     } else if (cond == 0x8) {
 581         /* unconditional taken */
 582         if (a) {
 583             dc->pc = target;
 584             dc->npc = dc->pc + 4;
 585         } else {
 586             dc->pc = dc->npc;
 587             dc->npc = target;
 588         }
 589     } else {
 590         flush_T2(dc);
 591         gen_fcond(cond);
 592         if (a) {
 593             gen_op_branch_a((long)dc->tb, target, dc->npc);
 594             dc->is_br = 1;
 595         } else {
 596             dc->pc = dc->npc;
 597             dc->jump_pc[0] = target;
 598             dc->jump_pc[1] = dc->npc + 4;
 599             dc->npc = JUMP_PC;
 600         }
 601     }
 602 }
 603
 604 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
 605
 606 static int sign_extend(int x, int len)
 607 {
 608     len = 32 - len;
 609     return (x << len) >> len;
 610 }
 611
 612 static void disas_sparc_insn(DisasContext * dc)
 613 {
 614     unsigned int insn, opc, rs1, rs2, rd;
 615
 616     insn = ldl_code(dc->pc);
 617     opc = GET_FIELD(insn, 0, 1);
 618
 619     rd = GET_FIELD(insn, 2, 6);
 620     switch (opc) {
 621     case 0:                     /* branches/sethi */
 622         {
 623             unsigned int xop = GET_FIELD(insn, 7, 9);
 624             int32_t target;
 625             target = GET_FIELD(insn, 10, 31);
 626             switch (xop) {
 627             case 0x0:           /* UNIMPL */
 628             case 0x1:           /* V9 BPcc */
 629             case 0x3:           /* V9 BPr */
 630             case 0x5:           /* V9 FBPcc */
 631             default:
 632                 goto illegal_insn;
 633             case 0x2:           /* BN+x */
 634                 {
 635                     target <<= 2;
 636                     target = sign_extend(target, 22);
 637                     do_branch(dc, target, insn);
 638                     goto jmp_insn;
 639                 }
 640             case 0x6:           /* FBN+x */
 641                 {
 642 #if !defined(CONFIG_USER_ONLY)
 643                     gen_op_trap_ifnofpu();
 644 #endif
 645                     target <<= 2;
 646                     target = sign_extend(target, 22);
 647                     do_fbranch(dc, target, insn);
 648                     goto jmp_insn;
 649                 }
 650             case 0x4:           /* SETHI */
 651 #define OPTIM
 652 #if defined(OPTIM)
 653                 if (rd) { // nop
 654 #endif
 655                     gen_movl_imm_T0(target << 10);
 656                     gen_movl_T0_reg(rd);
 657 #if defined(OPTIM)
 658                 }
 659 #endif
 660                 break;
 661             }
 662             break;
 663         }
 664         break;
 665     case 1:
 666         /*CALL*/ {
 667             target_long target = GET_FIELDs(insn, 2, 31) << 2;
 668
 669             gen_op_movl_T0_im(dc->pc);
 670             gen_movl_T0_reg(15);
 671             target += dc->pc;
 672             dc->pc = dc->npc;
 673             dc->npc = target;
 674         }
 675         goto jmp_insn;
 676     case 2:                     /* FPU & Logical Operations */
 677         {
 678             unsigned int xop = GET_FIELD(insn, 7, 12);
 679             if (xop == 0x3a) {  /* generate trap */
 680                 int cond;
 681                 rs1 = GET_FIELD(insn, 13, 17);
 682                 gen_movl_reg_T0(rs1);
 683                 if (IS_IMM) {
 684                     rs2 = GET_FIELD(insn, 25, 31);
 685 #if defined(OPTIM)
 686                     if (rs2 != 0) {
 687 #endif
 688                         gen_movl_imm_T1(rs2);
 689                         gen_op_add_T1_T0();
 690 #if defined(OPTIM)
 691                     }
 692 #endif
 693                 } else {
 694                     rs2 = GET_FIELD(insn, 27, 31);
 695 #if defined(OPTIM)
 696                     if (rs2 != 0) {
 697 #endif
 698                         gen_movl_reg_T1(rs2);
 699                         gen_op_add_T1_T0();
 700 #if defined(OPTIM)
 701                     }
 702 #endif
 703                 }
 704                 save_state(dc);
 705                 /* V9 icc/xcc */
 706                 cond = GET_FIELD(insn, 3, 6);
 707                 if (cond == 0x8) {
 708                     gen_op_trap_T0();
 709                     dc->is_br = 1;
 710                     goto jmp_insn;
 711                 } else if (cond != 0) {
 712                     gen_cond(cond);
 713                     gen_op_trapcc_T0();
 714                 }
 715             } else if (xop == 0x28) {
 716                 rs1 = GET_FIELD(insn, 13, 17);
 717                 switch(rs1) {
 718                 case 0: /* rdy */
 719                     gen_op_rdy();
 720                     gen_movl_T0_reg(rd);
 721                     break;
 722                 case 15: /* stbar / V9 membar */
 723                     break; /* no effect? */
 724                 default:
 725                 case 0x2: /* V9 rdccr */
 726                 case 0x3: /* V9 rdasi */
 727                 case 0x4: /* V9 rdtick */
 728                 case 0x5: /* V9 rdpc */
 729                 case 0x6: /* V9 rdfprs */
 730                     goto illegal_insn;
 731                 }
 732 #if !defined(CONFIG_USER_ONLY)
 733             } else if (xop == 0x29) {
 734                 if (!supervisor(dc))
 735                     goto priv_insn;
 736                 gen_op_rdpsr();
 737                 gen_movl_T0_reg(rd);
 738                 break;
 739             } else if (xop == 0x2a) {
 740                 if (!supervisor(dc))
 741                     goto priv_insn;
 742                 gen_op_rdwim();
 743                 gen_movl_T0_reg(rd);
 744                 break;
 745             } else if (xop == 0x2b) {
 746                 if (!supervisor(dc))
 747                     goto priv_insn;
 748                 gen_op_rdtbr();
 749                 gen_movl_T0_reg(rd);
 750                 break;
 751 #endif
 752             } else if (xop == 0x34) {   /* FPU Operations */
 753 #if !defined(CONFIG_USER_ONLY)
 754                 gen_op_trap_ifnofpu();
 755 #endif
 756                 rs1 = GET_FIELD(insn, 13, 17);
 757                 rs2 = GET_FIELD(insn, 27, 31);
 758                 xop = GET_FIELD(insn, 18, 26);
 759                 switch (xop) {
 760                     case 0x1: /* fmovs */
 761                         gen_op_load_fpr_FT0(rs2);
 762                         gen_op_store_FT0_fpr(rd);
 763                         break;
 764                     case 0x5: /* fnegs */
 765                         gen_op_load_fpr_FT1(rs2);
 766                         gen_op_fnegs();
 767                         gen_op_store_FT0_fpr(rd);
 768                         break;
 769                     case 0x9: /* fabss */
 770                         gen_op_load_fpr_FT1(rs2);
 771                         gen_op_fabss();
 772                         gen_op_store_FT0_fpr(rd);
 773                         break;
 774                     case 0x29: /* fsqrts */
 775                         gen_op_load_fpr_FT1(rs2);
 776                         gen_op_fsqrts();
 777                         gen_op_store_FT0_fpr(rd);
 778                         break;
 779                     case 0x2a: /* fsqrtd */
 780                         gen_op_load_fpr_DT1(rs2);
 781                         gen_op_fsqrtd();
 782                         gen_op_store_DT0_fpr(rd);
 783                         break;
 784                     case 0x2b: /* fsqrtq */
 785                         goto nfpu_insn;
 786                     case 0x41:
 787                         gen_op_load_fpr_FT0(rs1);
 788                         gen_op_load_fpr_FT1(rs2);
 789                         gen_op_fadds();
 790                         gen_op_store_FT0_fpr(rd);
 791                         break;
 792                     case 0x42:
 793                         gen_op_load_fpr_DT0(rs1);
 794                         gen_op_load_fpr_DT1(rs2);
 795                         gen_op_faddd();
 796                         gen_op_store_DT0_fpr(rd);
 797                         break;
 798                     case 0x43: /* faddq */
 799                         goto nfpu_insn;
 800                     case 0x45:
 801                         gen_op_load_fpr_FT0(rs1);
 802                         gen_op_load_fpr_FT1(rs2);
 803                         gen_op_fsubs();
 804                         gen_op_store_FT0_fpr(rd);
 805                         break;
 806                     case 0x46:
 807                         gen_op_load_fpr_DT0(rs1);
 808                         gen_op_load_fpr_DT1(rs2);
 809                         gen_op_fsubd();
 810                         gen_op_store_DT0_fpr(rd);
 811                         break;
 812                     case 0x47: /* fsubq */
 813                         goto nfpu_insn;
 814                     case 0x49:
 815                         gen_op_load_fpr_FT0(rs1);
 816                         gen_op_load_fpr_FT1(rs2);
 817                         gen_op_fmuls();
 818                         gen_op_store_FT0_fpr(rd);
 819                         break;
 820                     case 0x4a:
 821                         gen_op_load_fpr_DT0(rs1);
 822                         gen_op_load_fpr_DT1(rs2);
 823                         gen_op_fmuld();
 824                         gen_op_store_DT0_fpr(rd);
 825                         break;
 826                     case 0x4b: /* fmulq */
 827                         goto nfpu_insn;
 828                     case 0x4d:
 829                         gen_op_load_fpr_FT0(rs1);
 830                         gen_op_load_fpr_FT1(rs2);
 831                         gen_op_fdivs();
 832                         gen_op_store_FT0_fpr(rd);
 833                         break;
 834                     case 0x4e:
 835                         gen_op_load_fpr_DT0(rs1);
 836                         gen_op_load_fpr_DT1(rs2);
 837                         gen_op_fdivd();
 838                         gen_op_store_DT0_fpr(rd);
 839                         break;
 840                     case 0x4f: /* fdivq */
 841                         goto nfpu_insn;
 842                     case 0x69:
 843                         gen_op_load_fpr_FT0(rs1);
 844                         gen_op_load_fpr_FT1(rs2);
 845                         gen_op_fsmuld();
 846                         gen_op_store_DT0_fpr(rd);
 847                         break;
 848                     case 0x6e: /* fdmulq */
 849                         goto nfpu_insn;
 850                     case 0xc4:
 851                         gen_op_load_fpr_FT1(rs2);
 852                         gen_op_fitos();
 853                         gen_op_store_FT0_fpr(rd);
 854                         break;
 855                     case 0xc6:
 856                         gen_op_load_fpr_DT1(rs2);
 857                         gen_op_fdtos();
 858                         gen_op_store_FT0_fpr(rd);
 859                         break;
 860                     case 0xc7: /* fqtos */
 861                         goto nfpu_insn;
 862                     case 0xc8:
 863                         gen_op_load_fpr_FT1(rs2);
 864                         gen_op_fitod();
 865                         gen_op_store_DT0_fpr(rd);
 866                         break;
 867                     case 0xc9:
 868                         gen_op_load_fpr_FT1(rs2);
 869                         gen_op_fstod();
 870                         gen_op_store_DT0_fpr(rd);
 871                         break;
 872                     case 0xcb: /* fqtod */
 873                         goto nfpu_insn;
 874                     case 0xcc: /* fitoq */
 875                         goto nfpu_insn;
 876                     case 0xcd: /* fstoq */
 877                         goto nfpu_insn;
 878                     case 0xce: /* fdtoq */
 879                         goto nfpu_insn;
 880                     case 0xd1:
 881                         gen_op_load_fpr_FT1(rs2);
 882                         gen_op_fstoi();
 883                         gen_op_store_FT0_fpr(rd);
 884                         break;
 885                     case 0xd2:
 886                         gen_op_load_fpr_DT1(rs2);
 887                         gen_op_fdtoi();
 888                         gen_op_store_FT0_fpr(rd);
 889                         break;
 890                     case 0xd3: /* fqtoi */
 891                         goto nfpu_insn;
 892                     default:
 893                     case 0x2: /* V9 fmovd */
 894                     case 0x6: /* V9 fnegd */
 895                     case 0xa: /* V9 fabsd */
 896                     case 0x81: /* V9 fstox */
 897                     case 0x82: /* V9 fdtox */
 898                     case 0x84: /* V9 fxtos */
 899                     case 0x88: /* V9 fxtod */
 900
 901                     case 0x3: /* V9 fmovq */
 902                     case 0x7: /* V9 fnegq */
 903                     case 0xb: /* V9 fabsq */
 904                     case 0x83: /* V9 fqtox */
 905                     case 0x8c: /* V9 fxtoq */
 906                         goto illegal_insn;
 907                 }
 908             } else if (xop == 0x35) {   /* FPU Operations */
 909 #if !defined(CONFIG_USER_ONLY)
 910                 gen_op_trap_ifnofpu();
 911 #endif
 912                 rs1 = GET_FIELD(insn, 13, 17);
 913                 rs2 = GET_FIELD(insn, 27, 31);
 914                 xop = GET_FIELD(insn, 18, 26);
 915                 /* V9 fmovscc: x5, cond = x >> 1 */
 916                 /* V9 fmovdcc: x6, cond = x >> 1 */
 917
 918                 /* V9 fmovqcc: x7, cond = x >> 1 */
 919                 switch (xop) {
 920                     case 0x51:
 921                         gen_op_load_fpr_FT0(rs1);
 922                         gen_op_load_fpr_FT1(rs2);
 923                         gen_op_fcmps();
 924                         break;
 925                     case 0x52:
 926                         gen_op_load_fpr_DT0(rs1);
 927                         gen_op_load_fpr_DT1(rs2);
 928                         gen_op_fcmpd();
 929                         break;
 930                     case 0x53: /* fcmpq */
 931                         goto nfpu_insn;
 932                     case 0x55: /* fcmpes */
 933                         gen_op_load_fpr_FT0(rs1);
 934                         gen_op_load_fpr_FT1(rs2);
 935                         gen_op_fcmps(); /* XXX should trap if qNaN or sNaN  */
 936                         break;
 937                     case 0x56: /* fcmped */
 938                         gen_op_load_fpr_DT0(rs1);
 939                         gen_op_load_fpr_DT1(rs2);
 940                         gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN  */
 941                         break;
 942                     case 0x57: /* fcmpeq */
 943                         goto nfpu_insn;
 944                     default:
 945                         goto illegal_insn;
 946                 }
 947 #if defined(OPTIM)
 948             } else if (xop == 0x2) {
 949                 // clr/mov shortcut
 950
 951                 rs1 = GET_FIELD(insn, 13, 17);
 952                 if (rs1 == 0) {
 953                     // or %g0, x, y -> mov T1, x; mov y, T1
 954                     if (IS_IMM) {       /* immediate */
 955                         rs2 = GET_FIELDs(insn, 19, 31);
 956                         gen_movl_imm_T1(rs2);
 957                     } else {            /* register */
 958                         rs2 = GET_FIELD(insn, 27, 31);
 959                         gen_movl_reg_T1(rs2);
 960                     }
 961                     gen_movl_T1_reg(rd);
 962                 } else {
 963                     gen_movl_reg_T0(rs1);
 964                     if (IS_IMM) {       /* immediate */
 965                         // or x, #0, y -> mov T1, x; mov y, T1
 966                         rs2 = GET_FIELDs(insn, 19, 31);
 967                         if (rs2 != 0) {
 968                             gen_movl_imm_T1(rs2);
 969                             gen_op_or_T1_T0();
 970                         }
 971                     } else {            /* register */
 972                         // or x, %g0, y -> mov T1, x; mov y, T1
 973                         rs2 = GET_FIELD(insn, 27, 31);
 974                         if (rs2 != 0) {
 975                             gen_movl_reg_T1(rs2);
 976                             gen_op_or_T1_T0();
 977                         }
 978                     }
 979                     gen_movl_T0_reg(rd);
 980                 }
 981 #endif
 982             } else if (xop < 0x38) {
 983                 rs1 = GET_FIELD(insn, 13, 17);
 984                 gen_movl_reg_T0(rs1);
 985                 if (IS_IMM) {   /* immediate */
 986                     rs2 = GET_FIELDs(insn, 19, 31);
 987                     gen_movl_imm_T1(rs2);
 988                 } else {                /* register */
 989                     rs2 = GET_FIELD(insn, 27, 31);
 990                     gen_movl_reg_T1(rs2);
 991                 }
 992                 if (xop < 0x20) {
 993                     switch (xop & ~0x10) {
 994                     case 0x0:
 995                         if (xop & 0x10)
 996                             gen_op_add_T1_T0_cc();
 997                         else
 998                             gen_op_add_T1_T0();
 999                         break;
1000                     case 0x1:
1001                         gen_op_and_T1_T0();
1002                         if (xop & 0x10)
1003                             gen_op_logic_T0_cc();
1004                         break;
1005                     case 0x2:
1006                         gen_op_or_T1_T0();
1007                         if (xop & 0x10)
1008                             gen_op_logic_T0_cc();
1009                         break;
1010                     case 0x3:
1011                         gen_op_xor_T1_T0();
1012                         if (xop & 0x10)
1013                             gen_op_logic_T0_cc();
1014                         break;
1015                     case 0x4:
1016                         if (xop & 0x10)
1017                             gen_op_sub_T1_T0_cc();
1018                         else
1019                             gen_op_sub_T1_T0();
1020                         break;
1021                     case 0x5:
1022                         gen_op_andn_T1_T0();
1023                         if (xop & 0x10)
1024                             gen_op_logic_T0_cc();
1025                         break;
1026                     case 0x6:
1027                         gen_op_orn_T1_T0();
1028                         if (xop & 0x10)
1029                             gen_op_logic_T0_cc();
1030                         break;
1031                     case 0x7:
1032                         gen_op_xnor_T1_T0();
1033                         if (xop & 0x10)
1034                             gen_op_logic_T0_cc();
1035                         break;
1036                     case 0x8:
1037                         if (xop & 0x10)
1038                             gen_op_addx_T1_T0_cc();
1039                         else
1040                             gen_op_addx_T1_T0();
1041                         break;
1042                     case 0xa:
1043                         gen_op_umul_T1_T0();
1044                         if (xop & 0x10)
1045                             gen_op_logic_T0_cc();
1046                         break;
1047                     case 0xb:
1048                         gen_op_smul_T1_T0();
1049                         if (xop & 0x10)
1050                             gen_op_logic_T0_cc();
1051                         break;
1052                     case 0xc:
1053                         if (xop & 0x10)
1054                             gen_op_subx_T1_T0_cc();
1055                         else
1056                             gen_op_subx_T1_T0();
1057                         break;
1058                     case 0xe:
1059                         gen_op_udiv_T1_T0();
1060                         if (xop & 0x10)
1061                             gen_op_div_cc();
1062                         break;
1063                     case 0xf:
1064                         gen_op_sdiv_T1_T0();
1065                         if (xop & 0x10)
1066                             gen_op_div_cc();
1067                         break;
1068                     default:
1069                     case 0x9: /* V9 mulx */
1070                     case 0xd: /* V9 udivx */
1071                         goto illegal_insn;
1072                     }
1073                     gen_movl_T0_reg(rd);
1074                 } else {
1075                     switch (xop) {
1076                     case 0x20: /* taddcc */
1077                     case 0x21: /* tsubcc */
1078                     case 0x22: /* taddcctv */
1079                     case 0x23: /* tsubcctv */
1080                         goto illegal_insn;
1081                     case 0x24: /* mulscc */
1082                         gen_op_mulscc_T1_T0();
1083                         gen_movl_T0_reg(rd);
1084                         break;
1085                     case 0x25:  /* sll, V9 sllx */
1086                         gen_op_sll();
1087                         gen_movl_T0_reg(rd);
1088                         break;
1089                     case 0x26:  /* srl, V9 srlx */
1090                         gen_op_srl();
1091                         gen_movl_T0_reg(rd);
1092                         break;
1093                     case 0x27:  /* sra, V9 srax */
1094                         gen_op_sra();
1095                         gen_movl_T0_reg(rd);
1096                         break;
1097                     case 0x30:
1098                         {
1099                             gen_op_xor_T1_T0();
1100                             switch(rd) {
1101                             case 0:
1102                                 gen_op_wry();
1103                                 break;
1104                             default:
1105                             case 0x2: /* V9 wrccr */
1106                             case 0x3: /* V9 wrasi */
1107                             case 0x6: /* V9 wrfprs */
1108                             case 0xf: /* V9 sir */
1109                                 goto illegal_insn;
1110                             }
1111                         }
1112                         break;
1113 #if !defined(CONFIG_USER_ONLY)
1114                     case 0x31: /* wrpsr, V9 saved, restored */
1115                         {
1116                             if (!supervisor(dc))
1117                                 goto priv_insn;
1118                             gen_op_xor_T1_T0();
1119                             gen_op_wrpsr();
1120                         }
1121                         break;
1122                     case 0x32: /* wrwim, V9 wrpr */
1123                         {
1124                             if (!supervisor(dc))
1125                                 goto priv_insn;
1126                             gen_op_xor_T1_T0();
1127                             gen_op_wrwim();
1128                         }
1129                         break;
1130                     case 0x33:
1131                         {
1132                             if (!supervisor(dc))
1133                                 goto priv_insn;
1134                             gen_op_xor_T1_T0();
1135                             gen_op_wrtbr();
1136                         }
1137                         break;
1138 #endif
1139                     default:
1140                     case 0x2a: /* V9 rdpr */
1141                     case 0x2b: /* V9 flushw */
1142                     case 0x2c: /* V9 movcc */
1143                     case 0x2d: /* V9 sdivx */
1144                     case 0x2e: /* V9 popc */
1145                     case 0x2f: /* V9 movr */
1146                         goto illegal_insn;
1147                     }
1148                 }
1149             } else {
1150                 rs1 = GET_FIELD(insn, 13, 17);
1151                 gen_movl_reg_T0(rs1);
1152                 if (IS_IMM) {   /* immediate */
1153                     rs2 = GET_FIELDs(insn, 19, 31);
1154 #if defined(OPTIM)
1155                     if (rs2) {
1156 #endif
1157                         gen_movl_imm_T1(rs2);
1158                         gen_op_add_T1_T0();
1159 #if defined(OPTIM)
1160                     }
1161 #endif
1162                 } else {                /* register */
1163                     rs2 = GET_FIELD(insn, 27, 31);
1164 #if defined(OPTIM)
1165                     if (rs2) {
1166 #endif
1167                         gen_movl_reg_T1(rs2);
1168                         gen_op_add_T1_T0();
1169 #if defined(OPTIM)
1170                     }
1171 #endif
1172                 }
1173                 switch (xop) {
1174                 case 0x38:      /* jmpl */
1175                     {
1176                         gen_op_movl_npc_T0();
1177                         if (rd != 0) {
1178                             gen_op_movl_T0_im(dc->pc);
1179                             gen_movl_T0_reg(rd);
1180                         }
1181                         dc->pc = dc->npc;
1182                         dc->npc = DYNAMIC_PC;
1183                     }
1184                     goto jmp_insn;
1185 #if !defined(CONFIG_USER_ONLY)
1186                 case 0x39:      /* rett, V9 return */
1187                     {
1188                         if (!supervisor(dc))
1189                             goto priv_insn;
1190                         gen_op_movl_npc_T0();
1191                         gen_op_rett();
1192                     }
1193                     break;
1194 #endif
1195                 case 0x3b: /* flush */
1196                     gen_op_flush_T0();
1197                     break;
1198                 case 0x3c:      /* save */
1199                     save_state(dc);
1200                     gen_op_save();
1201                     gen_movl_T0_reg(rd);
1202                     break;
1203                 case 0x3d:      /* restore */
1204                     save_state(dc);
1205                     gen_op_restore();
1206                     gen_movl_T0_reg(rd);
1207                     break;
1208                 default:
1209                 case 0x3e:      /* V9 done/retry */
1210                     goto illegal_insn;
1211                 }
1212             }
1213             break;
1214         }
1215         break;
1216     case 3:                     /* load/store instructions */
1217         {
1218             unsigned int xop = GET_FIELD(insn, 7, 12);
1219             rs1 = GET_FIELD(insn, 13, 17);
1220             gen_movl_reg_T0(rs1);
1221             if (IS_IMM) {       /* immediate */
1222                 rs2 = GET_FIELDs(insn, 19, 31);
1223 #if defined(OPTIM)
1224                 if (rs2 != 0) {
1225 #endif
1226                     gen_movl_imm_T1(rs2);
1227                     gen_op_add_T1_T0();
1228 #if defined(OPTIM)
1229                 }
1230 #endif
1231             } else {            /* register */
1232                 rs2 = GET_FIELD(insn, 27, 31);
1233 #if defined(OPTIM)
1234                 if (rs2 != 0) {
1235 #endif
1236                     gen_movl_reg_T1(rs2);
1237                     gen_op_add_T1_T0();
1238 #if defined(OPTIM)
1239                 }
1240 #endif
1241             }
1242             if (xop < 4 || (xop > 7 && xop < 0x14) || \
1243                     (xop > 0x17 && xop < 0x20)) {
1244                 switch (xop) {
1245                 case 0x0:       /* load word */
1246                     gen_op_ldst(ld);
1247                     break;
1248                 case 0x1:       /* load unsigned byte */
1249                     gen_op_ldst(ldub);
1250                     break;
1251                 case 0x2:       /* load unsigned halfword */
1252                     gen_op_ldst(lduh);
1253                     break;
1254                 case 0x3:       /* load double word */
1255                     gen_op_ldst(ldd);
1256                     gen_movl_T0_reg(rd + 1);
1257                     break;
1258                 case 0x9:       /* load signed byte */
1259                     gen_op_ldst(ldsb);
1260                     break;
1261                 case 0xa:       /* load signed halfword */
1262                     gen_op_ldst(ldsh);
1263                     break;
1264                 case 0xd:       /* ldstub -- XXX: should be atomically */
1265                     gen_op_ldst(ldstub);
1266                     break;
1267                 case 0x0f:      /* swap register with memory. Also atomically */
1268                     gen_movl_reg_T1(rd);
1269                     gen_op_ldst(swap);
1270                     break;
1271 #if !defined(CONFIG_USER_ONLY)
1272                 case 0x10:      /* load word alternate */
1273                     if (!supervisor(dc))
1274                         goto priv_insn;
1275                     gen_op_lda(insn, 1, 4, 0);
1276                     break;
1277                 case 0x11:      /* load unsigned byte alternate */
1278                     if (!supervisor(dc))
1279                         goto priv_insn;
1280                     gen_op_lduba(insn, 1, 1, 0);
1281                     break;
1282                 case 0x12:      /* load unsigned halfword alternate */
1283                     if (!supervisor(dc))
1284                         goto priv_insn;
1285                     gen_op_lduha(insn, 1, 2, 0);
1286                     break;
1287                 case 0x13:      /* load double word alternate */
1288                     if (!supervisor(dc))
1289                         goto priv_insn;
1290                     gen_op_ldda(insn, 1, 8, 0);
1291                     gen_movl_T0_reg(rd + 1);
1292                     break;
1293                 case 0x19:      /* load signed byte alternate */
1294                     if (!supervisor(dc))
1295                         goto priv_insn;
1296                     gen_op_ldsba(insn, 1, 1, 1);
1297                     break;
1298                 case 0x1a:      /* load signed halfword alternate */
1299                     if (!supervisor(dc))
1300                         goto priv_insn;
1301                     gen_op_ldsha(insn, 1, 2 ,1);
1302                     break;
1303                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
1304                     if (!supervisor(dc))
1305                         goto priv_insn;
1306                     gen_op_ldstuba(insn, 1, 1, 0);
1307                     break;
1308                 case 0x1f:      /* swap reg with alt. memory. Also atomically */
1309                     if (!supervisor(dc))
1310                         goto priv_insn;
1311                     gen_movl_reg_T1(rd);
1312                     gen_op_swapa(insn, 1, 4, 0);
1313                     break;
1314
1315                     /* avoid warnings */
1316                     (void) &gen_op_stfa;
1317                     (void) &gen_op_stdfa;
1318                     (void) &gen_op_ldfa;
1319                     (void) &gen_op_lddfa;
1320 #endif
1321                 default:
1322                 case 0x08: /* V9 ldsw */
1323                 case 0x0b: /* V9 ldx */
1324                 case 0x18: /* V9 ldswa */
1325                 case 0x1b: /* V9 ldxa */
1326                 case 0x2d: /* V9 prefetch */
1327                 case 0x30: /* V9 ldfa */
1328                 case 0x33: /* V9 lddfa */
1329                 case 0x3d: /* V9 prefetcha */
1330
1331                 case 0x32: /* V9 ldqfa */
1332                     goto illegal_insn;
1333                 }
1334                 gen_movl_T1_reg(rd);
1335             } else if (xop >= 0x20 && xop < 0x24) {
1336 #if !defined(CONFIG_USER_ONLY)
1337                 gen_op_trap_ifnofpu();
1338 #endif
1339                 switch (xop) {
1340                 case 0x20:      /* load fpreg */
1341                     gen_op_ldst(ldf);
1342                     gen_op_store_FT0_fpr(rd);
1343                     break;
1344                 case 0x21:      /* load fsr */
1345                     gen_op_ldfsr();
1346                     gen_op_store_FT0_fpr(rd);
1347                     break;
1348                 case 0x22:      /* load quad fpreg */
1349                     goto nfpu_insn;
1350                 case 0x23:      /* load double fpreg */
1351                     gen_op_ldst(lddf);
1352                     gen_op_store_DT0_fpr(rd);
1353                     break;
1354                 default:
1355                     goto illegal_insn;
1356                 }
1357             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18)) {
1358                 gen_movl_reg_T1(rd);
1359                 switch (xop) {
1360                 case 0x4:
1361                     gen_op_ldst(st);
1362                     break;
1363                 case 0x5:
1364                     gen_op_ldst(stb);
1365                     break;
1366                 case 0x6:
1367                     gen_op_ldst(sth);
1368                     break;
1369                 case 0x7:
1370                     flush_T2(dc);
1371                     gen_movl_reg_T2(rd + 1);
1372                     gen_op_ldst(std);
1373                     break;
1374 #if !defined(CONFIG_USER_ONLY)
1375                 case 0x14:
1376                     if (!supervisor(dc))
1377                         goto priv_insn;
1378                     gen_op_sta(insn, 0, 4, 0);
1379                     break;
1380                 case 0x15:
1381                     if (!supervisor(dc))
1382                         goto priv_insn;
1383                     gen_op_stba(insn, 0, 1, 0);
1384                     break;
1385                 case 0x16:
1386                     if (!supervisor(dc))
1387                         goto priv_insn;
1388                     gen_op_stha(insn, 0, 2, 0);
1389                     break;
1390                 case 0x17:
1391                     if (!supervisor(dc))
1392                         goto priv_insn;
1393                     flush_T2(dc);
1394                     gen_movl_reg_T2(rd + 1);
1395                     gen_op_stda(insn, 0, 8, 0);
1396                     break;
1397 #endif
1398                 default:
1399                 case 0x0e: /* V9 stx */
1400                 case 0x1e: /* V9 stxa */
1401                     goto illegal_insn;
1402                 }
1403             } else if (xop > 0x23 && xop < 0x28) {
1404 #if !defined(CONFIG_USER_ONLY)
1405                 gen_op_trap_ifnofpu();
1406 #endif
1407                 switch (xop) {
1408                 case 0x24:
1409                     gen_op_load_fpr_FT0(rd);
1410                     gen_op_ldst(stf);
1411                     break;
1412                 case 0x25: /* stfsr, V9 stxfsr */
1413                     gen_op_load_fpr_FT0(rd);
1414                     gen_op_stfsr();
1415                     break;
1416                 case 0x26: /* stdfq */
1417                     goto nfpu_insn;
1418                 case 0x27:
1419                     gen_op_load_fpr_DT0(rd);
1420                     gen_op_ldst(stdf);
1421                     break;
1422                 default:
1423                 case 0x34: /* V9 stfa */
1424                 case 0x37: /* V9 stdfa */
1425                 case 0x3c: /* V9 casa */
1426                 case 0x3e: /* V9 casxa */
1427
1428                 case 0x36: /* V9 stqfa */
1429                     goto illegal_insn;
1430                 }
1431             } else if (xop > 0x33 && xop < 0x38) {
1432                 /* Co-processor */
1433                 goto illegal_insn;
1434             }
1435             else
1436                 goto illegal_insn;
1437         }
1438         break;
1439     }
1440     /* default case for non jump instructions */
1441     if (dc->npc == DYNAMIC_PC) {
1442         dc->pc = DYNAMIC_PC;
1443         gen_op_next_insn();
1444     } else if (dc->npc == JUMP_PC) {
1445         /* we can do a static jump */
1446         gen_op_branch2((long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
1447         dc->is_br = 1;
1448     } else {
1449         dc->pc = dc->npc;
1450         dc->npc = dc->npc + 4;
1451     }
1452  jmp_insn:
1453     return;
1454  illegal_insn:
1455     save_state(dc);
1456     gen_op_exception(TT_ILL_INSN);
1457     dc->is_br = 1;
1458     return;
1459 #if !defined(CONFIG_USER_ONLY)
1460  priv_insn:
1461     save_state(dc);
1462     gen_op_exception(TT_PRIV_INSN);
1463     dc->is_br = 1;
1464     return;
1465 #endif
1466  nfpu_insn:
1467     save_state(dc);
1468     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
1469     dc->is_br = 1;
1470 }
1471
1472 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
1473                                                  int spc, CPUSPARCState *env)
1474 {
1475     target_ulong pc_start, last_pc;
1476     uint16_t *gen_opc_end;
1477     DisasContext dc1, *dc = &dc1;
1478     int j, lj = -1;
1479
1480     memset(dc, 0, sizeof(DisasContext));
1481     dc->tb = tb;
1482     pc_start = tb->pc;
1483     dc->pc = pc_start;
1484     last_pc = dc->pc;
1485     dc->npc = (target_ulong) tb->cs_base;
1486 #if defined(CONFIG_USER_ONLY)
1487     dc->mem_idx = 0;
1488 #else
1489     dc->mem_idx = ((env->psrs) != 0);
1490 #endif
1491     gen_opc_ptr = gen_opc_buf;
1492     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1493     gen_opparam_ptr = gen_opparam_buf;
1494
1495     do {
1496         if (env->nb_breakpoints > 0) {
1497             for(j = 0; j < env->nb_breakpoints; j++) {
1498                 if (env->breakpoints[j] == dc->pc) {
1499                     if (dc->pc != pc_start)
1500                         save_state(dc);
1501                     gen_op_debug();
1502                     gen_op_movl_T0_0();
1503                     gen_op_exit_tb();
1504                     dc->is_br = 1;
1505                     goto exit_gen_loop;
1506                 }
1507             }
1508         }
1509         if (spc) {
1510             if (loglevel > 0)
1511                 fprintf(logfile, "Search PC...\n");
1512             j = gen_opc_ptr - gen_opc_buf;
1513             if (lj < j) {
1514                 lj++;
1515                 while (lj < j)
1516                     gen_opc_instr_start[lj++] = 0;
1517                 gen_opc_pc[lj] = dc->pc;
1518                 gen_opc_npc[lj] = dc->npc;
1519                 gen_opc_instr_start[lj] = 1;
1520             }
1521         }
1522         last_pc = dc->pc;
1523         disas_sparc_insn(dc);
1524         if (dc->is_br)
1525             break;
1526         /* if the next PC is different, we abort now */
1527         if (dc->pc != (last_pc + 4))
1528             break;
1529         /* if single step mode, we generate only one instruction and
1530            generate an exception */
1531         if (env->singlestep_enabled) {
1532             gen_op_jmp_im(dc->pc);
1533             gen_op_movl_T0_0();
1534             gen_op_exit_tb();
1535             break;
1536         }
1537     } while ((gen_opc_ptr < gen_opc_end) &&
1538              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
1539
1540  exit_gen_loop:
1541     if (!dc->is_br) {
1542         if (dc->pc != DYNAMIC_PC &&
1543             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
1544             /* static PC and NPC: we can use direct chaining */
1545             gen_op_branch((long)tb, dc->pc, dc->npc);
1546         } else {
1547             if (dc->pc != DYNAMIC_PC)
1548                 gen_op_jmp_im(dc->pc);
1549             save_npc(dc);
1550             gen_op_movl_T0_0();
1551             gen_op_exit_tb();
1552         }
1553     }
1554     *gen_opc_ptr = INDEX_op_end;
1555     if (spc) {
1556         j = gen_opc_ptr - gen_opc_buf;
1557         lj++;
1558         while (lj <= j)
1559             gen_opc_instr_start[lj++] = 0;
1560         tb->size = 0;
1561 #if 0
1562         if (loglevel > 0) {
1563             page_dump(logfile);
1564         }
1565 #endif
1566     } else {
1567         tb->size = last_pc + 4 - pc_start;
1568     }
1569 #ifdef DEBUG_DISAS
1570     if (loglevel & CPU_LOG_TB_IN_ASM) {
1571         fprintf(logfile, "--------------\n");
1572         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
1573         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
1574         fprintf(logfile, "\n");
1575         if (loglevel & CPU_LOG_TB_OP) {
1576             fprintf(logfile, "OP:\n");
1577             dump_ops(gen_opc_buf, gen_opparam_buf);
1578             fprintf(logfile, "\n");
1579         }
1580     }
1581 #endif
1582     return 0;
1583 }
1584
1585 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
1586 {
1587     return gen_intermediate_code_internal(tb, 0, env);
1588 }
1589
1590 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
1591 {
1592     return gen_intermediate_code_internal(tb, 1, env);
1593 }
1594
1595 extern int ram_size;
1596
1597 void cpu_reset(CPUSPARCState *env)
1598 {
1599     memset(env, 0, sizeof(*env));
1600     tlb_flush(env, 1);
1601     env->cwp = 0;
1602     env->wim = 1;
1603     env->regwptr = env->regbase + (env->cwp * 16);
1604 #if defined(CONFIG_USER_ONLY)
1605     env->user_mode_only = 1;
1606 #else
1607     env->psrs = 1;
1608     env->pc = 0xffd00000;
1609     env->gregs[1] = ram_size;
1610     env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */
1611     env->npc = env->pc + 4;
1612 #endif
1613 }
1614
1615 CPUSPARCState *cpu_sparc_init(void)
1616 {
1617     CPUSPARCState *env;
1618
1619     cpu_exec_init();
1620
1621     if (!(env = malloc(sizeof(CPUSPARCState))))
1622         return (NULL);
1623     cpu_single_env = env;
1624     cpu_reset(env);
1625     return (env);
1626 }
1627
1628 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1629
1630 void cpu_dump_state(CPUState *env, FILE *f,
1631                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1632                     int flags)
1633 {
1634     int i, x;
1635
1636     cpu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
1637     cpu_fprintf(f, "General Registers:\n");
1638     for (i = 0; i < 4; i++)
1639         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1640     cpu_fprintf(f, "\n");
1641     for (; i < 8; i++)
1642         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1643     cpu_fprintf(f, "\nCurrent Register Window:\n");
1644     for (x = 0; x < 3; x++) {
1645         for (i = 0; i < 4; i++)
1646             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1647                     (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1648                     env->regwptr[i + x * 8]);
1649         cpu_fprintf(f, "\n");
1650         for (; i < 8; i++)
1651             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1652                     (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1653                     env->regwptr[i + x * 8]);
1654         cpu_fprintf(f, "\n");
1655     }
1656     cpu_fprintf(f, "\nFloating Point Registers:\n");
1657     for (i = 0; i < 32; i++) {
1658         if ((i & 3) == 0)
1659             cpu_fprintf(f, "%%f%02d:", i);
1660         cpu_fprintf(f, " %016lf", env->fpr[i]);
1661         if ((i & 3) == 3)
1662             cpu_fprintf(f, "\n");
1663     }
1664     cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
1665             GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1666             GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1667             env->psrs?'S':'-', env->psrps?'P':'-',
1668             env->psret?'E':'-', env->wim);
1669     cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr);
1670 }
1671
1672 #if defined(CONFIG_USER_ONLY)
1673 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1674 {
1675     return addr;
1676 }
1677
1678 #else
1679 extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
1680                                  int *access_index, target_ulong address, int rw,
1681                                  int is_user);
1682
1683 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1684 {
1685     target_phys_addr_t phys_addr;
1686     int prot, access_index;
1687
1688     if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
1689         return -1;
1690     return phys_addr;
1691 }
1692 #endif
1693
1694 void helper_flush(target_ulong addr)
1695 {
1696     addr &= ~7;
1697     tb_invalidate_page_range(addr, addr + 8);
1698 }