git.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23    TODO-list:
  24
  25    Rest of V9 instructions, VIS instructions
  26    NPC/PC static optimisations (use JUMP_TB when possible)
  27    Optimize synthetic instructions
  28 */
  29
  30 #include <stdarg.h>
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <string.h>
  34 #include <inttypes.h>
  35
  36 #include "cpu.h"
  37 #include "exec-all.h"
  38 #include "disas.h"
  39 #include "helper.h"
  40 #include "tcg-op.h"
  41
  42 #define DEBUG_DISAS
  43
  44 #define DYNAMIC_PC  1 /* dynamic pc value */
  45 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  46                          according to jump_pc[T2] */
  47
  48 /* global register indexes */
  49 static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
  50 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
  51 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
  52 #ifdef TARGET_SPARC64
  53 static TCGv cpu_xcc;
  54 #endif
  55 /* local register indexes (only used inside old micro ops) */
  56 static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
  57
  58 typedef struct DisasContext {
  59     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  60     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  61     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  62     int is_br;
  63     int mem_idx;
  64     int fpu_enabled;
  65     struct TranslationBlock *tb;
  66 } DisasContext;
  67
  68 extern FILE *logfile;
  69 extern int loglevel;
  70
  71 // This function uses non-native bit order
  72 #define GET_FIELD(X, FROM, TO) \
  73   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  74
  75 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  76 #define GET_FIELD_SP(X, FROM, TO) \
  77     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  78
  79 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  80 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
  81
  82 #ifdef TARGET_SPARC64
  83 #define FFPREG(r) (r)
  84 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
  85 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
  86 #else
  87 #define FFPREG(r) (r)
  88 #define DFPREG(r) (r & 0x1e)
  89 #define QFPREG(r) (r & 0x1c)
  90 #endif
  91
  92 static int sign_extend(int x, int len)
  93 {
  94     len = 32 - len;
  95     return (x << len) >> len;
  96 }
  97
  98 #define IS_IMM (insn & (1<<13))
  99
 100 /* floating point registers moves */
 101 static void gen_op_load_fpr_FT0(unsigned int src)
 102 {
 103     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 104     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
 105 }
 106
 107 static void gen_op_load_fpr_FT1(unsigned int src)
 108 {
 109     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 110     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
 111 }
 112
 113 static void gen_op_store_FT0_fpr(unsigned int dst)
 114 {
 115     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
 116     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 117 }
 118
 119 static void gen_op_load_fpr_DT0(unsigned int src)
 120 {
 121     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 122     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
 123     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 124     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
 125 }
 126
 127 static void gen_op_load_fpr_DT1(unsigned int src)
 128 {
 129     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 130     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
 131     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 132     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
 133 }
 134
 135 static void gen_op_store_DT0_fpr(unsigned int dst)
 136 {
 137     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
 138     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 139     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
 140     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 141 }
 142
 143 #ifdef CONFIG_USER_ONLY
 144 static void gen_op_load_fpr_QT0(unsigned int src)
 145 {
 146     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 147     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
 148     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 149     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
 150     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 151     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
 152     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 153     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
 154 }
 155
 156 static void gen_op_load_fpr_QT1(unsigned int src)
 157 {
 158     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 159     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
 160     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 161     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
 162     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 163     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
 164     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 165     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
 166 }
 167
 168 static void gen_op_store_QT0_fpr(unsigned int dst)
 169 {
 170     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
 171     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 172     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
 173     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 174     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
 175     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
 176     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
 177     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
 178 }
 179 #endif
 180
 181 /* moves */
 182 #ifdef CONFIG_USER_ONLY
 183 #define supervisor(dc) 0
 184 #ifdef TARGET_SPARC64
 185 #define hypervisor(dc) 0
 186 #endif
 187 #define gen_op_ldst(name)        gen_op_##name##_raw()
 188 #else
 189 #define supervisor(dc) (dc->mem_idx >= 1)
 190 #ifdef TARGET_SPARC64
 191 #define hypervisor(dc) (dc->mem_idx == 2)
 192 #define OP_LD_TABLE(width)                                              \
 193     static GenOpFunc * const gen_op_##width[] = {                       \
 194         &gen_op_##width##_user,                                         \
 195         &gen_op_##width##_kernel,                                       \
 196         &gen_op_##width##_hypv,                                         \
 197     };
 198 #else
 199 #define OP_LD_TABLE(width)                                              \
 200     static GenOpFunc * const gen_op_##width[] = {                       \
 201         &gen_op_##width##_user,                                         \
 202         &gen_op_##width##_kernel,                                       \
 203     };
 204 #endif
 205 #define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
 206 #endif
 207
 208 #ifndef CONFIG_USER_ONLY
 209 #ifdef __i386__
 210 OP_LD_TABLE(std);
 211 #endif /* __i386__ */
 212 OP_LD_TABLE(stdf);
 213 OP_LD_TABLE(lddf);
 214 #endif
 215
 216 #ifdef TARGET_ABI32
 217 #define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
 218 #else
 219 #define ABI32_MASK(addr)
 220 #endif
 221
 222 static inline void gen_movl_reg_TN(int reg, TCGv tn)
 223 {
 224     if (reg == 0)
 225         tcg_gen_movi_tl(tn, 0);
 226     else if (reg < 8)
 227         tcg_gen_mov_tl(tn, cpu_gregs[reg]);
 228     else {
 229         tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 230     }
 231 }
 232
 233 static inline void gen_movl_TN_reg(int reg, TCGv tn)
 234 {
 235     if (reg == 0)
 236         return;
 237     else if (reg < 8)
 238         tcg_gen_mov_tl(cpu_gregs[reg], tn);
 239     else {
 240         tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 241     }
 242 }
 243
 244 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 245                                target_ulong pc, target_ulong npc)
 246 {
 247     TranslationBlock *tb;
 248
 249     tb = s->tb;
 250     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 251         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 252         /* jump to same page: we can use a direct jump */
 253         tcg_gen_goto_tb(tb_num);
 254         tcg_gen_movi_tl(cpu_pc, pc);
 255         tcg_gen_movi_tl(cpu_npc, npc);
 256         tcg_gen_exit_tb((long)tb + tb_num);
 257     } else {
 258         /* jump to another page: currently not optimized */
 259         tcg_gen_movi_tl(cpu_pc, pc);
 260         tcg_gen_movi_tl(cpu_npc, npc);
 261         tcg_gen_exit_tb(0);
 262     }
 263 }
 264
 265 // XXX suboptimal
 266 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
 267 {
 268     tcg_gen_extu_i32_tl(reg, src);
 269     tcg_gen_shri_tl(reg, reg, 23);
 270     tcg_gen_andi_tl(reg, reg, 0x1);
 271 }
 272
 273 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
 274 {
 275     tcg_gen_extu_i32_tl(reg, src);
 276     tcg_gen_shri_tl(reg, reg, 22);
 277     tcg_gen_andi_tl(reg, reg, 0x1);
 278 }
 279
 280 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
 281 {
 282     tcg_gen_extu_i32_tl(reg, src);
 283     tcg_gen_shri_tl(reg, reg, 21);
 284     tcg_gen_andi_tl(reg, reg, 0x1);
 285 }
 286
 287 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
 288 {
 289     tcg_gen_extu_i32_tl(reg, src);
 290     tcg_gen_shri_tl(reg, reg, 20);
 291     tcg_gen_andi_tl(reg, reg, 0x1);
 292 }
 293
 294 static inline void gen_cc_clear_icc(void)
 295 {
 296     tcg_gen_movi_i32(cpu_psr, 0);
 297 }
 298
 299 #ifdef TARGET_SPARC64
 300 static inline void gen_cc_clear_xcc(void)
 301 {
 302     tcg_gen_movi_i32(cpu_xcc, 0);
 303 }
 304 #endif
 305
 306 /* old op:
 307     if (!T0)
 308         env->psr |= PSR_ZERO;
 309     if ((int32_t) T0 < 0)
 310         env->psr |= PSR_NEG;
 311 */
 312 static inline void gen_cc_NZ_icc(TCGv dst)
 313 {
 314     TCGv r_temp;
 315     int l1, l2;
 316
 317     l1 = gen_new_label();
 318     l2 = gen_new_label();
 319     r_temp = tcg_temp_new(TCG_TYPE_TL);
 320     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 321     tcg_gen_brcond_tl(TCG_COND_NE, r_temp, tcg_const_tl(0), l1);
 322     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
 323     gen_set_label(l1);
 324     tcg_gen_ext_i32_tl(r_temp, dst);
 325     tcg_gen_brcond_tl(TCG_COND_GE, r_temp, tcg_const_tl(0), l2);
 326     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
 327     gen_set_label(l2);
 328 }
 329
 330 #ifdef TARGET_SPARC64
 331 static inline void gen_cc_NZ_xcc(TCGv dst)
 332 {
 333     int l1, l2;
 334
 335     l1 = gen_new_label();
 336     l2 = gen_new_label();
 337     tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l1);
 338     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
 339     gen_set_label(l1);
 340     tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l2);
 341     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
 342     gen_set_label(l2);
 343 }
 344 #endif
 345
 346 /* old op:
 347     if (T0 < src1)
 348         env->psr |= PSR_CARRY;
 349 */
 350 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
 351 {
 352     TCGv r_temp;
 353     int l1;
 354
 355     l1 = gen_new_label();
 356     r_temp = tcg_temp_new(TCG_TYPE_TL);
 357     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 358     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 359     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 360     gen_set_label(l1);
 361 }
 362
 363 #ifdef TARGET_SPARC64
 364 static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
 365 {
 366     int l1;
 367
 368     l1 = gen_new_label();
 369     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 370     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 371     gen_set_label(l1);
 372 }
 373 #endif
 374
 375 /* old op:
 376     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
 377         env->psr |= PSR_OVF;
 378 */
 379 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
 380 {
 381     TCGv r_temp;
 382     int l1;
 383
 384     l1 = gen_new_label();
 385
 386     r_temp = tcg_temp_new(TCG_TYPE_TL);
 387     tcg_gen_xor_tl(r_temp, src1, src2);
 388     tcg_gen_xori_tl(r_temp, r_temp, -1);
 389     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 390     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 391     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 392     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 393     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 394     gen_set_label(l1);
 395 }
 396
 397 #ifdef TARGET_SPARC64
 398 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
 399 {
 400     TCGv r_temp;
 401     int l1;
 402
 403     l1 = gen_new_label();
 404
 405     r_temp = tcg_temp_new(TCG_TYPE_TL);
 406     tcg_gen_xor_tl(r_temp, src1, src2);
 407     tcg_gen_xori_tl(r_temp, r_temp, -1);
 408     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 409     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 410     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 411     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 412     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
 413     gen_set_label(l1);
 414 }
 415 #endif
 416
 417 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
 418 {
 419     TCGv r_temp;
 420     int l1;
 421
 422     l1 = gen_new_label();
 423
 424     r_temp = tcg_temp_new(TCG_TYPE_TL);
 425     tcg_gen_xor_tl(r_temp, src1, src2);
 426     tcg_gen_xori_tl(r_temp, r_temp, -1);
 427     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 428     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 429     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 430     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 431     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 432     gen_set_label(l1);
 433 }
 434
 435 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
 436 {
 437     int l1;
 438
 439     l1 = gen_new_label();
 440     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 441     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 442     tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
 443     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 444     gen_set_label(l1);
 445 }
 446
 447 static inline void gen_tag_tv(TCGv src1, TCGv src2)
 448 {
 449     int l1;
 450
 451     l1 = gen_new_label();
 452     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 453     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 454     tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
 455     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 456     gen_set_label(l1);
 457 }
 458
 459 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
 460 {
 461     tcg_gen_mov_tl(cpu_cc_src, src1);
 462     tcg_gen_add_tl(dst, src1, src2);
 463     gen_cc_clear_icc();
 464     gen_cc_NZ_icc(dst);
 465     gen_cc_C_add_icc(dst, cpu_cc_src);
 466     gen_cc_V_add_icc(dst, cpu_cc_src, src2);
 467 #ifdef TARGET_SPARC64
 468     gen_cc_clear_xcc();
 469     gen_cc_NZ_xcc(dst);
 470     gen_cc_C_add_xcc(dst, cpu_cc_src);
 471     gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
 472 #endif
 473 }
 474
 475 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
 476 {
 477     tcg_gen_mov_tl(cpu_cc_src, src1);
 478     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 479     tcg_gen_add_tl(dst, src1, cpu_tmp0);
 480     gen_cc_clear_icc();
 481     gen_cc_C_add_icc(dst, cpu_cc_src);
 482 #ifdef TARGET_SPARC64
 483     gen_cc_clear_xcc();
 484     gen_cc_C_add_xcc(dst, cpu_cc_src);
 485 #endif
 486     tcg_gen_add_tl(dst, dst, src2);
 487     gen_cc_NZ_icc(dst);
 488     gen_cc_C_add_icc(dst, cpu_cc_src);
 489     gen_cc_V_add_icc(dst, cpu_cc_src, src2);
 490 #ifdef TARGET_SPARC64
 491     gen_cc_NZ_xcc(dst);
 492     gen_cc_C_add_xcc(dst, cpu_cc_src);
 493     gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
 494 #endif
 495 }
 496
 497 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
 498 {
 499     tcg_gen_mov_tl(cpu_cc_src, src1);
 500     tcg_gen_add_tl(dst, src1, src2);
 501     gen_cc_clear_icc();
 502     gen_cc_NZ_icc(dst);
 503     gen_cc_C_add_icc(dst, cpu_cc_src);
 504     gen_cc_V_add_icc(dst, cpu_cc_src, src2);
 505     gen_cc_V_tag(cpu_cc_src, src2);
 506 #ifdef TARGET_SPARC64
 507     gen_cc_clear_xcc();
 508     gen_cc_NZ_xcc(dst);
 509     gen_cc_C_add_xcc(dst, cpu_cc_src);
 510     gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
 511 #endif
 512 }
 513
 514 static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
 515 {
 516     gen_tag_tv(src1, src2);
 517     tcg_gen_mov_tl(cpu_cc_src, src1);
 518     tcg_gen_add_tl(dst, src1, src2);
 519     gen_add_tv(dst, cpu_cc_src, src2);
 520     gen_cc_clear_icc();
 521     gen_cc_NZ_icc(dst);
 522     gen_cc_C_add_icc(dst, cpu_cc_src);
 523 #ifdef TARGET_SPARC64
 524     gen_cc_clear_xcc();
 525     gen_cc_NZ_xcc(dst);
 526     gen_cc_C_add_xcc(dst, cpu_cc_src);
 527     gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
 528 #endif
 529 }
 530
 531 /* old op:
 532     if (src1 < T1)
 533         env->psr |= PSR_CARRY;
 534 */
 535 static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
 536 {
 537     TCGv r_temp1, r_temp2;
 538     int l1;
 539
 540     l1 = gen_new_label();
 541     r_temp1 = tcg_temp_new(TCG_TYPE_TL);
 542     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 543     tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
 544     tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
 545     tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
 546     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 547     gen_set_label(l1);
 548 }
 549
 550 #ifdef TARGET_SPARC64
 551 static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
 552 {
 553     int l1;
 554
 555     l1 = gen_new_label();
 556     tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
 557     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 558     gen_set_label(l1);
 559 }
 560 #endif
 561
 562 /* old op:
 563     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
 564         env->psr |= PSR_OVF;
 565 */
 566 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
 567 {
 568     TCGv r_temp;
 569     int l1;
 570
 571     l1 = gen_new_label();
 572
 573     r_temp = tcg_temp_new(TCG_TYPE_TL);
 574     tcg_gen_xor_tl(r_temp, src1, src2);
 575     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 576     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 577     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 578     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 579     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 580     gen_set_label(l1);
 581 }
 582
 583 #ifdef TARGET_SPARC64
 584 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
 585 {
 586     TCGv r_temp;
 587     int l1;
 588
 589     l1 = gen_new_label();
 590
 591     r_temp = tcg_temp_new(TCG_TYPE_TL);
 592     tcg_gen_xor_tl(r_temp, src1, src2);
 593     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 594     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 595     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 596     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 597     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
 598     gen_set_label(l1);
 599 }
 600 #endif
 601
 602 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
 603 {
 604     TCGv r_temp;
 605     int l1;
 606
 607     l1 = gen_new_label();
 608
 609     r_temp = tcg_temp_new(TCG_TYPE_TL);
 610     tcg_gen_xor_tl(r_temp, src1, src2);
 611     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 612     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 613     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 614     tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
 615     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 616     gen_set_label(l1);
 617     tcg_gen_discard_tl(r_temp);
 618 }
 619
 620 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
 621 {
 622     tcg_gen_mov_tl(cpu_cc_src, src1);
 623     tcg_gen_sub_tl(dst, src1, src2);
 624     gen_cc_clear_icc();
 625     gen_cc_NZ_icc(dst);
 626     gen_cc_C_sub_icc(cpu_cc_src, src2);
 627     gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
 628 #ifdef TARGET_SPARC64
 629     gen_cc_clear_xcc();
 630     gen_cc_NZ_xcc(dst);
 631     gen_cc_C_sub_xcc(cpu_cc_src, src2);
 632     gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
 633 #endif
 634 }
 635
 636 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
 637 {
 638     tcg_gen_mov_tl(cpu_cc_src, src1);
 639     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 640     tcg_gen_sub_tl(dst, src1, cpu_tmp0);
 641     gen_cc_clear_icc();
 642     gen_cc_C_sub_icc(dst, cpu_cc_src);
 643 #ifdef TARGET_SPARC64
 644     gen_cc_clear_xcc();
 645     gen_cc_C_sub_xcc(dst, cpu_cc_src);
 646 #endif
 647     tcg_gen_sub_tl(dst, dst, src2);
 648     gen_cc_NZ_icc(dst);
 649     gen_cc_C_sub_icc(dst, cpu_cc_src);
 650     gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
 651 #ifdef TARGET_SPARC64
 652     gen_cc_NZ_xcc(dst);
 653     gen_cc_C_sub_xcc(dst, cpu_cc_src);
 654     gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
 655 #endif
 656 }
 657
 658 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
 659 {
 660     tcg_gen_mov_tl(cpu_cc_src, src1);
 661     tcg_gen_sub_tl(dst, src1, src2);
 662     gen_cc_clear_icc();
 663     gen_cc_NZ_icc(dst);
 664     gen_cc_C_sub_icc(cpu_cc_src, src2);
 665     gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
 666     gen_cc_V_tag(cpu_cc_src, src2);
 667 #ifdef TARGET_SPARC64
 668     gen_cc_clear_xcc();
 669     gen_cc_NZ_xcc(dst);
 670     gen_cc_C_sub_xcc(cpu_cc_src, src2);
 671     gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
 672 #endif
 673 }
 674
 675 static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
 676 {
 677     gen_tag_tv(src1, src2);
 678     tcg_gen_mov_tl(cpu_cc_src, src1);
 679     tcg_gen_sub_tl(dst, src1, src2);
 680     gen_sub_tv(dst, cpu_cc_src, src2);
 681     gen_cc_clear_icc();
 682     gen_cc_NZ_icc(dst);
 683     gen_cc_C_sub_icc(cpu_cc_src, src2);
 684 #ifdef TARGET_SPARC64
 685     gen_cc_clear_xcc();
 686     gen_cc_NZ_xcc(dst);
 687     gen_cc_C_sub_xcc(cpu_cc_src, src2);
 688     gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
 689 #endif
 690 }
 691
 692 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
 693 {
 694     TCGv r_temp, r_temp2;
 695     int l1, l2;
 696
 697     l1 = gen_new_label();
 698     l2 = gen_new_label();
 699     r_temp = tcg_temp_new(TCG_TYPE_TL);
 700     r_temp2 = tcg_temp_new(TCG_TYPE_I32);
 701
 702     /* old op:
 703     if (!(env->y & 1))
 704         T1 = 0;
 705     */
 706     tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 707     tcg_gen_trunc_tl_i32(r_temp2, r_temp);
 708     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 709     tcg_gen_brcond_i32(TCG_COND_EQ, r_temp2, tcg_const_i32(0), l1);
 710     tcg_gen_mov_tl(cpu_cc_src2, src2);
 711     tcg_gen_br(l2);
 712     gen_set_label(l1);
 713     tcg_gen_movi_tl(cpu_cc_src2, 0);
 714     gen_set_label(l2);
 715
 716     // b2 = T0 & 1;
 717     // env->y = (b2 << 31) | (env->y >> 1);
 718     tcg_gen_trunc_tl_i32(r_temp2, src1);
 719     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 720     tcg_gen_shli_i32(r_temp2, r_temp2, 31);
 721     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 722     tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
 723     tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
 724     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 725
 726     // b1 = N ^ V;
 727     gen_mov_reg_N(cpu_tmp0, cpu_psr);
 728     gen_mov_reg_V(r_temp, cpu_psr);
 729     tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
 730
 731     // T0 = (b1 << 31) | (T0 >> 1);
 732     // src1 = T0;
 733     tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
 734     tcg_gen_shri_tl(cpu_cc_src, src1, 1);
 735     tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
 736
 737     /* do addition and update flags */
 738     tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
 739     tcg_gen_discard_tl(r_temp);
 740
 741     gen_cc_clear_icc();
 742     gen_cc_NZ_icc(dst);
 743     gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2);
 744     gen_cc_C_add_icc(dst, cpu_cc_src);
 745 }
 746
 747 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
 748 {
 749     TCGv r_temp, r_temp2;
 750
 751     r_temp = tcg_temp_new(TCG_TYPE_I64);
 752     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 753
 754     tcg_gen_extu_tl_i64(r_temp, src2);
 755     tcg_gen_extu_tl_i64(r_temp2, src1);
 756     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 757
 758     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 759     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 760     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 761 #ifdef TARGET_SPARC64
 762     tcg_gen_mov_i64(dst, r_temp2);
 763 #else
 764     tcg_gen_trunc_i64_tl(dst, r_temp2);
 765 #endif
 766
 767     tcg_gen_discard_i64(r_temp);
 768     tcg_gen_discard_i64(r_temp2);
 769 }
 770
 771 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
 772 {
 773     TCGv r_temp, r_temp2;
 774
 775     r_temp = tcg_temp_new(TCG_TYPE_I64);
 776     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 777
 778     tcg_gen_ext_tl_i64(r_temp, src2);
 779     tcg_gen_ext_tl_i64(r_temp2, src1);
 780     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 781
 782     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 783     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 784     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 785 #ifdef TARGET_SPARC64
 786     tcg_gen_mov_i64(dst, r_temp2);
 787 #else
 788     tcg_gen_trunc_i64_tl(dst, r_temp2);
 789 #endif
 790
 791     tcg_gen_discard_i64(r_temp);
 792     tcg_gen_discard_i64(r_temp2);
 793 }
 794
 795 #ifdef TARGET_SPARC64
 796 static inline void gen_trap_ifdivzero_tl(TCGv divisor)
 797 {
 798     int l1;
 799
 800     l1 = gen_new_label();
 801     tcg_gen_brcond_tl(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
 802     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO));
 803     gen_set_label(l1);
 804 }
 805
 806 static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
 807 {
 808     int l1, l2;
 809
 810     l1 = gen_new_label();
 811     l2 = gen_new_label();
 812     gen_trap_ifdivzero_tl(src2);
 813     tcg_gen_brcond_tl(TCG_COND_NE, src1, tcg_const_tl(INT64_MIN), l1);
 814     tcg_gen_brcond_tl(TCG_COND_NE, src2, tcg_const_tl(-1), l1);
 815     tcg_gen_movi_i64(dst, INT64_MIN);
 816     tcg_gen_br(l2);
 817     gen_set_label(l1);
 818     tcg_gen_div_i64(dst, src1, src2);
 819     gen_set_label(l2);
 820 }
 821 #endif
 822
 823 static inline void gen_op_div_cc(TCGv dst)
 824 {
 825     int l1;
 826
 827     gen_cc_clear_icc();
 828     gen_cc_NZ_icc(dst);
 829     l1 = gen_new_label();
 830     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
 831     tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
 832     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 833     gen_set_label(l1);
 834 }
 835
 836 static inline void gen_op_logic_cc(TCGv dst)
 837 {
 838     gen_cc_clear_icc();
 839     gen_cc_NZ_icc(dst);
 840 #ifdef TARGET_SPARC64
 841     gen_cc_clear_xcc();
 842     gen_cc_NZ_xcc(dst);
 843 #endif
 844 }
 845
 846 // 1
 847 static inline void gen_op_eval_ba(TCGv dst)
 848 {
 849     tcg_gen_movi_tl(dst, 1);
 850 }
 851
 852 // Z
 853 static inline void gen_op_eval_be(TCGv dst, TCGv src)
 854 {
 855     gen_mov_reg_Z(dst, src);
 856 }
 857
 858 // Z | (N ^ V)
 859 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
 860 {
 861     gen_mov_reg_N(cpu_tmp0, src);
 862     gen_mov_reg_V(dst, src);
 863     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 864     gen_mov_reg_Z(cpu_tmp0, src);
 865     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 866 }
 867
 868 // N ^ V
 869 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
 870 {
 871     gen_mov_reg_V(cpu_tmp0, src);
 872     gen_mov_reg_N(dst, src);
 873     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 874 }
 875
 876 // C | Z
 877 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
 878 {
 879     gen_mov_reg_Z(cpu_tmp0, src);
 880     gen_mov_reg_C(dst, src);
 881     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 882 }
 883
 884 // C
 885 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
 886 {
 887     gen_mov_reg_C(dst, src);
 888 }
 889
 890 // V
 891 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
 892 {
 893     gen_mov_reg_V(dst, src);
 894 }
 895
 896 // 0
 897 static inline void gen_op_eval_bn(TCGv dst)
 898 {
 899     tcg_gen_movi_tl(dst, 0);
 900 }
 901
 902 // N
 903 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
 904 {
 905     gen_mov_reg_N(dst, src);
 906 }
 907
 908 // !Z
 909 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
 910 {
 911     gen_mov_reg_Z(dst, src);
 912     tcg_gen_xori_tl(dst, dst, 0x1);
 913 }
 914
 915 // !(Z | (N ^ V))
 916 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
 917 {
 918     gen_mov_reg_N(cpu_tmp0, src);
 919     gen_mov_reg_V(dst, src);
 920     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 921     gen_mov_reg_Z(cpu_tmp0, src);
 922     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 923     tcg_gen_xori_tl(dst, dst, 0x1);
 924 }
 925
 926 // !(N ^ V)
 927 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
 928 {
 929     gen_mov_reg_V(cpu_tmp0, src);
 930     gen_mov_reg_N(dst, src);
 931     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 932     tcg_gen_xori_tl(dst, dst, 0x1);
 933 }
 934
 935 // !(C | Z)
 936 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
 937 {
 938     gen_mov_reg_Z(cpu_tmp0, src);
 939     gen_mov_reg_C(dst, src);
 940     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 941     tcg_gen_xori_tl(dst, dst, 0x1);
 942 }
 943
 944 // !C
 945 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
 946 {
 947     gen_mov_reg_C(dst, src);
 948     tcg_gen_xori_tl(dst, dst, 0x1);
 949 }
 950
 951 // !N
 952 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
 953 {
 954     gen_mov_reg_N(dst, src);
 955     tcg_gen_xori_tl(dst, dst, 0x1);
 956 }
 957
 958 // !V
 959 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
 960 {
 961     gen_mov_reg_V(dst, src);
 962     tcg_gen_xori_tl(dst, dst, 0x1);
 963 }
 964
 965 /*
 966   FPSR bit field FCC1 | FCC0:
 967    0 =
 968    1 <
 969    2 >
 970    3 unordered
 971 */
 972 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
 973                                     unsigned int fcc_offset)
 974 {
 975     tcg_gen_extu_i32_tl(reg, src);
 976     tcg_gen_shri_tl(reg, reg, 10 + fcc_offset);
 977     tcg_gen_andi_tl(reg, reg, 0x1);
 978 }
 979
 980 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
 981                                     unsigned int fcc_offset)
 982 {
 983     tcg_gen_extu_i32_tl(reg, src);
 984     tcg_gen_shri_tl(reg, reg, 11 + fcc_offset);
 985     tcg_gen_andi_tl(reg, reg, 0x1);
 986 }
 987
 988 // !0: FCC0 | FCC1
 989 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
 990                                     unsigned int fcc_offset)
 991 {
 992     gen_mov_reg_FCC0(dst, src, fcc_offset);
 993     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
 994     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 995 }
 996
 997 // 1 or 2: FCC0 ^ FCC1
 998 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
 999                                     unsigned int fcc_offset)
1000 {
1001     gen_mov_reg_FCC0(dst, src, fcc_offset);
1002     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1003     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1004 }
1005
1006 // 1 or 3: FCC0
1007 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1008                                     unsigned int fcc_offset)
1009 {
1010     gen_mov_reg_FCC0(dst, src, fcc_offset);
1011 }
1012
1013 // 1: FCC0 & !FCC1
1014 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1015                                     unsigned int fcc_offset)
1016 {
1017     gen_mov_reg_FCC0(dst, src, fcc_offset);
1018     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1019     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1020     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1021 }
1022
1023 // 2 or 3: FCC1
1024 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1025                                     unsigned int fcc_offset)
1026 {
1027     gen_mov_reg_FCC1(dst, src, fcc_offset);
1028 }
1029
1030 // 2: !FCC0 & FCC1
1031 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1032                                     unsigned int fcc_offset)
1033 {
1034     gen_mov_reg_FCC0(dst, src, fcc_offset);
1035     tcg_gen_xori_tl(dst, dst, 0x1);
1036     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1037     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1038 }
1039
1040 // 3: FCC0 & FCC1
1041 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1042                                     unsigned int fcc_offset)
1043 {
1044     gen_mov_reg_FCC0(dst, src, fcc_offset);
1045     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1046     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1047 }
1048
1049 // 0: !(FCC0 | FCC1)
1050 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1051                                     unsigned int fcc_offset)
1052 {
1053     gen_mov_reg_FCC0(dst, src, fcc_offset);
1054     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1055     tcg_gen_or_tl(dst, dst, cpu_tmp0);
1056     tcg_gen_xori_tl(dst, dst, 0x1);
1057 }
1058
1059 // 0 or 3: !(FCC0 ^ FCC1)
1060 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1061                                     unsigned int fcc_offset)
1062 {
1063     gen_mov_reg_FCC0(dst, src, fcc_offset);
1064     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1065     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1066     tcg_gen_xori_tl(dst, dst, 0x1);
1067 }
1068
1069 // 0 or 2: !FCC0
1070 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1071                                     unsigned int fcc_offset)
1072 {
1073     gen_mov_reg_FCC0(dst, src, fcc_offset);
1074     tcg_gen_xori_tl(dst, dst, 0x1);
1075 }
1076
1077 // !1: !(FCC0 & !FCC1)
1078 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1079                                     unsigned int fcc_offset)
1080 {
1081     gen_mov_reg_FCC0(dst, src, fcc_offset);
1082     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1083     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1084     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1085     tcg_gen_xori_tl(dst, dst, 0x1);
1086 }
1087
1088 // 0 or 1: !FCC1
1089 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1090                                     unsigned int fcc_offset)
1091 {
1092     gen_mov_reg_FCC1(dst, src, fcc_offset);
1093     tcg_gen_xori_tl(dst, dst, 0x1);
1094 }
1095
1096 // !2: !(!FCC0 & FCC1)
1097 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1098                                     unsigned int fcc_offset)
1099 {
1100     gen_mov_reg_FCC0(dst, src, fcc_offset);
1101     tcg_gen_xori_tl(dst, dst, 0x1);
1102     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1103     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1104     tcg_gen_xori_tl(dst, dst, 0x1);
1105 }
1106
1107 // !3: !(FCC0 & FCC1)
1108 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1109                                     unsigned int fcc_offset)
1110 {
1111     gen_mov_reg_FCC0(dst, src, fcc_offset);
1112     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1113     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1114     tcg_gen_xori_tl(dst, dst, 0x1);
1115 }
1116
1117 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1118                                target_ulong pc2, TCGv r_cond)
1119 {
1120     int l1;
1121
1122     l1 = gen_new_label();
1123
1124     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1125
1126     gen_goto_tb(dc, 0, pc1, pc1 + 4);
1127
1128     gen_set_label(l1);
1129     gen_goto_tb(dc, 1, pc2, pc2 + 4);
1130 }
1131
1132 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1133                                 target_ulong pc2, TCGv r_cond)
1134 {
1135     int l1;
1136
1137     l1 = gen_new_label();
1138
1139     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1140
1141     gen_goto_tb(dc, 0, pc2, pc1);
1142
1143     gen_set_label(l1);
1144     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1145 }
1146
1147 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1148                                       TCGv r_cond)
1149 {
1150     int l1, l2;
1151
1152     l1 = gen_new_label();
1153     l2 = gen_new_label();
1154
1155     tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1156
1157     tcg_gen_movi_tl(cpu_npc, npc1);
1158     tcg_gen_br(l2);
1159
1160     gen_set_label(l1);
1161     tcg_gen_movi_tl(cpu_npc, npc2);
1162     gen_set_label(l2);
1163 }
1164
1165 /* call this function before using the condition register as it may
1166    have been set for a jump */
1167 static inline void flush_cond(DisasContext *dc, TCGv cond)
1168 {
1169     if (dc->npc == JUMP_PC) {
1170         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1171         dc->npc = DYNAMIC_PC;
1172     }
1173 }
1174
1175 static inline void save_npc(DisasContext *dc, TCGv cond)
1176 {
1177     if (dc->npc == JUMP_PC) {
1178         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1179         dc->npc = DYNAMIC_PC;
1180     } else if (dc->npc != DYNAMIC_PC) {
1181         tcg_gen_movi_tl(cpu_npc, dc->npc);
1182     }
1183 }
1184
1185 static inline void save_state(DisasContext *dc, TCGv cond)
1186 {
1187     tcg_gen_movi_tl(cpu_pc, dc->pc);
1188     save_npc(dc, cond);
1189 }
1190
1191 static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1192 {
1193     if (dc->npc == JUMP_PC) {
1194         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1195         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1196         dc->pc = DYNAMIC_PC;
1197     } else if (dc->npc == DYNAMIC_PC) {
1198         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1199         dc->pc = DYNAMIC_PC;
1200     } else {
1201         dc->pc = dc->npc;
1202     }
1203 }
1204
1205 static inline void gen_op_next_insn(void)
1206 {
1207     tcg_gen_mov_tl(cpu_pc, cpu_npc);
1208     tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1209 }
1210
1211 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1212 {
1213     TCGv r_src;
1214
1215 #ifdef TARGET_SPARC64
1216     if (cc)
1217         r_src = cpu_xcc;
1218     else
1219         r_src = cpu_psr;
1220 #else
1221     r_src = cpu_psr;
1222 #endif
1223     switch (cond) {
1224     case 0x0:
1225         gen_op_eval_bn(r_dst);
1226         break;
1227     case 0x1:
1228         gen_op_eval_be(r_dst, r_src);
1229         break;
1230     case 0x2:
1231         gen_op_eval_ble(r_dst, r_src);
1232         break;
1233     case 0x3:
1234         gen_op_eval_bl(r_dst, r_src);
1235         break;
1236     case 0x4:
1237         gen_op_eval_bleu(r_dst, r_src);
1238         break;
1239     case 0x5:
1240         gen_op_eval_bcs(r_dst, r_src);
1241         break;
1242     case 0x6:
1243         gen_op_eval_bneg(r_dst, r_src);
1244         break;
1245     case 0x7:
1246         gen_op_eval_bvs(r_dst, r_src);
1247         break;
1248     case 0x8:
1249         gen_op_eval_ba(r_dst);
1250         break;
1251     case 0x9:
1252         gen_op_eval_bne(r_dst, r_src);
1253         break;
1254     case 0xa:
1255         gen_op_eval_bg(r_dst, r_src);
1256         break;
1257     case 0xb:
1258         gen_op_eval_bge(r_dst, r_src);
1259         break;
1260     case 0xc:
1261         gen_op_eval_bgu(r_dst, r_src);
1262         break;
1263     case 0xd:
1264         gen_op_eval_bcc(r_dst, r_src);
1265         break;
1266     case 0xe:
1267         gen_op_eval_bpos(r_dst, r_src);
1268         break;
1269     case 0xf:
1270         gen_op_eval_bvc(r_dst, r_src);
1271         break;
1272     }
1273 }
1274
1275 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1276 {
1277     unsigned int offset;
1278
1279     switch (cc) {
1280     default:
1281     case 0x0:
1282         offset = 0;
1283         break;
1284     case 0x1:
1285         offset = 32 - 10;
1286         break;
1287     case 0x2:
1288         offset = 34 - 10;
1289         break;
1290     case 0x3:
1291         offset = 36 - 10;
1292         break;
1293     }
1294
1295     switch (cond) {
1296     case 0x0:
1297         gen_op_eval_bn(r_dst);
1298         break;
1299     case 0x1:
1300         gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1301         break;
1302     case 0x2:
1303         gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1304         break;
1305     case 0x3:
1306         gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1307         break;
1308     case 0x4:
1309         gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1310         break;
1311     case 0x5:
1312         gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1313         break;
1314     case 0x6:
1315         gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1316         break;
1317     case 0x7:
1318         gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1319         break;
1320     case 0x8:
1321         gen_op_eval_ba(r_dst);
1322         break;
1323     case 0x9:
1324         gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1325         break;
1326     case 0xa:
1327         gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1328         break;
1329     case 0xb:
1330         gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1331         break;
1332     case 0xc:
1333         gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1334         break;
1335     case 0xd:
1336         gen_op_eval_fble(r_dst, cpu_fsr, offset);
1337         break;
1338     case 0xe:
1339         gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1340         break;
1341     case 0xf:
1342         gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1343         break;
1344     }
1345 }
1346
1347 #ifdef TARGET_SPARC64
1348 // Inverted logic
1349 static const int gen_tcg_cond_reg[8] = {
1350     -1,
1351     TCG_COND_NE,
1352     TCG_COND_GT,
1353     TCG_COND_GE,
1354     -1,
1355     TCG_COND_EQ,
1356     TCG_COND_LE,
1357     TCG_COND_LT,
1358 };
1359
1360 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1361 {
1362     int l1;
1363
1364     l1 = gen_new_label();
1365     tcg_gen_movi_tl(r_dst, 0);
1366     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], r_src, tcg_const_tl(0), l1);
1367     tcg_gen_movi_tl(r_dst, 1);
1368     gen_set_label(l1);
1369 }
1370 #endif
1371
1372 /* XXX: potentially incorrect if dynamic npc */
1373 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1374                       TCGv r_cond)
1375 {
1376     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1377     target_ulong target = dc->pc + offset;
1378
1379     if (cond == 0x0) {
1380         /* unconditional not taken */
1381         if (a) {
1382             dc->pc = dc->npc + 4;
1383             dc->npc = dc->pc + 4;
1384         } else {
1385             dc->pc = dc->npc;
1386             dc->npc = dc->pc + 4;
1387         }
1388     } else if (cond == 0x8) {
1389         /* unconditional taken */
1390         if (a) {
1391             dc->pc = target;
1392             dc->npc = dc->pc + 4;
1393         } else {
1394             dc->pc = dc->npc;
1395             dc->npc = target;
1396         }
1397     } else {
1398         flush_cond(dc, r_cond);
1399         gen_cond(r_cond, cc, cond);
1400         if (a) {
1401             gen_branch_a(dc, target, dc->npc, r_cond);
1402             dc->is_br = 1;
1403         } else {
1404             dc->pc = dc->npc;
1405             dc->jump_pc[0] = target;
1406             dc->jump_pc[1] = dc->npc + 4;
1407             dc->npc = JUMP_PC;
1408         }
1409     }
1410 }
1411
1412 /* XXX: potentially incorrect if dynamic npc */
1413 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1414                       TCGv r_cond)
1415 {
1416     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1417     target_ulong target = dc->pc + offset;
1418
1419     if (cond == 0x0) {
1420         /* unconditional not taken */
1421         if (a) {
1422             dc->pc = dc->npc + 4;
1423             dc->npc = dc->pc + 4;
1424         } else {
1425             dc->pc = dc->npc;
1426             dc->npc = dc->pc + 4;
1427         }
1428     } else if (cond == 0x8) {
1429         /* unconditional taken */
1430         if (a) {
1431             dc->pc = target;
1432             dc->npc = dc->pc + 4;
1433         } else {
1434             dc->pc = dc->npc;
1435             dc->npc = target;
1436         }
1437     } else {
1438         flush_cond(dc, r_cond);
1439         gen_fcond(r_cond, cc, cond);
1440         if (a) {
1441             gen_branch_a(dc, target, dc->npc, r_cond);
1442             dc->is_br = 1;
1443         } else {
1444             dc->pc = dc->npc;
1445             dc->jump_pc[0] = target;
1446             dc->jump_pc[1] = dc->npc + 4;
1447             dc->npc = JUMP_PC;
1448         }
1449     }
1450 }
1451
1452 #ifdef TARGET_SPARC64
1453 /* XXX: potentially incorrect if dynamic npc */
1454 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1455                           TCGv r_cond, TCGv r_reg)
1456 {
1457     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1458     target_ulong target = dc->pc + offset;
1459
1460     flush_cond(dc, r_cond);
1461     gen_cond_reg(r_cond, cond, r_reg);
1462     if (a) {
1463         gen_branch_a(dc, target, dc->npc, r_cond);
1464         dc->is_br = 1;
1465     } else {
1466         dc->pc = dc->npc;
1467         dc->jump_pc[0] = target;
1468         dc->jump_pc[1] = dc->npc + 4;
1469         dc->npc = JUMP_PC;
1470     }
1471 }
1472
1473 static GenOpFunc * const gen_fcmps[4] = {
1474     helper_fcmps,
1475     helper_fcmps_fcc1,
1476     helper_fcmps_fcc2,
1477     helper_fcmps_fcc3,
1478 };
1479
1480 static GenOpFunc * const gen_fcmpd[4] = {
1481     helper_fcmpd,
1482     helper_fcmpd_fcc1,
1483     helper_fcmpd_fcc2,
1484     helper_fcmpd_fcc3,
1485 };
1486
1487 #if defined(CONFIG_USER_ONLY)
1488 static GenOpFunc * const gen_fcmpq[4] = {
1489     helper_fcmpq,
1490     helper_fcmpq_fcc1,
1491     helper_fcmpq_fcc2,
1492     helper_fcmpq_fcc3,
1493 };
1494 #endif
1495
1496 static GenOpFunc * const gen_fcmpes[4] = {
1497     helper_fcmpes,
1498     helper_fcmpes_fcc1,
1499     helper_fcmpes_fcc2,
1500     helper_fcmpes_fcc3,
1501 };
1502
1503 static GenOpFunc * const gen_fcmped[4] = {
1504     helper_fcmped,
1505     helper_fcmped_fcc1,
1506     helper_fcmped_fcc2,
1507     helper_fcmped_fcc3,
1508 };
1509
1510 #if defined(CONFIG_USER_ONLY)
1511 static GenOpFunc * const gen_fcmpeq[4] = {
1512     helper_fcmpeq,
1513     helper_fcmpeq_fcc1,
1514     helper_fcmpeq_fcc2,
1515     helper_fcmpeq_fcc3,
1516 };
1517 #endif
1518
1519 static inline void gen_op_fcmps(int fccno)
1520 {
1521     tcg_gen_helper_0_0(gen_fcmps[fccno]);
1522 }
1523
1524 static inline void gen_op_fcmpd(int fccno)
1525 {
1526     tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1527 }
1528
1529 #if defined(CONFIG_USER_ONLY)
1530 static inline void gen_op_fcmpq(int fccno)
1531 {
1532     tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1533 }
1534 #endif
1535
1536 static inline void gen_op_fcmpes(int fccno)
1537 {
1538     tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1539 }
1540
1541 static inline void gen_op_fcmped(int fccno)
1542 {
1543     tcg_gen_helper_0_0(gen_fcmped[fccno]);
1544 }
1545
1546 #if defined(CONFIG_USER_ONLY)
1547 static inline void gen_op_fcmpeq(int fccno)
1548 {
1549     tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1550 }
1551 #endif
1552
1553 #else
1554
1555 static inline void gen_op_fcmps(int fccno)
1556 {
1557     tcg_gen_helper_0_0(helper_fcmps);
1558 }
1559
1560 static inline void gen_op_fcmpd(int fccno)
1561 {
1562     tcg_gen_helper_0_0(helper_fcmpd);
1563 }
1564
1565 #if defined(CONFIG_USER_ONLY)
1566 static inline void gen_op_fcmpq(int fccno)
1567 {
1568     tcg_gen_helper_0_0(helper_fcmpq);
1569 }
1570 #endif
1571
1572 static inline void gen_op_fcmpes(int fccno)
1573 {
1574     tcg_gen_helper_0_0(helper_fcmpes);
1575 }
1576
1577 static inline void gen_op_fcmped(int fccno)
1578 {
1579     tcg_gen_helper_0_0(helper_fcmped);
1580 }
1581
1582 #if defined(CONFIG_USER_ONLY)
1583 static inline void gen_op_fcmpeq(int fccno)
1584 {
1585     tcg_gen_helper_0_0(helper_fcmpeq);
1586 }
1587 #endif
1588
1589 #endif
1590
1591 static inline void gen_op_fpexception_im(int fsr_flags)
1592 {
1593     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1594     tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1595     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
1596 }
1597
1598 static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1599 {
1600 #if !defined(CONFIG_USER_ONLY)
1601     if (!dc->fpu_enabled) {
1602         save_state(dc, r_cond);
1603         tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
1604         dc->is_br = 1;
1605         return 1;
1606     }
1607 #endif
1608     return 0;
1609 }
1610
1611 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1612 {
1613     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1614 }
1615
1616 static inline void gen_clear_float_exceptions(void)
1617 {
1618     tcg_gen_helper_0_0(helper_clear_float_exceptions);
1619 }
1620
1621 /* asi moves */
1622 #ifdef TARGET_SPARC64
1623 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1624 {
1625     int asi, offset;
1626     TCGv r_asi;
1627
1628     if (IS_IMM) {
1629         r_asi = tcg_temp_new(TCG_TYPE_I32);
1630         offset = GET_FIELD(insn, 25, 31);
1631         tcg_gen_addi_tl(r_addr, r_addr, offset);
1632         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1633     } else {
1634         asi = GET_FIELD(insn, 19, 26);
1635         r_asi = tcg_const_i32(asi);
1636     }
1637     return r_asi;
1638 }
1639
1640 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1641 {
1642     TCGv r_asi;
1643
1644     r_asi = gen_get_asi(insn, addr);
1645     tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi,
1646                        tcg_const_i32(size), tcg_const_i32(sign));
1647     tcg_gen_discard_i32(r_asi);
1648 }
1649
1650 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1651 {
1652     TCGv r_asi;
1653
1654     r_asi = gen_get_asi(insn, addr);
1655     tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, tcg_const_i32(size));
1656     tcg_gen_discard_i32(r_asi);
1657 }
1658
1659 static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1660 {
1661     TCGv r_asi;
1662
1663     r_asi = gen_get_asi(insn, addr);
1664     tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, tcg_const_i32(size),
1665                        tcg_const_i32(rd));
1666     tcg_gen_discard_i32(r_asi);
1667 }
1668
1669 static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1670 {
1671     TCGv r_asi;
1672
1673     r_asi = gen_get_asi(insn, addr);
1674     tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, tcg_const_i32(size),
1675                        tcg_const_i32(rd));
1676     tcg_gen_discard_i32(r_asi);
1677 }
1678
1679 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1680 {
1681     TCGv r_temp, r_asi;
1682
1683     r_temp = tcg_temp_new(TCG_TYPE_I32);
1684     r_asi = gen_get_asi(insn, addr);
1685     tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, r_asi,
1686                        tcg_const_i32(4), tcg_const_i32(0));
1687     tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi,
1688                        tcg_const_i32(4));
1689     tcg_gen_extu_i32_tl(dst, r_temp);
1690     tcg_gen_discard_i32(r_asi);
1691     tcg_gen_discard_i32(r_temp);
1692 }
1693
1694 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1695 {
1696     TCGv r_asi;
1697
1698     r_asi = gen_get_asi(insn, addr);
1699     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi,
1700                        tcg_const_i32(8), tcg_const_i32(0));
1701     tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1702     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1703     tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1704     tcg_gen_discard_i32(r_asi);
1705 }
1706
1707 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1708 {
1709     TCGv r_temp, r_asi;
1710
1711     r_temp = tcg_temp_new(TCG_TYPE_I32);
1712     gen_movl_reg_TN(rd + 1, r_temp);
1713     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1714                        r_temp);
1715     r_asi = gen_get_asi(insn, addr);
1716     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi,
1717                        tcg_const_i32(8));
1718     tcg_gen_discard_i32(r_asi);
1719     tcg_gen_discard_i32(r_temp);
1720 }
1721
1722 static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1723 {
1724     TCGv r_val1, r_asi;
1725
1726     r_val1 = tcg_temp_new(TCG_TYPE_I32);
1727     gen_movl_reg_TN(rd, r_val1);
1728     r_asi = gen_get_asi(insn, addr);
1729     tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1730     tcg_gen_discard_i32(r_asi);
1731     tcg_gen_discard_i32(r_val1);
1732 }
1733
1734 static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1735 {
1736     TCGv r_asi;
1737
1738     gen_movl_reg_TN(rd, cpu_tmp64);
1739     r_asi = gen_get_asi(insn, addr);
1740     tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1741     tcg_gen_discard_i32(r_asi);
1742 }
1743
1744 #elif !defined(CONFIG_USER_ONLY)
1745
1746 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1747 {
1748     int asi;
1749
1750     asi = GET_FIELD(insn, 19, 26);
1751     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1752                        tcg_const_i32(size), tcg_const_i32(sign));
1753     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1754 }
1755
1756 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1757 {
1758     int asi;
1759
1760     tcg_gen_extu_tl_i64(cpu_tmp64, src);
1761     asi = GET_FIELD(insn, 19, 26);
1762     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1763                        tcg_const_i32(size));
1764 }
1765
1766 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1767 {
1768     int asi;
1769     TCGv r_temp;
1770
1771     r_temp = tcg_temp_new(TCG_TYPE_I32);
1772     asi = GET_FIELD(insn, 19, 26);
1773     tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, tcg_const_i32(asi),
1774                        tcg_const_i32(4), tcg_const_i32(0));
1775     tcg_gen_helper_0_4(helper_st_asi, addr, dst, tcg_const_i32(asi),
1776                        tcg_const_i32(4));
1777     tcg_gen_extu_i32_tl(dst, r_temp);
1778     tcg_gen_discard_i32(r_temp);
1779 }
1780
1781 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1782 {
1783     int asi;
1784
1785     asi = GET_FIELD(insn, 19, 26);
1786     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1787                        tcg_const_i32(8), tcg_const_i32(0));
1788     tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1789     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1790     tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1791 }
1792
1793 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1794 {
1795     int asi;
1796     TCGv r_temp;
1797
1798     r_temp = tcg_temp_new(TCG_TYPE_I32);
1799     gen_movl_reg_TN(rd + 1, r_temp);
1800     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1801     asi = GET_FIELD(insn, 19, 26);
1802     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1803                        tcg_const_i32(8));
1804 }
1805 #endif
1806
1807 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1808 static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1809 {
1810     int asi;
1811
1812     gen_ld_asi(dst, addr, insn, 1, 0);
1813
1814     asi = GET_FIELD(insn, 19, 26);
1815     tcg_gen_helper_0_4(helper_st_asi, addr, tcg_const_i64(0xffULL),
1816                        tcg_const_i32(asi), tcg_const_i32(1));
1817 }
1818 #endif
1819
1820 /* before an instruction, dc->pc must be static */
1821 static void disas_sparc_insn(DisasContext * dc)
1822 {
1823     unsigned int insn, opc, rs1, rs2, rd;
1824
1825     insn = ldl_code(dc->pc);
1826     opc = GET_FIELD(insn, 0, 1);
1827
1828     rd = GET_FIELD(insn, 2, 6);
1829
1830     cpu_dst = cpu_T[0];
1831     cpu_src1 = cpu_T[0]; // const
1832     cpu_src2 = cpu_T[1]; // const
1833
1834     // loads and stores
1835     cpu_addr = cpu_T[0];
1836     cpu_val = cpu_T[1];
1837
1838     switch (opc) {
1839     case 0:                     /* branches/sethi */
1840         {
1841             unsigned int xop = GET_FIELD(insn, 7, 9);
1842             int32_t target;
1843             switch (xop) {
1844 #ifdef TARGET_SPARC64
1845             case 0x1:           /* V9 BPcc */
1846                 {
1847                     int cc;
1848
1849                     target = GET_FIELD_SP(insn, 0, 18);
1850                     target = sign_extend(target, 18);
1851                     target <<= 2;
1852                     cc = GET_FIELD_SP(insn, 20, 21);
1853                     if (cc == 0)
1854                         do_branch(dc, target, insn, 0, cpu_cond);
1855                     else if (cc == 2)
1856                         do_branch(dc, target, insn, 1, cpu_cond);
1857                     else
1858                         goto illegal_insn;
1859                     goto jmp_insn;
1860                 }
1861             case 0x3:           /* V9 BPr */
1862                 {
1863                     target = GET_FIELD_SP(insn, 0, 13) |
1864                         (GET_FIELD_SP(insn, 20, 21) << 14);
1865                     target = sign_extend(target, 16);
1866                     target <<= 2;
1867                     rs1 = GET_FIELD(insn, 13, 17);
1868                     gen_movl_reg_TN(rs1, cpu_src1);
1869                     do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1870                     goto jmp_insn;
1871                 }
1872             case 0x5:           /* V9 FBPcc */
1873                 {
1874                     int cc = GET_FIELD_SP(insn, 20, 21);
1875                     if (gen_trap_ifnofpu(dc, cpu_cond))
1876                         goto jmp_insn;
1877                     target = GET_FIELD_SP(insn, 0, 18);
1878                     target = sign_extend(target, 19);
1879                     target <<= 2;
1880                     do_fbranch(dc, target, insn, cc, cpu_cond);
1881                     goto jmp_insn;
1882                 }
1883 #else
1884             case 0x7:           /* CBN+x */
1885                 {
1886                     goto ncp_insn;
1887                 }
1888 #endif
1889             case 0x2:           /* BN+x */
1890                 {
1891                     target = GET_FIELD(insn, 10, 31);
1892                     target = sign_extend(target, 22);
1893                     target <<= 2;
1894                     do_branch(dc, target, insn, 0, cpu_cond);
1895                     goto jmp_insn;
1896                 }
1897             case 0x6:           /* FBN+x */
1898                 {
1899                     if (gen_trap_ifnofpu(dc, cpu_cond))
1900                         goto jmp_insn;
1901                     target = GET_FIELD(insn, 10, 31);
1902                     target = sign_extend(target, 22);
1903                     target <<= 2;
1904                     do_fbranch(dc, target, insn, 0, cpu_cond);
1905                     goto jmp_insn;
1906                 }
1907             case 0x4:           /* SETHI */
1908 #define OPTIM
1909 #if defined(OPTIM)
1910                 if (rd) { // nop
1911 #endif
1912                     uint32_t value = GET_FIELD(insn, 10, 31);
1913                     tcg_gen_movi_tl(cpu_dst, value << 10);
1914                     gen_movl_TN_reg(rd, cpu_dst);
1915 #if defined(OPTIM)
1916                 }
1917 #endif
1918                 break;
1919             case 0x0:           /* UNIMPL */
1920             default:
1921                 goto illegal_insn;
1922             }
1923             break;
1924         }
1925         break;
1926     case 1:
1927         /*CALL*/ {
1928             target_long target = GET_FIELDs(insn, 2, 31) << 2;
1929
1930             gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
1931             target += dc->pc;
1932             gen_mov_pc_npc(dc, cpu_cond);
1933             dc->npc = target;
1934         }
1935         goto jmp_insn;
1936     case 2:                     /* FPU & Logical Operations */
1937         {
1938             unsigned int xop = GET_FIELD(insn, 7, 12);
1939             if (xop == 0x3a) {  /* generate trap */
1940                 int cond;
1941
1942                 rs1 = GET_FIELD(insn, 13, 17);
1943                 gen_movl_reg_TN(rs1, cpu_src1);
1944                 if (IS_IMM) {
1945                     rs2 = GET_FIELD(insn, 25, 31);
1946                     tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
1947                 } else {
1948                     rs2 = GET_FIELD(insn, 27, 31);
1949 #if defined(OPTIM)
1950                     if (rs2 != 0) {
1951 #endif
1952                         gen_movl_reg_TN(rs2, cpu_src2);
1953                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
1954 #if defined(OPTIM)
1955                     }
1956 #endif
1957                 }
1958                 cond = GET_FIELD(insn, 3, 6);
1959                 if (cond == 0x8) {
1960                     save_state(dc, cpu_cond);
1961                     tcg_gen_helper_0_1(helper_trap, cpu_dst);
1962                 } else if (cond != 0) {
1963                     TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
1964 #ifdef TARGET_SPARC64
1965                     /* V9 icc/xcc */
1966                     int cc = GET_FIELD_SP(insn, 11, 12);
1967
1968                     save_state(dc, cpu_cond);
1969                     if (cc == 0)
1970                         gen_cond(r_cond, 0, cond);
1971                     else if (cc == 2)
1972                         gen_cond(r_cond, 1, cond);
1973                     else
1974                         goto illegal_insn;
1975 #else
1976                     save_state(dc, cpu_cond);
1977                     gen_cond(r_cond, 0, cond);
1978 #endif
1979                     tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
1980                     tcg_gen_discard_tl(r_cond);
1981                 }
1982                 gen_op_next_insn();
1983                 tcg_gen_exit_tb(0);
1984                 dc->is_br = 1;
1985                 goto jmp_insn;
1986             } else if (xop == 0x28) {
1987                 rs1 = GET_FIELD(insn, 13, 17);
1988                 switch(rs1) {
1989                 case 0: /* rdy */
1990 #ifndef TARGET_SPARC64
1991                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1992                                        manual, rdy on the microSPARC
1993                                        II */
1994                 case 0x0f:          /* stbar in the SPARCv8 manual,
1995                                        rdy on the microSPARC II */
1996                 case 0x10 ... 0x1f: /* implementation-dependent in the
1997                                        SPARCv8 manual, rdy on the
1998                                        microSPARC II */
1999 #endif
2000                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
2001                     gen_movl_TN_reg(rd, cpu_dst);
2002                     break;
2003 #ifdef TARGET_SPARC64
2004                 case 0x2: /* V9 rdccr */
2005                     tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2006                     gen_movl_TN_reg(rd, cpu_dst);
2007                     break;
2008                 case 0x3: /* V9 rdasi */
2009                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
2010                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2011                     gen_movl_TN_reg(rd, cpu_dst);
2012                     break;
2013                 case 0x4: /* V9 rdtick */
2014                     {
2015                         TCGv r_tickptr;
2016
2017                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2018                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2019                                        offsetof(CPUState, tick));
2020                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2021                                            r_tickptr);
2022                         gen_movl_TN_reg(rd, cpu_dst);
2023                         tcg_gen_discard_ptr(r_tickptr);
2024                     }
2025                     break;
2026                 case 0x5: /* V9 rdpc */
2027                     tcg_gen_movi_tl(cpu_dst, dc->pc);
2028                     gen_movl_TN_reg(rd, cpu_dst);
2029                     break;
2030                 case 0x6: /* V9 rdfprs */
2031                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
2032                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2033                     gen_movl_TN_reg(rd, cpu_dst);
2034                     break;
2035                 case 0xf: /* V9 membar */
2036                     break; /* no effect */
2037                 case 0x13: /* Graphics Status */
2038                     if (gen_trap_ifnofpu(dc, cpu_cond))
2039                         goto jmp_insn;
2040                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
2041                     gen_movl_TN_reg(rd, cpu_dst);
2042                     break;
2043                 case 0x17: /* Tick compare */
2044                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tick_cmpr));
2045                     gen_movl_TN_reg(rd, cpu_dst);
2046                     break;
2047                 case 0x18: /* System tick */
2048                     {
2049                         TCGv r_tickptr;
2050
2051                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2052                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2053                                        offsetof(CPUState, stick));
2054                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2055                                            r_tickptr);
2056                         gen_movl_TN_reg(rd, cpu_dst);
2057                         tcg_gen_discard_ptr(r_tickptr);
2058                     }
2059                     break;
2060                 case 0x19: /* System tick compare */
2061                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, stick_cmpr));
2062                     gen_movl_TN_reg(rd, cpu_dst);
2063                     break;
2064                 case 0x10: /* Performance Control */
2065                 case 0x11: /* Performance Instrumentation Counter */
2066                 case 0x12: /* Dispatch Control */
2067                 case 0x14: /* Softint set, WO */
2068                 case 0x15: /* Softint clear, WO */
2069                 case 0x16: /* Softint write */
2070 #endif
2071                 default:
2072                     goto illegal_insn;
2073                 }
2074 #if !defined(CONFIG_USER_ONLY)
2075             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2076 #ifndef TARGET_SPARC64
2077                 if (!supervisor(dc))
2078                     goto priv_insn;
2079                 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2080 #else
2081                 if (!hypervisor(dc))
2082                     goto priv_insn;
2083                 rs1 = GET_FIELD(insn, 13, 17);
2084                 switch (rs1) {
2085                 case 0: // hpstate
2086                     // gen_op_rdhpstate();
2087                     break;
2088                 case 1: // htstate
2089                     // gen_op_rdhtstate();
2090                     break;
2091                 case 3: // hintp
2092                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
2093                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2094                     break;
2095                 case 5: // htba
2096                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
2097                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2098                     break;
2099                 case 6: // hver
2100                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver));
2101                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2102                     break;
2103                 case 31: // hstick_cmpr
2104                     tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2105                     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr));
2106                     break;
2107                 default:
2108                     goto illegal_insn;
2109                 }
2110 #endif
2111                 gen_movl_TN_reg(rd, cpu_dst);
2112                 break;
2113             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2114                 if (!supervisor(dc))
2115                     goto priv_insn;
2116 #ifdef TARGET_SPARC64
2117                 rs1 = GET_FIELD(insn, 13, 17);
2118                 switch (rs1) {
2119                 case 0: // tpc
2120                     {
2121                         TCGv r_tsptr;
2122
2123                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2124                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2125                                        offsetof(CPUState, tsptr));
2126                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2127                                       offsetof(trap_state, tpc));
2128                         tcg_gen_discard_ptr(r_tsptr);
2129                     }
2130                     break;
2131                 case 1: // tnpc
2132                     {
2133                         TCGv r_tsptr;
2134
2135                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2136                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2137                                        offsetof(CPUState, tsptr));
2138                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2139                                       offsetof(trap_state, tnpc));
2140                         tcg_gen_discard_ptr(r_tsptr);
2141                     }
2142                     break;
2143                 case 2: // tstate
2144                     {
2145                         TCGv r_tsptr;
2146
2147                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2148                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2149                                        offsetof(CPUState, tsptr));
2150                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2151                                       offsetof(trap_state, tstate));
2152                         tcg_gen_discard_ptr(r_tsptr);
2153                     }
2154                     break;
2155                 case 3: // tt
2156                     {
2157                         TCGv r_tsptr;
2158
2159                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2160                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2161                                        offsetof(CPUState, tsptr));
2162                         tcg_gen_ld_i32(cpu_dst, r_tsptr,
2163                                        offsetof(trap_state, tt));
2164                         tcg_gen_discard_ptr(r_tsptr);
2165                     }
2166                     break;
2167                 case 4: // tick
2168                     {
2169                         TCGv r_tickptr;
2170
2171                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2172                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2173                                        offsetof(CPUState, tick));
2174                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2175                                            r_tickptr);
2176                         gen_movl_TN_reg(rd, cpu_dst);
2177                         tcg_gen_discard_ptr(r_tickptr);
2178                     }
2179                     break;
2180                 case 5: // tba
2181                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2182                     break;
2183                 case 6: // pstate
2184                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate));
2185                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2186                     break;
2187                 case 7: // tl
2188                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
2189                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2190                     break;
2191                 case 8: // pil
2192                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
2193                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2194                     break;
2195                 case 9: // cwp
2196                     tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
2197                     break;
2198                 case 10: // cansave
2199                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
2200                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2201                     break;
2202                 case 11: // canrestore
2203                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
2204                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2205                     break;
2206                 case 12: // cleanwin
2207                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
2208                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2209                     break;
2210                 case 13: // otherwin
2211                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
2212                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2213                     break;
2214                 case 14: // wstate
2215                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
2216                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2217                     break;
2218                 case 16: // UA2005 gl
2219                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
2220                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2221                     break;
2222                 case 26: // UA2005 strand status
2223                     if (!hypervisor(dc))
2224                         goto priv_insn;
2225                     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
2226                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2227                     break;
2228                 case 31: // ver
2229                     tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, version));
2230                     break;
2231                 case 15: // fq
2232                 default:
2233                     goto illegal_insn;
2234                 }
2235 #else
2236                 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
2237                 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2238 #endif
2239                 gen_movl_TN_reg(rd, cpu_dst);
2240                 break;
2241             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2242 #ifdef TARGET_SPARC64
2243                 tcg_gen_helper_0_0(helper_flushw);
2244 #else
2245                 if (!supervisor(dc))
2246                     goto priv_insn;
2247                 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2248                 gen_movl_TN_reg(rd, cpu_dst);
2249 #endif
2250                 break;
2251 #endif
2252             } else if (xop == 0x34) {   /* FPU Operations */
2253                 if (gen_trap_ifnofpu(dc, cpu_cond))
2254                     goto jmp_insn;
2255                 gen_op_clear_ieee_excp_and_FTT();
2256                 rs1 = GET_FIELD(insn, 13, 17);
2257                 rs2 = GET_FIELD(insn, 27, 31);
2258                 xop = GET_FIELD(insn, 18, 26);
2259                 switch (xop) {
2260                     case 0x1: /* fmovs */
2261                         gen_op_load_fpr_FT0(rs2);
2262                         gen_op_store_FT0_fpr(rd);
2263                         break;
2264                     case 0x5: /* fnegs */
2265                         gen_op_load_fpr_FT1(rs2);
2266                         tcg_gen_helper_0_0(helper_fnegs);
2267                         gen_op_store_FT0_fpr(rd);
2268                         break;
2269                     case 0x9: /* fabss */
2270                         gen_op_load_fpr_FT1(rs2);
2271                         tcg_gen_helper_0_0(helper_fabss);
2272                         gen_op_store_FT0_fpr(rd);
2273                         break;
2274                     case 0x29: /* fsqrts */
2275                         gen_op_load_fpr_FT1(rs2);
2276                         gen_clear_float_exceptions();
2277                         tcg_gen_helper_0_0(helper_fsqrts);
2278                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2279                         gen_op_store_FT0_fpr(rd);
2280                         break;
2281                     case 0x2a: /* fsqrtd */
2282                         gen_op_load_fpr_DT1(DFPREG(rs2));
2283                         gen_clear_float_exceptions();
2284                         tcg_gen_helper_0_0(helper_fsqrtd);
2285                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2286                         gen_op_store_DT0_fpr(DFPREG(rd));
2287                         break;
2288                     case 0x2b: /* fsqrtq */
2289 #if defined(CONFIG_USER_ONLY)
2290                         gen_op_load_fpr_QT1(QFPREG(rs2));
2291                         gen_clear_float_exceptions();
2292                         tcg_gen_helper_0_0(helper_fsqrtq);
2293                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2294                         gen_op_store_QT0_fpr(QFPREG(rd));
2295                         break;
2296 #else
2297                         goto nfpu_insn;
2298 #endif
2299                     case 0x41:
2300                         gen_op_load_fpr_FT0(rs1);
2301                         gen_op_load_fpr_FT1(rs2);
2302                         gen_clear_float_exceptions();
2303                         tcg_gen_helper_0_0(helper_fadds);
2304                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2305                         gen_op_store_FT0_fpr(rd);
2306                         break;
2307                     case 0x42:
2308                         gen_op_load_fpr_DT0(DFPREG(rs1));
2309                         gen_op_load_fpr_DT1(DFPREG(rs2));
2310                         gen_clear_float_exceptions();
2311                         tcg_gen_helper_0_0(helper_faddd);
2312                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2313                         gen_op_store_DT0_fpr(DFPREG(rd));
2314                         break;
2315                     case 0x43: /* faddq */
2316 #if defined(CONFIG_USER_ONLY)
2317                         gen_op_load_fpr_QT0(QFPREG(rs1));
2318                         gen_op_load_fpr_QT1(QFPREG(rs2));
2319                         gen_clear_float_exceptions();
2320                         tcg_gen_helper_0_0(helper_faddq);
2321                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2322                         gen_op_store_QT0_fpr(QFPREG(rd));
2323                         break;
2324 #else
2325                         goto nfpu_insn;
2326 #endif
2327                     case 0x45:
2328                         gen_op_load_fpr_FT0(rs1);
2329                         gen_op_load_fpr_FT1(rs2);
2330                         gen_clear_float_exceptions();
2331                         tcg_gen_helper_0_0(helper_fsubs);
2332                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2333                         gen_op_store_FT0_fpr(rd);
2334                         break;
2335                     case 0x46:
2336                         gen_op_load_fpr_DT0(DFPREG(rs1));
2337                         gen_op_load_fpr_DT1(DFPREG(rs2));
2338                         gen_clear_float_exceptions();
2339                         tcg_gen_helper_0_0(helper_fsubd);
2340                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2341                         gen_op_store_DT0_fpr(DFPREG(rd));
2342                         break;
2343                     case 0x47: /* fsubq */
2344 #if defined(CONFIG_USER_ONLY)
2345                         gen_op_load_fpr_QT0(QFPREG(rs1));
2346                         gen_op_load_fpr_QT1(QFPREG(rs2));
2347                         gen_clear_float_exceptions();
2348                         tcg_gen_helper_0_0(helper_fsubq);
2349                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2350                         gen_op_store_QT0_fpr(QFPREG(rd));
2351                         break;
2352 #else
2353                         goto nfpu_insn;
2354 #endif
2355                     case 0x49:
2356                         gen_op_load_fpr_FT0(rs1);
2357                         gen_op_load_fpr_FT1(rs2);
2358                         gen_clear_float_exceptions();
2359                         tcg_gen_helper_0_0(helper_fmuls);
2360                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2361                         gen_op_store_FT0_fpr(rd);
2362                         break;
2363                     case 0x4a:
2364                         gen_op_load_fpr_DT0(DFPREG(rs1));
2365                         gen_op_load_fpr_DT1(DFPREG(rs2));
2366                         gen_clear_float_exceptions();
2367                         tcg_gen_helper_0_0(helper_fmuld);
2368                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2369                         gen_op_store_DT0_fpr(DFPREG(rd));
2370                         break;
2371                     case 0x4b: /* fmulq */
2372 #if defined(CONFIG_USER_ONLY)
2373                         gen_op_load_fpr_QT0(QFPREG(rs1));
2374                         gen_op_load_fpr_QT1(QFPREG(rs2));
2375                         gen_clear_float_exceptions();
2376                         tcg_gen_helper_0_0(helper_fmulq);
2377                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2378                         gen_op_store_QT0_fpr(QFPREG(rd));
2379                         break;
2380 #else
2381                         goto nfpu_insn;
2382 #endif
2383                     case 0x4d:
2384                         gen_op_load_fpr_FT0(rs1);
2385                         gen_op_load_fpr_FT1(rs2);
2386                         gen_clear_float_exceptions();
2387                         tcg_gen_helper_0_0(helper_fdivs);
2388                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2389                         gen_op_store_FT0_fpr(rd);
2390                         break;
2391                     case 0x4e:
2392                         gen_op_load_fpr_DT0(DFPREG(rs1));
2393                         gen_op_load_fpr_DT1(DFPREG(rs2));
2394                         gen_clear_float_exceptions();
2395                         tcg_gen_helper_0_0(helper_fdivd);
2396                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2397                         gen_op_store_DT0_fpr(DFPREG(rd));
2398                         break;
2399                     case 0x4f: /* fdivq */
2400 #if defined(CONFIG_USER_ONLY)
2401                         gen_op_load_fpr_QT0(QFPREG(rs1));
2402                         gen_op_load_fpr_QT1(QFPREG(rs2));
2403                         gen_clear_float_exceptions();
2404                         tcg_gen_helper_0_0(helper_fdivq);
2405                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2406                         gen_op_store_QT0_fpr(QFPREG(rd));
2407                         break;
2408 #else
2409                         goto nfpu_insn;
2410 #endif
2411                     case 0x69:
2412                         gen_op_load_fpr_FT0(rs1);
2413                         gen_op_load_fpr_FT1(rs2);
2414                         gen_clear_float_exceptions();
2415                         tcg_gen_helper_0_0(helper_fsmuld);
2416                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2417                         gen_op_store_DT0_fpr(DFPREG(rd));
2418                         break;
2419                     case 0x6e: /* fdmulq */
2420 #if defined(CONFIG_USER_ONLY)
2421                         gen_op_load_fpr_DT0(DFPREG(rs1));
2422                         gen_op_load_fpr_DT1(DFPREG(rs2));
2423                         gen_clear_float_exceptions();
2424                         tcg_gen_helper_0_0(helper_fdmulq);
2425                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2426                         gen_op_store_QT0_fpr(QFPREG(rd));
2427                         break;
2428 #else
2429                         goto nfpu_insn;
2430 #endif
2431                     case 0xc4:
2432                         gen_op_load_fpr_FT1(rs2);
2433                         gen_clear_float_exceptions();
2434                         tcg_gen_helper_0_0(helper_fitos);
2435                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2436                         gen_op_store_FT0_fpr(rd);
2437                         break;
2438                     case 0xc6:
2439                         gen_op_load_fpr_DT1(DFPREG(rs2));
2440                         gen_clear_float_exceptions();
2441                         tcg_gen_helper_0_0(helper_fdtos);
2442                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2443                         gen_op_store_FT0_fpr(rd);
2444                         break;
2445                     case 0xc7: /* fqtos */
2446 #if defined(CONFIG_USER_ONLY)
2447                         gen_op_load_fpr_QT1(QFPREG(rs2));
2448                         gen_clear_float_exceptions();
2449                         tcg_gen_helper_0_0(helper_fqtos);
2450                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2451                         gen_op_store_FT0_fpr(rd);
2452                         break;
2453 #else
2454                         goto nfpu_insn;
2455 #endif
2456                     case 0xc8:
2457                         gen_op_load_fpr_FT1(rs2);
2458                         tcg_gen_helper_0_0(helper_fitod);
2459                         gen_op_store_DT0_fpr(DFPREG(rd));
2460                         break;
2461                     case 0xc9:
2462                         gen_op_load_fpr_FT1(rs2);
2463                         tcg_gen_helper_0_0(helper_fstod);
2464                         gen_op_store_DT0_fpr(DFPREG(rd));
2465                         break;
2466                     case 0xcb: /* fqtod */
2467 #if defined(CONFIG_USER_ONLY)
2468                         gen_op_load_fpr_QT1(QFPREG(rs2));
2469                         gen_clear_float_exceptions();
2470                         tcg_gen_helper_0_0(helper_fqtod);
2471                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2472                         gen_op_store_DT0_fpr(DFPREG(rd));
2473                         break;
2474 #else
2475                         goto nfpu_insn;
2476 #endif
2477                     case 0xcc: /* fitoq */
2478 #if defined(CONFIG_USER_ONLY)
2479                         gen_op_load_fpr_FT1(rs2);
2480                         tcg_gen_helper_0_0(helper_fitoq);
2481                         gen_op_store_QT0_fpr(QFPREG(rd));
2482                         break;
2483 #else
2484                         goto nfpu_insn;
2485 #endif
2486                     case 0xcd: /* fstoq */
2487 #if defined(CONFIG_USER_ONLY)
2488                         gen_op_load_fpr_FT1(rs2);
2489                         tcg_gen_helper_0_0(helper_fstoq);
2490                         gen_op_store_QT0_fpr(QFPREG(rd));
2491                         break;
2492 #else
2493                         goto nfpu_insn;
2494 #endif
2495                     case 0xce: /* fdtoq */
2496 #if defined(CONFIG_USER_ONLY)
2497                         gen_op_load_fpr_DT1(DFPREG(rs2));
2498                         tcg_gen_helper_0_0(helper_fdtoq);
2499                         gen_op_store_QT0_fpr(QFPREG(rd));
2500                         break;
2501 #else
2502                         goto nfpu_insn;
2503 #endif
2504                     case 0xd1:
2505                         gen_op_load_fpr_FT1(rs2);
2506                         gen_clear_float_exceptions();
2507                         tcg_gen_helper_0_0(helper_fstoi);
2508                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2509                         gen_op_store_FT0_fpr(rd);
2510                         break;
2511                     case 0xd2:
2512                         gen_op_load_fpr_DT1(DFPREG(rs2));
2513                         gen_clear_float_exceptions();
2514                         tcg_gen_helper_0_0(helper_fdtoi);
2515                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2516                         gen_op_store_FT0_fpr(rd);
2517                         break;
2518                     case 0xd3: /* fqtoi */
2519 #if defined(CONFIG_USER_ONLY)
2520                         gen_op_load_fpr_QT1(QFPREG(rs2));
2521                         gen_clear_float_exceptions();
2522                         tcg_gen_helper_0_0(helper_fqtoi);
2523                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2524                         gen_op_store_FT0_fpr(rd);
2525                         break;
2526 #else
2527                         goto nfpu_insn;
2528 #endif
2529 #ifdef TARGET_SPARC64
2530                     case 0x2: /* V9 fmovd */
2531                         gen_op_load_fpr_DT0(DFPREG(rs2));
2532                         gen_op_store_DT0_fpr(DFPREG(rd));
2533                         break;
2534                     case 0x3: /* V9 fmovq */
2535 #if defined(CONFIG_USER_ONLY)
2536                         gen_op_load_fpr_QT0(QFPREG(rs2));
2537                         gen_op_store_QT0_fpr(QFPREG(rd));
2538                         break;
2539 #else
2540                         goto nfpu_insn;
2541 #endif
2542                     case 0x6: /* V9 fnegd */
2543                         gen_op_load_fpr_DT1(DFPREG(rs2));
2544                         tcg_gen_helper_0_0(helper_fnegd);
2545                         gen_op_store_DT0_fpr(DFPREG(rd));
2546                         break;
2547                     case 0x7: /* V9 fnegq */
2548 #if defined(CONFIG_USER_ONLY)
2549                         gen_op_load_fpr_QT1(QFPREG(rs2));
2550                         tcg_gen_helper_0_0(helper_fnegq);
2551                         gen_op_store_QT0_fpr(QFPREG(rd));
2552                         break;
2553 #else
2554                         goto nfpu_insn;
2555 #endif
2556                     case 0xa: /* V9 fabsd */
2557                         gen_op_load_fpr_DT1(DFPREG(rs2));
2558                         tcg_gen_helper_0_0(helper_fabsd);
2559                         gen_op_store_DT0_fpr(DFPREG(rd));
2560                         break;
2561                     case 0xb: /* V9 fabsq */
2562 #if defined(CONFIG_USER_ONLY)
2563                         gen_op_load_fpr_QT1(QFPREG(rs2));
2564                         tcg_gen_helper_0_0(helper_fabsq);
2565                         gen_op_store_QT0_fpr(QFPREG(rd));
2566                         break;
2567 #else
2568                         goto nfpu_insn;
2569 #endif
2570                     case 0x81: /* V9 fstox */
2571                         gen_op_load_fpr_FT1(rs2);
2572                         gen_clear_float_exceptions();
2573                         tcg_gen_helper_0_0(helper_fstox);
2574                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2575                         gen_op_store_DT0_fpr(DFPREG(rd));
2576                         break;
2577                     case 0x82: /* V9 fdtox */
2578                         gen_op_load_fpr_DT1(DFPREG(rs2));
2579                         gen_clear_float_exceptions();
2580                         tcg_gen_helper_0_0(helper_fdtox);
2581                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2582                         gen_op_store_DT0_fpr(DFPREG(rd));
2583                         break;
2584                     case 0x83: /* V9 fqtox */
2585 #if defined(CONFIG_USER_ONLY)
2586                         gen_op_load_fpr_QT1(QFPREG(rs2));
2587                         gen_clear_float_exceptions();
2588                         tcg_gen_helper_0_0(helper_fqtox);
2589                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2590                         gen_op_store_DT0_fpr(DFPREG(rd));
2591                         break;
2592 #else
2593                         goto nfpu_insn;
2594 #endif
2595                     case 0x84: /* V9 fxtos */
2596                         gen_op_load_fpr_DT1(DFPREG(rs2));
2597                         gen_clear_float_exceptions();
2598                         tcg_gen_helper_0_0(helper_fxtos);
2599                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2600                         gen_op_store_FT0_fpr(rd);
2601                         break;
2602                     case 0x88: /* V9 fxtod */
2603                         gen_op_load_fpr_DT1(DFPREG(rs2));
2604                         gen_clear_float_exceptions();
2605                         tcg_gen_helper_0_0(helper_fxtod);
2606                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2607                         gen_op_store_DT0_fpr(DFPREG(rd));
2608                         break;
2609                     case 0x8c: /* V9 fxtoq */
2610 #if defined(CONFIG_USER_ONLY)
2611                         gen_op_load_fpr_DT1(DFPREG(rs2));
2612                         gen_clear_float_exceptions();
2613                         tcg_gen_helper_0_0(helper_fxtoq);
2614                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2615                         gen_op_store_QT0_fpr(QFPREG(rd));
2616                         break;
2617 #else
2618                         goto nfpu_insn;
2619 #endif
2620 #endif
2621                     default:
2622                         goto illegal_insn;
2623                 }
2624             } else if (xop == 0x35) {   /* FPU Operations */
2625 #ifdef TARGET_SPARC64
2626                 int cond;
2627 #endif
2628                 if (gen_trap_ifnofpu(dc, cpu_cond))
2629                     goto jmp_insn;
2630                 gen_op_clear_ieee_excp_and_FTT();
2631                 rs1 = GET_FIELD(insn, 13, 17);
2632                 rs2 = GET_FIELD(insn, 27, 31);
2633                 xop = GET_FIELD(insn, 18, 26);
2634 #ifdef TARGET_SPARC64
2635                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2636                     int l1;
2637
2638                     l1 = gen_new_label();
2639                     cond = GET_FIELD_SP(insn, 14, 17);
2640                     rs1 = GET_FIELD(insn, 13, 17);
2641                     gen_movl_reg_TN(rs1, cpu_src1);
2642                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2643                                       tcg_const_tl(0), l1);
2644                     gen_op_load_fpr_FT0(rs2);
2645                     gen_op_store_FT0_fpr(rd);
2646                     gen_set_label(l1);
2647                     break;
2648                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2649                     int l1;
2650
2651                     l1 = gen_new_label();
2652                     cond = GET_FIELD_SP(insn, 14, 17);
2653                     rs1 = GET_FIELD(insn, 13, 17);
2654                     gen_movl_reg_TN(rs1, cpu_src1);
2655                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2656                                       tcg_const_tl(0), l1);
2657                     gen_op_load_fpr_DT0(DFPREG(rs2));
2658                     gen_op_store_DT0_fpr(DFPREG(rd));
2659                     gen_set_label(l1);
2660                     break;
2661                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2662 #if defined(CONFIG_USER_ONLY)
2663                     int l1;
2664
2665                     l1 = gen_new_label();
2666                     cond = GET_FIELD_SP(insn, 14, 17);
2667                     rs1 = GET_FIELD(insn, 13, 17);
2668                     gen_movl_reg_TN(rs1, cpu_src1);
2669                     tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2670                                       tcg_const_tl(0), l1);
2671                     gen_op_load_fpr_QT0(QFPREG(rs2));
2672                     gen_op_store_QT0_fpr(QFPREG(rd));
2673                     gen_set_label(l1);
2674                     break;
2675 #else
2676                     goto nfpu_insn;
2677 #endif
2678                 }
2679 #endif
2680                 switch (xop) {
2681 #ifdef TARGET_SPARC64
2682 #define FMOVCC(size_FDQ, fcc)                                           \
2683                     {                                                   \
2684                         TCGv r_cond;                                    \
2685                         int l1;                                         \
2686                                                                         \
2687                         l1 = gen_new_label();                           \
2688                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2689                         cond = GET_FIELD_SP(insn, 14, 17);              \
2690                         gen_fcond(r_cond, fcc, cond);                   \
2691                         tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,          \
2692                                           tcg_const_tl(0), l1);         \
2693                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2694                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2695                         gen_set_label(l1);                              \
2696                         tcg_gen_discard_tl(r_cond);                     \
2697                     }
2698                     case 0x001: /* V9 fmovscc %fcc0 */
2699                         FMOVCC(F, 0);
2700                         break;
2701                     case 0x002: /* V9 fmovdcc %fcc0 */
2702                         FMOVCC(D, 0);
2703                         break;
2704                     case 0x003: /* V9 fmovqcc %fcc0 */
2705 #if defined(CONFIG_USER_ONLY)
2706                         FMOVCC(Q, 0);
2707                         break;
2708 #else
2709                         goto nfpu_insn;
2710 #endif
2711                     case 0x041: /* V9 fmovscc %fcc1 */
2712                         FMOVCC(F, 1);
2713                         break;
2714                     case 0x042: /* V9 fmovdcc %fcc1 */
2715                         FMOVCC(D, 1);
2716                         break;
2717                     case 0x043: /* V9 fmovqcc %fcc1 */
2718 #if defined(CONFIG_USER_ONLY)
2719                         FMOVCC(Q, 1);
2720                         break;
2721 #else
2722                         goto nfpu_insn;
2723 #endif
2724                     case 0x081: /* V9 fmovscc %fcc2 */
2725                         FMOVCC(F, 2);
2726                         break;
2727                     case 0x082: /* V9 fmovdcc %fcc2 */
2728                         FMOVCC(D, 2);
2729                         break;
2730                     case 0x083: /* V9 fmovqcc %fcc2 */
2731 #if defined(CONFIG_USER_ONLY)
2732                         FMOVCC(Q, 2);
2733                         break;
2734 #else
2735                         goto nfpu_insn;
2736 #endif
2737                     case 0x0c1: /* V9 fmovscc %fcc3 */
2738                         FMOVCC(F, 3);
2739                         break;
2740                     case 0x0c2: /* V9 fmovdcc %fcc3 */
2741                         FMOVCC(D, 3);
2742                         break;
2743                     case 0x0c3: /* V9 fmovqcc %fcc3 */
2744 #if defined(CONFIG_USER_ONLY)
2745                         FMOVCC(Q, 3);
2746                         break;
2747 #else
2748                         goto nfpu_insn;
2749 #endif
2750 #undef FMOVCC
2751 #define FMOVCC(size_FDQ, icc)                                           \
2752                     {                                                   \
2753                         TCGv r_cond;                                    \
2754                         int l1;                                         \
2755                                                                         \
2756                         l1 = gen_new_label();                           \
2757                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2758                         cond = GET_FIELD_SP(insn, 14, 17);              \
2759                         gen_cond(r_cond, icc, cond);                    \
2760                         tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,          \
2761                                           tcg_const_tl(0), l1);         \
2762                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2763                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2764                         gen_set_label(l1);                              \
2765                         tcg_gen_discard_tl(r_cond);                     \
2766                     }
2767
2768                     case 0x101: /* V9 fmovscc %icc */
2769                         FMOVCC(F, 0);
2770                         break;
2771                     case 0x102: /* V9 fmovdcc %icc */
2772                         FMOVCC(D, 0);
2773                     case 0x103: /* V9 fmovqcc %icc */
2774 #if defined(CONFIG_USER_ONLY)
2775                         FMOVCC(D, 0);
2776                         break;
2777 #else
2778                         goto nfpu_insn;
2779 #endif
2780                     case 0x181: /* V9 fmovscc %xcc */
2781                         FMOVCC(F, 1);
2782                         break;
2783                     case 0x182: /* V9 fmovdcc %xcc */
2784                         FMOVCC(D, 1);
2785                         break;
2786                     case 0x183: /* V9 fmovqcc %xcc */
2787 #if defined(CONFIG_USER_ONLY)
2788                         FMOVCC(Q, 1);
2789                         break;
2790 #else
2791                         goto nfpu_insn;
2792 #endif
2793 #undef FMOVCC
2794 #endif
2795                     case 0x51: /* fcmps, V9 %fcc */
2796                         gen_op_load_fpr_FT0(rs1);
2797                         gen_op_load_fpr_FT1(rs2);
2798                         gen_op_fcmps(rd & 3);
2799                         break;
2800                     case 0x52: /* fcmpd, V9 %fcc */
2801                         gen_op_load_fpr_DT0(DFPREG(rs1));
2802                         gen_op_load_fpr_DT1(DFPREG(rs2));
2803                         gen_op_fcmpd(rd & 3);
2804                         break;
2805                     case 0x53: /* fcmpq, V9 %fcc */
2806 #if defined(CONFIG_USER_ONLY)
2807                         gen_op_load_fpr_QT0(QFPREG(rs1));
2808                         gen_op_load_fpr_QT1(QFPREG(rs2));
2809                         gen_op_fcmpq(rd & 3);
2810                         break;
2811 #else /* !defined(CONFIG_USER_ONLY) */
2812                         goto nfpu_insn;
2813 #endif
2814                     case 0x55: /* fcmpes, V9 %fcc */
2815                         gen_op_load_fpr_FT0(rs1);
2816                         gen_op_load_fpr_FT1(rs2);
2817                         gen_op_fcmpes(rd & 3);
2818                         break;
2819                     case 0x56: /* fcmped, V9 %fcc */
2820                         gen_op_load_fpr_DT0(DFPREG(rs1));
2821                         gen_op_load_fpr_DT1(DFPREG(rs2));
2822                         gen_op_fcmped(rd & 3);
2823                         break;
2824                     case 0x57: /* fcmpeq, V9 %fcc */
2825 #if defined(CONFIG_USER_ONLY)
2826                         gen_op_load_fpr_QT0(QFPREG(rs1));
2827                         gen_op_load_fpr_QT1(QFPREG(rs2));
2828                         gen_op_fcmpeq(rd & 3);
2829                         break;
2830 #else/* !defined(CONFIG_USER_ONLY) */
2831                         goto nfpu_insn;
2832 #endif
2833                     default:
2834                         goto illegal_insn;
2835                 }
2836 #if defined(OPTIM)
2837             } else if (xop == 0x2) {
2838                 // clr/mov shortcut
2839
2840                 rs1 = GET_FIELD(insn, 13, 17);
2841                 if (rs1 == 0) {
2842                     // or %g0, x, y -> mov T0, x; mov y, T0
2843                     if (IS_IMM) {       /* immediate */
2844                         rs2 = GET_FIELDs(insn, 19, 31);
2845                         tcg_gen_movi_tl(cpu_dst, (int)rs2);
2846                     } else {            /* register */
2847                         rs2 = GET_FIELD(insn, 27, 31);
2848                         gen_movl_reg_TN(rs2, cpu_dst);
2849                     }
2850                 } else {
2851                     gen_movl_reg_TN(rs1, cpu_src1);
2852                     if (IS_IMM) {       /* immediate */
2853                         rs2 = GET_FIELDs(insn, 19, 31);
2854                         tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2855                     } else {            /* register */
2856                         // or x, %g0, y -> mov T1, x; mov y, T1
2857                         rs2 = GET_FIELD(insn, 27, 31);
2858                         if (rs2 != 0) {
2859                             gen_movl_reg_TN(rs2, cpu_src2);
2860                             tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2861                         }
2862                     }
2863                 }
2864                 gen_movl_TN_reg(rd, cpu_dst);
2865 #endif
2866 #ifdef TARGET_SPARC64
2867             } else if (xop == 0x25) { /* sll, V9 sllx */
2868                 rs1 = GET_FIELD(insn, 13, 17);
2869                 gen_movl_reg_TN(rs1, cpu_src1);
2870                 if (IS_IMM) {   /* immediate */
2871                     rs2 = GET_FIELDs(insn, 20, 31);
2872                     if (insn & (1 << 12)) {
2873                         tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2874                     } else {
2875                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2876                         tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2877                     }
2878                 } else {                /* register */
2879                     rs2 = GET_FIELD(insn, 27, 31);
2880                     gen_movl_reg_TN(rs2, cpu_src2);
2881                     if (insn & (1 << 12)) {
2882                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2883                         tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2884                     } else {
2885                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2886                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2887                         tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2888                     }
2889                 }
2890                 gen_movl_TN_reg(rd, cpu_dst);
2891             } else if (xop == 0x26) { /* srl, V9 srlx */
2892                 rs1 = GET_FIELD(insn, 13, 17);
2893                 gen_movl_reg_TN(rs1, cpu_src1);
2894                 if (IS_IMM) {   /* immediate */
2895                     rs2 = GET_FIELDs(insn, 20, 31);
2896                     if (insn & (1 << 12)) {
2897                         tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2898                     } else {
2899                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2900                         tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2901                     }
2902                 } else {                /* register */
2903                     rs2 = GET_FIELD(insn, 27, 31);
2904                     gen_movl_reg_TN(rs2, cpu_src2);
2905                     if (insn & (1 << 12)) {
2906                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2907                         tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2908                     } else {
2909                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2910                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2911                         tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2912                     }
2913                 }
2914                 gen_movl_TN_reg(rd, cpu_dst);
2915             } else if (xop == 0x27) { /* sra, V9 srax */
2916                 rs1 = GET_FIELD(insn, 13, 17);
2917                 gen_movl_reg_TN(rs1, cpu_src1);
2918                 if (IS_IMM) {   /* immediate */
2919                     rs2 = GET_FIELDs(insn, 20, 31);
2920                     if (insn & (1 << 12)) {
2921                         tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2922                     } else {
2923                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2924                         tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2925                         tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2926                     }
2927                 } else {                /* register */
2928                     rs2 = GET_FIELD(insn, 27, 31);
2929                     gen_movl_reg_TN(rs2, cpu_src2);
2930                     if (insn & (1 << 12)) {
2931                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2932                         tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2933                     } else {
2934                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2935                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2936                         tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2937                     }
2938                 }
2939                 gen_movl_TN_reg(rd, cpu_dst);
2940 #endif
2941             } else if (xop < 0x36) {
2942                 rs1 = GET_FIELD(insn, 13, 17);
2943                 gen_movl_reg_TN(rs1, cpu_src1);
2944                 if (IS_IMM) {   /* immediate */
2945                     rs2 = GET_FIELDs(insn, 19, 31);
2946                     tcg_gen_movi_tl(cpu_src2, (int)rs2);
2947                 } else {                /* register */
2948                     rs2 = GET_FIELD(insn, 27, 31);
2949                     gen_movl_reg_TN(rs2, cpu_src2);
2950                 }
2951                 if (xop < 0x20) {
2952                     switch (xop & ~0x10) {
2953                     case 0x0:
2954                         if (xop & 0x10)
2955                             gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2956                         else
2957                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2958                         break;
2959                     case 0x1:
2960                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2961                         if (xop & 0x10)
2962                             gen_op_logic_cc(cpu_dst);
2963                         break;
2964                     case 0x2:
2965                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2966                         if (xop & 0x10)
2967                             gen_op_logic_cc(cpu_dst);
2968                         break;
2969                     case 0x3:
2970                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
2971                         if (xop & 0x10)
2972                             gen_op_logic_cc(cpu_dst);
2973                         break;
2974                     case 0x4:
2975                         if (xop & 0x10)
2976                             gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
2977                         else
2978                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
2979                         break;
2980                     case 0x5:
2981                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2982                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
2983                         if (xop & 0x10)
2984                             gen_op_logic_cc(cpu_dst);
2985                         break;
2986                     case 0x6:
2987                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2988                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
2989                         if (xop & 0x10)
2990                             gen_op_logic_cc(cpu_dst);
2991                         break;
2992                     case 0x7:
2993                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2994                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
2995                         if (xop & 0x10)
2996                             gen_op_logic_cc(cpu_dst);
2997                         break;
2998                     case 0x8:
2999                         if (xop & 0x10)
3000                             gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3001                         else {
3002                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3003                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3004                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3005                         }
3006                         break;
3007 #ifdef TARGET_SPARC64
3008                     case 0x9: /* V9 mulx */
3009                         tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3010                         break;
3011 #endif
3012                     case 0xa:
3013                         gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3014                         if (xop & 0x10)
3015                             gen_op_logic_cc(cpu_dst);
3016                         break;
3017                     case 0xb:
3018                         gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3019                         if (xop & 0x10)
3020                             gen_op_logic_cc(cpu_dst);
3021                         break;
3022                     case 0xc:
3023                         if (xop & 0x10)
3024                             gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3025                         else {
3026                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3027                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3028                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3029                         }
3030                         break;
3031 #ifdef TARGET_SPARC64
3032                     case 0xd: /* V9 udivx */
3033                         gen_trap_ifdivzero_tl(cpu_src2);
3034                         tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2);
3035                         break;
3036 #endif
3037                     case 0xe:
3038                         tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, cpu_src2);
3039                         if (xop & 0x10)
3040                             gen_op_div_cc(cpu_dst);
3041                         break;
3042                     case 0xf:
3043                         tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, cpu_src2);
3044                         if (xop & 0x10)
3045                             gen_op_div_cc(cpu_dst);
3046                         break;
3047                     default:
3048                         goto illegal_insn;
3049                     }
3050                     gen_movl_TN_reg(rd, cpu_dst);
3051                 } else {
3052                     switch (xop) {
3053                     case 0x20: /* taddcc */
3054                         gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3055                         gen_movl_TN_reg(rd, cpu_dst);
3056                         break;
3057                     case 0x21: /* tsubcc */
3058                         gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3059                         gen_movl_TN_reg(rd, cpu_dst);
3060                         break;
3061                     case 0x22: /* taddcctv */
3062                         save_state(dc, cpu_cond);
3063                         gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3064                         gen_movl_TN_reg(rd, cpu_dst);
3065                         break;
3066                     case 0x23: /* tsubcctv */
3067                         save_state(dc, cpu_cond);
3068                         gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3069                         gen_movl_TN_reg(rd, cpu_dst);
3070                         break;
3071                     case 0x24: /* mulscc */
3072                         gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3073                         gen_movl_TN_reg(rd, cpu_dst);
3074                         break;
3075 #ifndef TARGET_SPARC64
3076                     case 0x25:  /* sll */
3077                         tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3078                         tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3079                         gen_movl_TN_reg(rd, cpu_dst);
3080                         break;
3081                     case 0x26:  /* srl */
3082                         tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3083                         tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3084                         gen_movl_TN_reg(rd, cpu_dst);
3085                         break;
3086                     case 0x27:  /* sra */
3087                         tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3088                         tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3089                         gen_movl_TN_reg(rd, cpu_dst);
3090                         break;
3091 #endif
3092                     case 0x30:
3093                         {
3094                             switch(rd) {
3095                             case 0: /* wry */
3096                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3097                                 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
3098                                 break;
3099 #ifndef TARGET_SPARC64
3100                             case 0x01 ... 0x0f: /* undefined in the
3101                                                    SPARCv8 manual, nop
3102                                                    on the microSPARC
3103                                                    II */
3104                             case 0x10 ... 0x1f: /* implementation-dependent
3105                                                    in the SPARCv8
3106                                                    manual, nop on the
3107                                                    microSPARC II */
3108                                 break;
3109 #else
3110                             case 0x2: /* V9 wrccr */
3111                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3112                                 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3113                                 break;
3114                             case 0x3: /* V9 wrasi */
3115                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3116                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3117                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
3118                                 break;
3119                             case 0x6: /* V9 wrfprs */
3120                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3121                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3122                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
3123                                 save_state(dc, cpu_cond);
3124                                 gen_op_next_insn();
3125                                 tcg_gen_exit_tb(0);
3126                                 dc->is_br = 1;
3127                                 break;
3128                             case 0xf: /* V9 sir, nop if user */
3129 #if !defined(CONFIG_USER_ONLY)
3130                                 if (supervisor(dc))
3131                                     ; // XXX
3132 #endif
3133                                 break;
3134                             case 0x13: /* Graphics Status */
3135                                 if (gen_trap_ifnofpu(dc, cpu_cond))
3136                                     goto jmp_insn;
3137                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3138                                 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
3139                                 break;
3140                             case 0x17: /* Tick compare */
3141 #if !defined(CONFIG_USER_ONLY)
3142                                 if (!supervisor(dc))
3143                                     goto illegal_insn;
3144 #endif
3145                                 {
3146                                     TCGv r_tickptr;
3147
3148                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3149                                                    cpu_src2);
3150                                     tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3151                                                                  tick_cmpr));
3152                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3153                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3154                                                    offsetof(CPUState, tick));
3155                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3156                                                        r_tickptr, cpu_dst);
3157                                     tcg_gen_discard_ptr(r_tickptr);
3158                                 }
3159                                 break;
3160                             case 0x18: /* System tick */
3161 #if !defined(CONFIG_USER_ONLY)
3162                                 if (!supervisor(dc))
3163                                     goto illegal_insn;
3164 #endif
3165                                 {
3166                                     TCGv r_tickptr;
3167
3168                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3169                                                    cpu_src2);
3170                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3171                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3172                                                    offsetof(CPUState, stick));
3173                                     tcg_gen_helper_0_2(helper_tick_set_count,
3174                                                        r_tickptr, cpu_dst);
3175                                     tcg_gen_discard_ptr(r_tickptr);
3176                                 }
3177                                 break;
3178                             case 0x19: /* System tick compare */
3179 #if !defined(CONFIG_USER_ONLY)
3180                                 if (!supervisor(dc))
3181                                     goto illegal_insn;
3182 #endif
3183                                 {
3184                                     TCGv r_tickptr;
3185
3186                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3187                                                    cpu_src2);
3188                                     tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3189                                                                  stick_cmpr));
3190                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3191                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3192                                                    offsetof(CPUState, stick));
3193                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3194                                                        r_tickptr, cpu_dst);
3195                                     tcg_gen_discard_ptr(r_tickptr);
3196                                 }
3197                                 break;
3198
3199                             case 0x10: /* Performance Control */
3200                             case 0x11: /* Performance Instrumentation Counter */
3201                             case 0x12: /* Dispatch Control */
3202                             case 0x14: /* Softint set */
3203                             case 0x15: /* Softint clear */
3204                             case 0x16: /* Softint write */
3205 #endif
3206                             default:
3207                                 goto illegal_insn;
3208                             }
3209                         }
3210                         break;
3211 #if !defined(CONFIG_USER_ONLY)
3212                     case 0x31: /* wrpsr, V9 saved, restored */
3213                         {
3214                             if (!supervisor(dc))
3215                                 goto priv_insn;
3216 #ifdef TARGET_SPARC64
3217                             switch (rd) {
3218                             case 0:
3219                                 tcg_gen_helper_0_0(helper_saved);
3220                                 break;
3221                             case 1:
3222                                 tcg_gen_helper_0_0(helper_restored);
3223                                 break;
3224                             case 2: /* UA2005 allclean */
3225                             case 3: /* UA2005 otherw */
3226                             case 4: /* UA2005 normalw */
3227                             case 5: /* UA2005 invalw */
3228                                 // XXX
3229                             default:
3230                                 goto illegal_insn;
3231                             }
3232 #else
3233                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3234                             tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3235                             save_state(dc, cpu_cond);
3236                             gen_op_next_insn();
3237                             tcg_gen_exit_tb(0);
3238                             dc->is_br = 1;
3239 #endif
3240                         }
3241                         break;
3242                     case 0x32: /* wrwim, V9 wrpr */
3243                         {
3244                             if (!supervisor(dc))
3245                                 goto priv_insn;
3246                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3247 #ifdef TARGET_SPARC64
3248                             switch (rd) {
3249                             case 0: // tpc
3250                                 {
3251                                     TCGv r_tsptr;
3252
3253                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3254                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3255                                                    offsetof(CPUState, tsptr));
3256                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3257                                                   offsetof(trap_state, tpc));
3258                                     tcg_gen_discard_ptr(r_tsptr);
3259                                 }
3260                                 break;
3261                             case 1: // tnpc
3262                                 {
3263                                     TCGv r_tsptr;
3264
3265                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3266                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3267                                                    offsetof(CPUState, tsptr));
3268                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3269                                                   offsetof(trap_state, tnpc));
3270                                     tcg_gen_discard_ptr(r_tsptr);
3271                                 }
3272                                 break;
3273                             case 2: // tstate
3274                                 {
3275                                     TCGv r_tsptr;
3276
3277                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3278                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3279                                                    offsetof(CPUState, tsptr));
3280                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3281                                                   offsetof(trap_state, tstate));
3282                                     tcg_gen_discard_ptr(r_tsptr);
3283                                 }
3284                                 break;
3285                             case 3: // tt
3286                                 {
3287                                     TCGv r_tsptr;
3288
3289                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3290                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3291                                                    offsetof(CPUState, tsptr));
3292                                     tcg_gen_st_i32(cpu_dst, r_tsptr,
3293                                                    offsetof(trap_state, tt));
3294                                     tcg_gen_discard_ptr(r_tsptr);
3295                                 }
3296                                 break;
3297                             case 4: // tick
3298                                 {
3299                                     TCGv r_tickptr;
3300
3301                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3302                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3303                                                    offsetof(CPUState, tick));
3304                                     tcg_gen_helper_0_2(helper_tick_set_count,
3305                                                        r_tickptr, cpu_dst);
3306                                     tcg_gen_discard_ptr(r_tickptr);
3307                                 }
3308                                 break;
3309                             case 5: // tba
3310                                 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
3311                                 break;
3312                             case 6: // pstate
3313                                 save_state(dc, cpu_cond);
3314                                 tcg_gen_helper_0_1(helper_wrpstate, cpu_dst);
3315                                 gen_op_next_insn();
3316                                 tcg_gen_exit_tb(0);
3317                                 dc->is_br = 1;
3318                                 break;
3319                             case 7: // tl
3320                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3321                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
3322                                 break;
3323                             case 8: // pil
3324                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3325                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
3326                                 break;
3327                             case 9: // cwp
3328                                 tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
3329                                 break;
3330                             case 10: // cansave
3331                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3332                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
3333                                 break;
3334                             case 11: // canrestore
3335                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3336                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
3337                                 break;
3338                             case 12: // cleanwin
3339                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3340                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
3341                                 break;
3342                             case 13: // otherwin
3343                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3344                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
3345                                 break;
3346                             case 14: // wstate
3347                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3348                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
3349                                 break;
3350                             case 16: // UA2005 gl
3351                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3352                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
3353                                 break;
3354                             case 26: // UA2005 strand status
3355                                 if (!hypervisor(dc))
3356                                     goto priv_insn;
3357                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3358                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
3359                                 break;
3360                             default:
3361                                 goto illegal_insn;
3362                             }
3363 #else
3364                             tcg_gen_andi_tl(cpu_dst, cpu_dst, ((1 << NWINDOWS) - 1));
3365                             tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3366                             tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
3367 #endif
3368                         }
3369                         break;
3370                     case 0x33: /* wrtbr, UA2005 wrhpr */
3371                         {
3372 #ifndef TARGET_SPARC64
3373                             if (!supervisor(dc))
3374                                 goto priv_insn;
3375                             tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3376                             tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
3377 #else
3378                             if (!hypervisor(dc))
3379                                 goto priv_insn;
3380                             tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3381                             switch (rd) {
3382                             case 0: // hpstate
3383                                 // XXX gen_op_wrhpstate();
3384                                 save_state(dc, cpu_cond);
3385                                 gen_op_next_insn();
3386                                 tcg_gen_exit_tb(0);
3387                                 dc->is_br = 1;
3388                                 break;
3389                             case 1: // htstate
3390                                 // XXX gen_op_wrhtstate();
3391                                 break;
3392                             case 3: // hintp
3393                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3394                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
3395                                 break;
3396                             case 5: // htba
3397                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3398                                 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
3399                                 break;
3400                             case 31: // hstick_cmpr
3401                                 {
3402                                     TCGv r_tickptr;
3403
3404                                     tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3405                                                                  hstick_cmpr));
3406                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3407                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3408                                                    offsetof(CPUState, hstick));
3409                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3410                                                        r_tickptr, cpu_dst);
3411                                     tcg_gen_discard_ptr(r_tickptr);
3412                                 }
3413                                 break;
3414                             case 6: // hver readonly
3415                             default:
3416                                 goto illegal_insn;
3417                             }
3418 #endif
3419                         }
3420                         break;
3421 #endif
3422 #ifdef TARGET_SPARC64
3423                     case 0x2c: /* V9 movcc */
3424                         {
3425                             int cc = GET_FIELD_SP(insn, 11, 12);
3426                             int cond = GET_FIELD_SP(insn, 14, 17);
3427                             TCGv r_cond;
3428                             int l1;
3429
3430                             r_cond = tcg_temp_new(TCG_TYPE_TL);
3431                             if (insn & (1 << 18)) {
3432                                 if (cc == 0)
3433                                     gen_cond(r_cond, 0, cond);
3434                                 else if (cc == 2)
3435                                     gen_cond(r_cond, 1, cond);
3436                                 else
3437                                     goto illegal_insn;
3438                             } else {
3439                                 gen_fcond(r_cond, cc, cond);
3440                             }
3441
3442                             l1 = gen_new_label();
3443
3444                             tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,
3445                                               tcg_const_tl(0), l1);
3446                             if (IS_IMM) {       /* immediate */
3447                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
3448                                 tcg_gen_movi_tl(cpu_dst, (int)rs2);
3449                             } else {
3450                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3451                                 gen_movl_reg_TN(rs2, cpu_dst);
3452                             }
3453                             gen_movl_TN_reg(rd, cpu_dst);
3454                             gen_set_label(l1);
3455                             tcg_gen_discard_tl(r_cond);
3456                             break;
3457                         }
3458                     case 0x2d: /* V9 sdivx */
3459                         gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3460                         gen_movl_TN_reg(rd, cpu_dst);
3461                         break;
3462                     case 0x2e: /* V9 popc */
3463                         {
3464                             if (IS_IMM) {       /* immediate */
3465                                 rs2 = GET_FIELD_SPs(insn, 0, 12);
3466                                 tcg_gen_movi_tl(cpu_src2, (int)rs2);
3467                                 // XXX optimize: popc(constant)
3468                             }
3469                             else {
3470                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3471                                 gen_movl_reg_TN(rs2, cpu_src2);
3472                             }
3473                             tcg_gen_helper_1_1(helper_popc, cpu_dst,
3474                                                cpu_src2);
3475                             gen_movl_TN_reg(rd, cpu_dst);
3476                         }
3477                     case 0x2f: /* V9 movr */
3478                         {
3479                             int cond = GET_FIELD_SP(insn, 10, 12);
3480                             int l1;
3481
3482                             rs1 = GET_FIELD(insn, 13, 17);
3483                             gen_movl_reg_TN(rs1, cpu_src1);
3484
3485                             l1 = gen_new_label();
3486
3487                             tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
3488                                               tcg_const_tl(0), l1);
3489                             if (IS_IMM) {       /* immediate */
3490                                 rs2 = GET_FIELD_SPs(insn, 0, 9);
3491                                 tcg_gen_movi_tl(cpu_dst, (int)rs2);
3492                             } else {
3493                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3494                                 gen_movl_reg_TN(rs2, cpu_dst);
3495                             }
3496                             gen_movl_TN_reg(rd, cpu_dst);
3497                             gen_set_label(l1);
3498                             break;
3499                         }
3500 #endif
3501                     default:
3502                         goto illegal_insn;
3503                     }
3504                 }
3505             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3506 #ifdef TARGET_SPARC64
3507                 int opf = GET_FIELD_SP(insn, 5, 13);
3508                 rs1 = GET_FIELD(insn, 13, 17);
3509                 rs2 = GET_FIELD(insn, 27, 31);
3510                 if (gen_trap_ifnofpu(dc, cpu_cond))
3511                     goto jmp_insn;
3512
3513                 switch (opf) {
3514                 case 0x000: /* VIS I edge8cc */
3515                 case 0x001: /* VIS II edge8n */
3516                 case 0x002: /* VIS I edge8lcc */
3517                 case 0x003: /* VIS II edge8ln */
3518                 case 0x004: /* VIS I edge16cc */
3519                 case 0x005: /* VIS II edge16n */
3520                 case 0x006: /* VIS I edge16lcc */
3521                 case 0x007: /* VIS II edge16ln */
3522                 case 0x008: /* VIS I edge32cc */
3523                 case 0x009: /* VIS II edge32n */
3524                 case 0x00a: /* VIS I edge32lcc */
3525                 case 0x00b: /* VIS II edge32ln */
3526                     // XXX
3527                     goto illegal_insn;
3528                 case 0x010: /* VIS I array8 */
3529                     gen_movl_reg_TN(rs1, cpu_src1);
3530                     gen_movl_reg_TN(rs2, cpu_src2);
3531                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3532                                        cpu_src2);
3533                     gen_movl_TN_reg(rd, cpu_dst);
3534                     break;
3535                 case 0x012: /* VIS I array16 */
3536                     gen_movl_reg_TN(rs1, cpu_src1);
3537                     gen_movl_reg_TN(rs2, cpu_src2);
3538                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3539                                        cpu_src2);
3540                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3541                     gen_movl_TN_reg(rd, cpu_dst);
3542                     break;
3543                 case 0x014: /* VIS I array32 */
3544                     gen_movl_reg_TN(rs1, cpu_src1);
3545                     gen_movl_reg_TN(rs2, cpu_src2);
3546                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3547                                        cpu_src2);
3548                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3549                     gen_movl_TN_reg(rd, cpu_dst);
3550                     break;
3551                 case 0x018: /* VIS I alignaddr */
3552                     gen_movl_reg_TN(rs1, cpu_src1);
3553                     gen_movl_reg_TN(rs2, cpu_src2);
3554                     tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3555                                        cpu_src2);
3556                     gen_movl_TN_reg(rd, cpu_dst);
3557                     break;
3558                 case 0x019: /* VIS II bmask */
3559                 case 0x01a: /* VIS I alignaddrl */
3560                     // XXX
3561                     goto illegal_insn;
3562                 case 0x020: /* VIS I fcmple16 */
3563                     gen_op_load_fpr_DT0(DFPREG(rs1));
3564                     gen_op_load_fpr_DT1(DFPREG(rs2));
3565                     tcg_gen_helper_0_0(helper_fcmple16);
3566                     gen_op_store_DT0_fpr(DFPREG(rd));
3567                     break;
3568                 case 0x022: /* VIS I fcmpne16 */
3569                     gen_op_load_fpr_DT0(DFPREG(rs1));
3570                     gen_op_load_fpr_DT1(DFPREG(rs2));
3571                     tcg_gen_helper_0_0(helper_fcmpne16);
3572                     gen_op_store_DT0_fpr(DFPREG(rd));
3573                     break;
3574                 case 0x024: /* VIS I fcmple32 */
3575                     gen_op_load_fpr_DT0(DFPREG(rs1));
3576                     gen_op_load_fpr_DT1(DFPREG(rs2));
3577                     tcg_gen_helper_0_0(helper_fcmple32);
3578                     gen_op_store_DT0_fpr(DFPREG(rd));
3579                     break;
3580                 case 0x026: /* VIS I fcmpne32 */
3581                     gen_op_load_fpr_DT0(DFPREG(rs1));
3582                     gen_op_load_fpr_DT1(DFPREG(rs2));
3583                     tcg_gen_helper_0_0(helper_fcmpne32);
3584                     gen_op_store_DT0_fpr(DFPREG(rd));
3585                     break;
3586                 case 0x028: /* VIS I fcmpgt16 */
3587                     gen_op_load_fpr_DT0(DFPREG(rs1));
3588                     gen_op_load_fpr_DT1(DFPREG(rs2));
3589                     tcg_gen_helper_0_0(helper_fcmpgt16);
3590                     gen_op_store_DT0_fpr(DFPREG(rd));
3591                     break;
3592                 case 0x02a: /* VIS I fcmpeq16 */
3593                     gen_op_load_fpr_DT0(DFPREG(rs1));
3594                     gen_op_load_fpr_DT1(DFPREG(rs2));
3595                     tcg_gen_helper_0_0(helper_fcmpeq16);
3596                     gen_op_store_DT0_fpr(DFPREG(rd));
3597                     break;
3598                 case 0x02c: /* VIS I fcmpgt32 */
3599                     gen_op_load_fpr_DT0(DFPREG(rs1));
3600                     gen_op_load_fpr_DT1(DFPREG(rs2));
3601                     tcg_gen_helper_0_0(helper_fcmpgt32);
3602                     gen_op_store_DT0_fpr(DFPREG(rd));
3603                     break;
3604                 case 0x02e: /* VIS I fcmpeq32 */
3605                     gen_op_load_fpr_DT0(DFPREG(rs1));
3606                     gen_op_load_fpr_DT1(DFPREG(rs2));
3607                     tcg_gen_helper_0_0(helper_fcmpeq32);
3608                     gen_op_store_DT0_fpr(DFPREG(rd));
3609                     break;
3610                 case 0x031: /* VIS I fmul8x16 */
3611                     gen_op_load_fpr_DT0(DFPREG(rs1));
3612                     gen_op_load_fpr_DT1(DFPREG(rs2));
3613                     tcg_gen_helper_0_0(helper_fmul8x16);
3614                     gen_op_store_DT0_fpr(DFPREG(rd));
3615                     break;
3616                 case 0x033: /* VIS I fmul8x16au */
3617                     gen_op_load_fpr_DT0(DFPREG(rs1));
3618                     gen_op_load_fpr_DT1(DFPREG(rs2));
3619                     tcg_gen_helper_0_0(helper_fmul8x16au);
3620                     gen_op_store_DT0_fpr(DFPREG(rd));
3621                     break;
3622                 case 0x035: /* VIS I fmul8x16al */
3623                     gen_op_load_fpr_DT0(DFPREG(rs1));
3624                     gen_op_load_fpr_DT1(DFPREG(rs2));
3625                     tcg_gen_helper_0_0(helper_fmul8x16al);
3626                     gen_op_store_DT0_fpr(DFPREG(rd));
3627                     break;
3628                 case 0x036: /* VIS I fmul8sux16 */
3629                     gen_op_load_fpr_DT0(DFPREG(rs1));
3630                     gen_op_load_fpr_DT1(DFPREG(rs2));
3631                     tcg_gen_helper_0_0(helper_fmul8sux16);
3632                     gen_op_store_DT0_fpr(DFPREG(rd));
3633                     break;
3634                 case 0x037: /* VIS I fmul8ulx16 */
3635                     gen_op_load_fpr_DT0(DFPREG(rs1));
3636                     gen_op_load_fpr_DT1(DFPREG(rs2));
3637                     tcg_gen_helper_0_0(helper_fmul8ulx16);
3638                     gen_op_store_DT0_fpr(DFPREG(rd));
3639                     break;
3640                 case 0x038: /* VIS I fmuld8sux16 */
3641                     gen_op_load_fpr_DT0(DFPREG(rs1));
3642                     gen_op_load_fpr_DT1(DFPREG(rs2));
3643                     tcg_gen_helper_0_0(helper_fmuld8sux16);
3644                     gen_op_store_DT0_fpr(DFPREG(rd));
3645                     break;
3646                 case 0x039: /* VIS I fmuld8ulx16 */
3647                     gen_op_load_fpr_DT0(DFPREG(rs1));
3648                     gen_op_load_fpr_DT1(DFPREG(rs2));
3649                     tcg_gen_helper_0_0(helper_fmuld8ulx16);
3650                     gen_op_store_DT0_fpr(DFPREG(rd));
3651                     break;
3652                 case 0x03a: /* VIS I fpack32 */
3653                 case 0x03b: /* VIS I fpack16 */
3654                 case 0x03d: /* VIS I fpackfix */
3655                 case 0x03e: /* VIS I pdist */
3656                     // XXX
3657                     goto illegal_insn;
3658                 case 0x048: /* VIS I faligndata */
3659                     gen_op_load_fpr_DT0(DFPREG(rs1));
3660                     gen_op_load_fpr_DT1(DFPREG(rs2));
3661                     tcg_gen_helper_0_0(helper_faligndata);
3662                     gen_op_store_DT0_fpr(DFPREG(rd));
3663                     break;
3664                 case 0x04b: /* VIS I fpmerge */
3665                     gen_op_load_fpr_DT0(DFPREG(rs1));
3666                     gen_op_load_fpr_DT1(DFPREG(rs2));
3667                     tcg_gen_helper_0_0(helper_fpmerge);
3668                     gen_op_store_DT0_fpr(DFPREG(rd));
3669                     break;
3670                 case 0x04c: /* VIS II bshuffle */
3671                     // XXX
3672                     goto illegal_insn;
3673                 case 0x04d: /* VIS I fexpand */
3674                     gen_op_load_fpr_DT0(DFPREG(rs1));
3675                     gen_op_load_fpr_DT1(DFPREG(rs2));
3676                     tcg_gen_helper_0_0(helper_fexpand);
3677                     gen_op_store_DT0_fpr(DFPREG(rd));
3678                     break;
3679                 case 0x050: /* VIS I fpadd16 */
3680                     gen_op_load_fpr_DT0(DFPREG(rs1));
3681                     gen_op_load_fpr_DT1(DFPREG(rs2));
3682                     tcg_gen_helper_0_0(helper_fpadd16);
3683                     gen_op_store_DT0_fpr(DFPREG(rd));
3684                     break;
3685                 case 0x051: /* VIS I fpadd16s */
3686                     gen_op_load_fpr_FT0(rs1);
3687                     gen_op_load_fpr_FT1(rs2);
3688                     tcg_gen_helper_0_0(helper_fpadd16s);
3689                     gen_op_store_FT0_fpr(rd);
3690                     break;
3691                 case 0x052: /* VIS I fpadd32 */
3692                     gen_op_load_fpr_DT0(DFPREG(rs1));
3693                     gen_op_load_fpr_DT1(DFPREG(rs2));
3694                     tcg_gen_helper_0_0(helper_fpadd32);
3695                     gen_op_store_DT0_fpr(DFPREG(rd));
3696                     break;
3697                 case 0x053: /* VIS I fpadd32s */
3698                     gen_op_load_fpr_FT0(rs1);
3699                     gen_op_load_fpr_FT1(rs2);
3700                     tcg_gen_helper_0_0(helper_fpadd32s);
3701                     gen_op_store_FT0_fpr(rd);
3702                     break;
3703                 case 0x054: /* VIS I fpsub16 */
3704                     gen_op_load_fpr_DT0(DFPREG(rs1));
3705                     gen_op_load_fpr_DT1(DFPREG(rs2));
3706                     tcg_gen_helper_0_0(helper_fpsub16);
3707                     gen_op_store_DT0_fpr(DFPREG(rd));
3708                     break;
3709                 case 0x055: /* VIS I fpsub16s */
3710                     gen_op_load_fpr_FT0(rs1);
3711                     gen_op_load_fpr_FT1(rs2);
3712                     tcg_gen_helper_0_0(helper_fpsub16s);
3713                     gen_op_store_FT0_fpr(rd);
3714                     break;
3715                 case 0x056: /* VIS I fpsub32 */
3716                     gen_op_load_fpr_DT0(DFPREG(rs1));
3717                     gen_op_load_fpr_DT1(DFPREG(rs2));
3718                     tcg_gen_helper_0_0(helper_fpadd32);
3719                     gen_op_store_DT0_fpr(DFPREG(rd));
3720                     break;
3721                 case 0x057: /* VIS I fpsub32s */
3722                     gen_op_load_fpr_FT0(rs1);
3723                     gen_op_load_fpr_FT1(rs2);
3724                     tcg_gen_helper_0_0(helper_fpsub32s);
3725                     gen_op_store_FT0_fpr(rd);
3726                     break;
3727                 case 0x060: /* VIS I fzero */
3728                     tcg_gen_helper_0_0(helper_movl_DT0_0);
3729                     gen_op_store_DT0_fpr(DFPREG(rd));
3730                     break;
3731                 case 0x061: /* VIS I fzeros */
3732                     tcg_gen_helper_0_0(helper_movl_FT0_0);
3733                     gen_op_store_FT0_fpr(rd);
3734                     break;
3735                 case 0x062: /* VIS I fnor */
3736                     gen_op_load_fpr_DT0(DFPREG(rs1));
3737                     gen_op_load_fpr_DT1(DFPREG(rs2));
3738                     tcg_gen_helper_0_0(helper_fnor);
3739                     gen_op_store_DT0_fpr(DFPREG(rd));
3740                     break;
3741                 case 0x063: /* VIS I fnors */
3742                     gen_op_load_fpr_FT0(rs1);
3743                     gen_op_load_fpr_FT1(rs2);
3744                     tcg_gen_helper_0_0(helper_fnors);
3745                     gen_op_store_FT0_fpr(rd);
3746                     break;
3747                 case 0x064: /* VIS I fandnot2 */
3748                     gen_op_load_fpr_DT1(DFPREG(rs1));
3749                     gen_op_load_fpr_DT0(DFPREG(rs2));
3750                     tcg_gen_helper_0_0(helper_fandnot);
3751                     gen_op_store_DT0_fpr(DFPREG(rd));
3752                     break;
3753                 case 0x065: /* VIS I fandnot2s */
3754                     gen_op_load_fpr_FT1(rs1);
3755                     gen_op_load_fpr_FT0(rs2);
3756                     tcg_gen_helper_0_0(helper_fandnots);
3757                     gen_op_store_FT0_fpr(rd);
3758                     break;
3759                 case 0x066: /* VIS I fnot2 */
3760                     gen_op_load_fpr_DT1(DFPREG(rs2));
3761                     tcg_gen_helper_0_0(helper_fnot);
3762                     gen_op_store_DT0_fpr(DFPREG(rd));
3763                     break;
3764                 case 0x067: /* VIS I fnot2s */
3765                     gen_op_load_fpr_FT1(rs2);
3766                     tcg_gen_helper_0_0(helper_fnot);
3767                     gen_op_store_FT0_fpr(rd);
3768                     break;
3769                 case 0x068: /* VIS I fandnot1 */
3770                     gen_op_load_fpr_DT0(DFPREG(rs1));
3771                     gen_op_load_fpr_DT1(DFPREG(rs2));
3772                     tcg_gen_helper_0_0(helper_fandnot);
3773                     gen_op_store_DT0_fpr(DFPREG(rd));
3774                     break;
3775                 case 0x069: /* VIS I fandnot1s */
3776                     gen_op_load_fpr_FT0(rs1);
3777                     gen_op_load_fpr_FT1(rs2);
3778                     tcg_gen_helper_0_0(helper_fandnots);
3779                     gen_op_store_FT0_fpr(rd);
3780                     break;
3781                 case 0x06a: /* VIS I fnot1 */
3782                     gen_op_load_fpr_DT1(DFPREG(rs1));
3783                     tcg_gen_helper_0_0(helper_fnot);
3784                     gen_op_store_DT0_fpr(DFPREG(rd));
3785                     break;
3786                 case 0x06b: /* VIS I fnot1s */
3787                     gen_op_load_fpr_FT1(rs1);
3788                     tcg_gen_helper_0_0(helper_fnot);
3789                     gen_op_store_FT0_fpr(rd);
3790                     break;
3791                 case 0x06c: /* VIS I fxor */
3792                     gen_op_load_fpr_DT0(DFPREG(rs1));
3793                     gen_op_load_fpr_DT1(DFPREG(rs2));
3794                     tcg_gen_helper_0_0(helper_fxor);
3795                     gen_op_store_DT0_fpr(DFPREG(rd));
3796                     break;
3797                 case 0x06d: /* VIS I fxors */
3798                     gen_op_load_fpr_FT0(rs1);
3799                     gen_op_load_fpr_FT1(rs2);
3800                     tcg_gen_helper_0_0(helper_fxors);
3801                     gen_op_store_FT0_fpr(rd);
3802                     break;
3803                 case 0x06e: /* VIS I fnand */
3804                     gen_op_load_fpr_DT0(DFPREG(rs1));
3805                     gen_op_load_fpr_DT1(DFPREG(rs2));
3806                     tcg_gen_helper_0_0(helper_fnand);
3807                     gen_op_store_DT0_fpr(DFPREG(rd));
3808                     break;
3809                 case 0x06f: /* VIS I fnands */
3810                     gen_op_load_fpr_FT0(rs1);
3811                     gen_op_load_fpr_FT1(rs2);
3812                     tcg_gen_helper_0_0(helper_fnands);
3813                     gen_op_store_FT0_fpr(rd);
3814                     break;
3815                 case 0x070: /* VIS I fand */
3816                     gen_op_load_fpr_DT0(DFPREG(rs1));
3817                     gen_op_load_fpr_DT1(DFPREG(rs2));
3818                     tcg_gen_helper_0_0(helper_fand);
3819                     gen_op_store_DT0_fpr(DFPREG(rd));
3820                     break;
3821                 case 0x071: /* VIS I fands */
3822                     gen_op_load_fpr_FT0(rs1);
3823                     gen_op_load_fpr_FT1(rs2);
3824                     tcg_gen_helper_0_0(helper_fands);
3825                     gen_op_store_FT0_fpr(rd);
3826                     break;
3827                 case 0x072: /* VIS I fxnor */
3828                     gen_op_load_fpr_DT0(DFPREG(rs1));
3829                     gen_op_load_fpr_DT1(DFPREG(rs2));
3830                     tcg_gen_helper_0_0(helper_fxnor);
3831                     gen_op_store_DT0_fpr(DFPREG(rd));
3832                     break;
3833                 case 0x073: /* VIS I fxnors */
3834                     gen_op_load_fpr_FT0(rs1);
3835                     gen_op_load_fpr_FT1(rs2);
3836                     tcg_gen_helper_0_0(helper_fxnors);
3837                     gen_op_store_FT0_fpr(rd);
3838                     break;
3839                 case 0x074: /* VIS I fsrc1 */
3840                     gen_op_load_fpr_DT0(DFPREG(rs1));
3841                     gen_op_store_DT0_fpr(DFPREG(rd));
3842                     break;
3843                 case 0x075: /* VIS I fsrc1s */
3844                     gen_op_load_fpr_FT0(rs1);
3845                     gen_op_store_FT0_fpr(rd);
3846                     break;
3847                 case 0x076: /* VIS I fornot2 */
3848                     gen_op_load_fpr_DT1(DFPREG(rs1));
3849                     gen_op_load_fpr_DT0(DFPREG(rs2));
3850                     tcg_gen_helper_0_0(helper_fornot);
3851                     gen_op_store_DT0_fpr(DFPREG(rd));
3852                     break;
3853                 case 0x077: /* VIS I fornot2s */
3854                     gen_op_load_fpr_FT1(rs1);
3855                     gen_op_load_fpr_FT0(rs2);
3856                     tcg_gen_helper_0_0(helper_fornots);
3857                     gen_op_store_FT0_fpr(rd);
3858                     break;
3859                 case 0x078: /* VIS I fsrc2 */
3860                     gen_op_load_fpr_DT0(DFPREG(rs2));
3861                     gen_op_store_DT0_fpr(DFPREG(rd));
3862                     break;
3863                 case 0x079: /* VIS I fsrc2s */
3864                     gen_op_load_fpr_FT0(rs2);
3865                     gen_op_store_FT0_fpr(rd);
3866                     break;
3867                 case 0x07a: /* VIS I fornot1 */
3868                     gen_op_load_fpr_DT0(DFPREG(rs1));
3869                     gen_op_load_fpr_DT1(DFPREG(rs2));
3870                     tcg_gen_helper_0_0(helper_fornot);
3871                     gen_op_store_DT0_fpr(DFPREG(rd));
3872                     break;
3873                 case 0x07b: /* VIS I fornot1s */
3874                     gen_op_load_fpr_FT0(rs1);
3875                     gen_op_load_fpr_FT1(rs2);
3876                     tcg_gen_helper_0_0(helper_fornots);
3877                     gen_op_store_FT0_fpr(rd);
3878                     break;
3879                 case 0x07c: /* VIS I for */
3880                     gen_op_load_fpr_DT0(DFPREG(rs1));
3881                     gen_op_load_fpr_DT1(DFPREG(rs2));
3882                     tcg_gen_helper_0_0(helper_for);
3883                     gen_op_store_DT0_fpr(DFPREG(rd));
3884                     break;
3885                 case 0x07d: /* VIS I fors */
3886                     gen_op_load_fpr_FT0(rs1);
3887                     gen_op_load_fpr_FT1(rs2);
3888                     tcg_gen_helper_0_0(helper_fors);
3889                     gen_op_store_FT0_fpr(rd);
3890                     break;
3891                 case 0x07e: /* VIS I fone */
3892                     tcg_gen_helper_0_0(helper_movl_DT0_1);
3893                     gen_op_store_DT0_fpr(DFPREG(rd));
3894                     break;
3895                 case 0x07f: /* VIS I fones */
3896                     tcg_gen_helper_0_0(helper_movl_FT0_1);
3897                     gen_op_store_FT0_fpr(rd);
3898                     break;
3899                 case 0x080: /* VIS I shutdown */
3900                 case 0x081: /* VIS II siam */
3901                     // XXX
3902                     goto illegal_insn;
3903                 default:
3904                     goto illegal_insn;
3905                 }
3906 #else
3907                 goto ncp_insn;
3908 #endif
3909             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
3910 #ifdef TARGET_SPARC64
3911                 goto illegal_insn;
3912 #else
3913                 goto ncp_insn;
3914 #endif
3915 #ifdef TARGET_SPARC64
3916             } else if (xop == 0x39) { /* V9 return */
3917                 rs1 = GET_FIELD(insn, 13, 17);
3918                 save_state(dc, cpu_cond);
3919                 gen_movl_reg_TN(rs1, cpu_src1);
3920                 if (IS_IMM) {   /* immediate */
3921                     rs2 = GET_FIELDs(insn, 19, 31);
3922                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3923                 } else {                /* register */
3924                     rs2 = GET_FIELD(insn, 27, 31);
3925 #if defined(OPTIM)
3926                     if (rs2) {
3927 #endif
3928                         gen_movl_reg_TN(rs2, cpu_src2);
3929                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3930 #if defined(OPTIM)
3931                     }
3932 #endif
3933                 }
3934                 tcg_gen_helper_0_0(helper_restore);
3935                 gen_mov_pc_npc(dc, cpu_cond);
3936                 tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3937                 tcg_gen_mov_tl(cpu_npc, cpu_dst);
3938                 dc->npc = DYNAMIC_PC;
3939                 goto jmp_insn;
3940 #endif
3941             } else {
3942                 rs1 = GET_FIELD(insn, 13, 17);
3943                 gen_movl_reg_TN(rs1, cpu_src1);
3944                 if (IS_IMM) {   /* immediate */
3945                     rs2 = GET_FIELDs(insn, 19, 31);
3946                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3947                 } else {                /* register */
3948                     rs2 = GET_FIELD(insn, 27, 31);
3949 #if defined(OPTIM)
3950                     if (rs2) {
3951 #endif
3952                         gen_movl_reg_TN(rs2, cpu_src2);
3953                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3954 #if defined(OPTIM)
3955                     }
3956 #endif
3957                 }
3958                 switch (xop) {
3959                 case 0x38:      /* jmpl */
3960                     {
3961                         if (rd != 0) {
3962                             tcg_gen_movi_tl(cpu_tmp0, dc->pc);
3963                             gen_movl_TN_reg(rd, cpu_tmp0);
3964                         }
3965                         gen_mov_pc_npc(dc, cpu_cond);
3966                         tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3967                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
3968                         dc->npc = DYNAMIC_PC;
3969                     }
3970                     goto jmp_insn;
3971 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3972                 case 0x39:      /* rett, V9 return */
3973                     {
3974                         if (!supervisor(dc))
3975                             goto priv_insn;
3976                         gen_mov_pc_npc(dc, cpu_cond);
3977                         tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3978                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
3979                         dc->npc = DYNAMIC_PC;
3980                         tcg_gen_helper_0_0(helper_rett);
3981                     }
3982                     goto jmp_insn;
3983 #endif
3984                 case 0x3b: /* flush */
3985                     tcg_gen_helper_0_1(helper_flush, cpu_dst);
3986                     break;
3987                 case 0x3c:      /* save */
3988                     save_state(dc, cpu_cond);
3989                     tcg_gen_helper_0_0(helper_save);
3990                     gen_movl_TN_reg(rd, cpu_dst);
3991                     break;
3992                 case 0x3d:      /* restore */
3993                     save_state(dc, cpu_cond);
3994                     tcg_gen_helper_0_0(helper_restore);
3995                     gen_movl_TN_reg(rd, cpu_dst);
3996                     break;
3997 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
3998                 case 0x3e:      /* V9 done/retry */
3999                     {
4000                         switch (rd) {
4001                         case 0:
4002                             if (!supervisor(dc))
4003                                 goto priv_insn;
4004                             dc->npc = DYNAMIC_PC;
4005                             dc->pc = DYNAMIC_PC;
4006                             tcg_gen_helper_0_0(helper_done);
4007                             goto jmp_insn;
4008                         case 1:
4009                             if (!supervisor(dc))
4010                                 goto priv_insn;
4011                             dc->npc = DYNAMIC_PC;
4012                             dc->pc = DYNAMIC_PC;
4013                             tcg_gen_helper_0_0(helper_retry);
4014                             goto jmp_insn;
4015                         default:
4016                             goto illegal_insn;
4017                         }
4018                     }
4019                     break;
4020 #endif
4021                 default:
4022                     goto illegal_insn;
4023                 }
4024             }
4025             break;
4026         }
4027         break;
4028     case 3:                     /* load/store instructions */
4029         {
4030             unsigned int xop = GET_FIELD(insn, 7, 12);
4031             rs1 = GET_FIELD(insn, 13, 17);
4032             save_state(dc, cpu_cond);
4033             gen_movl_reg_TN(rs1, cpu_src1);
4034             if (xop == 0x3c || xop == 0x3e)
4035             {
4036                 rs2 = GET_FIELD(insn, 27, 31);
4037                 gen_movl_reg_TN(rs2, cpu_src2);
4038             }
4039             else if (IS_IMM) {       /* immediate */
4040                 rs2 = GET_FIELDs(insn, 19, 31);
4041                 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4042             } else {            /* register */
4043                 rs2 = GET_FIELD(insn, 27, 31);
4044 #if defined(OPTIM)
4045                 if (rs2 != 0) {
4046 #endif
4047                     gen_movl_reg_TN(rs2, cpu_src2);
4048                     tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4049 #if defined(OPTIM)
4050                 }
4051 #endif
4052             }
4053             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4054                 (xop > 0x17 && xop <= 0x1d ) ||
4055                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4056                 switch (xop) {
4057                 case 0x0:       /* load unsigned word */
4058                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4059                     ABI32_MASK(cpu_addr);
4060                     tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4061                     break;
4062                 case 0x1:       /* load unsigned byte */
4063                     ABI32_MASK(cpu_addr);
4064                     tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4065                     break;
4066                 case 0x2:       /* load unsigned halfword */
4067                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4068                     ABI32_MASK(cpu_addr);
4069                     tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4070                     break;
4071                 case 0x3:       /* load double word */
4072                     if (rd & 1)
4073                         goto illegal_insn;
4074                     else {
4075                         tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4076                         ABI32_MASK(cpu_addr);
4077                         tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4078                         tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4079                         tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4080                         gen_movl_TN_reg(rd + 1, cpu_tmp0);
4081                         tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4082                         tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4083                         tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4084                     }
4085                     break;
4086                 case 0x9:       /* load signed byte */
4087                     ABI32_MASK(cpu_addr);
4088                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4089                     break;
4090                 case 0xa:       /* load signed halfword */
4091                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4092                     ABI32_MASK(cpu_addr);
4093                     tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4094                     break;
4095                 case 0xd:       /* ldstub -- XXX: should be atomically */
4096                     ABI32_MASK(cpu_addr);
4097                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4098                     tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, dc->mem_idx);
4099                     break;
4100                 case 0x0f:      /* swap register with memory. Also atomically */
4101                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4102                     gen_movl_reg_TN(rd, cpu_val);
4103                     ABI32_MASK(cpu_addr);
4104                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4105                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4106                     tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4107                     break;
4108 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4109                 case 0x10:      /* load word alternate */
4110 #ifndef TARGET_SPARC64
4111                     if (IS_IMM)
4112                         goto illegal_insn;
4113                     if (!supervisor(dc))
4114                         goto priv_insn;
4115 #endif
4116                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4117                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4118                     break;
4119                 case 0x11:      /* load unsigned byte alternate */
4120 #ifndef TARGET_SPARC64
4121                     if (IS_IMM)
4122                         goto illegal_insn;
4123                     if (!supervisor(dc))
4124                         goto priv_insn;
4125 #endif
4126                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4127                     break;
4128                 case 0x12:      /* load unsigned halfword alternate */
4129 #ifndef TARGET_SPARC64
4130                     if (IS_IMM)
4131                         goto illegal_insn;
4132                     if (!supervisor(dc))
4133                         goto priv_insn;
4134 #endif
4135                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4136                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4137                     break;
4138                 case 0x13:      /* load double word alternate */
4139 #ifndef TARGET_SPARC64
4140                     if (IS_IMM)
4141                         goto illegal_insn;
4142                     if (!supervisor(dc))
4143                         goto priv_insn;
4144 #endif
4145                     if (rd & 1)
4146                         goto illegal_insn;
4147                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4148                     gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4149                     gen_movl_TN_reg(rd + 1, cpu_tmp0);
4150                     break;
4151                 case 0x19:      /* load signed byte alternate */
4152 #ifndef TARGET_SPARC64
4153                     if (IS_IMM)
4154                         goto illegal_insn;
4155                     if (!supervisor(dc))
4156                         goto priv_insn;
4157 #endif
4158                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4159                     break;
4160                 case 0x1a:      /* load signed halfword alternate */
4161 #ifndef TARGET_SPARC64
4162                     if (IS_IMM)
4163                         goto illegal_insn;
4164                     if (!supervisor(dc))
4165                         goto priv_insn;
4166 #endif
4167                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4168                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4169                     break;
4170                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
4171 #ifndef TARGET_SPARC64
4172                     if (IS_IMM)
4173                         goto illegal_insn;
4174                     if (!supervisor(dc))
4175                         goto priv_insn;
4176 #endif
4177                     gen_ldstub_asi(cpu_val, cpu_addr, insn);
4178                     break;
4179                 case 0x1f:      /* swap reg with alt. memory. Also atomically */
4180 #ifndef TARGET_SPARC64
4181                     if (IS_IMM)
4182                         goto illegal_insn;
4183                     if (!supervisor(dc))
4184                         goto priv_insn;
4185 #endif
4186                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4187                     gen_movl_reg_TN(rd, cpu_val);
4188                     gen_swap_asi(cpu_val, cpu_addr, insn);
4189                     break;
4190
4191 #ifndef TARGET_SPARC64
4192                 case 0x30: /* ldc */
4193                 case 0x31: /* ldcsr */
4194                 case 0x33: /* lddc */
4195                     goto ncp_insn;
4196 #endif
4197 #endif
4198 #ifdef TARGET_SPARC64
4199                 case 0x08: /* V9 ldsw */
4200                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4201                     ABI32_MASK(cpu_addr);
4202                     tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4203                     break;
4204                 case 0x0b: /* V9 ldx */
4205                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4206                     ABI32_MASK(cpu_addr);
4207                     tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4208                     break;
4209                 case 0x18: /* V9 ldswa */
4210                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4211                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4212                     break;
4213                 case 0x1b: /* V9 ldxa */
4214                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4215                     gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4216                     break;
4217                 case 0x2d: /* V9 prefetch, no effect */
4218                     goto skip_move;
4219                 case 0x30: /* V9 ldfa */
4220                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4221                     gen_ldf_asi(cpu_addr, insn, 4, rd);
4222                     goto skip_move;
4223                 case 0x33: /* V9 lddfa */
4224                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4225                     gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4226                     goto skip_move;
4227                 case 0x3d: /* V9 prefetcha, no effect */
4228                     goto skip_move;
4229                 case 0x32: /* V9 ldqfa */
4230 #if defined(CONFIG_USER_ONLY)
4231                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4232                     gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4233                     goto skip_move;
4234 #else
4235                     goto nfpu_insn;
4236 #endif
4237 #endif
4238                 default:
4239                     goto illegal_insn;
4240                 }
4241                 gen_movl_TN_reg(rd, cpu_val);
4242 #ifdef TARGET_SPARC64
4243             skip_move: ;
4244 #endif
4245             } else if (xop >= 0x20 && xop < 0x24) {
4246                 if (gen_trap_ifnofpu(dc, cpu_cond))
4247                     goto jmp_insn;
4248                 switch (xop) {
4249                 case 0x20:      /* load fpreg */
4250                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4251                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4252                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4253                                    offsetof(CPUState, fpr[rd]));
4254                     break;
4255                 case 0x21:      /* load fsr */
4256                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4257                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4258                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4259                                    offsetof(CPUState, ft0));
4260                     tcg_gen_helper_0_0(helper_ldfsr);
4261                     break;
4262                 case 0x22:      /* load quad fpreg */
4263 #if defined(CONFIG_USER_ONLY)
4264                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4265                     gen_op_ldst(ldqf);
4266                     gen_op_store_QT0_fpr(QFPREG(rd));
4267                     break;
4268 #else
4269                     goto nfpu_insn;
4270 #endif
4271                 case 0x23:      /* load double fpreg */
4272                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4273                     gen_op_ldst(lddf);
4274                     gen_op_store_DT0_fpr(DFPREG(rd));
4275                     break;
4276                 default:
4277                     goto illegal_insn;
4278                 }
4279             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4280                        xop == 0xe || xop == 0x1e) {
4281                 gen_movl_reg_TN(rd, cpu_val);
4282                 switch (xop) {
4283                 case 0x4: /* store word */
4284                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4285                     ABI32_MASK(cpu_addr);
4286                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4287                     break;
4288                 case 0x5: /* store byte */
4289                     ABI32_MASK(cpu_addr);
4290                     tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4291                     break;
4292                 case 0x6: /* store halfword */
4293                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4294                     ABI32_MASK(cpu_addr);
4295                     tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4296                     break;
4297                 case 0x7: /* store double word */
4298                     if (rd & 1)
4299                         goto illegal_insn;
4300 #ifndef __i386__
4301                     else {
4302                         TCGv r_low;
4303
4304                         tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4305                         r_low = tcg_temp_new(TCG_TYPE_I32);
4306                         gen_movl_reg_TN(rd + 1, r_low);
4307                         tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4308                                            r_low);
4309                         tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4310                     }
4311 #else /* __i386__ */
4312                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4313                     flush_cond(dc, cpu_cond);
4314                     gen_movl_reg_TN(rd + 1, cpu_cond);
4315                     gen_op_ldst(std);
4316 #endif /* __i386__ */
4317                     break;
4318 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4319                 case 0x14: /* store word alternate */
4320 #ifndef TARGET_SPARC64
4321                     if (IS_IMM)
4322                         goto illegal_insn;
4323                     if (!supervisor(dc))
4324                         goto priv_insn;
4325 #endif
4326                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4327                     gen_st_asi(cpu_val, cpu_addr, insn, 4);
4328                     break;
4329                 case 0x15: /* store byte alternate */
4330 #ifndef TARGET_SPARC64
4331                     if (IS_IMM)
4332                         goto illegal_insn;
4333                     if (!supervisor(dc))
4334                         goto priv_insn;
4335 #endif
4336                     gen_st_asi(cpu_val, cpu_addr, insn, 1);
4337                     break;
4338                 case 0x16: /* store halfword alternate */
4339 #ifndef TARGET_SPARC64
4340                     if (IS_IMM)
4341                         goto illegal_insn;
4342                     if (!supervisor(dc))
4343                         goto priv_insn;
4344 #endif
4345                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4346                     gen_st_asi(cpu_val, cpu_addr, insn, 2);
4347                     break;
4348                 case 0x17: /* store double word alternate */
4349 #ifndef TARGET_SPARC64
4350                     if (IS_IMM)
4351                         goto illegal_insn;
4352                     if (!supervisor(dc))
4353                         goto priv_insn;
4354 #endif
4355                     if (rd & 1)
4356                         goto illegal_insn;
4357                     else {
4358                         tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4359                         gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4360                     }
4361                     break;
4362 #endif
4363 #ifdef TARGET_SPARC64
4364                 case 0x0e: /* V9 stx */
4365                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4366                     ABI32_MASK(cpu_addr);
4367                     tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4368                     break;
4369                 case 0x1e: /* V9 stxa */
4370                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4371                     gen_st_asi(cpu_val, cpu_addr, insn, 8);
4372                     break;
4373 #endif
4374                 default:
4375                     goto illegal_insn;
4376                 }
4377             } else if (xop > 0x23 && xop < 0x28) {
4378                 if (gen_trap_ifnofpu(dc, cpu_cond))
4379                     goto jmp_insn;
4380                 switch (xop) {
4381                 case 0x24: /* store fpreg */
4382                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4383                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4384                                    offsetof(CPUState, fpr[rd]));
4385                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4386                     break;
4387                 case 0x25: /* stfsr, V9 stxfsr */
4388 #ifdef CONFIG_USER_ONLY
4389                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4390 #endif
4391                     tcg_gen_helper_0_0(helper_stfsr);
4392                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4393                                    offsetof(CPUState, ft0));
4394                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4395                     break;
4396                 case 0x26:
4397 #ifdef TARGET_SPARC64
4398 #if defined(CONFIG_USER_ONLY)
4399                     /* V9 stqf, store quad fpreg */
4400                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4401                     gen_op_load_fpr_QT0(QFPREG(rd));
4402                     gen_op_ldst(stqf);
4403                     break;
4404 #else
4405                     goto nfpu_insn;
4406 #endif
4407 #else /* !TARGET_SPARC64 */
4408                     /* stdfq, store floating point queue */
4409 #if defined(CONFIG_USER_ONLY)
4410                     goto illegal_insn;
4411 #else
4412                     if (!supervisor(dc))
4413                         goto priv_insn;
4414                     if (gen_trap_ifnofpu(dc, cpu_cond))
4415                         goto jmp_insn;
4416                     goto nfq_insn;
4417 #endif
4418 #endif
4419                 case 0x27:
4420                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4421                     gen_op_load_fpr_DT0(DFPREG(rd));
4422                     gen_op_ldst(stdf);
4423                     break;
4424                 default:
4425                     goto illegal_insn;
4426                 }
4427             } else if (xop > 0x33 && xop < 0x3f) {
4428                 switch (xop) {
4429 #ifdef TARGET_SPARC64
4430                 case 0x34: /* V9 stfa */
4431                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4432                     gen_op_load_fpr_FT0(rd);
4433                     gen_stf_asi(cpu_addr, insn, 4, rd);
4434                     break;
4435                 case 0x36: /* V9 stqfa */
4436 #if defined(CONFIG_USER_ONLY)
4437                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4438                     gen_op_load_fpr_QT0(QFPREG(rd));
4439                     gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4440                     break;
4441 #else
4442                     goto nfpu_insn;
4443 #endif
4444                 case 0x37: /* V9 stdfa */
4445                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4446                     gen_op_load_fpr_DT0(DFPREG(rd));
4447                     gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4448                     break;
4449                 case 0x3c: /* V9 casa */
4450                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4451                     gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4452                     gen_movl_TN_reg(rd, cpu_val);
4453                     break;
4454                 case 0x3e: /* V9 casxa */
4455                     tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4456                     gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4457                     gen_movl_TN_reg(rd, cpu_val);
4458                     break;
4459 #else
4460                 case 0x34: /* stc */
4461                 case 0x35: /* stcsr */
4462                 case 0x36: /* stdcq */
4463                 case 0x37: /* stdc */
4464                     goto ncp_insn;
4465 #endif
4466                 default:
4467                     goto illegal_insn;
4468                 }
4469             }
4470             else
4471                 goto illegal_insn;
4472         }
4473         break;
4474     }
4475     /* default case for non jump instructions */
4476     if (dc->npc == DYNAMIC_PC) {
4477         dc->pc = DYNAMIC_PC;
4478         gen_op_next_insn();
4479     } else if (dc->npc == JUMP_PC) {
4480         /* we can do a static jump */
4481         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4482         dc->is_br = 1;
4483     } else {
4484         dc->pc = dc->npc;
4485         dc->npc = dc->npc + 4;
4486     }
4487  jmp_insn:
4488     return;
4489  illegal_insn:
4490     save_state(dc, cpu_cond);
4491     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
4492     dc->is_br = 1;
4493     return;
4494 #if !defined(CONFIG_USER_ONLY)
4495  priv_insn:
4496     save_state(dc, cpu_cond);
4497     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
4498     dc->is_br = 1;
4499     return;
4500  nfpu_insn:
4501     save_state(dc, cpu_cond);
4502     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4503     dc->is_br = 1;
4504     return;
4505 #ifndef TARGET_SPARC64
4506  nfq_insn:
4507     save_state(dc, cpu_cond);
4508     gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4509     dc->is_br = 1;
4510     return;
4511 #endif
4512 #endif
4513 #ifndef TARGET_SPARC64
4514  ncp_insn:
4515     save_state(dc, cpu_cond);
4516     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
4517     dc->is_br = 1;
4518     return;
4519 #endif
4520 }
4521
4522 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
4523 {
4524 }
4525
4526 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4527                                                  int spc, CPUSPARCState *env)
4528 {
4529     target_ulong pc_start, last_pc;
4530     uint16_t *gen_opc_end;
4531     DisasContext dc1, *dc = &dc1;
4532     int j, lj = -1;
4533
4534     memset(dc, 0, sizeof(DisasContext));
4535     dc->tb = tb;
4536     pc_start = tb->pc;
4537     dc->pc = pc_start;
4538     last_pc = dc->pc;
4539     dc->npc = (target_ulong) tb->cs_base;
4540     dc->mem_idx = cpu_mmu_index(env);
4541     dc->fpu_enabled = cpu_fpu_enabled(env);
4542     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4543
4544     cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4545     cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4546     cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4547
4548     cpu_cond = cpu_T[2];
4549
4550     do {
4551         if (env->nb_breakpoints > 0) {
4552             for(j = 0; j < env->nb_breakpoints; j++) {
4553                 if (env->breakpoints[j] == dc->pc) {
4554                     if (dc->pc != pc_start)
4555                         save_state(dc, cpu_cond);
4556                     tcg_gen_helper_0_0(helper_debug);
4557                     tcg_gen_exit_tb(0);
4558                     dc->is_br = 1;
4559                     goto exit_gen_loop;
4560                 }
4561             }
4562         }
4563         if (spc) {
4564             if (loglevel > 0)
4565                 fprintf(logfile, "Search PC...\n");
4566             j = gen_opc_ptr - gen_opc_buf;
4567             if (lj < j) {
4568                 lj++;
4569                 while (lj < j)
4570                     gen_opc_instr_start[lj++] = 0;
4571                 gen_opc_pc[lj] = dc->pc;
4572                 gen_opc_npc[lj] = dc->npc;
4573                 gen_opc_instr_start[lj] = 1;
4574             }
4575         }
4576         last_pc = dc->pc;
4577         disas_sparc_insn(dc);
4578
4579         if (dc->is_br)
4580             break;
4581         /* if the next PC is different, we abort now */
4582         if (dc->pc != (last_pc + 4))
4583             break;
4584         /* if we reach a page boundary, we stop generation so that the
4585            PC of a TT_TFAULT exception is always in the right page */
4586         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4587             break;
4588         /* if single step mode, we generate only one instruction and
4589            generate an exception */
4590         if (env->singlestep_enabled) {
4591             tcg_gen_movi_tl(cpu_pc, dc->pc);
4592             tcg_gen_exit_tb(0);
4593             break;
4594         }
4595     } while ((gen_opc_ptr < gen_opc_end) &&
4596              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4597
4598  exit_gen_loop:
4599     if (!dc->is_br) {
4600         if (dc->pc != DYNAMIC_PC &&
4601             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4602             /* static PC and NPC: we can use direct chaining */
4603             gen_goto_tb(dc, 0, dc->pc, dc->npc);
4604         } else {
4605             if (dc->pc != DYNAMIC_PC)
4606                 tcg_gen_movi_tl(cpu_pc, dc->pc);
4607             save_npc(dc, cpu_cond);
4608             tcg_gen_exit_tb(0);
4609         }
4610     }
4611     *gen_opc_ptr = INDEX_op_end;
4612     if (spc) {
4613         j = gen_opc_ptr - gen_opc_buf;
4614         lj++;
4615         while (lj <= j)
4616             gen_opc_instr_start[lj++] = 0;
4617 #if 0
4618         if (loglevel > 0) {
4619             page_dump(logfile);
4620         }
4621 #endif
4622         gen_opc_jump_pc[0] = dc->jump_pc[0];
4623         gen_opc_jump_pc[1] = dc->jump_pc[1];
4624     } else {
4625         tb->size = last_pc + 4 - pc_start;
4626     }
4627 #ifdef DEBUG_DISAS
4628     if (loglevel & CPU_LOG_TB_IN_ASM) {
4629         fprintf(logfile, "--------------\n");
4630         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4631         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4632         fprintf(logfile, "\n");
4633     }
4634 #endif
4635     return 0;
4636 }
4637
4638 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4639 {
4640     return gen_intermediate_code_internal(tb, 0, env);
4641 }
4642
4643 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4644 {
4645     return gen_intermediate_code_internal(tb, 1, env);
4646 }
4647
4648 void gen_intermediate_code_init(CPUSPARCState *env)
4649 {
4650     unsigned int i;
4651     static int inited;
4652     static const char * const gregnames[8] = {
4653         NULL, // g0 not used
4654         "g1",
4655         "g2",
4656         "g3",
4657         "g4",
4658         "g5",
4659         "g6",
4660         "g7",
4661     };
4662
4663     /* init various static tables */
4664     if (!inited) {
4665         inited = 1;
4666
4667         tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
4668         cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4669         cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4670                                          offsetof(CPUState, regwptr),
4671                                          "regwptr");
4672         //#if TARGET_LONG_BITS > HOST_LONG_BITS
4673 #ifdef TARGET_SPARC64
4674         cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4675                                       TCG_AREG0, offsetof(CPUState, t0), "T0");
4676         cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4677                                       TCG_AREG0, offsetof(CPUState, t1), "T1");
4678         cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4679                                       TCG_AREG0, offsetof(CPUState, t2), "T2");
4680         cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4681                                      TCG_AREG0, offsetof(CPUState, xcc),
4682                                      "xcc");
4683 #else
4684         cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4685         cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4686         cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4687 #endif
4688         cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4689                                         TCG_AREG0, offsetof(CPUState, cc_src),
4690                                         "cc_src");
4691         cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4692                                          offsetof(CPUState, cc_src2),
4693                                          "cc_src2");
4694         cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4695                                         TCG_AREG0, offsetof(CPUState, cc_dst),
4696                                         "cc_dst");
4697         cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4698                                      TCG_AREG0, offsetof(CPUState, psr),
4699                                      "psr");
4700         cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4701                                      TCG_AREG0, offsetof(CPUState, fsr),
4702                                      "fsr");
4703         cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4704                                     TCG_AREG0, offsetof(CPUState, pc),
4705                                     "pc");
4706         cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4707                                     TCG_AREG0, offsetof(CPUState, npc),
4708                                     "npc");
4709         for (i = 1; i < 8; i++)
4710             cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4711                                               offsetof(CPUState, gregs[i]),
4712                                               gregnames[i]);
4713     }
4714 }