git.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <stdarg.h>
  23 #include <stdlib.h>
  24 #include <stdio.h>
  25 #include <string.h>
  26 #include <inttypes.h>
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30 #include "disas.h"
  31 #include "helper.h"
  32 #include "tcg-op.h"
  33
  34 #define DEBUG_DISAS
  35
  36 #define DYNAMIC_PC  1 /* dynamic pc value */
  37 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  38                          according to jump_pc[T2] */
  39
  40 /* global register indexes */
  41 static TCGv cpu_env, cpu_T[2], cpu_regwptr;
  42 static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
  43 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
  44 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
  45 #ifdef TARGET_SPARC64
  46 static TCGv cpu_xcc;
  47 #endif
  48 /* local register indexes (only used inside old micro ops) */
  49 static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
  50
  51 typedef struct DisasContext {
  52     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  53     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  54     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  55     int is_br;
  56     int mem_idx;
  57     int fpu_enabled;
  58     struct TranslationBlock *tb;
  59     uint32_t features;
  60 } DisasContext;
  61
  62 // This function uses non-native bit order
  63 #define GET_FIELD(X, FROM, TO) \
  64   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  65
  66 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  67 #define GET_FIELD_SP(X, FROM, TO) \
  68     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  69
  70 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  71 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
  72
  73 #ifdef TARGET_SPARC64
  74 #define FFPREG(r) (r)
  75 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
  76 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
  77 #else
  78 #define FFPREG(r) (r)
  79 #define DFPREG(r) (r & 0x1e)
  80 #define QFPREG(r) (r & 0x1c)
  81 #endif
  82
  83 static int sign_extend(int x, int len)
  84 {
  85     len = 32 - len;
  86     return (x << len) >> len;
  87 }
  88
  89 #define IS_IMM (insn & (1<<13))
  90
  91 /* floating point registers moves */
  92 static void gen_op_load_fpr_FT0(unsigned int src)
  93 {
  94     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  95     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
  96 }
  97
  98 static void gen_op_load_fpr_FT1(unsigned int src)
  99 {
 100     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 101     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
 102 }
 103
 104 static void gen_op_store_FT0_fpr(unsigned int dst)
 105 {
 106     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
 107     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 108 }
 109
 110 static void gen_op_load_fpr_DT0(unsigned int src)
 111 {
 112     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 113     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 114                    offsetof(CPU_DoubleU, l.upper));
 115     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 116     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 117                    offsetof(CPU_DoubleU, l.lower));
 118 }
 119
 120 static void gen_op_load_fpr_DT1(unsigned int src)
 121 {
 122     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 123     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
 124                    offsetof(CPU_DoubleU, l.upper));
 125     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 126     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
 127                    offsetof(CPU_DoubleU, l.lower));
 128 }
 129
 130 static void gen_op_store_DT0_fpr(unsigned int dst)
 131 {
 132     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 133                    offsetof(CPU_DoubleU, l.upper));
 134     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 135     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 136                    offsetof(CPU_DoubleU, l.lower));
 137     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 138 }
 139
 140 static void gen_op_load_fpr_QT0(unsigned int src)
 141 {
 142     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 143     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 144                    offsetof(CPU_QuadU, l.upmost));
 145     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 146     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 147                    offsetof(CPU_QuadU, l.upper));
 148     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 149     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 150                    offsetof(CPU_QuadU, l.lower));
 151     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 152     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 153                    offsetof(CPU_QuadU, l.lowest));
 154 }
 155
 156 static void gen_op_load_fpr_QT1(unsigned int src)
 157 {
 158     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 159     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 160                    offsetof(CPU_QuadU, l.upmost));
 161     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 162     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 163                    offsetof(CPU_QuadU, l.upper));
 164     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 165     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 166                    offsetof(CPU_QuadU, l.lower));
 167     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 168     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 169                    offsetof(CPU_QuadU, l.lowest));
 170 }
 171
 172 static void gen_op_store_QT0_fpr(unsigned int dst)
 173 {
 174     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 175                    offsetof(CPU_QuadU, l.upmost));
 176     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 177     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 178                    offsetof(CPU_QuadU, l.upper));
 179     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 180     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 181                    offsetof(CPU_QuadU, l.lower));
 182     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
 183     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 184                    offsetof(CPU_QuadU, l.lowest));
 185     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
 186 }
 187
 188 /* moves */
 189 #ifdef CONFIG_USER_ONLY
 190 #define supervisor(dc) 0
 191 #ifdef TARGET_SPARC64
 192 #define hypervisor(dc) 0
 193 #endif
 194 #else
 195 #define supervisor(dc) (dc->mem_idx >= 1)
 196 #ifdef TARGET_SPARC64
 197 #define hypervisor(dc) (dc->mem_idx == 2)
 198 #else
 199 #endif
 200 #endif
 201
 202 #ifdef TARGET_ABI32
 203 #define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
 204 #else
 205 #define ABI32_MASK(addr)
 206 #endif
 207
 208 static inline void gen_movl_reg_TN(int reg, TCGv tn)
 209 {
 210     if (reg == 0)
 211         tcg_gen_movi_tl(tn, 0);
 212     else if (reg < 8)
 213         tcg_gen_mov_tl(tn, cpu_gregs[reg]);
 214     else {
 215         tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 216     }
 217 }
 218
 219 static inline void gen_movl_TN_reg(int reg, TCGv tn)
 220 {
 221     if (reg == 0)
 222         return;
 223     else if (reg < 8)
 224         tcg_gen_mov_tl(cpu_gregs[reg], tn);
 225     else {
 226         tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 227     }
 228 }
 229
 230 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 231                                target_ulong pc, target_ulong npc)
 232 {
 233     TranslationBlock *tb;
 234
 235     tb = s->tb;
 236     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 237         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 238         /* jump to same page: we can use a direct jump */
 239         tcg_gen_goto_tb(tb_num);
 240         tcg_gen_movi_tl(cpu_pc, pc);
 241         tcg_gen_movi_tl(cpu_npc, npc);
 242         tcg_gen_exit_tb((long)tb + tb_num);
 243     } else {
 244         /* jump to another page: currently not optimized */
 245         tcg_gen_movi_tl(cpu_pc, pc);
 246         tcg_gen_movi_tl(cpu_npc, npc);
 247         tcg_gen_exit_tb(0);
 248     }
 249 }
 250
 251 // XXX suboptimal
 252 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
 253 {
 254     tcg_gen_extu_i32_tl(reg, src);
 255     tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
 256     tcg_gen_andi_tl(reg, reg, 0x1);
 257 }
 258
 259 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
 260 {
 261     tcg_gen_extu_i32_tl(reg, src);
 262     tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
 263     tcg_gen_andi_tl(reg, reg, 0x1);
 264 }
 265
 266 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
 267 {
 268     tcg_gen_extu_i32_tl(reg, src);
 269     tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
 270     tcg_gen_andi_tl(reg, reg, 0x1);
 271 }
 272
 273 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
 274 {
 275     tcg_gen_extu_i32_tl(reg, src);
 276     tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
 277     tcg_gen_andi_tl(reg, reg, 0x1);
 278 }
 279
 280 static inline void gen_cc_clear_icc(void)
 281 {
 282     tcg_gen_movi_i32(cpu_psr, 0);
 283 }
 284
 285 #ifdef TARGET_SPARC64
 286 static inline void gen_cc_clear_xcc(void)
 287 {
 288     tcg_gen_movi_i32(cpu_xcc, 0);
 289 }
 290 #endif
 291
 292 /* old op:
 293     if (!T0)
 294         env->psr |= PSR_ZERO;
 295     if ((int32_t) T0 < 0)
 296         env->psr |= PSR_NEG;
 297 */
 298 static inline void gen_cc_NZ_icc(TCGv dst)
 299 {
 300     TCGv r_temp;
 301     int l1, l2;
 302
 303     l1 = gen_new_label();
 304     l2 = gen_new_label();
 305     r_temp = tcg_temp_new(TCG_TYPE_TL);
 306     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 307     tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
 308     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
 309     gen_set_label(l1);
 310     tcg_gen_ext_i32_tl(r_temp, dst);
 311     tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
 312     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
 313     gen_set_label(l2);
 314 }
 315
 316 #ifdef TARGET_SPARC64
 317 static inline void gen_cc_NZ_xcc(TCGv dst)
 318 {
 319     int l1, l2;
 320
 321     l1 = gen_new_label();
 322     l2 = gen_new_label();
 323     tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
 324     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
 325     gen_set_label(l1);
 326     tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
 327     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
 328     gen_set_label(l2);
 329 }
 330 #endif
 331
 332 /* old op:
 333     if (T0 < src1)
 334         env->psr |= PSR_CARRY;
 335 */
 336 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
 337 {
 338     TCGv r_temp;
 339     int l1;
 340
 341     l1 = gen_new_label();
 342     r_temp = tcg_temp_new(TCG_TYPE_TL);
 343     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 344     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 345     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 346     gen_set_label(l1);
 347 }
 348
 349 #ifdef TARGET_SPARC64
 350 static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
 351 {
 352     int l1;
 353
 354     l1 = gen_new_label();
 355     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 356     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 357     gen_set_label(l1);
 358 }
 359 #endif
 360
 361 /* old op:
 362     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
 363         env->psr |= PSR_OVF;
 364 */
 365 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
 366 {
 367     TCGv r_temp;
 368
 369     r_temp = tcg_temp_new(TCG_TYPE_TL);
 370     tcg_gen_xor_tl(r_temp, src1, src2);
 371     tcg_gen_xori_tl(r_temp, r_temp, -1);
 372     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 373     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 374     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 375     tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
 376     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 377     tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
 378 }
 379
 380 #ifdef TARGET_SPARC64
 381 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
 382 {
 383     TCGv r_temp;
 384
 385     r_temp = tcg_temp_new(TCG_TYPE_TL);
 386     tcg_gen_xor_tl(r_temp, src1, src2);
 387     tcg_gen_xori_tl(r_temp, r_temp, -1);
 388     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 389     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 390     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 391     tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
 392     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 393     tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
 394 }
 395 #endif
 396
 397 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
 398 {
 399     TCGv r_temp;
 400     int l1;
 401
 402     l1 = gen_new_label();
 403
 404     r_temp = tcg_temp_new(TCG_TYPE_TL);
 405     tcg_gen_xor_tl(r_temp, src1, src2);
 406     tcg_gen_xori_tl(r_temp, r_temp, -1);
 407     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 408     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 409     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 410     tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
 411     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 412     gen_set_label(l1);
 413 }
 414
 415 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
 416 {
 417     int l1;
 418
 419     l1 = gen_new_label();
 420     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 421     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 422     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
 423     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 424     gen_set_label(l1);
 425 }
 426
 427 static inline void gen_tag_tv(TCGv src1, TCGv src2)
 428 {
 429     int l1;
 430
 431     l1 = gen_new_label();
 432     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 433     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 434     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
 435     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 436     gen_set_label(l1);
 437 }
 438
 439 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
 440 {
 441     tcg_gen_mov_tl(cpu_cc_src, src1);
 442     tcg_gen_mov_tl(cpu_cc_src2, src2);
 443     tcg_gen_add_tl(dst, src1, src2);
 444     tcg_gen_mov_tl(cpu_cc_dst, dst);
 445     gen_cc_clear_icc();
 446     gen_cc_NZ_icc(cpu_cc_dst);
 447     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 448     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 449 #ifdef TARGET_SPARC64
 450     gen_cc_clear_xcc();
 451     gen_cc_NZ_xcc(cpu_cc_dst);
 452     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 453     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 454 #endif
 455 }
 456
 457 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
 458 {
 459     tcg_gen_mov_tl(cpu_cc_src, src1);
 460     tcg_gen_mov_tl(cpu_cc_src2, src2);
 461     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 462     tcg_gen_add_tl(dst, src1, cpu_tmp0);
 463     gen_cc_clear_icc();
 464     gen_cc_C_add_icc(dst, cpu_cc_src);
 465 #ifdef TARGET_SPARC64
 466     gen_cc_clear_xcc();
 467     gen_cc_C_add_xcc(dst, cpu_cc_src);
 468 #endif
 469     tcg_gen_add_tl(dst, dst, cpu_cc_src2);
 470     tcg_gen_mov_tl(cpu_cc_dst, dst);
 471     gen_cc_NZ_icc(cpu_cc_dst);
 472     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 473     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 474 #ifdef TARGET_SPARC64
 475     gen_cc_NZ_xcc(cpu_cc_dst);
 476     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 477     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 478 #endif
 479 }
 480
 481 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
 482 {
 483     tcg_gen_mov_tl(cpu_cc_src, src1);
 484     tcg_gen_mov_tl(cpu_cc_src2, src2);
 485     tcg_gen_add_tl(dst, src1, src2);
 486     tcg_gen_mov_tl(cpu_cc_dst, dst);
 487     gen_cc_clear_icc();
 488     gen_cc_NZ_icc(cpu_cc_dst);
 489     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 490     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 491     gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
 492 #ifdef TARGET_SPARC64
 493     gen_cc_clear_xcc();
 494     gen_cc_NZ_xcc(cpu_cc_dst);
 495     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 496     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 497 #endif
 498 }
 499
 500 static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
 501 {
 502     tcg_gen_mov_tl(cpu_cc_src, src1);
 503     tcg_gen_mov_tl(cpu_cc_src2, src2);
 504     gen_tag_tv(cpu_cc_src, cpu_cc_src2);
 505     tcg_gen_add_tl(dst, src1, src2);
 506     tcg_gen_mov_tl(cpu_cc_dst, dst);
 507     gen_add_tv(dst, cpu_cc_src, cpu_cc_src2);
 508     gen_cc_clear_icc();
 509     gen_cc_NZ_icc(cpu_cc_dst);
 510     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 511 #ifdef TARGET_SPARC64
 512     gen_cc_clear_xcc();
 513     gen_cc_NZ_xcc(cpu_cc_dst);
 514     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 515     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 516 #endif
 517 }
 518
 519 /* old op:
 520     if (src1 < T1)
 521         env->psr |= PSR_CARRY;
 522 */
 523 static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
 524 {
 525     TCGv r_temp1, r_temp2;
 526     int l1;
 527
 528     l1 = gen_new_label();
 529     r_temp1 = tcg_temp_new(TCG_TYPE_TL);
 530     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 531     tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
 532     tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
 533     tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
 534     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 535     gen_set_label(l1);
 536 }
 537
 538 #ifdef TARGET_SPARC64
 539 static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
 540 {
 541     int l1;
 542
 543     l1 = gen_new_label();
 544     tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
 545     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 546     gen_set_label(l1);
 547 }
 548 #endif
 549
 550 /* old op:
 551     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
 552         env->psr |= PSR_OVF;
 553 */
 554 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
 555 {
 556     TCGv r_temp;
 557
 558     r_temp = tcg_temp_new(TCG_TYPE_TL);
 559     tcg_gen_xor_tl(r_temp, src1, src2);
 560     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 561     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 562     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 563     tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
 564     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 565     tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
 566 }
 567
 568 #ifdef TARGET_SPARC64
 569 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
 570 {
 571     TCGv r_temp;
 572
 573     r_temp = tcg_temp_new(TCG_TYPE_TL);
 574     tcg_gen_xor_tl(r_temp, src1, src2);
 575     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 576     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 577     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 578     tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
 579     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 580     tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
 581 }
 582 #endif
 583
 584 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
 585 {
 586     TCGv r_temp;
 587     int l1;
 588
 589     l1 = gen_new_label();
 590
 591     r_temp = tcg_temp_new(TCG_TYPE_TL);
 592     tcg_gen_xor_tl(r_temp, src1, src2);
 593     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 594     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 595     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 596     tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
 597     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
 598     gen_set_label(l1);
 599 }
 600
 601 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
 602 {
 603     tcg_gen_mov_tl(cpu_cc_src, src1);
 604     tcg_gen_mov_tl(cpu_cc_src2, src2);
 605     tcg_gen_sub_tl(dst, src1, src2);
 606     tcg_gen_mov_tl(cpu_cc_dst, dst);
 607     gen_cc_clear_icc();
 608     gen_cc_NZ_icc(cpu_cc_dst);
 609     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 610     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 611 #ifdef TARGET_SPARC64
 612     gen_cc_clear_xcc();
 613     gen_cc_NZ_xcc(cpu_cc_dst);
 614     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 615     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 616 #endif
 617 }
 618
 619 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
 620 {
 621     tcg_gen_mov_tl(cpu_cc_src, src1);
 622     tcg_gen_mov_tl(cpu_cc_src2, src2);
 623     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 624     tcg_gen_sub_tl(dst, src1, cpu_tmp0);
 625     gen_cc_clear_icc();
 626     gen_cc_C_sub_icc(dst, cpu_cc_src);
 627 #ifdef TARGET_SPARC64
 628     gen_cc_clear_xcc();
 629     gen_cc_C_sub_xcc(dst, cpu_cc_src);
 630 #endif
 631     tcg_gen_sub_tl(dst, dst, cpu_cc_src2);
 632     tcg_gen_mov_tl(cpu_cc_dst, dst);
 633     gen_cc_NZ_icc(cpu_cc_dst);
 634     gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
 635     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 636 #ifdef TARGET_SPARC64
 637     gen_cc_NZ_xcc(cpu_cc_dst);
 638     gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
 639     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 640 #endif
 641 }
 642
 643 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
 644 {
 645     tcg_gen_mov_tl(cpu_cc_src, src1);
 646     tcg_gen_mov_tl(cpu_cc_src2, src2);
 647     tcg_gen_sub_tl(dst, src1, src2);
 648     tcg_gen_mov_tl(cpu_cc_dst, dst);
 649     gen_cc_clear_icc();
 650     gen_cc_NZ_icc(cpu_cc_dst);
 651     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 652     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 653     gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
 654 #ifdef TARGET_SPARC64
 655     gen_cc_clear_xcc();
 656     gen_cc_NZ_xcc(cpu_cc_dst);
 657     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 658     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 659 #endif
 660 }
 661
 662 static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
 663 {
 664     tcg_gen_mov_tl(cpu_cc_src, src1);
 665     tcg_gen_mov_tl(cpu_cc_src2, src2);
 666     gen_tag_tv(cpu_cc_src, cpu_cc_src2);
 667     tcg_gen_sub_tl(dst, src1, src2);
 668     tcg_gen_mov_tl(cpu_cc_dst, dst);
 669     gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2);
 670     gen_cc_clear_icc();
 671     gen_cc_NZ_icc(cpu_cc_dst);
 672     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 673 #ifdef TARGET_SPARC64
 674     gen_cc_clear_xcc();
 675     gen_cc_NZ_xcc(cpu_cc_dst);
 676     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 677     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 678 #endif
 679 }
 680
 681 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
 682 {
 683     TCGv r_temp, r_temp2;
 684     int l1;
 685
 686     l1 = gen_new_label();
 687     r_temp = tcg_temp_new(TCG_TYPE_TL);
 688     r_temp2 = tcg_temp_new(TCG_TYPE_I32);
 689
 690     /* old op:
 691     if (!(env->y & 1))
 692         T1 = 0;
 693     */
 694     tcg_gen_mov_tl(cpu_cc_src, src1);
 695     tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 696     tcg_gen_trunc_tl_i32(r_temp2, r_temp);
 697     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 698     tcg_gen_mov_tl(cpu_cc_src2, src2);
 699     tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
 700     tcg_gen_movi_tl(cpu_cc_src2, 0);
 701     gen_set_label(l1);
 702
 703     // b2 = T0 & 1;
 704     // env->y = (b2 << 31) | (env->y >> 1);
 705     tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
 706     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 707     tcg_gen_shli_i32(r_temp2, r_temp2, 31);
 708     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 709     tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
 710     tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
 711     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 712
 713     // b1 = N ^ V;
 714     gen_mov_reg_N(cpu_tmp0, cpu_psr);
 715     gen_mov_reg_V(r_temp, cpu_psr);
 716     tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
 717
 718     // T0 = (b1 << 31) | (T0 >> 1);
 719     // src1 = T0;
 720     tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
 721     tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
 722     tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
 723
 724     /* do addition and update flags */
 725     tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
 726     tcg_gen_mov_tl(cpu_cc_dst, dst);
 727
 728     gen_cc_clear_icc();
 729     gen_cc_NZ_icc(cpu_cc_dst);
 730     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 731     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 732 }
 733
 734 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
 735 {
 736     TCGv r_temp, r_temp2;
 737
 738     r_temp = tcg_temp_new(TCG_TYPE_I64);
 739     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 740
 741     tcg_gen_extu_tl_i64(r_temp, src2);
 742     tcg_gen_extu_tl_i64(r_temp2, src1);
 743     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 744
 745     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 746     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 747     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 748 #ifdef TARGET_SPARC64
 749     tcg_gen_mov_i64(dst, r_temp2);
 750 #else
 751     tcg_gen_trunc_i64_tl(dst, r_temp2);
 752 #endif
 753 }
 754
 755 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
 756 {
 757     TCGv r_temp, r_temp2;
 758
 759     r_temp = tcg_temp_new(TCG_TYPE_I64);
 760     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 761
 762     tcg_gen_ext_tl_i64(r_temp, src2);
 763     tcg_gen_ext_tl_i64(r_temp2, src1);
 764     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 765
 766     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 767     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 768     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 769 #ifdef TARGET_SPARC64
 770     tcg_gen_mov_i64(dst, r_temp2);
 771 #else
 772     tcg_gen_trunc_i64_tl(dst, r_temp2);
 773 #endif
 774 }
 775
 776 #ifdef TARGET_SPARC64
 777 static inline void gen_trap_ifdivzero_tl(TCGv divisor)
 778 {
 779     int l1;
 780
 781     l1 = gen_new_label();
 782     tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
 783     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO));
 784     gen_set_label(l1);
 785 }
 786
 787 static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
 788 {
 789     int l1, l2;
 790
 791     l1 = gen_new_label();
 792     l2 = gen_new_label();
 793     tcg_gen_mov_tl(cpu_cc_src, src1);
 794     tcg_gen_mov_tl(cpu_cc_src2, src2);
 795     gen_trap_ifdivzero_tl(src2);
 796     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
 797     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
 798     tcg_gen_movi_i64(dst, INT64_MIN);
 799     tcg_gen_br(l2);
 800     gen_set_label(l1);
 801     tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
 802     gen_set_label(l2);
 803 }
 804 #endif
 805
 806 static inline void gen_op_div_cc(TCGv dst)
 807 {
 808     int l1;
 809
 810     tcg_gen_mov_tl(cpu_cc_dst, dst);
 811     gen_cc_clear_icc();
 812     gen_cc_NZ_icc(cpu_cc_dst);
 813     l1 = gen_new_label();
 814     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
 815     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
 816     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 817     gen_set_label(l1);
 818 }
 819
 820 static inline void gen_op_logic_cc(TCGv dst)
 821 {
 822     tcg_gen_mov_tl(cpu_cc_dst, dst);
 823
 824     gen_cc_clear_icc();
 825     gen_cc_NZ_icc(cpu_cc_dst);
 826 #ifdef TARGET_SPARC64
 827     gen_cc_clear_xcc();
 828     gen_cc_NZ_xcc(cpu_cc_dst);
 829 #endif
 830 }
 831
 832 // 1
 833 static inline void gen_op_eval_ba(TCGv dst)
 834 {
 835     tcg_gen_movi_tl(dst, 1);
 836 }
 837
 838 // Z
 839 static inline void gen_op_eval_be(TCGv dst, TCGv src)
 840 {
 841     gen_mov_reg_Z(dst, src);
 842 }
 843
 844 // Z | (N ^ V)
 845 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
 846 {
 847     gen_mov_reg_N(cpu_tmp0, src);
 848     gen_mov_reg_V(dst, src);
 849     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 850     gen_mov_reg_Z(cpu_tmp0, src);
 851     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 852 }
 853
 854 // N ^ V
 855 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
 856 {
 857     gen_mov_reg_V(cpu_tmp0, src);
 858     gen_mov_reg_N(dst, src);
 859     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 860 }
 861
 862 // C | Z
 863 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
 864 {
 865     gen_mov_reg_Z(cpu_tmp0, src);
 866     gen_mov_reg_C(dst, src);
 867     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 868 }
 869
 870 // C
 871 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
 872 {
 873     gen_mov_reg_C(dst, src);
 874 }
 875
 876 // V
 877 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
 878 {
 879     gen_mov_reg_V(dst, src);
 880 }
 881
 882 // 0
 883 static inline void gen_op_eval_bn(TCGv dst)
 884 {
 885     tcg_gen_movi_tl(dst, 0);
 886 }
 887
 888 // N
 889 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
 890 {
 891     gen_mov_reg_N(dst, src);
 892 }
 893
 894 // !Z
 895 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
 896 {
 897     gen_mov_reg_Z(dst, src);
 898     tcg_gen_xori_tl(dst, dst, 0x1);
 899 }
 900
 901 // !(Z | (N ^ V))
 902 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
 903 {
 904     gen_mov_reg_N(cpu_tmp0, src);
 905     gen_mov_reg_V(dst, src);
 906     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 907     gen_mov_reg_Z(cpu_tmp0, src);
 908     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 909     tcg_gen_xori_tl(dst, dst, 0x1);
 910 }
 911
 912 // !(N ^ V)
 913 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
 914 {
 915     gen_mov_reg_V(cpu_tmp0, src);
 916     gen_mov_reg_N(dst, src);
 917     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 918     tcg_gen_xori_tl(dst, dst, 0x1);
 919 }
 920
 921 // !(C | Z)
 922 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
 923 {
 924     gen_mov_reg_Z(cpu_tmp0, src);
 925     gen_mov_reg_C(dst, src);
 926     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 927     tcg_gen_xori_tl(dst, dst, 0x1);
 928 }
 929
 930 // !C
 931 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
 932 {
 933     gen_mov_reg_C(dst, src);
 934     tcg_gen_xori_tl(dst, dst, 0x1);
 935 }
 936
 937 // !N
 938 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
 939 {
 940     gen_mov_reg_N(dst, src);
 941     tcg_gen_xori_tl(dst, dst, 0x1);
 942 }
 943
 944 // !V
 945 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
 946 {
 947     gen_mov_reg_V(dst, src);
 948     tcg_gen_xori_tl(dst, dst, 0x1);
 949 }
 950
 951 /*
 952   FPSR bit field FCC1 | FCC0:
 953    0 =
 954    1 <
 955    2 >
 956    3 unordered
 957 */
 958 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
 959                                     unsigned int fcc_offset)
 960 {
 961     tcg_gen_extu_i32_tl(reg, src);
 962     tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
 963     tcg_gen_andi_tl(reg, reg, 0x1);
 964 }
 965
 966 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
 967                                     unsigned int fcc_offset)
 968 {
 969     tcg_gen_extu_i32_tl(reg, src);
 970     tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
 971     tcg_gen_andi_tl(reg, reg, 0x1);
 972 }
 973
 974 // !0: FCC0 | FCC1
 975 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
 976                                     unsigned int fcc_offset)
 977 {
 978     gen_mov_reg_FCC0(dst, src, fcc_offset);
 979     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
 980     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 981 }
 982
 983 // 1 or 2: FCC0 ^ FCC1
 984 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
 985                                     unsigned int fcc_offset)
 986 {
 987     gen_mov_reg_FCC0(dst, src, fcc_offset);
 988     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
 989     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 990 }
 991
 992 // 1 or 3: FCC0
 993 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
 994                                     unsigned int fcc_offset)
 995 {
 996     gen_mov_reg_FCC0(dst, src, fcc_offset);
 997 }
 998
 999 // 1: FCC0 & !FCC1
1000 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1001                                     unsigned int fcc_offset)
1002 {
1003     gen_mov_reg_FCC0(dst, src, fcc_offset);
1004     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1005     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1006     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1007 }
1008
1009 // 2 or 3: FCC1
1010 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1011                                     unsigned int fcc_offset)
1012 {
1013     gen_mov_reg_FCC1(dst, src, fcc_offset);
1014 }
1015
1016 // 2: !FCC0 & FCC1
1017 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1018                                     unsigned int fcc_offset)
1019 {
1020     gen_mov_reg_FCC0(dst, src, fcc_offset);
1021     tcg_gen_xori_tl(dst, dst, 0x1);
1022     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1023     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1024 }
1025
1026 // 3: FCC0 & FCC1
1027 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1028                                     unsigned int fcc_offset)
1029 {
1030     gen_mov_reg_FCC0(dst, src, fcc_offset);
1031     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1032     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1033 }
1034
1035 // 0: !(FCC0 | FCC1)
1036 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1037                                     unsigned int fcc_offset)
1038 {
1039     gen_mov_reg_FCC0(dst, src, fcc_offset);
1040     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1041     tcg_gen_or_tl(dst, dst, cpu_tmp0);
1042     tcg_gen_xori_tl(dst, dst, 0x1);
1043 }
1044
1045 // 0 or 3: !(FCC0 ^ FCC1)
1046 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1047                                     unsigned int fcc_offset)
1048 {
1049     gen_mov_reg_FCC0(dst, src, fcc_offset);
1050     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1051     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1052     tcg_gen_xori_tl(dst, dst, 0x1);
1053 }
1054
1055 // 0 or 2: !FCC0
1056 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1057                                     unsigned int fcc_offset)
1058 {
1059     gen_mov_reg_FCC0(dst, src, fcc_offset);
1060     tcg_gen_xori_tl(dst, dst, 0x1);
1061 }
1062
1063 // !1: !(FCC0 & !FCC1)
1064 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1065                                     unsigned int fcc_offset)
1066 {
1067     gen_mov_reg_FCC0(dst, src, fcc_offset);
1068     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1069     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1070     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1071     tcg_gen_xori_tl(dst, dst, 0x1);
1072 }
1073
1074 // 0 or 1: !FCC1
1075 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1076                                     unsigned int fcc_offset)
1077 {
1078     gen_mov_reg_FCC1(dst, src, fcc_offset);
1079     tcg_gen_xori_tl(dst, dst, 0x1);
1080 }
1081
1082 // !2: !(!FCC0 & FCC1)
1083 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1084                                     unsigned int fcc_offset)
1085 {
1086     gen_mov_reg_FCC0(dst, src, fcc_offset);
1087     tcg_gen_xori_tl(dst, dst, 0x1);
1088     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1089     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1090     tcg_gen_xori_tl(dst, dst, 0x1);
1091 }
1092
1093 // !3: !(FCC0 & FCC1)
1094 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1095                                     unsigned int fcc_offset)
1096 {
1097     gen_mov_reg_FCC0(dst, src, fcc_offset);
1098     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1099     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1100     tcg_gen_xori_tl(dst, dst, 0x1);
1101 }
1102
1103 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1104                                target_ulong pc2, TCGv r_cond)
1105 {
1106     int l1;
1107
1108     l1 = gen_new_label();
1109
1110     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1111
1112     gen_goto_tb(dc, 0, pc1, pc1 + 4);
1113
1114     gen_set_label(l1);
1115     gen_goto_tb(dc, 1, pc2, pc2 + 4);
1116 }
1117
1118 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1119                                 target_ulong pc2, TCGv r_cond)
1120 {
1121     int l1;
1122
1123     l1 = gen_new_label();
1124
1125     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1126
1127     gen_goto_tb(dc, 0, pc2, pc1);
1128
1129     gen_set_label(l1);
1130     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1131 }
1132
1133 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1134                                       TCGv r_cond)
1135 {
1136     int l1, l2;
1137
1138     l1 = gen_new_label();
1139     l2 = gen_new_label();
1140
1141     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1142
1143     tcg_gen_movi_tl(cpu_npc, npc1);
1144     tcg_gen_br(l2);
1145
1146     gen_set_label(l1);
1147     tcg_gen_movi_tl(cpu_npc, npc2);
1148     gen_set_label(l2);
1149 }
1150
1151 /* call this function before using the condition register as it may
1152    have been set for a jump */
1153 static inline void flush_cond(DisasContext *dc, TCGv cond)
1154 {
1155     if (dc->npc == JUMP_PC) {
1156         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1157         dc->npc = DYNAMIC_PC;
1158     }
1159 }
1160
1161 static inline void save_npc(DisasContext *dc, TCGv cond)
1162 {
1163     if (dc->npc == JUMP_PC) {
1164         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1165         dc->npc = DYNAMIC_PC;
1166     } else if (dc->npc != DYNAMIC_PC) {
1167         tcg_gen_movi_tl(cpu_npc, dc->npc);
1168     }
1169 }
1170
1171 static inline void save_state(DisasContext *dc, TCGv cond)
1172 {
1173     tcg_gen_movi_tl(cpu_pc, dc->pc);
1174     save_npc(dc, cond);
1175 }
1176
1177 static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1178 {
1179     if (dc->npc == JUMP_PC) {
1180         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1181         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1182         dc->pc = DYNAMIC_PC;
1183     } else if (dc->npc == DYNAMIC_PC) {
1184         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1185         dc->pc = DYNAMIC_PC;
1186     } else {
1187         dc->pc = dc->npc;
1188     }
1189 }
1190
1191 static inline void gen_op_next_insn(void)
1192 {
1193     tcg_gen_mov_tl(cpu_pc, cpu_npc);
1194     tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1195 }
1196
1197 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1198 {
1199     TCGv r_src;
1200
1201 #ifdef TARGET_SPARC64
1202     if (cc)
1203         r_src = cpu_xcc;
1204     else
1205         r_src = cpu_psr;
1206 #else
1207     r_src = cpu_psr;
1208 #endif
1209     switch (cond) {
1210     case 0x0:
1211         gen_op_eval_bn(r_dst);
1212         break;
1213     case 0x1:
1214         gen_op_eval_be(r_dst, r_src);
1215         break;
1216     case 0x2:
1217         gen_op_eval_ble(r_dst, r_src);
1218         break;
1219     case 0x3:
1220         gen_op_eval_bl(r_dst, r_src);
1221         break;
1222     case 0x4:
1223         gen_op_eval_bleu(r_dst, r_src);
1224         break;
1225     case 0x5:
1226         gen_op_eval_bcs(r_dst, r_src);
1227         break;
1228     case 0x6:
1229         gen_op_eval_bneg(r_dst, r_src);
1230         break;
1231     case 0x7:
1232         gen_op_eval_bvs(r_dst, r_src);
1233         break;
1234     case 0x8:
1235         gen_op_eval_ba(r_dst);
1236         break;
1237     case 0x9:
1238         gen_op_eval_bne(r_dst, r_src);
1239         break;
1240     case 0xa:
1241         gen_op_eval_bg(r_dst, r_src);
1242         break;
1243     case 0xb:
1244         gen_op_eval_bge(r_dst, r_src);
1245         break;
1246     case 0xc:
1247         gen_op_eval_bgu(r_dst, r_src);
1248         break;
1249     case 0xd:
1250         gen_op_eval_bcc(r_dst, r_src);
1251         break;
1252     case 0xe:
1253         gen_op_eval_bpos(r_dst, r_src);
1254         break;
1255     case 0xf:
1256         gen_op_eval_bvc(r_dst, r_src);
1257         break;
1258     }
1259 }
1260
1261 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1262 {
1263     unsigned int offset;
1264
1265     switch (cc) {
1266     default:
1267     case 0x0:
1268         offset = 0;
1269         break;
1270     case 0x1:
1271         offset = 32 - 10;
1272         break;
1273     case 0x2:
1274         offset = 34 - 10;
1275         break;
1276     case 0x3:
1277         offset = 36 - 10;
1278         break;
1279     }
1280
1281     switch (cond) {
1282     case 0x0:
1283         gen_op_eval_bn(r_dst);
1284         break;
1285     case 0x1:
1286         gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1287         break;
1288     case 0x2:
1289         gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1290         break;
1291     case 0x3:
1292         gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1293         break;
1294     case 0x4:
1295         gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1296         break;
1297     case 0x5:
1298         gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1299         break;
1300     case 0x6:
1301         gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1302         break;
1303     case 0x7:
1304         gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1305         break;
1306     case 0x8:
1307         gen_op_eval_ba(r_dst);
1308         break;
1309     case 0x9:
1310         gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1311         break;
1312     case 0xa:
1313         gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1314         break;
1315     case 0xb:
1316         gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1317         break;
1318     case 0xc:
1319         gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1320         break;
1321     case 0xd:
1322         gen_op_eval_fble(r_dst, cpu_fsr, offset);
1323         break;
1324     case 0xe:
1325         gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1326         break;
1327     case 0xf:
1328         gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1329         break;
1330     }
1331 }
1332
1333 #ifdef TARGET_SPARC64
1334 // Inverted logic
1335 static const int gen_tcg_cond_reg[8] = {
1336     -1,
1337     TCG_COND_NE,
1338     TCG_COND_GT,
1339     TCG_COND_GE,
1340     -1,
1341     TCG_COND_EQ,
1342     TCG_COND_LE,
1343     TCG_COND_LT,
1344 };
1345
1346 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1347 {
1348     int l1;
1349
1350     l1 = gen_new_label();
1351     tcg_gen_movi_tl(r_dst, 0);
1352     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1353     tcg_gen_movi_tl(r_dst, 1);
1354     gen_set_label(l1);
1355 }
1356 #endif
1357
1358 /* XXX: potentially incorrect if dynamic npc */
1359 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1360                       TCGv r_cond)
1361 {
1362     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1363     target_ulong target = dc->pc + offset;
1364
1365     if (cond == 0x0) {
1366         /* unconditional not taken */
1367         if (a) {
1368             dc->pc = dc->npc + 4;
1369             dc->npc = dc->pc + 4;
1370         } else {
1371             dc->pc = dc->npc;
1372             dc->npc = dc->pc + 4;
1373         }
1374     } else if (cond == 0x8) {
1375         /* unconditional taken */
1376         if (a) {
1377             dc->pc = target;
1378             dc->npc = dc->pc + 4;
1379         } else {
1380             dc->pc = dc->npc;
1381             dc->npc = target;
1382         }
1383     } else {
1384         flush_cond(dc, r_cond);
1385         gen_cond(r_cond, cc, cond);
1386         if (a) {
1387             gen_branch_a(dc, target, dc->npc, r_cond);
1388             dc->is_br = 1;
1389         } else {
1390             dc->pc = dc->npc;
1391             dc->jump_pc[0] = target;
1392             dc->jump_pc[1] = dc->npc + 4;
1393             dc->npc = JUMP_PC;
1394         }
1395     }
1396 }
1397
1398 /* XXX: potentially incorrect if dynamic npc */
1399 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1400                       TCGv r_cond)
1401 {
1402     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1403     target_ulong target = dc->pc + offset;
1404
1405     if (cond == 0x0) {
1406         /* unconditional not taken */
1407         if (a) {
1408             dc->pc = dc->npc + 4;
1409             dc->npc = dc->pc + 4;
1410         } else {
1411             dc->pc = dc->npc;
1412             dc->npc = dc->pc + 4;
1413         }
1414     } else if (cond == 0x8) {
1415         /* unconditional taken */
1416         if (a) {
1417             dc->pc = target;
1418             dc->npc = dc->pc + 4;
1419         } else {
1420             dc->pc = dc->npc;
1421             dc->npc = target;
1422         }
1423     } else {
1424         flush_cond(dc, r_cond);
1425         gen_fcond(r_cond, cc, cond);
1426         if (a) {
1427             gen_branch_a(dc, target, dc->npc, r_cond);
1428             dc->is_br = 1;
1429         } else {
1430             dc->pc = dc->npc;
1431             dc->jump_pc[0] = target;
1432             dc->jump_pc[1] = dc->npc + 4;
1433             dc->npc = JUMP_PC;
1434         }
1435     }
1436 }
1437
1438 #ifdef TARGET_SPARC64
1439 /* XXX: potentially incorrect if dynamic npc */
1440 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1441                           TCGv r_cond, TCGv r_reg)
1442 {
1443     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1444     target_ulong target = dc->pc + offset;
1445
1446     flush_cond(dc, r_cond);
1447     gen_cond_reg(r_cond, cond, r_reg);
1448     if (a) {
1449         gen_branch_a(dc, target, dc->npc, r_cond);
1450         dc->is_br = 1;
1451     } else {
1452         dc->pc = dc->npc;
1453         dc->jump_pc[0] = target;
1454         dc->jump_pc[1] = dc->npc + 4;
1455         dc->npc = JUMP_PC;
1456     }
1457 }
1458
1459 static GenOpFunc * const gen_fcmps[4] = {
1460     helper_fcmps,
1461     helper_fcmps_fcc1,
1462     helper_fcmps_fcc2,
1463     helper_fcmps_fcc3,
1464 };
1465
1466 static GenOpFunc * const gen_fcmpd[4] = {
1467     helper_fcmpd,
1468     helper_fcmpd_fcc1,
1469     helper_fcmpd_fcc2,
1470     helper_fcmpd_fcc3,
1471 };
1472
1473 static GenOpFunc * const gen_fcmpq[4] = {
1474     helper_fcmpq,
1475     helper_fcmpq_fcc1,
1476     helper_fcmpq_fcc2,
1477     helper_fcmpq_fcc3,
1478 };
1479
1480 static GenOpFunc * const gen_fcmpes[4] = {
1481     helper_fcmpes,
1482     helper_fcmpes_fcc1,
1483     helper_fcmpes_fcc2,
1484     helper_fcmpes_fcc3,
1485 };
1486
1487 static GenOpFunc * const gen_fcmped[4] = {
1488     helper_fcmped,
1489     helper_fcmped_fcc1,
1490     helper_fcmped_fcc2,
1491     helper_fcmped_fcc3,
1492 };
1493
1494 static GenOpFunc * const gen_fcmpeq[4] = {
1495     helper_fcmpeq,
1496     helper_fcmpeq_fcc1,
1497     helper_fcmpeq_fcc2,
1498     helper_fcmpeq_fcc3,
1499 };
1500
1501 static inline void gen_op_fcmps(int fccno)
1502 {
1503     tcg_gen_helper_0_0(gen_fcmps[fccno]);
1504 }
1505
1506 static inline void gen_op_fcmpd(int fccno)
1507 {
1508     tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1509 }
1510
1511 static inline void gen_op_fcmpq(int fccno)
1512 {
1513     tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1514 }
1515
1516 static inline void gen_op_fcmpes(int fccno)
1517 {
1518     tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1519 }
1520
1521 static inline void gen_op_fcmped(int fccno)
1522 {
1523     tcg_gen_helper_0_0(gen_fcmped[fccno]);
1524 }
1525
1526 static inline void gen_op_fcmpeq(int fccno)
1527 {
1528     tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1529 }
1530
1531 #else
1532
1533 static inline void gen_op_fcmps(int fccno)
1534 {
1535     tcg_gen_helper_0_0(helper_fcmps);
1536 }
1537
1538 static inline void gen_op_fcmpd(int fccno)
1539 {
1540     tcg_gen_helper_0_0(helper_fcmpd);
1541 }
1542
1543 static inline void gen_op_fcmpq(int fccno)
1544 {
1545     tcg_gen_helper_0_0(helper_fcmpq);
1546 }
1547
1548 static inline void gen_op_fcmpes(int fccno)
1549 {
1550     tcg_gen_helper_0_0(helper_fcmpes);
1551 }
1552
1553 static inline void gen_op_fcmped(int fccno)
1554 {
1555     tcg_gen_helper_0_0(helper_fcmped);
1556 }
1557
1558 static inline void gen_op_fcmpeq(int fccno)
1559 {
1560     tcg_gen_helper_0_0(helper_fcmpeq);
1561 }
1562 #endif
1563
1564 static inline void gen_op_fpexception_im(int fsr_flags)
1565 {
1566     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1567     tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1568     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
1569 }
1570
1571 static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1572 {
1573 #if !defined(CONFIG_USER_ONLY)
1574     if (!dc->fpu_enabled) {
1575         save_state(dc, r_cond);
1576         tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
1577         dc->is_br = 1;
1578         return 1;
1579     }
1580 #endif
1581     return 0;
1582 }
1583
1584 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1585 {
1586     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1587 }
1588
1589 static inline void gen_clear_float_exceptions(void)
1590 {
1591     tcg_gen_helper_0_0(helper_clear_float_exceptions);
1592 }
1593
1594 /* asi moves */
1595 #ifdef TARGET_SPARC64
1596 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1597 {
1598     int asi, offset;
1599     TCGv r_asi;
1600
1601     if (IS_IMM) {
1602         r_asi = tcg_temp_new(TCG_TYPE_I32);
1603         offset = GET_FIELD(insn, 25, 31);
1604         tcg_gen_addi_tl(r_addr, r_addr, offset);
1605         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1606     } else {
1607         asi = GET_FIELD(insn, 19, 26);
1608         r_asi = tcg_const_i32(asi);
1609     }
1610     return r_asi;
1611 }
1612
1613 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1614                               int sign)
1615 {
1616     TCGv r_asi;
1617
1618     r_asi = gen_get_asi(insn, addr);
1619     tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi,
1620                        tcg_const_i32(size), tcg_const_i32(sign));
1621 }
1622
1623 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1624 {
1625     TCGv r_asi;
1626
1627     r_asi = gen_get_asi(insn, addr);
1628     tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, tcg_const_i32(size));
1629 }
1630
1631 static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1632 {
1633     TCGv r_asi;
1634
1635     r_asi = gen_get_asi(insn, addr);
1636     tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, tcg_const_i32(size),
1637                        tcg_const_i32(rd));
1638 }
1639
1640 static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1641 {
1642     TCGv r_asi;
1643
1644     r_asi = gen_get_asi(insn, addr);
1645     tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, tcg_const_i32(size),
1646                        tcg_const_i32(rd));
1647 }
1648
1649 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1650 {
1651     TCGv r_temp, r_asi;
1652
1653     r_temp = tcg_temp_new(TCG_TYPE_I32);
1654     r_asi = gen_get_asi(insn, addr);
1655     tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, r_asi,
1656                        tcg_const_i32(4), tcg_const_i32(0));
1657     tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi,
1658                        tcg_const_i32(4));
1659     tcg_gen_extu_i32_tl(dst, r_temp);
1660 }
1661
1662 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1663 {
1664     TCGv r_asi;
1665
1666     r_asi = gen_get_asi(insn, addr);
1667     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi,
1668                        tcg_const_i32(8), tcg_const_i32(0));
1669     tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1670     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1671     tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1672 }
1673
1674 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1675 {
1676     TCGv r_temp, r_asi;
1677
1678     r_temp = tcg_temp_new(TCG_TYPE_I32);
1679     gen_movl_reg_TN(rd + 1, r_temp);
1680     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1681                        r_temp);
1682     r_asi = gen_get_asi(insn, addr);
1683     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi,
1684                        tcg_const_i32(8));
1685 }
1686
1687 static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1688                                int rd)
1689 {
1690     TCGv r_val1, r_asi;
1691
1692     r_val1 = tcg_temp_new(TCG_TYPE_TL);
1693     gen_movl_reg_TN(rd, r_val1);
1694     r_asi = gen_get_asi(insn, addr);
1695     tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1696 }
1697
1698 static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1699                                 int rd)
1700 {
1701     TCGv r_asi;
1702
1703     gen_movl_reg_TN(rd, cpu_tmp64);
1704     r_asi = gen_get_asi(insn, addr);
1705     tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1706 }
1707
1708 #elif !defined(CONFIG_USER_ONLY)
1709
1710 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1711                               int sign)
1712 {
1713     int asi;
1714
1715     asi = GET_FIELD(insn, 19, 26);
1716     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1717                        tcg_const_i32(size), tcg_const_i32(sign));
1718     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1719 }
1720
1721 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1722 {
1723     int asi;
1724
1725     tcg_gen_extu_tl_i64(cpu_tmp64, src);
1726     asi = GET_FIELD(insn, 19, 26);
1727     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1728                        tcg_const_i32(size));
1729 }
1730
1731 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1732 {
1733     int asi;
1734     TCGv r_temp;
1735
1736     r_temp = tcg_temp_new(TCG_TYPE_I32);
1737     asi = GET_FIELD(insn, 19, 26);
1738     tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, tcg_const_i32(asi),
1739                        tcg_const_i32(4), tcg_const_i32(0));
1740     tcg_gen_helper_0_4(helper_st_asi, addr, dst, tcg_const_i32(asi),
1741                        tcg_const_i32(4));
1742     tcg_gen_extu_i32_tl(dst, r_temp);
1743 }
1744
1745 static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1746 {
1747     int asi;
1748
1749     asi = GET_FIELD(insn, 19, 26);
1750     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1751                        tcg_const_i32(8), tcg_const_i32(0));
1752     tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1753     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1754     tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1755 }
1756
1757 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1758 {
1759     int asi;
1760     TCGv r_temp;
1761
1762     r_temp = tcg_temp_new(TCG_TYPE_I32);
1763     gen_movl_reg_TN(rd + 1, r_temp);
1764     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1765     asi = GET_FIELD(insn, 19, 26);
1766     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1767                        tcg_const_i32(8));
1768 }
1769 #endif
1770
1771 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1772 static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1773 {
1774     int asi;
1775
1776     gen_ld_asi(dst, addr, insn, 1, 0);
1777
1778     asi = GET_FIELD(insn, 19, 26);
1779     tcg_gen_helper_0_4(helper_st_asi, addr, tcg_const_i64(0xffULL),
1780                        tcg_const_i32(asi), tcg_const_i32(1));
1781 }
1782 #endif
1783
1784 static inline TCGv get_src1(unsigned int insn, TCGv def)
1785 {
1786     TCGv r_rs1 = def;
1787     unsigned int rs1;
1788
1789     rs1 = GET_FIELD(insn, 13, 17);
1790     if (rs1 == 0)
1791         //r_rs1 = tcg_const_tl(0);
1792         tcg_gen_movi_tl(def, 0);
1793     else if (rs1 < 8)
1794         //r_rs1 = cpu_gregs[rs1];
1795         tcg_gen_mov_tl(def, cpu_gregs[rs1]);
1796     else
1797         tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1798     return r_rs1;
1799 }
1800
1801 static inline TCGv get_src2(unsigned int insn, TCGv def)
1802 {
1803     TCGv r_rs2 = def;
1804     unsigned int rs2;
1805
1806     if (IS_IMM) { /* immediate */
1807         rs2 = GET_FIELDs(insn, 19, 31);
1808         r_rs2 = tcg_const_tl((int)rs2);
1809     } else { /* register */
1810         rs2 = GET_FIELD(insn, 27, 31);
1811         if (rs2 == 0)
1812             r_rs2 = tcg_const_tl(0);
1813         else if (rs2 < 8)
1814             r_rs2 = cpu_gregs[rs2];
1815         else
1816             tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1817     }
1818     return r_rs2;
1819 }
1820
1821 #define CHECK_IU_FEATURE(dc, FEATURE)                      \
1822     if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1823         goto illegal_insn;
1824 #define CHECK_FPU_FEATURE(dc, FEATURE)                     \
1825     if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1826         goto nfpu_insn;
1827
1828 /* before an instruction, dc->pc must be static */
1829 static void disas_sparc_insn(DisasContext * dc)
1830 {
1831     unsigned int insn, opc, rs1, rs2, rd;
1832
1833     if (unlikely(loglevel & CPU_LOG_TB_OP))
1834         tcg_gen_debug_insn_start(dc->pc);
1835     insn = ldl_code(dc->pc);
1836     opc = GET_FIELD(insn, 0, 1);
1837
1838     rd = GET_FIELD(insn, 2, 6);
1839
1840     cpu_dst = cpu_T[0];
1841     cpu_src1 = cpu_T[0]; // const
1842     cpu_src2 = cpu_T[1]; // const
1843
1844     // loads and stores
1845     cpu_addr = cpu_T[0];
1846     cpu_val = cpu_T[1];
1847
1848     switch (opc) {
1849     case 0:                     /* branches/sethi */
1850         {
1851             unsigned int xop = GET_FIELD(insn, 7, 9);
1852             int32_t target;
1853             switch (xop) {
1854 #ifdef TARGET_SPARC64
1855             case 0x1:           /* V9 BPcc */
1856                 {
1857                     int cc;
1858
1859                     target = GET_FIELD_SP(insn, 0, 18);
1860                     target = sign_extend(target, 18);
1861                     target <<= 2;
1862                     cc = GET_FIELD_SP(insn, 20, 21);
1863                     if (cc == 0)
1864                         do_branch(dc, target, insn, 0, cpu_cond);
1865                     else if (cc == 2)
1866                         do_branch(dc, target, insn, 1, cpu_cond);
1867                     else
1868                         goto illegal_insn;
1869                     goto jmp_insn;
1870                 }
1871             case 0x3:           /* V9 BPr */
1872                 {
1873                     target = GET_FIELD_SP(insn, 0, 13) |
1874                         (GET_FIELD_SP(insn, 20, 21) << 14);
1875                     target = sign_extend(target, 16);
1876                     target <<= 2;
1877                     cpu_src1 = get_src1(insn, cpu_src1);
1878                     do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1879                     goto jmp_insn;
1880                 }
1881             case 0x5:           /* V9 FBPcc */
1882                 {
1883                     int cc = GET_FIELD_SP(insn, 20, 21);
1884                     if (gen_trap_ifnofpu(dc, cpu_cond))
1885                         goto jmp_insn;
1886                     target = GET_FIELD_SP(insn, 0, 18);
1887                     target = sign_extend(target, 19);
1888                     target <<= 2;
1889                     do_fbranch(dc, target, insn, cc, cpu_cond);
1890                     goto jmp_insn;
1891                 }
1892 #else
1893             case 0x7:           /* CBN+x */
1894                 {
1895                     goto ncp_insn;
1896                 }
1897 #endif
1898             case 0x2:           /* BN+x */
1899                 {
1900                     target = GET_FIELD(insn, 10, 31);
1901                     target = sign_extend(target, 22);
1902                     target <<= 2;
1903                     do_branch(dc, target, insn, 0, cpu_cond);
1904                     goto jmp_insn;
1905                 }
1906             case 0x6:           /* FBN+x */
1907                 {
1908                     if (gen_trap_ifnofpu(dc, cpu_cond))
1909                         goto jmp_insn;
1910                     target = GET_FIELD(insn, 10, 31);
1911                     target = sign_extend(target, 22);
1912                     target <<= 2;
1913                     do_fbranch(dc, target, insn, 0, cpu_cond);
1914                     goto jmp_insn;
1915                 }
1916             case 0x4:           /* SETHI */
1917                 if (rd) { // nop
1918                     uint32_t value = GET_FIELD(insn, 10, 31);
1919                     gen_movl_TN_reg(rd, tcg_const_tl(value << 10));
1920                 }
1921                 break;
1922             case 0x0:           /* UNIMPL */
1923             default:
1924                 goto illegal_insn;
1925             }
1926             break;
1927         }
1928         break;
1929     case 1:
1930         /*CALL*/ {
1931             target_long target = GET_FIELDs(insn, 2, 31) << 2;
1932
1933             gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
1934             target += dc->pc;
1935             gen_mov_pc_npc(dc, cpu_cond);
1936             dc->npc = target;
1937         }
1938         goto jmp_insn;
1939     case 2:                     /* FPU & Logical Operations */
1940         {
1941             unsigned int xop = GET_FIELD(insn, 7, 12);
1942             if (xop == 0x3a) {  /* generate trap */
1943                 int cond;
1944
1945                 cpu_src1 = get_src1(insn, cpu_src1);
1946                 if (IS_IMM) {
1947                     rs2 = GET_FIELD(insn, 25, 31);
1948                     tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
1949                 } else {
1950                     rs2 = GET_FIELD(insn, 27, 31);
1951                     if (rs2 != 0) {
1952                         gen_movl_reg_TN(rs2, cpu_src2);
1953                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
1954                     } else
1955                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
1956                 }
1957                 cond = GET_FIELD(insn, 3, 6);
1958                 if (cond == 0x8) {
1959                     save_state(dc, cpu_cond);
1960                     tcg_gen_helper_0_1(helper_trap, cpu_dst);
1961                 } else if (cond != 0) {
1962                     TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
1963 #ifdef TARGET_SPARC64
1964                     /* V9 icc/xcc */
1965                     int cc = GET_FIELD_SP(insn, 11, 12);
1966
1967                     save_state(dc, cpu_cond);
1968                     if (cc == 0)
1969                         gen_cond(r_cond, 0, cond);
1970                     else if (cc == 2)
1971                         gen_cond(r_cond, 1, cond);
1972                     else
1973                         goto illegal_insn;
1974 #else
1975                     save_state(dc, cpu_cond);
1976                     gen_cond(r_cond, 0, cond);
1977 #endif
1978                     tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
1979                 }
1980                 gen_op_next_insn();
1981                 tcg_gen_exit_tb(0);
1982                 dc->is_br = 1;
1983                 goto jmp_insn;
1984             } else if (xop == 0x28) {
1985                 rs1 = GET_FIELD(insn, 13, 17);
1986                 switch(rs1) {
1987                 case 0: /* rdy */
1988 #ifndef TARGET_SPARC64
1989                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1990                                        manual, rdy on the microSPARC
1991                                        II */
1992                 case 0x0f:          /* stbar in the SPARCv8 manual,
1993                                        rdy on the microSPARC II */
1994                 case 0x10 ... 0x1f: /* implementation-dependent in the
1995                                        SPARCv8 manual, rdy on the
1996                                        microSPARC II */
1997 #endif
1998                     tcg_gen_ld_tl(cpu_dst, cpu_env,
1999                                   offsetof(CPUSPARCState, y));
2000                     gen_movl_TN_reg(rd, cpu_dst);
2001                     break;
2002 #ifdef TARGET_SPARC64
2003                 case 0x2: /* V9 rdccr */
2004                     tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2005                     gen_movl_TN_reg(rd, cpu_dst);
2006                     break;
2007                 case 0x3: /* V9 rdasi */
2008                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2009                                    offsetof(CPUSPARCState, asi));
2010                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2011                     gen_movl_TN_reg(rd, cpu_dst);
2012                     break;
2013                 case 0x4: /* V9 rdtick */
2014                     {
2015                         TCGv r_tickptr;
2016
2017                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2018                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2019                                        offsetof(CPUState, tick));
2020                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2021                                            r_tickptr);
2022                         gen_movl_TN_reg(rd, cpu_dst);
2023                     }
2024                     break;
2025                 case 0x5: /* V9 rdpc */
2026                     gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
2027                     break;
2028                 case 0x6: /* V9 rdfprs */
2029                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2030                                    offsetof(CPUSPARCState, fprs));
2031                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2032                     gen_movl_TN_reg(rd, cpu_dst);
2033                     break;
2034                 case 0xf: /* V9 membar */
2035                     break; /* no effect */
2036                 case 0x13: /* Graphics Status */
2037                     if (gen_trap_ifnofpu(dc, cpu_cond))
2038                         goto jmp_insn;
2039                     tcg_gen_ld_tl(cpu_dst, cpu_env,
2040                                   offsetof(CPUSPARCState, gsr));
2041                     gen_movl_TN_reg(rd, cpu_dst);
2042                     break;
2043                 case 0x17: /* Tick compare */
2044                     tcg_gen_ld_tl(cpu_dst, cpu_env,
2045                                   offsetof(CPUSPARCState, tick_cmpr));
2046                     gen_movl_TN_reg(rd, cpu_dst);
2047                     break;
2048                 case 0x18: /* System tick */
2049                     {
2050                         TCGv r_tickptr;
2051
2052                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2053                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2054                                        offsetof(CPUState, stick));
2055                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2056                                            r_tickptr);
2057                         gen_movl_TN_reg(rd, cpu_dst);
2058                     }
2059                     break;
2060                 case 0x19: /* System tick compare */
2061                     tcg_gen_ld_tl(cpu_dst, cpu_env,
2062                                   offsetof(CPUSPARCState, stick_cmpr));
2063                     gen_movl_TN_reg(rd, cpu_dst);
2064                     break;
2065                 case 0x10: /* Performance Control */
2066                 case 0x11: /* Performance Instrumentation Counter */
2067                 case 0x12: /* Dispatch Control */
2068                 case 0x14: /* Softint set, WO */
2069                 case 0x15: /* Softint clear, WO */
2070                 case 0x16: /* Softint write */
2071 #endif
2072                 default:
2073                     goto illegal_insn;
2074                 }
2075 #if !defined(CONFIG_USER_ONLY)
2076             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2077 #ifndef TARGET_SPARC64
2078                 if (!supervisor(dc))
2079                     goto priv_insn;
2080                 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2081 #else
2082                 if (!hypervisor(dc))
2083                     goto priv_insn;
2084                 rs1 = GET_FIELD(insn, 13, 17);
2085                 switch (rs1) {
2086                 case 0: // hpstate
2087                     // gen_op_rdhpstate();
2088                     break;
2089                 case 1: // htstate
2090                     // gen_op_rdhtstate();
2091                     break;
2092                 case 3: // hintp
2093                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2094                                    offsetof(CPUSPARCState, hintp));
2095                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2096                     break;
2097                 case 5: // htba
2098                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2099                                    offsetof(CPUSPARCState, htba));
2100                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2101                     break;
2102                 case 6: // hver
2103                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2104                                    offsetof(CPUSPARCState, hver));
2105                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2106                     break;
2107                 case 31: // hstick_cmpr
2108                     tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2109                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
2110                                    offsetof(CPUSPARCState, hstick_cmpr));
2111                     break;
2112                 default:
2113                     goto illegal_insn;
2114                 }
2115 #endif
2116                 gen_movl_TN_reg(rd, cpu_dst);
2117                 break;
2118             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2119                 if (!supervisor(dc))
2120                     goto priv_insn;
2121 #ifdef TARGET_SPARC64
2122                 rs1 = GET_FIELD(insn, 13, 17);
2123                 switch (rs1) {
2124                 case 0: // tpc
2125                     {
2126                         TCGv r_tsptr;
2127
2128                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2129                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2130                                        offsetof(CPUState, tsptr));
2131                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2132                                       offsetof(trap_state, tpc));
2133                     }
2134                     break;
2135                 case 1: // tnpc
2136                     {
2137                         TCGv r_tsptr;
2138
2139                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2140                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2141                                        offsetof(CPUState, tsptr));
2142                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2143                                       offsetof(trap_state, tnpc));
2144                     }
2145                     break;
2146                 case 2: // tstate
2147                     {
2148                         TCGv r_tsptr;
2149
2150                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2151                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2152                                        offsetof(CPUState, tsptr));
2153                         tcg_gen_ld_tl(cpu_dst, r_tsptr,
2154                                       offsetof(trap_state, tstate));
2155                     }
2156                     break;
2157                 case 3: // tt
2158                     {
2159                         TCGv r_tsptr;
2160
2161                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2162                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2163                                        offsetof(CPUState, tsptr));
2164                         tcg_gen_ld_i32(cpu_dst, r_tsptr,
2165                                        offsetof(trap_state, tt));
2166                     }
2167                     break;
2168                 case 4: // tick
2169                     {
2170                         TCGv r_tickptr;
2171
2172                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2173                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2174                                        offsetof(CPUState, tick));
2175                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2176                                            r_tickptr);
2177                         gen_movl_TN_reg(rd, cpu_dst);
2178                     }
2179                     break;
2180                 case 5: // tba
2181                     tcg_gen_ld_tl(cpu_dst, cpu_env,
2182                                   offsetof(CPUSPARCState, tbr));
2183                     break;
2184                 case 6: // pstate
2185                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2186                                    offsetof(CPUSPARCState, pstate));
2187                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2188                     break;
2189                 case 7: // tl
2190                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2191                                    offsetof(CPUSPARCState, tl));
2192                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2193                     break;
2194                 case 8: // pil
2195                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2196                                    offsetof(CPUSPARCState, psrpil));
2197                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2198                     break;
2199                 case 9: // cwp
2200                     tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
2201                     break;
2202                 case 10: // cansave
2203                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2204                                    offsetof(CPUSPARCState, cansave));
2205                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2206                     break;
2207                 case 11: // canrestore
2208                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2209                                    offsetof(CPUSPARCState, canrestore));
2210                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2211                     break;
2212                 case 12: // cleanwin
2213                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2214                                    offsetof(CPUSPARCState, cleanwin));
2215                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2216                     break;
2217                 case 13: // otherwin
2218                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2219                                    offsetof(CPUSPARCState, otherwin));
2220                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2221                     break;
2222                 case 14: // wstate
2223                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2224                                    offsetof(CPUSPARCState, wstate));
2225                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2226                     break;
2227                 case 16: // UA2005 gl
2228                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2229                                    offsetof(CPUSPARCState, gl));
2230                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2231                     break;
2232                 case 26: // UA2005 strand status
2233                     if (!hypervisor(dc))
2234                         goto priv_insn;
2235                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2236                                    offsetof(CPUSPARCState, ssr));
2237                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2238                     break;
2239                 case 31: // ver
2240                     tcg_gen_ld_tl(cpu_dst, cpu_env,
2241                                   offsetof(CPUSPARCState, version));
2242                     break;
2243                 case 15: // fq
2244                 default:
2245                     goto illegal_insn;
2246                 }
2247 #else
2248                 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2249                                offsetof(CPUSPARCState, wim));
2250                 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2251 #endif
2252                 gen_movl_TN_reg(rd, cpu_dst);
2253                 break;
2254             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2255 #ifdef TARGET_SPARC64
2256                 tcg_gen_helper_0_0(helper_flushw);
2257 #else
2258                 if (!supervisor(dc))
2259                     goto priv_insn;
2260                 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2261                 gen_movl_TN_reg(rd, cpu_dst);
2262 #endif
2263                 break;
2264 #endif
2265             } else if (xop == 0x34) {   /* FPU Operations */
2266                 if (gen_trap_ifnofpu(dc, cpu_cond))
2267                     goto jmp_insn;
2268                 gen_op_clear_ieee_excp_and_FTT();
2269                 rs1 = GET_FIELD(insn, 13, 17);
2270                 rs2 = GET_FIELD(insn, 27, 31);
2271                 xop = GET_FIELD(insn, 18, 26);
2272                 switch (xop) {
2273                     case 0x1: /* fmovs */
2274                         gen_op_load_fpr_FT0(rs2);
2275                         gen_op_store_FT0_fpr(rd);
2276                         break;
2277                     case 0x5: /* fnegs */
2278                         gen_op_load_fpr_FT1(rs2);
2279                         tcg_gen_helper_0_0(helper_fnegs);
2280                         gen_op_store_FT0_fpr(rd);
2281                         break;
2282                     case 0x9: /* fabss */
2283                         gen_op_load_fpr_FT1(rs2);
2284                         tcg_gen_helper_0_0(helper_fabss);
2285                         gen_op_store_FT0_fpr(rd);
2286                         break;
2287                     case 0x29: /* fsqrts */
2288                         CHECK_FPU_FEATURE(dc, FSQRT);
2289                         gen_op_load_fpr_FT1(rs2);
2290                         gen_clear_float_exceptions();
2291                         tcg_gen_helper_0_0(helper_fsqrts);
2292                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2293                         gen_op_store_FT0_fpr(rd);
2294                         break;
2295                     case 0x2a: /* fsqrtd */
2296                         CHECK_FPU_FEATURE(dc, FSQRT);
2297                         gen_op_load_fpr_DT1(DFPREG(rs2));
2298                         gen_clear_float_exceptions();
2299                         tcg_gen_helper_0_0(helper_fsqrtd);
2300                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2301                         gen_op_store_DT0_fpr(DFPREG(rd));
2302                         break;
2303                     case 0x2b: /* fsqrtq */
2304                         CHECK_FPU_FEATURE(dc, FLOAT128);
2305                         gen_op_load_fpr_QT1(QFPREG(rs2));
2306                         gen_clear_float_exceptions();
2307                         tcg_gen_helper_0_0(helper_fsqrtq);
2308                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2309                         gen_op_store_QT0_fpr(QFPREG(rd));
2310                         break;
2311                     case 0x41:
2312                         gen_op_load_fpr_FT0(rs1);
2313                         gen_op_load_fpr_FT1(rs2);
2314                         gen_clear_float_exceptions();
2315                         tcg_gen_helper_0_0(helper_fadds);
2316                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2317                         gen_op_store_FT0_fpr(rd);
2318                         break;
2319                     case 0x42:
2320                         gen_op_load_fpr_DT0(DFPREG(rs1));
2321                         gen_op_load_fpr_DT1(DFPREG(rs2));
2322                         gen_clear_float_exceptions();
2323                         tcg_gen_helper_0_0(helper_faddd);
2324                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2325                         gen_op_store_DT0_fpr(DFPREG(rd));
2326                         break;
2327                     case 0x43: /* faddq */
2328                         CHECK_FPU_FEATURE(dc, FLOAT128);
2329                         gen_op_load_fpr_QT0(QFPREG(rs1));
2330                         gen_op_load_fpr_QT1(QFPREG(rs2));
2331                         gen_clear_float_exceptions();
2332                         tcg_gen_helper_0_0(helper_faddq);
2333                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2334                         gen_op_store_QT0_fpr(QFPREG(rd));
2335                         break;
2336                     case 0x45:
2337                         gen_op_load_fpr_FT0(rs1);
2338                         gen_op_load_fpr_FT1(rs2);
2339                         gen_clear_float_exceptions();
2340                         tcg_gen_helper_0_0(helper_fsubs);
2341                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2342                         gen_op_store_FT0_fpr(rd);
2343                         break;
2344                     case 0x46:
2345                         gen_op_load_fpr_DT0(DFPREG(rs1));
2346                         gen_op_load_fpr_DT1(DFPREG(rs2));
2347                         gen_clear_float_exceptions();
2348                         tcg_gen_helper_0_0(helper_fsubd);
2349                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2350                         gen_op_store_DT0_fpr(DFPREG(rd));
2351                         break;
2352                     case 0x47: /* fsubq */
2353                         CHECK_FPU_FEATURE(dc, FLOAT128);
2354                         gen_op_load_fpr_QT0(QFPREG(rs1));
2355                         gen_op_load_fpr_QT1(QFPREG(rs2));
2356                         gen_clear_float_exceptions();
2357                         tcg_gen_helper_0_0(helper_fsubq);
2358                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2359                         gen_op_store_QT0_fpr(QFPREG(rd));
2360                         break;
2361                     case 0x49: /* fmuls */
2362                         CHECK_FPU_FEATURE(dc, FMUL);
2363                         gen_op_load_fpr_FT0(rs1);
2364                         gen_op_load_fpr_FT1(rs2);
2365                         gen_clear_float_exceptions();
2366                         tcg_gen_helper_0_0(helper_fmuls);
2367                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2368                         gen_op_store_FT0_fpr(rd);
2369                         break;
2370                     case 0x4a: /* fmuld */
2371                         CHECK_FPU_FEATURE(dc, FMUL);
2372                         gen_op_load_fpr_DT0(DFPREG(rs1));
2373                         gen_op_load_fpr_DT1(DFPREG(rs2));
2374                         gen_clear_float_exceptions();
2375                         tcg_gen_helper_0_0(helper_fmuld);
2376                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2377                         gen_op_store_DT0_fpr(DFPREG(rd));
2378                         break;
2379                     case 0x4b: /* fmulq */
2380                         CHECK_FPU_FEATURE(dc, FLOAT128);
2381                         CHECK_FPU_FEATURE(dc, FMUL);
2382                         gen_op_load_fpr_QT0(QFPREG(rs1));
2383                         gen_op_load_fpr_QT1(QFPREG(rs2));
2384                         gen_clear_float_exceptions();
2385                         tcg_gen_helper_0_0(helper_fmulq);
2386                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2387                         gen_op_store_QT0_fpr(QFPREG(rd));
2388                         break;
2389                     case 0x4d:
2390                         gen_op_load_fpr_FT0(rs1);
2391                         gen_op_load_fpr_FT1(rs2);
2392                         gen_clear_float_exceptions();
2393                         tcg_gen_helper_0_0(helper_fdivs);
2394                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2395                         gen_op_store_FT0_fpr(rd);
2396                         break;
2397                     case 0x4e:
2398                         gen_op_load_fpr_DT0(DFPREG(rs1));
2399                         gen_op_load_fpr_DT1(DFPREG(rs2));
2400                         gen_clear_float_exceptions();
2401                         tcg_gen_helper_0_0(helper_fdivd);
2402                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2403                         gen_op_store_DT0_fpr(DFPREG(rd));
2404                         break;
2405                     case 0x4f: /* fdivq */
2406                         CHECK_FPU_FEATURE(dc, FLOAT128);
2407                         gen_op_load_fpr_QT0(QFPREG(rs1));
2408                         gen_op_load_fpr_QT1(QFPREG(rs2));
2409                         gen_clear_float_exceptions();
2410                         tcg_gen_helper_0_0(helper_fdivq);
2411                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2412                         gen_op_store_QT0_fpr(QFPREG(rd));
2413                         break;
2414                     case 0x69:
2415                         gen_op_load_fpr_FT0(rs1);
2416                         gen_op_load_fpr_FT1(rs2);
2417                         gen_clear_float_exceptions();
2418                         tcg_gen_helper_0_0(helper_fsmuld);
2419                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2420                         gen_op_store_DT0_fpr(DFPREG(rd));
2421                         break;
2422                     case 0x6e: /* fdmulq */
2423                         CHECK_FPU_FEATURE(dc, FLOAT128);
2424                         gen_op_load_fpr_DT0(DFPREG(rs1));
2425                         gen_op_load_fpr_DT1(DFPREG(rs2));
2426                         gen_clear_float_exceptions();
2427                         tcg_gen_helper_0_0(helper_fdmulq);
2428                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2429                         gen_op_store_QT0_fpr(QFPREG(rd));
2430                         break;
2431                     case 0xc4:
2432                         gen_op_load_fpr_FT1(rs2);
2433                         gen_clear_float_exceptions();
2434                         tcg_gen_helper_0_0(helper_fitos);
2435                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2436                         gen_op_store_FT0_fpr(rd);
2437                         break;
2438                     case 0xc6:
2439                         gen_op_load_fpr_DT1(DFPREG(rs2));
2440                         gen_clear_float_exceptions();
2441                         tcg_gen_helper_0_0(helper_fdtos);
2442                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2443                         gen_op_store_FT0_fpr(rd);
2444                         break;
2445                     case 0xc7: /* fqtos */
2446                         CHECK_FPU_FEATURE(dc, FLOAT128);
2447                         gen_op_load_fpr_QT1(QFPREG(rs2));
2448                         gen_clear_float_exceptions();
2449                         tcg_gen_helper_0_0(helper_fqtos);
2450                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2451                         gen_op_store_FT0_fpr(rd);
2452                         break;
2453                     case 0xc8:
2454                         gen_op_load_fpr_FT1(rs2);
2455                         tcg_gen_helper_0_0(helper_fitod);
2456                         gen_op_store_DT0_fpr(DFPREG(rd));
2457                         break;
2458                     case 0xc9:
2459                         gen_op_load_fpr_FT1(rs2);
2460                         tcg_gen_helper_0_0(helper_fstod);
2461                         gen_op_store_DT0_fpr(DFPREG(rd));
2462                         break;
2463                     case 0xcb: /* fqtod */
2464                         CHECK_FPU_FEATURE(dc, FLOAT128);
2465                         gen_op_load_fpr_QT1(QFPREG(rs2));
2466                         gen_clear_float_exceptions();
2467                         tcg_gen_helper_0_0(helper_fqtod);
2468                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2469                         gen_op_store_DT0_fpr(DFPREG(rd));
2470                         break;
2471                     case 0xcc: /* fitoq */
2472                         CHECK_FPU_FEATURE(dc, FLOAT128);
2473                         gen_op_load_fpr_FT1(rs2);
2474                         tcg_gen_helper_0_0(helper_fitoq);
2475                         gen_op_store_QT0_fpr(QFPREG(rd));
2476                         break;
2477                     case 0xcd: /* fstoq */
2478                         CHECK_FPU_FEATURE(dc, FLOAT128);
2479                         gen_op_load_fpr_FT1(rs2);
2480                         tcg_gen_helper_0_0(helper_fstoq);
2481                         gen_op_store_QT0_fpr(QFPREG(rd));
2482                         break;
2483                     case 0xce: /* fdtoq */
2484                         CHECK_FPU_FEATURE(dc, FLOAT128);
2485                         gen_op_load_fpr_DT1(DFPREG(rs2));
2486                         tcg_gen_helper_0_0(helper_fdtoq);
2487                         gen_op_store_QT0_fpr(QFPREG(rd));
2488                         break;
2489                     case 0xd1:
2490                         gen_op_load_fpr_FT1(rs2);
2491                         gen_clear_float_exceptions();
2492                         tcg_gen_helper_0_0(helper_fstoi);
2493                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2494                         gen_op_store_FT0_fpr(rd);
2495                         break;
2496                     case 0xd2:
2497                         gen_op_load_fpr_DT1(DFPREG(rs2));
2498                         gen_clear_float_exceptions();
2499                         tcg_gen_helper_0_0(helper_fdtoi);
2500                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2501                         gen_op_store_FT0_fpr(rd);
2502                         break;
2503                     case 0xd3: /* fqtoi */
2504                         CHECK_FPU_FEATURE(dc, FLOAT128);
2505                         gen_op_load_fpr_QT1(QFPREG(rs2));
2506                         gen_clear_float_exceptions();
2507                         tcg_gen_helper_0_0(helper_fqtoi);
2508                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2509                         gen_op_store_FT0_fpr(rd);
2510                         break;
2511 #ifdef TARGET_SPARC64
2512                     case 0x2: /* V9 fmovd */
2513                         gen_op_load_fpr_DT0(DFPREG(rs2));
2514                         gen_op_store_DT0_fpr(DFPREG(rd));
2515                         break;
2516                     case 0x3: /* V9 fmovq */
2517                         CHECK_FPU_FEATURE(dc, FLOAT128);
2518                         gen_op_load_fpr_QT0(QFPREG(rs2));
2519                         gen_op_store_QT0_fpr(QFPREG(rd));
2520                         break;
2521                     case 0x6: /* V9 fnegd */
2522                         gen_op_load_fpr_DT1(DFPREG(rs2));
2523                         tcg_gen_helper_0_0(helper_fnegd);
2524                         gen_op_store_DT0_fpr(DFPREG(rd));
2525                         break;
2526                     case 0x7: /* V9 fnegq */
2527                         CHECK_FPU_FEATURE(dc, FLOAT128);
2528                         gen_op_load_fpr_QT1(QFPREG(rs2));
2529                         tcg_gen_helper_0_0(helper_fnegq);
2530                         gen_op_store_QT0_fpr(QFPREG(rd));
2531                         break;
2532                     case 0xa: /* V9 fabsd */
2533                         gen_op_load_fpr_DT1(DFPREG(rs2));
2534                         tcg_gen_helper_0_0(helper_fabsd);
2535                         gen_op_store_DT0_fpr(DFPREG(rd));
2536                         break;
2537                     case 0xb: /* V9 fabsq */
2538                         CHECK_FPU_FEATURE(dc, FLOAT128);
2539                         gen_op_load_fpr_QT1(QFPREG(rs2));
2540                         tcg_gen_helper_0_0(helper_fabsq);
2541                         gen_op_store_QT0_fpr(QFPREG(rd));
2542                         break;
2543                     case 0x81: /* V9 fstox */
2544                         gen_op_load_fpr_FT1(rs2);
2545                         gen_clear_float_exceptions();
2546                         tcg_gen_helper_0_0(helper_fstox);
2547                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2548                         gen_op_store_DT0_fpr(DFPREG(rd));
2549                         break;
2550                     case 0x82: /* V9 fdtox */
2551                         gen_op_load_fpr_DT1(DFPREG(rs2));
2552                         gen_clear_float_exceptions();
2553                         tcg_gen_helper_0_0(helper_fdtox);
2554                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2555                         gen_op_store_DT0_fpr(DFPREG(rd));
2556                         break;
2557                     case 0x83: /* V9 fqtox */
2558                         CHECK_FPU_FEATURE(dc, FLOAT128);
2559                         gen_op_load_fpr_QT1(QFPREG(rs2));
2560                         gen_clear_float_exceptions();
2561                         tcg_gen_helper_0_0(helper_fqtox);
2562                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2563                         gen_op_store_DT0_fpr(DFPREG(rd));
2564                         break;
2565                     case 0x84: /* V9 fxtos */
2566                         gen_op_load_fpr_DT1(DFPREG(rs2));
2567                         gen_clear_float_exceptions();
2568                         tcg_gen_helper_0_0(helper_fxtos);
2569                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2570                         gen_op_store_FT0_fpr(rd);
2571                         break;
2572                     case 0x88: /* V9 fxtod */
2573                         gen_op_load_fpr_DT1(DFPREG(rs2));
2574                         gen_clear_float_exceptions();
2575                         tcg_gen_helper_0_0(helper_fxtod);
2576                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2577                         gen_op_store_DT0_fpr(DFPREG(rd));
2578                         break;
2579                     case 0x8c: /* V9 fxtoq */
2580                         CHECK_FPU_FEATURE(dc, FLOAT128);
2581                         gen_op_load_fpr_DT1(DFPREG(rs2));
2582                         gen_clear_float_exceptions();
2583                         tcg_gen_helper_0_0(helper_fxtoq);
2584                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2585                         gen_op_store_QT0_fpr(QFPREG(rd));
2586                         break;
2587 #endif
2588                     default:
2589                         goto illegal_insn;
2590                 }
2591             } else if (xop == 0x35) {   /* FPU Operations */
2592 #ifdef TARGET_SPARC64
2593                 int cond;
2594 #endif
2595                 if (gen_trap_ifnofpu(dc, cpu_cond))
2596                     goto jmp_insn;
2597                 gen_op_clear_ieee_excp_and_FTT();
2598                 rs1 = GET_FIELD(insn, 13, 17);
2599                 rs2 = GET_FIELD(insn, 27, 31);
2600                 xop = GET_FIELD(insn, 18, 26);
2601 #ifdef TARGET_SPARC64
2602                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2603                     int l1;
2604
2605                     l1 = gen_new_label();
2606                     cond = GET_FIELD_SP(insn, 14, 17);
2607                     cpu_src1 = get_src1(insn, cpu_src1);
2608                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2609                                        0, l1);
2610                     gen_op_load_fpr_FT0(rs2);
2611                     gen_op_store_FT0_fpr(rd);
2612                     gen_set_label(l1);
2613                     break;
2614                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2615                     int l1;
2616
2617                     l1 = gen_new_label();
2618                     cond = GET_FIELD_SP(insn, 14, 17);
2619                     cpu_src1 = get_src1(insn, cpu_src1);
2620                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2621                                        0, l1);
2622                     gen_op_load_fpr_DT0(DFPREG(rs2));
2623                     gen_op_store_DT0_fpr(DFPREG(rd));
2624                     gen_set_label(l1);
2625                     break;
2626                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2627                     int l1;
2628
2629                     CHECK_FPU_FEATURE(dc, FLOAT128);
2630                     l1 = gen_new_label();
2631                     cond = GET_FIELD_SP(insn, 14, 17);
2632                     cpu_src1 = get_src1(insn, cpu_src1);
2633                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2634                                        0, l1);
2635                     gen_op_load_fpr_QT0(QFPREG(rs2));
2636                     gen_op_store_QT0_fpr(QFPREG(rd));
2637                     gen_set_label(l1);
2638                     break;
2639                 }
2640 #endif
2641                 switch (xop) {
2642 #ifdef TARGET_SPARC64
2643 #define FMOVCC(size_FDQ, fcc)                                           \
2644                     {                                                   \
2645                         TCGv r_cond;                                    \
2646                         int l1;                                         \
2647                                                                         \
2648                         l1 = gen_new_label();                           \
2649                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2650                         cond = GET_FIELD_SP(insn, 14, 17);              \
2651                         gen_fcond(r_cond, fcc, cond);                   \
2652                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2653                                            0, l1);                      \
2654                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2655                             (glue(size_FDQ, FPREG(rs2)));               \
2656                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2657                             (glue(size_FDQ, FPREG(rd)));                \
2658                         gen_set_label(l1);                              \
2659                     }
2660                     case 0x001: /* V9 fmovscc %fcc0 */
2661                         FMOVCC(F, 0);
2662                         break;
2663                     case 0x002: /* V9 fmovdcc %fcc0 */
2664                         FMOVCC(D, 0);
2665                         break;
2666                     case 0x003: /* V9 fmovqcc %fcc0 */
2667                         CHECK_FPU_FEATURE(dc, FLOAT128);
2668                         FMOVCC(Q, 0);
2669                         break;
2670                     case 0x041: /* V9 fmovscc %fcc1 */
2671                         FMOVCC(F, 1);
2672                         break;
2673                     case 0x042: /* V9 fmovdcc %fcc1 */
2674                         FMOVCC(D, 1);
2675                         break;
2676                     case 0x043: /* V9 fmovqcc %fcc1 */
2677                         CHECK_FPU_FEATURE(dc, FLOAT128);
2678                         FMOVCC(Q, 1);
2679                         break;
2680                     case 0x081: /* V9 fmovscc %fcc2 */
2681                         FMOVCC(F, 2);
2682                         break;
2683                     case 0x082: /* V9 fmovdcc %fcc2 */
2684                         FMOVCC(D, 2);
2685                         break;
2686                     case 0x083: /* V9 fmovqcc %fcc2 */
2687                         CHECK_FPU_FEATURE(dc, FLOAT128);
2688                         FMOVCC(Q, 2);
2689                         break;
2690                     case 0x0c1: /* V9 fmovscc %fcc3 */
2691                         FMOVCC(F, 3);
2692                         break;
2693                     case 0x0c2: /* V9 fmovdcc %fcc3 */
2694                         FMOVCC(D, 3);
2695                         break;
2696                     case 0x0c3: /* V9 fmovqcc %fcc3 */
2697                         CHECK_FPU_FEATURE(dc, FLOAT128);
2698                         FMOVCC(Q, 3);
2699                         break;
2700 #undef FMOVCC
2701 #define FMOVCC(size_FDQ, icc)                                           \
2702                     {                                                   \
2703                         TCGv r_cond;                                    \
2704                         int l1;                                         \
2705                                                                         \
2706                         l1 = gen_new_label();                           \
2707                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2708                         cond = GET_FIELD_SP(insn, 14, 17);              \
2709                         gen_cond(r_cond, icc, cond);                    \
2710                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2711                                            0, l1);                      \
2712                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2713                             (glue(size_FDQ, FPREG(rs2)));               \
2714                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2715                             (glue(size_FDQ, FPREG(rd)));                \
2716                         gen_set_label(l1);                              \
2717                     }
2718
2719                     case 0x101: /* V9 fmovscc %icc */
2720                         FMOVCC(F, 0);
2721                         break;
2722                     case 0x102: /* V9 fmovdcc %icc */
2723                         FMOVCC(D, 0);
2724                     case 0x103: /* V9 fmovqcc %icc */
2725                         CHECK_FPU_FEATURE(dc, FLOAT128);
2726                         FMOVCC(Q, 0);
2727                         break;
2728                     case 0x181: /* V9 fmovscc %xcc */
2729                         FMOVCC(F, 1);
2730                         break;
2731                     case 0x182: /* V9 fmovdcc %xcc */
2732                         FMOVCC(D, 1);
2733                         break;
2734                     case 0x183: /* V9 fmovqcc %xcc */
2735                         CHECK_FPU_FEATURE(dc, FLOAT128);
2736                         FMOVCC(Q, 1);
2737                         break;
2738 #undef FMOVCC
2739 #endif
2740                     case 0x51: /* fcmps, V9 %fcc */
2741                         gen_op_load_fpr_FT0(rs1);
2742                         gen_op_load_fpr_FT1(rs2);
2743                         gen_op_fcmps(rd & 3);
2744                         break;
2745                     case 0x52: /* fcmpd, V9 %fcc */
2746                         gen_op_load_fpr_DT0(DFPREG(rs1));
2747                         gen_op_load_fpr_DT1(DFPREG(rs2));
2748                         gen_op_fcmpd(rd & 3);
2749                         break;
2750                     case 0x53: /* fcmpq, V9 %fcc */
2751                         CHECK_FPU_FEATURE(dc, FLOAT128);
2752                         gen_op_load_fpr_QT0(QFPREG(rs1));
2753                         gen_op_load_fpr_QT1(QFPREG(rs2));
2754                         gen_op_fcmpq(rd & 3);
2755                         break;
2756                     case 0x55: /* fcmpes, V9 %fcc */
2757                         gen_op_load_fpr_FT0(rs1);
2758                         gen_op_load_fpr_FT1(rs2);
2759                         gen_op_fcmpes(rd & 3);
2760                         break;
2761                     case 0x56: /* fcmped, V9 %fcc */
2762                         gen_op_load_fpr_DT0(DFPREG(rs1));
2763                         gen_op_load_fpr_DT1(DFPREG(rs2));
2764                         gen_op_fcmped(rd & 3);
2765                         break;
2766                     case 0x57: /* fcmpeq, V9 %fcc */
2767                         CHECK_FPU_FEATURE(dc, FLOAT128);
2768                         gen_op_load_fpr_QT0(QFPREG(rs1));
2769                         gen_op_load_fpr_QT1(QFPREG(rs2));
2770                         gen_op_fcmpeq(rd & 3);
2771                         break;
2772                     default:
2773                         goto illegal_insn;
2774                 }
2775             } else if (xop == 0x2) {
2776                 // clr/mov shortcut
2777
2778                 rs1 = GET_FIELD(insn, 13, 17);
2779                 if (rs1 == 0) {
2780                     // or %g0, x, y -> mov T0, x; mov y, T0
2781                     if (IS_IMM) {       /* immediate */
2782                         rs2 = GET_FIELDs(insn, 19, 31);
2783                         gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
2784                     } else {            /* register */
2785                         rs2 = GET_FIELD(insn, 27, 31);
2786                         gen_movl_reg_TN(rs2, cpu_dst);
2787                         gen_movl_TN_reg(rd, cpu_dst);
2788                     }
2789                 } else {
2790                     cpu_src1 = get_src1(insn, cpu_src1);
2791                     if (IS_IMM) {       /* immediate */
2792                         rs2 = GET_FIELDs(insn, 19, 31);
2793                         tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2794                         gen_movl_TN_reg(rd, cpu_dst);
2795                     } else {            /* register */
2796                         // or x, %g0, y -> mov T1, x; mov y, T1
2797                         rs2 = GET_FIELD(insn, 27, 31);
2798                         if (rs2 != 0) {
2799                             gen_movl_reg_TN(rs2, cpu_src2);
2800                             tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2801                             gen_movl_TN_reg(rd, cpu_dst);
2802                         } else
2803                             gen_movl_TN_reg(rd, cpu_src1);
2804                     }
2805                 }
2806 #ifdef TARGET_SPARC64
2807             } else if (xop == 0x25) { /* sll, V9 sllx */
2808                 cpu_src1 = get_src1(insn, cpu_src1);
2809                 if (IS_IMM) {   /* immediate */
2810                     rs2 = GET_FIELDs(insn, 20, 31);
2811                     if (insn & (1 << 12)) {
2812                         tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2813                     } else {
2814                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2815                         tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2816                     }
2817                 } else {                /* register */
2818                     rs2 = GET_FIELD(insn, 27, 31);
2819                     gen_movl_reg_TN(rs2, cpu_src2);
2820                     if (insn & (1 << 12)) {
2821                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2822                         tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2823                     } else {
2824                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2825                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2826                         tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2827                     }
2828                 }
2829                 gen_movl_TN_reg(rd, cpu_dst);
2830             } else if (xop == 0x26) { /* srl, V9 srlx */
2831                 cpu_src1 = get_src1(insn, cpu_src1);
2832                 if (IS_IMM) {   /* immediate */
2833                     rs2 = GET_FIELDs(insn, 20, 31);
2834                     if (insn & (1 << 12)) {
2835                         tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2836                     } else {
2837                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2838                         tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2839                     }
2840                 } else {                /* register */
2841                     rs2 = GET_FIELD(insn, 27, 31);
2842                     gen_movl_reg_TN(rs2, cpu_src2);
2843                     if (insn & (1 << 12)) {
2844                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2845                         tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2846                     } else {
2847                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2848                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2849                         tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2850                     }
2851                 }
2852                 gen_movl_TN_reg(rd, cpu_dst);
2853             } else if (xop == 0x27) { /* sra, V9 srax */
2854                 cpu_src1 = get_src1(insn, cpu_src1);
2855                 if (IS_IMM) {   /* immediate */
2856                     rs2 = GET_FIELDs(insn, 20, 31);
2857                     if (insn & (1 << 12)) {
2858                         tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2859                     } else {
2860                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2861                         tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2862                         tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2863                     }
2864                 } else {                /* register */
2865                     rs2 = GET_FIELD(insn, 27, 31);
2866                     gen_movl_reg_TN(rs2, cpu_src2);
2867                     if (insn & (1 << 12)) {
2868                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2869                         tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2870                     } else {
2871                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2872                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2873                         tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2874                     }
2875                 }
2876                 gen_movl_TN_reg(rd, cpu_dst);
2877 #endif
2878             } else if (xop < 0x36) {
2879                 cpu_src1 = get_src1(insn, cpu_src1);
2880                 cpu_src2 = get_src2(insn, cpu_src2);
2881                 if (xop < 0x20) {
2882                     switch (xop & ~0x10) {
2883                     case 0x0:
2884                         if (xop & 0x10)
2885                             gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2886                         else
2887                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2888                         break;
2889                     case 0x1:
2890                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2891                         if (xop & 0x10)
2892                             gen_op_logic_cc(cpu_dst);
2893                         break;
2894                     case 0x2:
2895                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2896                         if (xop & 0x10)
2897                             gen_op_logic_cc(cpu_dst);
2898                         break;
2899                     case 0x3:
2900                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
2901                         if (xop & 0x10)
2902                             gen_op_logic_cc(cpu_dst);
2903                         break;
2904                     case 0x4:
2905                         if (xop & 0x10)
2906                             gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
2907                         else
2908                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
2909                         break;
2910                     case 0x5:
2911                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2912                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
2913                         if (xop & 0x10)
2914                             gen_op_logic_cc(cpu_dst);
2915                         break;
2916                     case 0x6:
2917                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2918                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
2919                         if (xop & 0x10)
2920                             gen_op_logic_cc(cpu_dst);
2921                         break;
2922                     case 0x7:
2923                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2924                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
2925                         if (xop & 0x10)
2926                             gen_op_logic_cc(cpu_dst);
2927                         break;
2928                     case 0x8:
2929                         if (xop & 0x10)
2930                             gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
2931                         else {
2932                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
2933                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
2934                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
2935                         }
2936                         break;
2937 #ifdef TARGET_SPARC64
2938                     case 0x9: /* V9 mulx */
2939                         tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
2940                         break;
2941 #endif
2942                     case 0xa:
2943                         CHECK_IU_FEATURE(dc, MUL);
2944                         gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
2945                         if (xop & 0x10)
2946                             gen_op_logic_cc(cpu_dst);
2947                         break;
2948                     case 0xb:
2949                         CHECK_IU_FEATURE(dc, MUL);
2950                         gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
2951                         if (xop & 0x10)
2952                             gen_op_logic_cc(cpu_dst);
2953                         break;
2954                     case 0xc:
2955                         if (xop & 0x10)
2956                             gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
2957                         else {
2958                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
2959                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
2960                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
2961                         }
2962                         break;
2963 #ifdef TARGET_SPARC64
2964                     case 0xd: /* V9 udivx */
2965                         gen_trap_ifdivzero_tl(cpu_src2);
2966                         tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2);
2967                         break;
2968 #endif
2969                     case 0xe:
2970                         CHECK_IU_FEATURE(dc, DIV);
2971                         tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
2972                                            cpu_src2);
2973                         if (xop & 0x10)
2974                             gen_op_div_cc(cpu_dst);
2975                         break;
2976                     case 0xf:
2977                         CHECK_IU_FEATURE(dc, DIV);
2978                         tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
2979                                            cpu_src2);
2980                         if (xop & 0x10)
2981                             gen_op_div_cc(cpu_dst);
2982                         break;
2983                     default:
2984                         goto illegal_insn;
2985                     }
2986                     gen_movl_TN_reg(rd, cpu_dst);
2987                 } else {
2988                     switch (xop) {
2989                     case 0x20: /* taddcc */
2990                         gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
2991                         gen_movl_TN_reg(rd, cpu_dst);
2992                         break;
2993                     case 0x21: /* tsubcc */
2994                         gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
2995                         gen_movl_TN_reg(rd, cpu_dst);
2996                         break;
2997                     case 0x22: /* taddcctv */
2998                         save_state(dc, cpu_cond);
2999                         gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3000                         gen_movl_TN_reg(rd, cpu_dst);
3001                         break;
3002                     case 0x23: /* tsubcctv */
3003                         save_state(dc, cpu_cond);
3004                         gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3005                         gen_movl_TN_reg(rd, cpu_dst);
3006                         break;
3007                     case 0x24: /* mulscc */
3008                         gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3009                         gen_movl_TN_reg(rd, cpu_dst);
3010                         break;
3011 #ifndef TARGET_SPARC64
3012                     case 0x25:  /* sll */
3013                         if (IS_IMM) { /* immediate */
3014                             rs2 = GET_FIELDs(insn, 20, 31);
3015                             tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3016                         } else { /* register */
3017                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3018                             tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3019                         }
3020                         gen_movl_TN_reg(rd, cpu_dst);
3021                         break;
3022                     case 0x26:  /* srl */
3023                         if (IS_IMM) { /* immediate */
3024                             rs2 = GET_FIELDs(insn, 20, 31);
3025                             tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3026                         } else { /* register */
3027                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3028                             tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3029                         }
3030                         gen_movl_TN_reg(rd, cpu_dst);
3031                         break;
3032                     case 0x27:  /* sra */
3033                         if (IS_IMM) { /* immediate */
3034                             rs2 = GET_FIELDs(insn, 20, 31);
3035                             tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3036                         } else { /* register */
3037                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3038                             tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3039                         }
3040                         gen_movl_TN_reg(rd, cpu_dst);
3041                         break;
3042 #endif
3043                     case 0x30:
3044                         {
3045                             switch(rd) {
3046                             case 0: /* wry */
3047                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3048                                 tcg_gen_st_tl(cpu_dst, cpu_env,
3049                                               offsetof(CPUSPARCState, y));
3050                                 break;
3051 #ifndef TARGET_SPARC64
3052                             case 0x01 ... 0x0f: /* undefined in the
3053                                                    SPARCv8 manual, nop
3054                                                    on the microSPARC
3055                                                    II */
3056                             case 0x10 ... 0x1f: /* implementation-dependent
3057                                                    in the SPARCv8
3058                                                    manual, nop on the
3059                                                    microSPARC II */
3060                                 break;
3061 #else
3062                             case 0x2: /* V9 wrccr */
3063                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3064                                 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3065                                 break;
3066                             case 0x3: /* V9 wrasi */
3067                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3068                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3069                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3070                                                offsetof(CPUSPARCState, asi));
3071                                 break;
3072                             case 0x6: /* V9 wrfprs */
3073                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3074                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3075                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3076                                                offsetof(CPUSPARCState, fprs));
3077                                 save_state(dc, cpu_cond);
3078                                 gen_op_next_insn();
3079                                 tcg_gen_exit_tb(0);
3080                                 dc->is_br = 1;
3081                                 break;
3082                             case 0xf: /* V9 sir, nop if user */
3083 #if !defined(CONFIG_USER_ONLY)
3084                                 if (supervisor(dc))
3085                                     ; // XXX
3086 #endif
3087                                 break;
3088                             case 0x13: /* Graphics Status */
3089                                 if (gen_trap_ifnofpu(dc, cpu_cond))
3090                                     goto jmp_insn;
3091                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3092                                 tcg_gen_st_tl(cpu_dst, cpu_env,
3093                                               offsetof(CPUSPARCState, gsr));
3094                                 break;
3095                             case 0x17: /* Tick compare */
3096 #if !defined(CONFIG_USER_ONLY)
3097                                 if (!supervisor(dc))
3098                                     goto illegal_insn;
3099 #endif
3100                                 {
3101                                     TCGv r_tickptr;
3102
3103                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3104                                                    cpu_src2);
3105                                     tcg_gen_st_tl(cpu_dst, cpu_env,
3106                                                   offsetof(CPUSPARCState,
3107                                                            tick_cmpr));
3108                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3109                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3110                                                    offsetof(CPUState, tick));
3111                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3112                                                        r_tickptr, cpu_dst);
3113                                 }
3114                                 break;
3115                             case 0x18: /* System tick */
3116 #if !defined(CONFIG_USER_ONLY)
3117                                 if (!supervisor(dc))
3118                                     goto illegal_insn;
3119 #endif
3120                                 {
3121                                     TCGv r_tickptr;
3122
3123                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3124                                                    cpu_src2);
3125                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3126                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3127                                                    offsetof(CPUState, stick));
3128                                     tcg_gen_helper_0_2(helper_tick_set_count,
3129                                                        r_tickptr, cpu_dst);
3130                                 }
3131                                 break;
3132                             case 0x19: /* System tick compare */
3133 #if !defined(CONFIG_USER_ONLY)
3134                                 if (!supervisor(dc))
3135                                     goto illegal_insn;
3136 #endif
3137                                 {
3138                                     TCGv r_tickptr;
3139
3140                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3141                                                    cpu_src2);
3142                                     tcg_gen_st_tl(cpu_dst, cpu_env,
3143                                                   offsetof(CPUSPARCState,
3144                                                            stick_cmpr));
3145                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3146                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3147                                                    offsetof(CPUState, stick));
3148                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3149                                                        r_tickptr, cpu_dst);
3150                                 }
3151                                 break;
3152
3153                             case 0x10: /* Performance Control */
3154                             case 0x11: /* Performance Instrumentation
3155                                           Counter */
3156                             case 0x12: /* Dispatch Control */
3157                             case 0x14: /* Softint set */
3158                             case 0x15: /* Softint clear */
3159                             case 0x16: /* Softint write */
3160 #endif
3161                             default:
3162                                 goto illegal_insn;
3163                             }
3164                         }
3165                         break;
3166 #if !defined(CONFIG_USER_ONLY)
3167                     case 0x31: /* wrpsr, V9 saved, restored */
3168                         {
3169                             if (!supervisor(dc))
3170                                 goto priv_insn;
3171 #ifdef TARGET_SPARC64
3172                             switch (rd) {
3173                             case 0:
3174                                 tcg_gen_helper_0_0(helper_saved);
3175                                 break;
3176                             case 1:
3177                                 tcg_gen_helper_0_0(helper_restored);
3178                                 break;
3179                             case 2: /* UA2005 allclean */
3180                             case 3: /* UA2005 otherw */
3181                             case 4: /* UA2005 normalw */
3182                             case 5: /* UA2005 invalw */
3183                                 // XXX
3184                             default:
3185                                 goto illegal_insn;
3186                             }
3187 #else
3188                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3189                             tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3190                             save_state(dc, cpu_cond);
3191                             gen_op_next_insn();
3192                             tcg_gen_exit_tb(0);
3193                             dc->is_br = 1;
3194 #endif
3195                         }
3196                         break;
3197                     case 0x32: /* wrwim, V9 wrpr */
3198                         {
3199                             if (!supervisor(dc))
3200                                 goto priv_insn;
3201                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3202 #ifdef TARGET_SPARC64
3203                             switch (rd) {
3204                             case 0: // tpc
3205                                 {
3206                                     TCGv r_tsptr;
3207
3208                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3209                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3210                                                    offsetof(CPUState, tsptr));
3211                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3212                                                   offsetof(trap_state, tpc));
3213                                 }
3214                                 break;
3215                             case 1: // tnpc
3216                                 {
3217                                     TCGv r_tsptr;
3218
3219                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3220                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3221                                                    offsetof(CPUState, tsptr));
3222                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3223                                                   offsetof(trap_state, tnpc));
3224                                 }
3225                                 break;
3226                             case 2: // tstate
3227                                 {
3228                                     TCGv r_tsptr;
3229
3230                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3231                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3232                                                    offsetof(CPUState, tsptr));
3233                                     tcg_gen_st_tl(cpu_dst, r_tsptr,
3234                                                   offsetof(trap_state,
3235                                                            tstate));
3236                                 }
3237                                 break;
3238                             case 3: // tt
3239                                 {
3240                                     TCGv r_tsptr;
3241
3242                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3243                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3244                                                    offsetof(CPUState, tsptr));
3245                                     tcg_gen_st_i32(cpu_dst, r_tsptr,
3246                                                    offsetof(trap_state, tt));
3247                                 }
3248                                 break;
3249                             case 4: // tick
3250                                 {
3251                                     TCGv r_tickptr;
3252
3253                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3254                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3255                                                    offsetof(CPUState, tick));
3256                                     tcg_gen_helper_0_2(helper_tick_set_count,
3257                                                        r_tickptr, cpu_dst);
3258                                 }
3259                                 break;
3260                             case 5: // tba
3261                                 tcg_gen_st_tl(cpu_dst, cpu_env,
3262                                               offsetof(CPUSPARCState, tbr));
3263                                 break;
3264                             case 6: // pstate
3265                                 save_state(dc, cpu_cond);
3266                                 tcg_gen_helper_0_1(helper_wrpstate, cpu_dst);
3267                                 gen_op_next_insn();
3268                                 tcg_gen_exit_tb(0);
3269                                 dc->is_br = 1;
3270                                 break;
3271                             case 7: // tl
3272                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3273                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3274                                                offsetof(CPUSPARCState, tl));
3275                                 break;
3276                             case 8: // pil
3277                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3278                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3279                                                offsetof(CPUSPARCState,
3280                                                         psrpil));
3281                                 break;
3282                             case 9: // cwp
3283                                 tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
3284                                 break;
3285                             case 10: // cansave
3286                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3287                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3288                                                offsetof(CPUSPARCState,
3289                                                         cansave));
3290                                 break;
3291                             case 11: // canrestore
3292                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3293                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3294                                                offsetof(CPUSPARCState,
3295                                                         canrestore));
3296                                 break;
3297                             case 12: // cleanwin
3298                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3299                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3300                                                offsetof(CPUSPARCState,
3301                                                         cleanwin));
3302                                 break;
3303                             case 13: // otherwin
3304                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3305                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3306                                                offsetof(CPUSPARCState,
3307                                                         otherwin));
3308                                 break;
3309                             case 14: // wstate
3310                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3311                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3312                                                offsetof(CPUSPARCState,
3313                                                         wstate));
3314                                 break;
3315                             case 16: // UA2005 gl
3316                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3317                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3318                                                offsetof(CPUSPARCState, gl));
3319                                 break;
3320                             case 26: // UA2005 strand status
3321                                 if (!hypervisor(dc))
3322                                     goto priv_insn;
3323                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3324                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3325                                                offsetof(CPUSPARCState, ssr));
3326                                 break;
3327                             default:
3328                                 goto illegal_insn;
3329                             }
3330 #else
3331                             tcg_gen_andi_tl(cpu_dst, cpu_dst,
3332                                             ((1 << NWINDOWS) - 1));
3333                             tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3334                             tcg_gen_st_i32(cpu_tmp32, cpu_env,
3335                                            offsetof(CPUSPARCState, wim));
3336 #endif
3337                         }
3338                         break;
3339                     case 0x33: /* wrtbr, UA2005 wrhpr */
3340                         {
3341 #ifndef TARGET_SPARC64
3342                             if (!supervisor(dc))
3343                                 goto priv_insn;
3344                             tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3345                             tcg_gen_st_tl(cpu_dst, cpu_env,
3346                                           offsetof(CPUSPARCState, tbr));
3347 #else
3348                             if (!hypervisor(dc))
3349                                 goto priv_insn;
3350                             tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3351                             switch (rd) {
3352                             case 0: // hpstate
3353                                 // XXX gen_op_wrhpstate();
3354                                 save_state(dc, cpu_cond);
3355                                 gen_op_next_insn();
3356                                 tcg_gen_exit_tb(0);
3357                                 dc->is_br = 1;
3358                                 break;
3359                             case 1: // htstate
3360                                 // XXX gen_op_wrhtstate();
3361                                 break;
3362                             case 3: // hintp
3363                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3364                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3365                                                offsetof(CPUSPARCState, hintp));
3366                                 break;
3367                             case 5: // htba
3368                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3369                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3370                                                offsetof(CPUSPARCState, htba));
3371                                 break;
3372                             case 31: // hstick_cmpr
3373                                 {
3374                                     TCGv r_tickptr;
3375
3376                                     tcg_gen_st_tl(cpu_dst, cpu_env,
3377                                                   offsetof(CPUSPARCState,
3378                                                            hstick_cmpr));
3379                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3380                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3381                                                    offsetof(CPUState, hstick));
3382                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3383                                                        r_tickptr, cpu_dst);
3384                                 }
3385                                 break;
3386                             case 6: // hver readonly
3387                             default:
3388                                 goto illegal_insn;
3389                             }
3390 #endif
3391                         }
3392                         break;
3393 #endif
3394 #ifdef TARGET_SPARC64
3395                     case 0x2c: /* V9 movcc */
3396                         {
3397                             int cc = GET_FIELD_SP(insn, 11, 12);
3398                             int cond = GET_FIELD_SP(insn, 14, 17);
3399                             TCGv r_cond;
3400                             int l1;
3401
3402                             r_cond = tcg_temp_new(TCG_TYPE_TL);
3403                             if (insn & (1 << 18)) {
3404                                 if (cc == 0)
3405                                     gen_cond(r_cond, 0, cond);
3406                                 else if (cc == 2)
3407                                     gen_cond(r_cond, 1, cond);
3408                                 else
3409                                     goto illegal_insn;
3410                             } else {
3411                                 gen_fcond(r_cond, cc, cond);
3412                             }
3413
3414                             l1 = gen_new_label();
3415
3416                             tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3417                             if (IS_IMM) {       /* immediate */
3418                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
3419                                 gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
3420                             } else {
3421                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3422                                 gen_movl_reg_TN(rs2, cpu_tmp0);
3423                                 gen_movl_TN_reg(rd, cpu_tmp0);
3424                             }
3425                             gen_set_label(l1);
3426                             break;
3427                         }
3428                     case 0x2d: /* V9 sdivx */
3429                         gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3430                         gen_movl_TN_reg(rd, cpu_dst);
3431                         break;
3432                     case 0x2e: /* V9 popc */
3433                         {
3434                             cpu_src2 = get_src2(insn, cpu_src2);
3435                             tcg_gen_helper_1_1(helper_popc, cpu_dst,
3436                                                cpu_src2);
3437                             gen_movl_TN_reg(rd, cpu_dst);
3438                         }
3439                     case 0x2f: /* V9 movr */
3440                         {
3441                             int cond = GET_FIELD_SP(insn, 10, 12);
3442                             int l1;
3443
3444                             cpu_src1 = get_src1(insn, cpu_src1);
3445
3446                             l1 = gen_new_label();
3447
3448                             tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3449                                               cpu_src1, 0, l1);
3450                             if (IS_IMM) {       /* immediate */
3451                                 rs2 = GET_FIELD_SPs(insn, 0, 9);
3452                                 gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
3453                             } else {
3454                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3455                                 gen_movl_reg_TN(rs2, cpu_tmp0);
3456                                 gen_movl_TN_reg(rd, cpu_tmp0);
3457                             }
3458                             gen_set_label(l1);
3459                             break;
3460                         }
3461 #endif
3462                     default:
3463                         goto illegal_insn;
3464                     }
3465                 }
3466             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3467 #ifdef TARGET_SPARC64
3468                 int opf = GET_FIELD_SP(insn, 5, 13);
3469                 rs1 = GET_FIELD(insn, 13, 17);
3470                 rs2 = GET_FIELD(insn, 27, 31);
3471                 if (gen_trap_ifnofpu(dc, cpu_cond))
3472                     goto jmp_insn;
3473
3474                 switch (opf) {
3475                 case 0x000: /* VIS I edge8cc */
3476                 case 0x001: /* VIS II edge8n */
3477                 case 0x002: /* VIS I edge8lcc */
3478                 case 0x003: /* VIS II edge8ln */
3479                 case 0x004: /* VIS I edge16cc */
3480                 case 0x005: /* VIS II edge16n */
3481                 case 0x006: /* VIS I edge16lcc */
3482                 case 0x007: /* VIS II edge16ln */
3483                 case 0x008: /* VIS I edge32cc */
3484                 case 0x009: /* VIS II edge32n */
3485                 case 0x00a: /* VIS I edge32lcc */
3486                 case 0x00b: /* VIS II edge32ln */
3487                     // XXX
3488                     goto illegal_insn;
3489                 case 0x010: /* VIS I array8 */
3490                     CHECK_FPU_FEATURE(dc, VIS1);
3491                     cpu_src1 = get_src1(insn, cpu_src1);
3492                     gen_movl_reg_TN(rs2, cpu_src2);
3493                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3494                                        cpu_src2);
3495                     gen_movl_TN_reg(rd, cpu_dst);
3496                     break;
3497                 case 0x012: /* VIS I array16 */
3498                     CHECK_FPU_FEATURE(dc, VIS1);
3499                     cpu_src1 = get_src1(insn, cpu_src1);
3500                     gen_movl_reg_TN(rs2, cpu_src2);
3501                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3502                                        cpu_src2);
3503                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3504                     gen_movl_TN_reg(rd, cpu_dst);
3505                     break;
3506                 case 0x014: /* VIS I array32 */
3507                     CHECK_FPU_FEATURE(dc, VIS1);
3508                     cpu_src1 = get_src1(insn, cpu_src1);
3509                     gen_movl_reg_TN(rs2, cpu_src2);
3510                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3511                                        cpu_src2);
3512                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3513                     gen_movl_TN_reg(rd, cpu_dst);
3514                     break;
3515                 case 0x018: /* VIS I alignaddr */
3516                     CHECK_FPU_FEATURE(dc, VIS1);
3517                     cpu_src1 = get_src1(insn, cpu_src1);
3518                     gen_movl_reg_TN(rs2, cpu_src2);
3519                     tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3520                                        cpu_src2);
3521                     gen_movl_TN_reg(rd, cpu_dst);
3522                     break;
3523                 case 0x019: /* VIS II bmask */
3524                 case 0x01a: /* VIS I alignaddrl */
3525                     // XXX
3526                     goto illegal_insn;
3527                 case 0x020: /* VIS I fcmple16 */
3528                     CHECK_FPU_FEATURE(dc, VIS1);
3529                     gen_op_load_fpr_DT0(DFPREG(rs1));
3530                     gen_op_load_fpr_DT1(DFPREG(rs2));
3531                     tcg_gen_helper_0_0(helper_fcmple16);
3532                     gen_op_store_DT0_fpr(DFPREG(rd));
3533                     break;
3534                 case 0x022: /* VIS I fcmpne16 */
3535                     CHECK_FPU_FEATURE(dc, VIS1);
3536                     gen_op_load_fpr_DT0(DFPREG(rs1));
3537                     gen_op_load_fpr_DT1(DFPREG(rs2));
3538                     tcg_gen_helper_0_0(helper_fcmpne16);
3539                     gen_op_store_DT0_fpr(DFPREG(rd));
3540                     break;
3541                 case 0x024: /* VIS I fcmple32 */
3542                     CHECK_FPU_FEATURE(dc, VIS1);
3543                     gen_op_load_fpr_DT0(DFPREG(rs1));
3544                     gen_op_load_fpr_DT1(DFPREG(rs2));
3545                     tcg_gen_helper_0_0(helper_fcmple32);
3546                     gen_op_store_DT0_fpr(DFPREG(rd));
3547                     break;
3548                 case 0x026: /* VIS I fcmpne32 */
3549                     CHECK_FPU_FEATURE(dc, VIS1);
3550                     gen_op_load_fpr_DT0(DFPREG(rs1));
3551                     gen_op_load_fpr_DT1(DFPREG(rs2));
3552                     tcg_gen_helper_0_0(helper_fcmpne32);
3553                     gen_op_store_DT0_fpr(DFPREG(rd));
3554                     break;
3555                 case 0x028: /* VIS I fcmpgt16 */
3556                     CHECK_FPU_FEATURE(dc, VIS1);
3557                     gen_op_load_fpr_DT0(DFPREG(rs1));
3558                     gen_op_load_fpr_DT1(DFPREG(rs2));
3559                     tcg_gen_helper_0_0(helper_fcmpgt16);
3560                     gen_op_store_DT0_fpr(DFPREG(rd));
3561                     break;
3562                 case 0x02a: /* VIS I fcmpeq16 */
3563                     CHECK_FPU_FEATURE(dc, VIS1);
3564                     gen_op_load_fpr_DT0(DFPREG(rs1));
3565                     gen_op_load_fpr_DT1(DFPREG(rs2));
3566                     tcg_gen_helper_0_0(helper_fcmpeq16);
3567                     gen_op_store_DT0_fpr(DFPREG(rd));
3568                     break;
3569                 case 0x02c: /* VIS I fcmpgt32 */
3570                     CHECK_FPU_FEATURE(dc, VIS1);
3571                     gen_op_load_fpr_DT0(DFPREG(rs1));
3572                     gen_op_load_fpr_DT1(DFPREG(rs2));
3573                     tcg_gen_helper_0_0(helper_fcmpgt32);
3574                     gen_op_store_DT0_fpr(DFPREG(rd));
3575                     break;
3576                 case 0x02e: /* VIS I fcmpeq32 */
3577                     CHECK_FPU_FEATURE(dc, VIS1);
3578                     gen_op_load_fpr_DT0(DFPREG(rs1));
3579                     gen_op_load_fpr_DT1(DFPREG(rs2));
3580                     tcg_gen_helper_0_0(helper_fcmpeq32);
3581                     gen_op_store_DT0_fpr(DFPREG(rd));
3582                     break;
3583                 case 0x031: /* VIS I fmul8x16 */
3584                     CHECK_FPU_FEATURE(dc, VIS1);
3585                     gen_op_load_fpr_DT0(DFPREG(rs1));
3586                     gen_op_load_fpr_DT1(DFPREG(rs2));
3587                     tcg_gen_helper_0_0(helper_fmul8x16);
3588                     gen_op_store_DT0_fpr(DFPREG(rd));
3589                     break;
3590                 case 0x033: /* VIS I fmul8x16au */
3591                     CHECK_FPU_FEATURE(dc, VIS1);
3592                     gen_op_load_fpr_DT0(DFPREG(rs1));
3593                     gen_op_load_fpr_DT1(DFPREG(rs2));
3594                     tcg_gen_helper_0_0(helper_fmul8x16au);
3595                     gen_op_store_DT0_fpr(DFPREG(rd));
3596                     break;
3597                 case 0x035: /* VIS I fmul8x16al */
3598                     CHECK_FPU_FEATURE(dc, VIS1);
3599                     gen_op_load_fpr_DT0(DFPREG(rs1));
3600                     gen_op_load_fpr_DT1(DFPREG(rs2));
3601                     tcg_gen_helper_0_0(helper_fmul8x16al);
3602                     gen_op_store_DT0_fpr(DFPREG(rd));
3603                     break;
3604                 case 0x036: /* VIS I fmul8sux16 */
3605                     CHECK_FPU_FEATURE(dc, VIS1);
3606                     gen_op_load_fpr_DT0(DFPREG(rs1));
3607                     gen_op_load_fpr_DT1(DFPREG(rs2));
3608                     tcg_gen_helper_0_0(helper_fmul8sux16);
3609                     gen_op_store_DT0_fpr(DFPREG(rd));
3610                     break;
3611                 case 0x037: /* VIS I fmul8ulx16 */
3612                     CHECK_FPU_FEATURE(dc, VIS1);
3613                     gen_op_load_fpr_DT0(DFPREG(rs1));
3614                     gen_op_load_fpr_DT1(DFPREG(rs2));
3615                     tcg_gen_helper_0_0(helper_fmul8ulx16);
3616                     gen_op_store_DT0_fpr(DFPREG(rd));
3617                     break;
3618                 case 0x038: /* VIS I fmuld8sux16 */
3619                     CHECK_FPU_FEATURE(dc, VIS1);
3620                     gen_op_load_fpr_DT0(DFPREG(rs1));
3621                     gen_op_load_fpr_DT1(DFPREG(rs2));
3622                     tcg_gen_helper_0_0(helper_fmuld8sux16);
3623                     gen_op_store_DT0_fpr(DFPREG(rd));
3624                     break;
3625                 case 0x039: /* VIS I fmuld8ulx16 */
3626                     CHECK_FPU_FEATURE(dc, VIS1);
3627                     gen_op_load_fpr_DT0(DFPREG(rs1));
3628                     gen_op_load_fpr_DT1(DFPREG(rs2));
3629                     tcg_gen_helper_0_0(helper_fmuld8ulx16);
3630                     gen_op_store_DT0_fpr(DFPREG(rd));
3631                     break;
3632                 case 0x03a: /* VIS I fpack32 */
3633                 case 0x03b: /* VIS I fpack16 */
3634                 case 0x03d: /* VIS I fpackfix */
3635                 case 0x03e: /* VIS I pdist */
3636                     // XXX
3637                     goto illegal_insn;
3638                 case 0x048: /* VIS I faligndata */
3639                     CHECK_FPU_FEATURE(dc, VIS1);
3640                     gen_op_load_fpr_DT0(DFPREG(rs1));
3641                     gen_op_load_fpr_DT1(DFPREG(rs2));
3642                     tcg_gen_helper_0_0(helper_faligndata);
3643                     gen_op_store_DT0_fpr(DFPREG(rd));
3644                     break;
3645                 case 0x04b: /* VIS I fpmerge */
3646                     CHECK_FPU_FEATURE(dc, VIS1);
3647                     gen_op_load_fpr_DT0(DFPREG(rs1));
3648                     gen_op_load_fpr_DT1(DFPREG(rs2));
3649                     tcg_gen_helper_0_0(helper_fpmerge);
3650                     gen_op_store_DT0_fpr(DFPREG(rd));
3651                     break;
3652                 case 0x04c: /* VIS II bshuffle */
3653                     // XXX
3654                     goto illegal_insn;
3655                 case 0x04d: /* VIS I fexpand */
3656                     CHECK_FPU_FEATURE(dc, VIS1);
3657                     gen_op_load_fpr_DT0(DFPREG(rs1));
3658                     gen_op_load_fpr_DT1(DFPREG(rs2));
3659                     tcg_gen_helper_0_0(helper_fexpand);
3660                     gen_op_store_DT0_fpr(DFPREG(rd));
3661                     break;
3662                 case 0x050: /* VIS I fpadd16 */
3663                     CHECK_FPU_FEATURE(dc, VIS1);
3664                     gen_op_load_fpr_DT0(DFPREG(rs1));
3665                     gen_op_load_fpr_DT1(DFPREG(rs2));
3666                     tcg_gen_helper_0_0(helper_fpadd16);
3667                     gen_op_store_DT0_fpr(DFPREG(rd));
3668                     break;
3669                 case 0x051: /* VIS I fpadd16s */
3670                     CHECK_FPU_FEATURE(dc, VIS1);
3671                     gen_op_load_fpr_FT0(rs1);
3672                     gen_op_load_fpr_FT1(rs2);
3673                     tcg_gen_helper_0_0(helper_fpadd16s);
3674                     gen_op_store_FT0_fpr(rd);
3675                     break;
3676                 case 0x052: /* VIS I fpadd32 */
3677                     CHECK_FPU_FEATURE(dc, VIS1);
3678                     gen_op_load_fpr_DT0(DFPREG(rs1));
3679                     gen_op_load_fpr_DT1(DFPREG(rs2));
3680                     tcg_gen_helper_0_0(helper_fpadd32);
3681                     gen_op_store_DT0_fpr(DFPREG(rd));
3682                     break;
3683                 case 0x053: /* VIS I fpadd32s */
3684                     CHECK_FPU_FEATURE(dc, VIS1);
3685                     gen_op_load_fpr_FT0(rs1);
3686                     gen_op_load_fpr_FT1(rs2);
3687                     tcg_gen_helper_0_0(helper_fpadd32s);
3688                     gen_op_store_FT0_fpr(rd);
3689                     break;
3690                 case 0x054: /* VIS I fpsub16 */
3691                     CHECK_FPU_FEATURE(dc, VIS1);
3692                     gen_op_load_fpr_DT0(DFPREG(rs1));
3693                     gen_op_load_fpr_DT1(DFPREG(rs2));
3694                     tcg_gen_helper_0_0(helper_fpsub16);
3695                     gen_op_store_DT0_fpr(DFPREG(rd));
3696                     break;
3697                 case 0x055: /* VIS I fpsub16s */
3698                     CHECK_FPU_FEATURE(dc, VIS1);
3699                     gen_op_load_fpr_FT0(rs1);
3700                     gen_op_load_fpr_FT1(rs2);
3701                     tcg_gen_helper_0_0(helper_fpsub16s);
3702                     gen_op_store_FT0_fpr(rd);
3703                     break;
3704                 case 0x056: /* VIS I fpsub32 */
3705                     CHECK_FPU_FEATURE(dc, VIS1);
3706                     gen_op_load_fpr_DT0(DFPREG(rs1));
3707                     gen_op_load_fpr_DT1(DFPREG(rs2));
3708                     tcg_gen_helper_0_0(helper_fpadd32);
3709                     gen_op_store_DT0_fpr(DFPREG(rd));
3710                     break;
3711                 case 0x057: /* VIS I fpsub32s */
3712                     CHECK_FPU_FEATURE(dc, VIS1);
3713                     gen_op_load_fpr_FT0(rs1);
3714                     gen_op_load_fpr_FT1(rs2);
3715                     tcg_gen_helper_0_0(helper_fpsub32s);
3716                     gen_op_store_FT0_fpr(rd);
3717                     break;
3718                 case 0x060: /* VIS I fzero */
3719                     CHECK_FPU_FEATURE(dc, VIS1);
3720                     tcg_gen_helper_0_0(helper_movl_DT0_0);
3721                     gen_op_store_DT0_fpr(DFPREG(rd));
3722                     break;
3723                 case 0x061: /* VIS I fzeros */
3724                     CHECK_FPU_FEATURE(dc, VIS1);
3725                     tcg_gen_helper_0_0(helper_movl_FT0_0);
3726                     gen_op_store_FT0_fpr(rd);
3727                     break;
3728                 case 0x062: /* VIS I fnor */
3729                     CHECK_FPU_FEATURE(dc, VIS1);
3730                     gen_op_load_fpr_DT0(DFPREG(rs1));
3731                     gen_op_load_fpr_DT1(DFPREG(rs2));
3732                     tcg_gen_helper_0_0(helper_fnor);
3733                     gen_op_store_DT0_fpr(DFPREG(rd));
3734                     break;
3735                 case 0x063: /* VIS I fnors */
3736                     CHECK_FPU_FEATURE(dc, VIS1);
3737                     gen_op_load_fpr_FT0(rs1);
3738                     gen_op_load_fpr_FT1(rs2);
3739                     tcg_gen_helper_0_0(helper_fnors);
3740                     gen_op_store_FT0_fpr(rd);
3741                     break;
3742                 case 0x064: /* VIS I fandnot2 */
3743                     CHECK_FPU_FEATURE(dc, VIS1);
3744                     gen_op_load_fpr_DT1(DFPREG(rs1));
3745                     gen_op_load_fpr_DT0(DFPREG(rs2));
3746                     tcg_gen_helper_0_0(helper_fandnot);
3747                     gen_op_store_DT0_fpr(DFPREG(rd));
3748                     break;
3749                 case 0x065: /* VIS I fandnot2s */
3750                     CHECK_FPU_FEATURE(dc, VIS1);
3751                     gen_op_load_fpr_FT1(rs1);
3752                     gen_op_load_fpr_FT0(rs2);
3753                     tcg_gen_helper_0_0(helper_fandnots);
3754                     gen_op_store_FT0_fpr(rd);
3755                     break;
3756                 case 0x066: /* VIS I fnot2 */
3757                     CHECK_FPU_FEATURE(dc, VIS1);
3758                     gen_op_load_fpr_DT1(DFPREG(rs2));
3759                     tcg_gen_helper_0_0(helper_fnot);
3760                     gen_op_store_DT0_fpr(DFPREG(rd));
3761                     break;
3762                 case 0x067: /* VIS I fnot2s */
3763                     CHECK_FPU_FEATURE(dc, VIS1);
3764                     gen_op_load_fpr_FT1(rs2);
3765                     tcg_gen_helper_0_0(helper_fnot);
3766                     gen_op_store_FT0_fpr(rd);
3767                     break;
3768                 case 0x068: /* VIS I fandnot1 */
3769                     CHECK_FPU_FEATURE(dc, VIS1);
3770                     gen_op_load_fpr_DT0(DFPREG(rs1));
3771                     gen_op_load_fpr_DT1(DFPREG(rs2));
3772                     tcg_gen_helper_0_0(helper_fandnot);
3773                     gen_op_store_DT0_fpr(DFPREG(rd));
3774                     break;
3775                 case 0x069: /* VIS I fandnot1s */
3776                     CHECK_FPU_FEATURE(dc, VIS1);
3777                     gen_op_load_fpr_FT0(rs1);
3778                     gen_op_load_fpr_FT1(rs2);
3779                     tcg_gen_helper_0_0(helper_fandnots);
3780                     gen_op_store_FT0_fpr(rd);
3781                     break;
3782                 case 0x06a: /* VIS I fnot1 */
3783                     CHECK_FPU_FEATURE(dc, VIS1);
3784                     gen_op_load_fpr_DT1(DFPREG(rs1));
3785                     tcg_gen_helper_0_0(helper_fnot);
3786                     gen_op_store_DT0_fpr(DFPREG(rd));
3787                     break;
3788                 case 0x06b: /* VIS I fnot1s */
3789                     CHECK_FPU_FEATURE(dc, VIS1);
3790                     gen_op_load_fpr_FT1(rs1);
3791                     tcg_gen_helper_0_0(helper_fnot);
3792                     gen_op_store_FT0_fpr(rd);
3793                     break;
3794                 case 0x06c: /* VIS I fxor */
3795                     CHECK_FPU_FEATURE(dc, VIS1);
3796                     gen_op_load_fpr_DT0(DFPREG(rs1));
3797                     gen_op_load_fpr_DT1(DFPREG(rs2));
3798                     tcg_gen_helper_0_0(helper_fxor);
3799                     gen_op_store_DT0_fpr(DFPREG(rd));
3800                     break;
3801                 case 0x06d: /* VIS I fxors */
3802                     CHECK_FPU_FEATURE(dc, VIS1);
3803                     gen_op_load_fpr_FT0(rs1);
3804                     gen_op_load_fpr_FT1(rs2);
3805                     tcg_gen_helper_0_0(helper_fxors);
3806                     gen_op_store_FT0_fpr(rd);
3807                     break;
3808                 case 0x06e: /* VIS I fnand */
3809                     CHECK_FPU_FEATURE(dc, VIS1);
3810                     gen_op_load_fpr_DT0(DFPREG(rs1));
3811                     gen_op_load_fpr_DT1(DFPREG(rs2));
3812                     tcg_gen_helper_0_0(helper_fnand);
3813                     gen_op_store_DT0_fpr(DFPREG(rd));
3814                     break;
3815                 case 0x06f: /* VIS I fnands */
3816                     CHECK_FPU_FEATURE(dc, VIS1);
3817                     gen_op_load_fpr_FT0(rs1);
3818                     gen_op_load_fpr_FT1(rs2);
3819                     tcg_gen_helper_0_0(helper_fnands);
3820                     gen_op_store_FT0_fpr(rd);
3821                     break;
3822                 case 0x070: /* VIS I fand */
3823                     CHECK_FPU_FEATURE(dc, VIS1);
3824                     gen_op_load_fpr_DT0(DFPREG(rs1));
3825                     gen_op_load_fpr_DT1(DFPREG(rs2));
3826                     tcg_gen_helper_0_0(helper_fand);
3827                     gen_op_store_DT0_fpr(DFPREG(rd));
3828                     break;
3829                 case 0x071: /* VIS I fands */
3830                     CHECK_FPU_FEATURE(dc, VIS1);
3831                     gen_op_load_fpr_FT0(rs1);
3832                     gen_op_load_fpr_FT1(rs2);
3833                     tcg_gen_helper_0_0(helper_fands);
3834                     gen_op_store_FT0_fpr(rd);
3835                     break;
3836                 case 0x072: /* VIS I fxnor */
3837                     CHECK_FPU_FEATURE(dc, VIS1);
3838                     gen_op_load_fpr_DT0(DFPREG(rs1));
3839                     gen_op_load_fpr_DT1(DFPREG(rs2));
3840                     tcg_gen_helper_0_0(helper_fxnor);
3841                     gen_op_store_DT0_fpr(DFPREG(rd));
3842                     break;
3843                 case 0x073: /* VIS I fxnors */
3844                     CHECK_FPU_FEATURE(dc, VIS1);
3845                     gen_op_load_fpr_FT0(rs1);
3846                     gen_op_load_fpr_FT1(rs2);
3847                     tcg_gen_helper_0_0(helper_fxnors);
3848                     gen_op_store_FT0_fpr(rd);
3849                     break;
3850                 case 0x074: /* VIS I fsrc1 */
3851                     CHECK_FPU_FEATURE(dc, VIS1);
3852                     gen_op_load_fpr_DT0(DFPREG(rs1));
3853                     gen_op_store_DT0_fpr(DFPREG(rd));
3854                     break;
3855                 case 0x075: /* VIS I fsrc1s */
3856                     CHECK_FPU_FEATURE(dc, VIS1);
3857                     gen_op_load_fpr_FT0(rs1);
3858                     gen_op_store_FT0_fpr(rd);
3859                     break;
3860                 case 0x076: /* VIS I fornot2 */
3861                     CHECK_FPU_FEATURE(dc, VIS1);
3862                     gen_op_load_fpr_DT1(DFPREG(rs1));
3863                     gen_op_load_fpr_DT0(DFPREG(rs2));
3864                     tcg_gen_helper_0_0(helper_fornot);
3865                     gen_op_store_DT0_fpr(DFPREG(rd));
3866                     break;
3867                 case 0x077: /* VIS I fornot2s */
3868                     CHECK_FPU_FEATURE(dc, VIS1);
3869                     gen_op_load_fpr_FT1(rs1);
3870                     gen_op_load_fpr_FT0(rs2);
3871                     tcg_gen_helper_0_0(helper_fornots);
3872                     gen_op_store_FT0_fpr(rd);
3873                     break;
3874                 case 0x078: /* VIS I fsrc2 */
3875                     CHECK_FPU_FEATURE(dc, VIS1);
3876                     gen_op_load_fpr_DT0(DFPREG(rs2));
3877                     gen_op_store_DT0_fpr(DFPREG(rd));
3878                     break;
3879                 case 0x079: /* VIS I fsrc2s */
3880                     CHECK_FPU_FEATURE(dc, VIS1);
3881                     gen_op_load_fpr_FT0(rs2);
3882                     gen_op_store_FT0_fpr(rd);
3883                     break;
3884                 case 0x07a: /* VIS I fornot1 */
3885                     CHECK_FPU_FEATURE(dc, VIS1);
3886                     gen_op_load_fpr_DT0(DFPREG(rs1));
3887                     gen_op_load_fpr_DT1(DFPREG(rs2));
3888                     tcg_gen_helper_0_0(helper_fornot);
3889                     gen_op_store_DT0_fpr(DFPREG(rd));
3890                     break;
3891                 case 0x07b: /* VIS I fornot1s */
3892                     CHECK_FPU_FEATURE(dc, VIS1);
3893                     gen_op_load_fpr_FT0(rs1);
3894                     gen_op_load_fpr_FT1(rs2);
3895                     tcg_gen_helper_0_0(helper_fornots);
3896                     gen_op_store_FT0_fpr(rd);
3897                     break;
3898                 case 0x07c: /* VIS I for */
3899                     CHECK_FPU_FEATURE(dc, VIS1);
3900                     gen_op_load_fpr_DT0(DFPREG(rs1));
3901                     gen_op_load_fpr_DT1(DFPREG(rs2));
3902                     tcg_gen_helper_0_0(helper_for);
3903                     gen_op_store_DT0_fpr(DFPREG(rd));
3904                     break;
3905                 case 0x07d: /* VIS I fors */
3906                     CHECK_FPU_FEATURE(dc, VIS1);
3907                     gen_op_load_fpr_FT0(rs1);
3908                     gen_op_load_fpr_FT1(rs2);
3909                     tcg_gen_helper_0_0(helper_fors);
3910                     gen_op_store_FT0_fpr(rd);
3911                     break;
3912                 case 0x07e: /* VIS I fone */
3913                     CHECK_FPU_FEATURE(dc, VIS1);
3914                     tcg_gen_helper_0_0(helper_movl_DT0_1);
3915                     gen_op_store_DT0_fpr(DFPREG(rd));
3916                     break;
3917                 case 0x07f: /* VIS I fones */
3918                     CHECK_FPU_FEATURE(dc, VIS1);
3919                     tcg_gen_helper_0_0(helper_movl_FT0_1);
3920                     gen_op_store_FT0_fpr(rd);
3921                     break;
3922                 case 0x080: /* VIS I shutdown */
3923                 case 0x081: /* VIS II siam */
3924                     // XXX
3925                     goto illegal_insn;
3926                 default:
3927                     goto illegal_insn;
3928                 }
3929 #else
3930                 goto ncp_insn;
3931 #endif
3932             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
3933 #ifdef TARGET_SPARC64
3934                 goto illegal_insn;
3935 #else
3936                 goto ncp_insn;
3937 #endif
3938 #ifdef TARGET_SPARC64
3939             } else if (xop == 0x39) { /* V9 return */
3940                 save_state(dc, cpu_cond);
3941                 cpu_src1 = get_src1(insn, cpu_src1);
3942                 if (IS_IMM) {   /* immediate */
3943                     rs2 = GET_FIELDs(insn, 19, 31);
3944                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3945                 } else {                /* register */
3946                     rs2 = GET_FIELD(insn, 27, 31);
3947                     if (rs2) {
3948                         gen_movl_reg_TN(rs2, cpu_src2);
3949                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3950                     } else
3951                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
3952                 }
3953                 tcg_gen_helper_0_0(helper_restore);
3954                 gen_mov_pc_npc(dc, cpu_cond);
3955                 tcg_gen_helper_0_2(helper_check_align, cpu_dst,
3956                                    tcg_const_i32(3));
3957                 tcg_gen_mov_tl(cpu_npc, cpu_dst);
3958                 dc->npc = DYNAMIC_PC;
3959                 goto jmp_insn;
3960 #endif
3961             } else {
3962                 cpu_src1 = get_src1(insn, cpu_src1);
3963                 if (IS_IMM) {   /* immediate */
3964                     rs2 = GET_FIELDs(insn, 19, 31);
3965                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3966                 } else {                /* register */
3967                     rs2 = GET_FIELD(insn, 27, 31);
3968                     if (rs2) {
3969                         gen_movl_reg_TN(rs2, cpu_src2);
3970                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3971                     } else
3972                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
3973                 }
3974                 switch (xop) {
3975                 case 0x38:      /* jmpl */
3976                     {
3977                         gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
3978                         gen_mov_pc_npc(dc, cpu_cond);
3979                         tcg_gen_helper_0_2(helper_check_align, cpu_dst,
3980                                            tcg_const_i32(3));
3981                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
3982                         dc->npc = DYNAMIC_PC;
3983                     }
3984                     goto jmp_insn;
3985 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3986                 case 0x39:      /* rett, V9 return */
3987                     {
3988                         if (!supervisor(dc))
3989                             goto priv_insn;
3990                         gen_mov_pc_npc(dc, cpu_cond);
3991                         tcg_gen_helper_0_2(helper_check_align, cpu_dst,
3992                                            tcg_const_i32(3));
3993                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
3994                         dc->npc = DYNAMIC_PC;
3995                         tcg_gen_helper_0_0(helper_rett);
3996                     }
3997                     goto jmp_insn;
3998 #endif
3999                 case 0x3b: /* flush */
4000                     if (!((dc)->features & CPU_FEATURE_FLUSH))
4001                         goto unimp_flush;
4002                     tcg_gen_helper_0_1(helper_flush, cpu_dst);
4003                     break;
4004                 case 0x3c:      /* save */
4005                     save_state(dc, cpu_cond);
4006                     tcg_gen_helper_0_0(helper_save);
4007                     gen_movl_TN_reg(rd, cpu_dst);
4008                     break;
4009                 case 0x3d:      /* restore */
4010                     save_state(dc, cpu_cond);
4011                     tcg_gen_helper_0_0(helper_restore);
4012                     gen_movl_TN_reg(rd, cpu_dst);
4013                     break;
4014 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4015                 case 0x3e:      /* V9 done/retry */
4016                     {
4017                         switch (rd) {
4018                         case 0:
4019                             if (!supervisor(dc))
4020                                 goto priv_insn;
4021                             dc->npc = DYNAMIC_PC;
4022                             dc->pc = DYNAMIC_PC;
4023                             tcg_gen_helper_0_0(helper_done);
4024                             goto jmp_insn;
4025                         case 1:
4026                             if (!supervisor(dc))
4027                                 goto priv_insn;
4028                             dc->npc = DYNAMIC_PC;
4029                             dc->pc = DYNAMIC_PC;
4030                             tcg_gen_helper_0_0(helper_retry);
4031                             goto jmp_insn;
4032                         default:
4033                             goto illegal_insn;
4034                         }
4035                     }
4036                     break;
4037 #endif
4038                 default:
4039                     goto illegal_insn;
4040                 }
4041             }
4042             break;
4043         }
4044         break;
4045     case 3:                     /* load/store instructions */
4046         {
4047             unsigned int xop = GET_FIELD(insn, 7, 12);
4048
4049             cpu_src1 = get_src1(insn, cpu_src1);
4050             if (xop == 0x3c || xop == 0x3e)
4051             {
4052                 rs2 = GET_FIELD(insn, 27, 31);
4053                 gen_movl_reg_TN(rs2, cpu_src2);
4054             }
4055             else if (IS_IMM) {       /* immediate */
4056                 rs2 = GET_FIELDs(insn, 19, 31);
4057                 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4058             } else {            /* register */
4059                 rs2 = GET_FIELD(insn, 27, 31);
4060                 if (rs2 != 0) {
4061                     gen_movl_reg_TN(rs2, cpu_src2);
4062                     tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4063                 } else
4064                     tcg_gen_mov_tl(cpu_addr, cpu_src1);
4065             }
4066             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4067                 (xop > 0x17 && xop <= 0x1d ) ||
4068                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4069                 switch (xop) {
4070                 case 0x0:       /* load unsigned word */
4071                     ABI32_MASK(cpu_addr);
4072                     tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4073                     break;
4074                 case 0x1:       /* load unsigned byte */
4075                     ABI32_MASK(cpu_addr);
4076                     tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4077                     break;
4078                 case 0x2:       /* load unsigned halfword */
4079                     ABI32_MASK(cpu_addr);
4080                     tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4081                     break;
4082                 case 0x3:       /* load double word */
4083                     if (rd & 1)
4084                         goto illegal_insn;
4085                     else {
4086                         save_state(dc, cpu_cond);
4087                         tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4088                                            tcg_const_i32(7)); // XXX remove
4089                         ABI32_MASK(cpu_addr);
4090                         tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4091                         tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4092                         tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4093                         gen_movl_TN_reg(rd + 1, cpu_tmp0);
4094                         tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4095                         tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4096                         tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4097                     }
4098                     break;
4099                 case 0x9:       /* load signed byte */
4100                     ABI32_MASK(cpu_addr);
4101                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4102                     break;
4103                 case 0xa:       /* load signed halfword */
4104                     ABI32_MASK(cpu_addr);
4105                     tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4106                     break;
4107                 case 0xd:       /* ldstub -- XXX: should be atomically */
4108                     ABI32_MASK(cpu_addr);
4109                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4110                     tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr,
4111                                      dc->mem_idx);
4112                     break;
4113                 case 0x0f:      /* swap register with memory. Also
4114                                    atomically */
4115                     CHECK_IU_FEATURE(dc, SWAP);
4116                     gen_movl_reg_TN(rd, cpu_val);
4117                     ABI32_MASK(cpu_addr);
4118                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4119                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4120                     tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4121                     break;
4122 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4123                 case 0x10:      /* load word alternate */
4124 #ifndef TARGET_SPARC64
4125                     if (IS_IMM)
4126                         goto illegal_insn;
4127                     if (!supervisor(dc))
4128                         goto priv_insn;
4129 #endif
4130                     save_state(dc, cpu_cond);
4131                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4132                     break;
4133                 case 0x11:      /* load unsigned byte alternate */
4134 #ifndef TARGET_SPARC64
4135                     if (IS_IMM)
4136                         goto illegal_insn;
4137                     if (!supervisor(dc))
4138                         goto priv_insn;
4139 #endif
4140                     save_state(dc, cpu_cond);
4141                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4142                     break;
4143                 case 0x12:      /* load unsigned halfword alternate */
4144 #ifndef TARGET_SPARC64
4145                     if (IS_IMM)
4146                         goto illegal_insn;
4147                     if (!supervisor(dc))
4148                         goto priv_insn;
4149 #endif
4150                     save_state(dc, cpu_cond);
4151                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4152                     break;
4153                 case 0x13:      /* load double word alternate */
4154 #ifndef TARGET_SPARC64
4155                     if (IS_IMM)
4156                         goto illegal_insn;
4157                     if (!supervisor(dc))
4158                         goto priv_insn;
4159 #endif
4160                     if (rd & 1)
4161                         goto illegal_insn;
4162                     save_state(dc, cpu_cond);
4163                     gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4164                     gen_movl_TN_reg(rd + 1, cpu_tmp0);
4165                     break;
4166                 case 0x19:      /* load signed byte alternate */
4167 #ifndef TARGET_SPARC64
4168                     if (IS_IMM)
4169                         goto illegal_insn;
4170                     if (!supervisor(dc))
4171                         goto priv_insn;
4172 #endif
4173                     save_state(dc, cpu_cond);
4174                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4175                     break;
4176                 case 0x1a:      /* load signed halfword alternate */
4177 #ifndef TARGET_SPARC64
4178                     if (IS_IMM)
4179                         goto illegal_insn;
4180                     if (!supervisor(dc))
4181                         goto priv_insn;
4182 #endif
4183                     save_state(dc, cpu_cond);
4184                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4185                     break;
4186                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
4187 #ifndef TARGET_SPARC64
4188                     if (IS_IMM)
4189                         goto illegal_insn;
4190                     if (!supervisor(dc))
4191                         goto priv_insn;
4192 #endif
4193                     save_state(dc, cpu_cond);
4194                     gen_ldstub_asi(cpu_val, cpu_addr, insn);
4195                     break;
4196                 case 0x1f:      /* swap reg with alt. memory. Also
4197                                    atomically */
4198                     CHECK_IU_FEATURE(dc, SWAP);
4199 #ifndef TARGET_SPARC64
4200                     if (IS_IMM)
4201                         goto illegal_insn;
4202                     if (!supervisor(dc))
4203                         goto priv_insn;
4204 #endif
4205                     save_state(dc, cpu_cond);
4206                     gen_movl_reg_TN(rd, cpu_val);
4207                     gen_swap_asi(cpu_val, cpu_addr, insn);
4208                     break;
4209
4210 #ifndef TARGET_SPARC64
4211                 case 0x30: /* ldc */
4212                 case 0x31: /* ldcsr */
4213                 case 0x33: /* lddc */
4214                     goto ncp_insn;
4215 #endif
4216 #endif
4217 #ifdef TARGET_SPARC64
4218                 case 0x08: /* V9 ldsw */
4219                     ABI32_MASK(cpu_addr);
4220                     tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4221                     break;
4222                 case 0x0b: /* V9 ldx */
4223                     ABI32_MASK(cpu_addr);
4224                     tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4225                     break;
4226                 case 0x18: /* V9 ldswa */
4227                     save_state(dc, cpu_cond);
4228                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4229                     break;
4230                 case 0x1b: /* V9 ldxa */
4231                     save_state(dc, cpu_cond);
4232                     gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4233                     break;
4234                 case 0x2d: /* V9 prefetch, no effect */
4235                     goto skip_move;
4236                 case 0x30: /* V9 ldfa */
4237                     save_state(dc, cpu_cond);
4238                     gen_ldf_asi(cpu_addr, insn, 4, rd);
4239                     goto skip_move;
4240                 case 0x33: /* V9 lddfa */
4241                     save_state(dc, cpu_cond);
4242                     gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4243                     goto skip_move;
4244                 case 0x3d: /* V9 prefetcha, no effect */
4245                     goto skip_move;
4246                 case 0x32: /* V9 ldqfa */
4247                     CHECK_FPU_FEATURE(dc, FLOAT128);
4248                     save_state(dc, cpu_cond);
4249                     gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4250                     goto skip_move;
4251 #endif
4252                 default:
4253                     goto illegal_insn;
4254                 }
4255                 gen_movl_TN_reg(rd, cpu_val);
4256 #ifdef TARGET_SPARC64
4257             skip_move: ;
4258 #endif
4259             } else if (xop >= 0x20 && xop < 0x24) {
4260                 if (gen_trap_ifnofpu(dc, cpu_cond))
4261                     goto jmp_insn;
4262                 save_state(dc, cpu_cond);
4263                 switch (xop) {
4264                 case 0x20:      /* load fpreg */
4265                     ABI32_MASK(cpu_addr);
4266                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4267                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4268                                    offsetof(CPUState, fpr[rd]));
4269                     break;
4270                 case 0x21:      /* load fsr */
4271                     ABI32_MASK(cpu_addr);
4272                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4273                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4274                                    offsetof(CPUState, ft0));
4275                     tcg_gen_helper_0_0(helper_ldfsr);
4276                     break;
4277                 case 0x22:      /* load quad fpreg */
4278                     CHECK_FPU_FEATURE(dc, FLOAT128);
4279                     tcg_gen_helper_0_2(helper_ldqf, cpu_addr,
4280                                        tcg_const_i32(dc->mem_idx));
4281                     gen_op_store_QT0_fpr(QFPREG(rd));
4282                     break;
4283                 case 0x23:      /* load double fpreg */
4284                     tcg_gen_helper_0_2(helper_lddf, cpu_addr,
4285                                        tcg_const_i32(dc->mem_idx));
4286                     gen_op_store_DT0_fpr(DFPREG(rd));
4287                     break;
4288                 default:
4289                     goto illegal_insn;
4290                 }
4291             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4292                        xop == 0xe || xop == 0x1e) {
4293                 gen_movl_reg_TN(rd, cpu_val);
4294                 switch (xop) {
4295                 case 0x4: /* store word */
4296                     ABI32_MASK(cpu_addr);
4297                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4298                     break;
4299                 case 0x5: /* store byte */
4300                     ABI32_MASK(cpu_addr);
4301                     tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4302                     break;
4303                 case 0x6: /* store halfword */
4304                     ABI32_MASK(cpu_addr);
4305                     tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4306                     break;
4307                 case 0x7: /* store double word */
4308                     if (rd & 1)
4309                         goto illegal_insn;
4310                     else {
4311                         TCGv r_low;
4312
4313                         save_state(dc, cpu_cond);
4314                         ABI32_MASK(cpu_addr);
4315                         tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4316                                            tcg_const_i32(7)); // XXX remove
4317                         r_low = tcg_temp_new(TCG_TYPE_I32);
4318                         gen_movl_reg_TN(rd + 1, r_low);
4319                         tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4320                                            r_low);
4321                         tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4322                     }
4323                     break;
4324 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4325                 case 0x14: /* store word alternate */
4326 #ifndef TARGET_SPARC64
4327                     if (IS_IMM)
4328                         goto illegal_insn;
4329                     if (!supervisor(dc))
4330                         goto priv_insn;
4331 #endif
4332                     save_state(dc, cpu_cond);
4333                     gen_st_asi(cpu_val, cpu_addr, insn, 4);
4334                     break;
4335                 case 0x15: /* store byte alternate */
4336 #ifndef TARGET_SPARC64
4337                     if (IS_IMM)
4338                         goto illegal_insn;
4339                     if (!supervisor(dc))
4340                         goto priv_insn;
4341 #endif
4342                     save_state(dc, cpu_cond);
4343                     gen_st_asi(cpu_val, cpu_addr, insn, 1);
4344                     break;
4345                 case 0x16: /* store halfword alternate */
4346 #ifndef TARGET_SPARC64
4347                     if (IS_IMM)
4348                         goto illegal_insn;
4349                     if (!supervisor(dc))
4350                         goto priv_insn;
4351 #endif
4352                     save_state(dc, cpu_cond);
4353                     gen_st_asi(cpu_val, cpu_addr, insn, 2);
4354                     break;
4355                 case 0x17: /* store double word alternate */
4356 #ifndef TARGET_SPARC64
4357                     if (IS_IMM)
4358                         goto illegal_insn;
4359                     if (!supervisor(dc))
4360                         goto priv_insn;
4361 #endif
4362                     if (rd & 1)
4363                         goto illegal_insn;
4364                     else {
4365                         save_state(dc, cpu_cond);
4366                         gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4367                     }
4368                     break;
4369 #endif
4370 #ifdef TARGET_SPARC64
4371                 case 0x0e: /* V9 stx */
4372                     ABI32_MASK(cpu_addr);
4373                     tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4374                     break;
4375                 case 0x1e: /* V9 stxa */
4376                     save_state(dc, cpu_cond);
4377                     gen_st_asi(cpu_val, cpu_addr, insn, 8);
4378                     break;
4379 #endif
4380                 default:
4381                     goto illegal_insn;
4382                 }
4383             } else if (xop > 0x23 && xop < 0x28) {
4384                 if (gen_trap_ifnofpu(dc, cpu_cond))
4385                     goto jmp_insn;
4386                 save_state(dc, cpu_cond);
4387                 switch (xop) {
4388                 case 0x24: /* store fpreg */
4389                     ABI32_MASK(cpu_addr);
4390                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4391                                    offsetof(CPUState, fpr[rd]));
4392                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4393                     break;
4394                 case 0x25: /* stfsr, V9 stxfsr */
4395                     ABI32_MASK(cpu_addr);
4396                     tcg_gen_helper_0_0(helper_stfsr);
4397                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4398                                    offsetof(CPUState, ft0));
4399                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4400                     break;
4401                 case 0x26:
4402 #ifdef TARGET_SPARC64
4403                     /* V9 stqf, store quad fpreg */
4404                     CHECK_FPU_FEATURE(dc, FLOAT128);
4405                     gen_op_load_fpr_QT0(QFPREG(rd));
4406                     tcg_gen_helper_0_2(helper_stqf, cpu_addr,
4407                                        tcg_const_i32(dc->mem_idx));
4408                     break;
4409 #else /* !TARGET_SPARC64 */
4410                     /* stdfq, store floating point queue */
4411 #if defined(CONFIG_USER_ONLY)
4412                     goto illegal_insn;
4413 #else
4414                     if (!supervisor(dc))
4415                         goto priv_insn;
4416                     if (gen_trap_ifnofpu(dc, cpu_cond))
4417                         goto jmp_insn;
4418                     goto nfq_insn;
4419 #endif
4420 #endif
4421                 case 0x27: /* store double fpreg */
4422                     gen_op_load_fpr_DT0(DFPREG(rd));
4423                     tcg_gen_helper_0_2(helper_stdf, cpu_addr,
4424                                        tcg_const_i32(dc->mem_idx));
4425                     break;
4426                 default:
4427                     goto illegal_insn;
4428                 }
4429             } else if (xop > 0x33 && xop < 0x3f) {
4430                 save_state(dc, cpu_cond);
4431                 switch (xop) {
4432 #ifdef TARGET_SPARC64
4433                 case 0x34: /* V9 stfa */
4434                     gen_op_load_fpr_FT0(rd);
4435                     gen_stf_asi(cpu_addr, insn, 4, rd);
4436                     break;
4437                 case 0x36: /* V9 stqfa */
4438                     CHECK_FPU_FEATURE(dc, FLOAT128);
4439                     tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4440                                        tcg_const_i32(7));
4441                     gen_op_load_fpr_QT0(QFPREG(rd));
4442                     gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4443                     break;
4444                 case 0x37: /* V9 stdfa */
4445                     gen_op_load_fpr_DT0(DFPREG(rd));
4446                     gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4447                     break;
4448                 case 0x3c: /* V9 casa */
4449                     gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4450                     gen_movl_TN_reg(rd, cpu_val);
4451                     break;
4452                 case 0x3e: /* V9 casxa */
4453                     gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4454                     gen_movl_TN_reg(rd, cpu_val);
4455                     break;
4456 #else
4457                 case 0x34: /* stc */
4458                 case 0x35: /* stcsr */
4459                 case 0x36: /* stdcq */
4460                 case 0x37: /* stdc */
4461                     goto ncp_insn;
4462 #endif
4463                 default:
4464                     goto illegal_insn;
4465                 }
4466             }
4467             else
4468                 goto illegal_insn;
4469         }
4470         break;
4471     }
4472     /* default case for non jump instructions */
4473     if (dc->npc == DYNAMIC_PC) {
4474         dc->pc = DYNAMIC_PC;
4475         gen_op_next_insn();
4476     } else if (dc->npc == JUMP_PC) {
4477         /* we can do a static jump */
4478         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4479         dc->is_br = 1;
4480     } else {
4481         dc->pc = dc->npc;
4482         dc->npc = dc->npc + 4;
4483     }
4484  jmp_insn:
4485     return;
4486  illegal_insn:
4487     save_state(dc, cpu_cond);
4488     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
4489     dc->is_br = 1;
4490     return;
4491  unimp_flush:
4492     save_state(dc, cpu_cond);
4493     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_UNIMP_FLUSH));
4494     dc->is_br = 1;
4495     return;
4496 #if !defined(CONFIG_USER_ONLY)
4497  priv_insn:
4498     save_state(dc, cpu_cond);
4499     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
4500     dc->is_br = 1;
4501     return;
4502 #endif
4503  nfpu_insn:
4504     save_state(dc, cpu_cond);
4505     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4506     dc->is_br = 1;
4507     return;
4508 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4509  nfq_insn:
4510     save_state(dc, cpu_cond);
4511     gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4512     dc->is_br = 1;
4513     return;
4514 #endif
4515 #ifndef TARGET_SPARC64
4516  ncp_insn:
4517     save_state(dc, cpu_cond);
4518     tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
4519     dc->is_br = 1;
4520     return;
4521 #endif
4522 }
4523
4524 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4525                                                  int spc, CPUSPARCState *env)
4526 {
4527     target_ulong pc_start, last_pc;
4528     uint16_t *gen_opc_end;
4529     DisasContext dc1, *dc = &dc1;
4530     int j, lj = -1;
4531
4532     memset(dc, 0, sizeof(DisasContext));
4533     dc->tb = tb;
4534     pc_start = tb->pc;
4535     dc->pc = pc_start;
4536     last_pc = dc->pc;
4537     dc->npc = (target_ulong) tb->cs_base;
4538     dc->mem_idx = cpu_mmu_index(env);
4539     dc->features = env->features;
4540     if ((dc->features & CPU_FEATURE_FLOAT)) {
4541         dc->fpu_enabled = cpu_fpu_enabled(env);
4542 #if defined(CONFIG_USER_ONLY)
4543         dc->features |= CPU_FEATURE_FLOAT128;
4544 #endif
4545     } else
4546         dc->fpu_enabled = 0;
4547     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4548
4549     cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4550     cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4551     cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4552
4553     do {
4554         if (env->nb_breakpoints > 0) {
4555             for(j = 0; j < env->nb_breakpoints; j++) {
4556                 if (env->breakpoints[j] == dc->pc) {
4557                     if (dc->pc != pc_start)
4558                         save_state(dc, cpu_cond);
4559                     tcg_gen_helper_0_0(helper_debug);
4560                     tcg_gen_exit_tb(0);
4561                     dc->is_br = 1;
4562                     goto exit_gen_loop;
4563                 }
4564             }
4565         }
4566         if (spc) {
4567             if (loglevel > 0)
4568                 fprintf(logfile, "Search PC...\n");
4569             j = gen_opc_ptr - gen_opc_buf;
4570             if (lj < j) {
4571                 lj++;
4572                 while (lj < j)
4573                     gen_opc_instr_start[lj++] = 0;
4574                 gen_opc_pc[lj] = dc->pc;
4575                 gen_opc_npc[lj] = dc->npc;
4576                 gen_opc_instr_start[lj] = 1;
4577             }
4578         }
4579         last_pc = dc->pc;
4580         disas_sparc_insn(dc);
4581
4582         if (dc->is_br)
4583             break;
4584         /* if the next PC is different, we abort now */
4585         if (dc->pc != (last_pc + 4))
4586             break;
4587         /* if we reach a page boundary, we stop generation so that the
4588            PC of a TT_TFAULT exception is always in the right page */
4589         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4590             break;
4591         /* if single step mode, we generate only one instruction and
4592            generate an exception */
4593         if (env->singlestep_enabled) {
4594             tcg_gen_movi_tl(cpu_pc, dc->pc);
4595             tcg_gen_exit_tb(0);
4596             break;
4597         }
4598     } while ((gen_opc_ptr < gen_opc_end) &&
4599              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4600
4601  exit_gen_loop:
4602     if (!dc->is_br) {
4603         if (dc->pc != DYNAMIC_PC &&
4604             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4605             /* static PC and NPC: we can use direct chaining */
4606             gen_goto_tb(dc, 0, dc->pc, dc->npc);
4607         } else {
4608             if (dc->pc != DYNAMIC_PC)
4609                 tcg_gen_movi_tl(cpu_pc, dc->pc);
4610             save_npc(dc, cpu_cond);
4611             tcg_gen_exit_tb(0);
4612         }
4613     }
4614     *gen_opc_ptr = INDEX_op_end;
4615     if (spc) {
4616         j = gen_opc_ptr - gen_opc_buf;
4617         lj++;
4618         while (lj <= j)
4619             gen_opc_instr_start[lj++] = 0;
4620 #if 0
4621         if (loglevel > 0) {
4622             page_dump(logfile);
4623         }
4624 #endif
4625         gen_opc_jump_pc[0] = dc->jump_pc[0];
4626         gen_opc_jump_pc[1] = dc->jump_pc[1];
4627     } else {
4628         tb->size = last_pc + 4 - pc_start;
4629     }
4630 #ifdef DEBUG_DISAS
4631     if (loglevel & CPU_LOG_TB_IN_ASM) {
4632         fprintf(logfile, "--------------\n");
4633         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4634         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4635         fprintf(logfile, "\n");
4636     }
4637 #endif
4638     return 0;
4639 }
4640
4641 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4642 {
4643     return gen_intermediate_code_internal(tb, 0, env);
4644 }
4645
4646 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4647 {
4648     return gen_intermediate_code_internal(tb, 1, env);
4649 }
4650
4651 void gen_intermediate_code_init(CPUSPARCState *env)
4652 {
4653     unsigned int i;
4654     static int inited;
4655     static const char * const gregnames[8] = {
4656         NULL, // g0 not used
4657         "g1",
4658         "g2",
4659         "g3",
4660         "g4",
4661         "g5",
4662         "g6",
4663         "g7",
4664     };
4665
4666     /* init various static tables */
4667     if (!inited) {
4668         inited = 1;
4669
4670         cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4671         cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4672                                          offsetof(CPUState, regwptr),
4673                                          "regwptr");
4674 #ifdef TARGET_SPARC64
4675         cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4676                                      TCG_AREG0, offsetof(CPUState, xcc),
4677                                      "xcc");
4678 #endif
4679         /* XXX: T0 and T1 should be temporaries */
4680         cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4681                                       TCG_AREG0, offsetof(CPUState, t0), "T0");
4682         cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4683                                       TCG_AREG0, offsetof(CPUState, t1), "T1");
4684         cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4685                                       TCG_AREG0, offsetof(CPUState, cond),
4686                                       "cond");
4687         cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4688                                         TCG_AREG0, offsetof(CPUState, cc_src),
4689                                         "cc_src");
4690         cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4691                                          offsetof(CPUState, cc_src2),
4692                                          "cc_src2");
4693         cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4694                                         TCG_AREG0, offsetof(CPUState, cc_dst),
4695                                         "cc_dst");
4696         cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4697                                      TCG_AREG0, offsetof(CPUState, psr),
4698                                      "psr");
4699         cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4700                                      TCG_AREG0, offsetof(CPUState, fsr),
4701                                      "fsr");
4702         cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4703                                     TCG_AREG0, offsetof(CPUState, pc),
4704                                     "pc");
4705         cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4706                                     TCG_AREG0, offsetof(CPUState, npc),
4707                                     "npc");
4708         for (i = 1; i < 8; i++)
4709             cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4710                                               offsetof(CPUState, gregs[i]),
4711                                               gregnames[i]);
4712         /* register helpers */
4713
4714 #undef DEF_HELPER
4715 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4716 #include "helper.h"
4717     }
4718 }
4719
4720 void gen_pc_load(CPUState *env, TranslationBlock *tb,
4721                 unsigned long searched_pc, int pc_pos, void *puc)
4722 {
4723     target_ulong npc;
4724     env->pc = gen_opc_pc[pc_pos];
4725     npc = gen_opc_npc[pc_pos];
4726     if (npc == 1) {
4727         /* dynamic NPC: already stored */
4728     } else if (npc == 2) {
4729         target_ulong t2 = (target_ulong)(unsigned long)puc;
4730         /* jump PC: use T2 and the jump targets of the translation */
4731         if (t2)
4732             env->npc = gen_opc_jump_pc[0];
4733         else
4734             env->npc = gen_opc_jump_pc[1];
4735     } else {
4736         env->npc = npc;
4737     }
4738 }