git.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <stdarg.h>
  23 #include <stdlib.h>
  24 #include <stdio.h>
  25 #include <string.h>
  26 #include <inttypes.h>
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30 #include "disas.h"
  31 #include "helper.h"
  32 #include "tcg-op.h"
  33
  34 #define DEBUG_DISAS
  35
  36 #define DYNAMIC_PC  1 /* dynamic pc value */
  37 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  38                          according to jump_pc[T2] */
  39
  40 /* global register indexes */
  41 static TCGv cpu_env, cpu_regwptr;
  42 static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
  43 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
  44 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
  45 #ifdef TARGET_SPARC64
  46 static TCGv cpu_xcc;
  47 #endif
  48 /* local register indexes (only used inside old micro ops) */
  49 static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
  50
  51 #include "gen-icount.h"
  52
  53 typedef struct DisasContext {
  54     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  55     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  56     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  57     int is_br;
  58     int mem_idx;
  59     int fpu_enabled;
  60     int address_mask_32bit;
  61     struct TranslationBlock *tb;
  62     uint32_t features;
  63 } DisasContext;
  64
  65 // This function uses non-native bit order
  66 #define GET_FIELD(X, FROM, TO) \
  67   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  68
  69 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  70 #define GET_FIELD_SP(X, FROM, TO) \
  71     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  72
  73 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  74 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
  75
  76 #ifdef TARGET_SPARC64
  77 #define FFPREG(r) (r)
  78 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
  79 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
  80 #else
  81 #define FFPREG(r) (r)
  82 #define DFPREG(r) (r & 0x1e)
  83 #define QFPREG(r) (r & 0x1c)
  84 #endif
  85
  86 static int sign_extend(int x, int len)
  87 {
  88     len = 32 - len;
  89     return (x << len) >> len;
  90 }
  91
  92 #define IS_IMM (insn & (1<<13))
  93
  94 /* floating point registers moves */
  95 static void gen_op_load_fpr_FT0(unsigned int src)
  96 {
  97     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
  98     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
  99 }
 100
 101 static void gen_op_load_fpr_FT1(unsigned int src)
 102 {
 103     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 104     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
 105 }
 106
 107 static void gen_op_store_FT0_fpr(unsigned int dst)
 108 {
 109     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
 110     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 111 }
 112
 113 static void gen_op_load_fpr_DT0(unsigned int src)
 114 {
 115     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 116     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 117                    offsetof(CPU_DoubleU, l.upper));
 118     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 119     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 120                    offsetof(CPU_DoubleU, l.lower));
 121 }
 122
 123 static void gen_op_load_fpr_DT1(unsigned int src)
 124 {
 125     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 126     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
 127                    offsetof(CPU_DoubleU, l.upper));
 128     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 129     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
 130                    offsetof(CPU_DoubleU, l.lower));
 131 }
 132
 133 static void gen_op_store_DT0_fpr(unsigned int dst)
 134 {
 135     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 136                    offsetof(CPU_DoubleU, l.upper));
 137     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 138     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
 139                    offsetof(CPU_DoubleU, l.lower));
 140     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 141 }
 142
 143 static void gen_op_load_fpr_QT0(unsigned int src)
 144 {
 145     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 146     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 147                    offsetof(CPU_QuadU, l.upmost));
 148     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 149     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 150                    offsetof(CPU_QuadU, l.upper));
 151     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 152     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 153                    offsetof(CPU_QuadU, l.lower));
 154     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 155     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 156                    offsetof(CPU_QuadU, l.lowest));
 157 }
 158
 159 static void gen_op_load_fpr_QT1(unsigned int src)
 160 {
 161     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
 162     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 163                    offsetof(CPU_QuadU, l.upmost));
 164     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
 165     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 166                    offsetof(CPU_QuadU, l.upper));
 167     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
 168     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 169                    offsetof(CPU_QuadU, l.lower));
 170     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
 171     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
 172                    offsetof(CPU_QuadU, l.lowest));
 173 }
 174
 175 static void gen_op_store_QT0_fpr(unsigned int dst)
 176 {
 177     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 178                    offsetof(CPU_QuadU, l.upmost));
 179     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
 180     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 181                    offsetof(CPU_QuadU, l.upper));
 182     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
 183     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 184                    offsetof(CPU_QuadU, l.lower));
 185     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
 186     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
 187                    offsetof(CPU_QuadU, l.lowest));
 188     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
 189 }
 190
 191 /* moves */
 192 #ifdef CONFIG_USER_ONLY
 193 #define supervisor(dc) 0
 194 #ifdef TARGET_SPARC64
 195 #define hypervisor(dc) 0
 196 #endif
 197 #else
 198 #define supervisor(dc) (dc->mem_idx >= 1)
 199 #ifdef TARGET_SPARC64
 200 #define hypervisor(dc) (dc->mem_idx == 2)
 201 #else
 202 #endif
 203 #endif
 204
 205 #ifdef TARGET_SPARC64
 206 #ifndef TARGET_ABI32
 207 #define AM_CHECK(dc) ((dc)->address_mask_32bit)
 208 #else
 209 #define AM_CHECK(dc) (1)
 210 #endif
 211 #endif
 212
 213 static inline void gen_address_mask(DisasContext *dc, TCGv addr)
 214 {
 215 #ifdef TARGET_SPARC64
 216     if (AM_CHECK(dc))
 217         tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
 218 #endif
 219 }
 220
 221 static inline void gen_movl_reg_TN(int reg, TCGv tn)
 222 {
 223     if (reg == 0)
 224         tcg_gen_movi_tl(tn, 0);
 225     else if (reg < 8)
 226         tcg_gen_mov_tl(tn, cpu_gregs[reg]);
 227     else {
 228         tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 229     }
 230 }
 231
 232 static inline void gen_movl_TN_reg(int reg, TCGv tn)
 233 {
 234     if (reg == 0)
 235         return;
 236     else if (reg < 8)
 237         tcg_gen_mov_tl(cpu_gregs[reg], tn);
 238     else {
 239         tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
 240     }
 241 }
 242
 243 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 244                                target_ulong pc, target_ulong npc)
 245 {
 246     TranslationBlock *tb;
 247
 248     tb = s->tb;
 249     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 250         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 251         /* jump to same page: we can use a direct jump */
 252         tcg_gen_goto_tb(tb_num);
 253         tcg_gen_movi_tl(cpu_pc, pc);
 254         tcg_gen_movi_tl(cpu_npc, npc);
 255         tcg_gen_exit_tb((long)tb + tb_num);
 256     } else {
 257         /* jump to another page: currently not optimized */
 258         tcg_gen_movi_tl(cpu_pc, pc);
 259         tcg_gen_movi_tl(cpu_npc, npc);
 260         tcg_gen_exit_tb(0);
 261     }
 262 }
 263
 264 // XXX suboptimal
 265 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
 266 {
 267     tcg_gen_extu_i32_tl(reg, src);
 268     tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
 269     tcg_gen_andi_tl(reg, reg, 0x1);
 270 }
 271
 272 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
 273 {
 274     tcg_gen_extu_i32_tl(reg, src);
 275     tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
 276     tcg_gen_andi_tl(reg, reg, 0x1);
 277 }
 278
 279 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
 280 {
 281     tcg_gen_extu_i32_tl(reg, src);
 282     tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
 283     tcg_gen_andi_tl(reg, reg, 0x1);
 284 }
 285
 286 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
 287 {
 288     tcg_gen_extu_i32_tl(reg, src);
 289     tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
 290     tcg_gen_andi_tl(reg, reg, 0x1);
 291 }
 292
 293 static inline void gen_cc_clear_icc(void)
 294 {
 295     tcg_gen_movi_i32(cpu_psr, 0);
 296 }
 297
 298 #ifdef TARGET_SPARC64
 299 static inline void gen_cc_clear_xcc(void)
 300 {
 301     tcg_gen_movi_i32(cpu_xcc, 0);
 302 }
 303 #endif
 304
 305 /* old op:
 306     if (!T0)
 307         env->psr |= PSR_ZERO;
 308     if ((int32_t) T0 < 0)
 309         env->psr |= PSR_NEG;
 310 */
 311 static inline void gen_cc_NZ_icc(TCGv dst)
 312 {
 313     TCGv r_temp;
 314     int l1, l2;
 315
 316     l1 = gen_new_label();
 317     l2 = gen_new_label();
 318     r_temp = tcg_temp_new(TCG_TYPE_TL);
 319     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 320     tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
 321     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
 322     gen_set_label(l1);
 323     tcg_gen_ext_i32_tl(r_temp, dst);
 324     tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
 325     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
 326     gen_set_label(l2);
 327     tcg_temp_free(r_temp);
 328 }
 329
 330 #ifdef TARGET_SPARC64
 331 static inline void gen_cc_NZ_xcc(TCGv dst)
 332 {
 333     int l1, l2;
 334
 335     l1 = gen_new_label();
 336     l2 = gen_new_label();
 337     tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
 338     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
 339     gen_set_label(l1);
 340     tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
 341     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
 342     gen_set_label(l2);
 343 }
 344 #endif
 345
 346 /* old op:
 347     if (T0 < src1)
 348         env->psr |= PSR_CARRY;
 349 */
 350 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
 351 {
 352     TCGv r_temp;
 353     int l1;
 354
 355     l1 = gen_new_label();
 356     r_temp = tcg_temp_new(TCG_TYPE_TL);
 357     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
 358     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 359     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 360     gen_set_label(l1);
 361     tcg_temp_free(r_temp);
 362 }
 363
 364 #ifdef TARGET_SPARC64
 365 static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
 366 {
 367     int l1;
 368
 369     l1 = gen_new_label();
 370     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
 371     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 372     gen_set_label(l1);
 373 }
 374 #endif
 375
 376 /* old op:
 377     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
 378         env->psr |= PSR_OVF;
 379 */
 380 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
 381 {
 382     TCGv r_temp;
 383
 384     r_temp = tcg_temp_new(TCG_TYPE_TL);
 385     tcg_gen_xor_tl(r_temp, src1, src2);
 386     tcg_gen_xori_tl(r_temp, r_temp, -1);
 387     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 388     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 389     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 390     tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
 391     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 392     tcg_temp_free(r_temp);
 393     tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
 394 }
 395
 396 #ifdef TARGET_SPARC64
 397 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
 398 {
 399     TCGv r_temp;
 400
 401     r_temp = tcg_temp_new(TCG_TYPE_TL);
 402     tcg_gen_xor_tl(r_temp, src1, src2);
 403     tcg_gen_xori_tl(r_temp, r_temp, -1);
 404     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 405     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 406     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 407     tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
 408     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 409     tcg_temp_free(r_temp);
 410     tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
 411 }
 412 #endif
 413
 414 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
 415 {
 416     TCGv r_temp, r_const;
 417     int l1;
 418
 419     l1 = gen_new_label();
 420
 421     r_temp = tcg_temp_new(TCG_TYPE_TL);
 422     tcg_gen_xor_tl(r_temp, src1, src2);
 423     tcg_gen_xori_tl(r_temp, r_temp, -1);
 424     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 425     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 426     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 427     tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
 428     r_const = tcg_const_i32(TT_TOVF);
 429     tcg_gen_helper_0_1(raise_exception, r_const);
 430     tcg_temp_free(r_const);
 431     gen_set_label(l1);
 432     tcg_temp_free(r_temp);
 433 }
 434
 435 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
 436 {
 437     int l1;
 438
 439     l1 = gen_new_label();
 440     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 441     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 442     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
 443     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 444     gen_set_label(l1);
 445 }
 446
 447 static inline void gen_tag_tv(TCGv src1, TCGv src2)
 448 {
 449     int l1;
 450     TCGv r_const;
 451
 452     l1 = gen_new_label();
 453     tcg_gen_or_tl(cpu_tmp0, src1, src2);
 454     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
 455     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
 456     r_const = tcg_const_i32(TT_TOVF);
 457     tcg_gen_helper_0_1(raise_exception, r_const);
 458     tcg_temp_free(r_const);
 459     gen_set_label(l1);
 460 }
 461
 462 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
 463 {
 464     tcg_gen_mov_tl(cpu_cc_src, src1);
 465     tcg_gen_mov_tl(cpu_cc_src2, src2);
 466     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 467     gen_cc_clear_icc();
 468     gen_cc_NZ_icc(cpu_cc_dst);
 469     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 470     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 471 #ifdef TARGET_SPARC64
 472     gen_cc_clear_xcc();
 473     gen_cc_NZ_xcc(cpu_cc_dst);
 474     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 475     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 476 #endif
 477     tcg_gen_mov_tl(dst, cpu_cc_dst);
 478 }
 479
 480 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
 481 {
 482     tcg_gen_mov_tl(cpu_cc_src, src1);
 483     tcg_gen_mov_tl(cpu_cc_src2, src2);
 484     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 485     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
 486     gen_cc_clear_icc();
 487     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 488 #ifdef TARGET_SPARC64
 489     gen_cc_clear_xcc();
 490     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 491 #endif
 492     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
 493     gen_cc_NZ_icc(cpu_cc_dst);
 494     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 495     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 496 #ifdef TARGET_SPARC64
 497     gen_cc_NZ_xcc(cpu_cc_dst);
 498     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 499     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 500 #endif
 501     tcg_gen_mov_tl(dst, cpu_cc_dst);
 502 }
 503
 504 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
 505 {
 506     tcg_gen_mov_tl(cpu_cc_src, src1);
 507     tcg_gen_mov_tl(cpu_cc_src2, src2);
 508     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 509     gen_cc_clear_icc();
 510     gen_cc_NZ_icc(cpu_cc_dst);
 511     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 512     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 513     gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
 514 #ifdef TARGET_SPARC64
 515     gen_cc_clear_xcc();
 516     gen_cc_NZ_xcc(cpu_cc_dst);
 517     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 518     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 519 #endif
 520     tcg_gen_mov_tl(dst, cpu_cc_dst);
 521 }
 522
 523 static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
 524 {
 525     tcg_gen_mov_tl(cpu_cc_src, src1);
 526     tcg_gen_mov_tl(cpu_cc_src2, src2);
 527     gen_tag_tv(cpu_cc_src, cpu_cc_src2);
 528     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 529     gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 530     gen_cc_clear_icc();
 531     gen_cc_NZ_icc(cpu_cc_dst);
 532     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 533 #ifdef TARGET_SPARC64
 534     gen_cc_clear_xcc();
 535     gen_cc_NZ_xcc(cpu_cc_dst);
 536     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
 537     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 538 #endif
 539     tcg_gen_mov_tl(dst, cpu_cc_dst);
 540 }
 541
 542 /* old op:
 543     if (src1 < T1)
 544         env->psr |= PSR_CARRY;
 545 */
 546 static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
 547 {
 548     TCGv r_temp1, r_temp2;
 549     int l1;
 550
 551     l1 = gen_new_label();
 552     r_temp1 = tcg_temp_new(TCG_TYPE_TL);
 553     r_temp2 = tcg_temp_new(TCG_TYPE_TL);
 554     tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
 555     tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
 556     tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
 557     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
 558     gen_set_label(l1);
 559     tcg_temp_free(r_temp1);
 560     tcg_temp_free(r_temp2);
 561 }
 562
 563 #ifdef TARGET_SPARC64
 564 static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
 565 {
 566     int l1;
 567
 568     l1 = gen_new_label();
 569     tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
 570     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
 571     gen_set_label(l1);
 572 }
 573 #endif
 574
 575 /* old op:
 576     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
 577         env->psr |= PSR_OVF;
 578 */
 579 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
 580 {
 581     TCGv r_temp;
 582
 583     r_temp = tcg_temp_new(TCG_TYPE_TL);
 584     tcg_gen_xor_tl(r_temp, src1, src2);
 585     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 586     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 587     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 588     tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
 589     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 590     tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
 591     tcg_temp_free(r_temp);
 592 }
 593
 594 #ifdef TARGET_SPARC64
 595 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
 596 {
 597     TCGv r_temp;
 598
 599     r_temp = tcg_temp_new(TCG_TYPE_TL);
 600     tcg_gen_xor_tl(r_temp, src1, src2);
 601     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 602     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 603     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
 604     tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
 605     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
 606     tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
 607     tcg_temp_free(r_temp);
 608 }
 609 #endif
 610
 611 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
 612 {
 613     TCGv r_temp, r_const;
 614     int l1;
 615
 616     l1 = gen_new_label();
 617
 618     r_temp = tcg_temp_new(TCG_TYPE_TL);
 619     tcg_gen_xor_tl(r_temp, src1, src2);
 620     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
 621     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
 622     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
 623     tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
 624     r_const = tcg_const_i32(TT_TOVF);
 625     tcg_gen_helper_0_1(raise_exception, r_const);
 626     tcg_temp_free(r_const);
 627     gen_set_label(l1);
 628     tcg_temp_free(r_temp);
 629 }
 630
 631 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
 632 {
 633     tcg_gen_mov_tl(cpu_cc_src, src1);
 634     tcg_gen_mov_tl(cpu_cc_src2, src2);
 635     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 636     gen_cc_clear_icc();
 637     gen_cc_NZ_icc(cpu_cc_dst);
 638     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 639     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 640 #ifdef TARGET_SPARC64
 641     gen_cc_clear_xcc();
 642     gen_cc_NZ_xcc(cpu_cc_dst);
 643     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 644     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 645 #endif
 646     tcg_gen_mov_tl(dst, cpu_cc_dst);
 647 }
 648
 649 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
 650 {
 651     tcg_gen_mov_tl(cpu_cc_src, src1);
 652     tcg_gen_mov_tl(cpu_cc_src2, src2);
 653     gen_mov_reg_C(cpu_tmp0, cpu_psr);
 654     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
 655     gen_cc_clear_icc();
 656     gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
 657 #ifdef TARGET_SPARC64
 658     gen_cc_clear_xcc();
 659     gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
 660 #endif
 661     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
 662     gen_cc_NZ_icc(cpu_cc_dst);
 663     gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
 664     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 665 #ifdef TARGET_SPARC64
 666     gen_cc_NZ_xcc(cpu_cc_dst);
 667     gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
 668     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 669 #endif
 670     tcg_gen_mov_tl(dst, cpu_cc_dst);
 671 }
 672
 673 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
 674 {
 675     tcg_gen_mov_tl(cpu_cc_src, src1);
 676     tcg_gen_mov_tl(cpu_cc_src2, src2);
 677     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 678     gen_cc_clear_icc();
 679     gen_cc_NZ_icc(cpu_cc_dst);
 680     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 681     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 682     gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
 683 #ifdef TARGET_SPARC64
 684     gen_cc_clear_xcc();
 685     gen_cc_NZ_xcc(cpu_cc_dst);
 686     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 687     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 688 #endif
 689     tcg_gen_mov_tl(dst, cpu_cc_dst);
 690 }
 691
 692 static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
 693 {
 694     tcg_gen_mov_tl(cpu_cc_src, src1);
 695     tcg_gen_mov_tl(cpu_cc_src2, src2);
 696     gen_tag_tv(cpu_cc_src, cpu_cc_src2);
 697     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 698     gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 699     gen_cc_clear_icc();
 700     gen_cc_NZ_icc(cpu_cc_dst);
 701     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
 702 #ifdef TARGET_SPARC64
 703     gen_cc_clear_xcc();
 704     gen_cc_NZ_xcc(cpu_cc_dst);
 705     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
 706     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 707 #endif
 708     tcg_gen_mov_tl(dst, cpu_cc_dst);
 709 }
 710
 711 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
 712 {
 713     TCGv r_temp, r_temp2;
 714     int l1;
 715
 716     l1 = gen_new_label();
 717     r_temp = tcg_temp_new(TCG_TYPE_TL);
 718     r_temp2 = tcg_temp_new(TCG_TYPE_I32);
 719
 720     /* old op:
 721     if (!(env->y & 1))
 722         T1 = 0;
 723     */
 724     tcg_gen_mov_tl(cpu_cc_src, src1);
 725     tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 726     tcg_gen_trunc_tl_i32(r_temp2, r_temp);
 727     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 728     tcg_gen_mov_tl(cpu_cc_src2, src2);
 729     tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
 730     tcg_gen_movi_tl(cpu_cc_src2, 0);
 731     gen_set_label(l1);
 732
 733     // b2 = T0 & 1;
 734     // env->y = (b2 << 31) | (env->y >> 1);
 735     tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
 736     tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
 737     tcg_gen_shli_i32(r_temp2, r_temp2, 31);
 738     tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 739     tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
 740     tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
 741     tcg_temp_free(r_temp2);
 742     tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
 743
 744     // b1 = N ^ V;
 745     gen_mov_reg_N(cpu_tmp0, cpu_psr);
 746     gen_mov_reg_V(r_temp, cpu_psr);
 747     tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
 748     tcg_temp_free(r_temp);
 749
 750     // T0 = (b1 << 31) | (T0 >> 1);
 751     // src1 = T0;
 752     tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
 753     tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
 754     tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
 755
 756     /* do addition and update flags */
 757     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 758
 759     gen_cc_clear_icc();
 760     gen_cc_NZ_icc(cpu_cc_dst);
 761     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
 762     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
 763     tcg_gen_mov_tl(dst, cpu_cc_dst);
 764 }
 765
 766 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
 767 {
 768     TCGv r_temp, r_temp2;
 769
 770     r_temp = tcg_temp_new(TCG_TYPE_I64);
 771     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 772
 773     tcg_gen_extu_tl_i64(r_temp, src2);
 774     tcg_gen_extu_tl_i64(r_temp2, src1);
 775     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 776
 777     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 778     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 779     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 780     tcg_temp_free(r_temp);
 781 #ifdef TARGET_SPARC64
 782     tcg_gen_mov_i64(dst, r_temp2);
 783 #else
 784     tcg_gen_trunc_i64_tl(dst, r_temp2);
 785 #endif
 786     tcg_temp_free(r_temp2);
 787 }
 788
 789 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
 790 {
 791     TCGv r_temp, r_temp2;
 792
 793     r_temp = tcg_temp_new(TCG_TYPE_I64);
 794     r_temp2 = tcg_temp_new(TCG_TYPE_I64);
 795
 796     tcg_gen_ext_tl_i64(r_temp, src2);
 797     tcg_gen_ext_tl_i64(r_temp2, src1);
 798     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 799
 800     tcg_gen_shri_i64(r_temp, r_temp2, 32);
 801     tcg_gen_trunc_i64_i32(r_temp, r_temp);
 802     tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
 803     tcg_temp_free(r_temp);
 804 #ifdef TARGET_SPARC64
 805     tcg_gen_mov_i64(dst, r_temp2);
 806 #else
 807     tcg_gen_trunc_i64_tl(dst, r_temp2);
 808 #endif
 809     tcg_temp_free(r_temp2);
 810 }
 811
 812 #ifdef TARGET_SPARC64
 813 static inline void gen_trap_ifdivzero_tl(TCGv divisor)
 814 {
 815     TCGv r_const;
 816     int l1;
 817
 818     l1 = gen_new_label();
 819     tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
 820     r_const = tcg_const_i32(TT_DIV_ZERO);
 821     tcg_gen_helper_0_1(raise_exception, r_const);
 822     tcg_temp_free(r_const);
 823     gen_set_label(l1);
 824 }
 825
 826 static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
 827 {
 828     int l1, l2;
 829
 830     l1 = gen_new_label();
 831     l2 = gen_new_label();
 832     tcg_gen_mov_tl(cpu_cc_src, src1);
 833     tcg_gen_mov_tl(cpu_cc_src2, src2);
 834     gen_trap_ifdivzero_tl(cpu_cc_src2);
 835     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
 836     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
 837     tcg_gen_movi_i64(dst, INT64_MIN);
 838     tcg_gen_br(l2);
 839     gen_set_label(l1);
 840     tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
 841     gen_set_label(l2);
 842 }
 843 #endif
 844
 845 static inline void gen_op_div_cc(TCGv dst)
 846 {
 847     int l1;
 848
 849     tcg_gen_mov_tl(cpu_cc_dst, dst);
 850     gen_cc_clear_icc();
 851     gen_cc_NZ_icc(cpu_cc_dst);
 852     l1 = gen_new_label();
 853     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
 854     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
 855     gen_set_label(l1);
 856 }
 857
 858 static inline void gen_op_logic_cc(TCGv dst)
 859 {
 860     tcg_gen_mov_tl(cpu_cc_dst, dst);
 861
 862     gen_cc_clear_icc();
 863     gen_cc_NZ_icc(cpu_cc_dst);
 864 #ifdef TARGET_SPARC64
 865     gen_cc_clear_xcc();
 866     gen_cc_NZ_xcc(cpu_cc_dst);
 867 #endif
 868 }
 869
 870 // 1
 871 static inline void gen_op_eval_ba(TCGv dst)
 872 {
 873     tcg_gen_movi_tl(dst, 1);
 874 }
 875
 876 // Z
 877 static inline void gen_op_eval_be(TCGv dst, TCGv src)
 878 {
 879     gen_mov_reg_Z(dst, src);
 880 }
 881
 882 // Z | (N ^ V)
 883 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
 884 {
 885     gen_mov_reg_N(cpu_tmp0, src);
 886     gen_mov_reg_V(dst, src);
 887     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 888     gen_mov_reg_Z(cpu_tmp0, src);
 889     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 890 }
 891
 892 // N ^ V
 893 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
 894 {
 895     gen_mov_reg_V(cpu_tmp0, src);
 896     gen_mov_reg_N(dst, src);
 897     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 898 }
 899
 900 // C | Z
 901 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
 902 {
 903     gen_mov_reg_Z(cpu_tmp0, src);
 904     gen_mov_reg_C(dst, src);
 905     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 906 }
 907
 908 // C
 909 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
 910 {
 911     gen_mov_reg_C(dst, src);
 912 }
 913
 914 // V
 915 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
 916 {
 917     gen_mov_reg_V(dst, src);
 918 }
 919
 920 // 0
 921 static inline void gen_op_eval_bn(TCGv dst)
 922 {
 923     tcg_gen_movi_tl(dst, 0);
 924 }
 925
 926 // N
 927 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
 928 {
 929     gen_mov_reg_N(dst, src);
 930 }
 931
 932 // !Z
 933 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
 934 {
 935     gen_mov_reg_Z(dst, src);
 936     tcg_gen_xori_tl(dst, dst, 0x1);
 937 }
 938
 939 // !(Z | (N ^ V))
 940 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
 941 {
 942     gen_mov_reg_N(cpu_tmp0, src);
 943     gen_mov_reg_V(dst, src);
 944     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 945     gen_mov_reg_Z(cpu_tmp0, src);
 946     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 947     tcg_gen_xori_tl(dst, dst, 0x1);
 948 }
 949
 950 // !(N ^ V)
 951 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
 952 {
 953     gen_mov_reg_V(cpu_tmp0, src);
 954     gen_mov_reg_N(dst, src);
 955     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
 956     tcg_gen_xori_tl(dst, dst, 0x1);
 957 }
 958
 959 // !(C | Z)
 960 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
 961 {
 962     gen_mov_reg_Z(cpu_tmp0, src);
 963     gen_mov_reg_C(dst, src);
 964     tcg_gen_or_tl(dst, dst, cpu_tmp0);
 965     tcg_gen_xori_tl(dst, dst, 0x1);
 966 }
 967
 968 // !C
 969 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
 970 {
 971     gen_mov_reg_C(dst, src);
 972     tcg_gen_xori_tl(dst, dst, 0x1);
 973 }
 974
 975 // !N
 976 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
 977 {
 978     gen_mov_reg_N(dst, src);
 979     tcg_gen_xori_tl(dst, dst, 0x1);
 980 }
 981
 982 // !V
 983 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
 984 {
 985     gen_mov_reg_V(dst, src);
 986     tcg_gen_xori_tl(dst, dst, 0x1);
 987 }
 988
 989 /*
 990   FPSR bit field FCC1 | FCC0:
 991    0 =
 992    1 <
 993    2 >
 994    3 unordered
 995 */
 996 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
 997                                     unsigned int fcc_offset)
 998 {
 999     tcg_gen_extu_i32_tl(reg, src);
1000     tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
1001     tcg_gen_andi_tl(reg, reg, 0x1);
1002 }
1003
1004 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
1005                                     unsigned int fcc_offset)
1006 {
1007     tcg_gen_extu_i32_tl(reg, src);
1008     tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
1009     tcg_gen_andi_tl(reg, reg, 0x1);
1010 }
1011
1012 // !0: FCC0 | FCC1
1013 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1014                                     unsigned int fcc_offset)
1015 {
1016     gen_mov_reg_FCC0(dst, src, fcc_offset);
1017     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1018     tcg_gen_or_tl(dst, dst, cpu_tmp0);
1019 }
1020
1021 // 1 or 2: FCC0 ^ FCC1
1022 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1023                                     unsigned int fcc_offset)
1024 {
1025     gen_mov_reg_FCC0(dst, src, fcc_offset);
1026     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1027     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1028 }
1029
1030 // 1 or 3: FCC0
1031 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1032                                     unsigned int fcc_offset)
1033 {
1034     gen_mov_reg_FCC0(dst, src, fcc_offset);
1035 }
1036
1037 // 1: FCC0 & !FCC1
1038 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1039                                     unsigned int fcc_offset)
1040 {
1041     gen_mov_reg_FCC0(dst, src, fcc_offset);
1042     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1043     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1044     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1045 }
1046
1047 // 2 or 3: FCC1
1048 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1049                                     unsigned int fcc_offset)
1050 {
1051     gen_mov_reg_FCC1(dst, src, fcc_offset);
1052 }
1053
1054 // 2: !FCC0 & FCC1
1055 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1056                                     unsigned int fcc_offset)
1057 {
1058     gen_mov_reg_FCC0(dst, src, fcc_offset);
1059     tcg_gen_xori_tl(dst, dst, 0x1);
1060     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1061     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1062 }
1063
1064 // 3: FCC0 & FCC1
1065 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1066                                     unsigned int fcc_offset)
1067 {
1068     gen_mov_reg_FCC0(dst, src, fcc_offset);
1069     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1070     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1071 }
1072
1073 // 0: !(FCC0 | FCC1)
1074 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1075                                     unsigned int fcc_offset)
1076 {
1077     gen_mov_reg_FCC0(dst, src, fcc_offset);
1078     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1079     tcg_gen_or_tl(dst, dst, cpu_tmp0);
1080     tcg_gen_xori_tl(dst, dst, 0x1);
1081 }
1082
1083 // 0 or 3: !(FCC0 ^ FCC1)
1084 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1085                                     unsigned int fcc_offset)
1086 {
1087     gen_mov_reg_FCC0(dst, src, fcc_offset);
1088     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1089     tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1090     tcg_gen_xori_tl(dst, dst, 0x1);
1091 }
1092
1093 // 0 or 2: !FCC0
1094 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1095                                     unsigned int fcc_offset)
1096 {
1097     gen_mov_reg_FCC0(dst, src, fcc_offset);
1098     tcg_gen_xori_tl(dst, dst, 0x1);
1099 }
1100
1101 // !1: !(FCC0 & !FCC1)
1102 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1103                                     unsigned int fcc_offset)
1104 {
1105     gen_mov_reg_FCC0(dst, src, fcc_offset);
1106     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1107     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1108     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1109     tcg_gen_xori_tl(dst, dst, 0x1);
1110 }
1111
1112 // 0 or 1: !FCC1
1113 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1114                                     unsigned int fcc_offset)
1115 {
1116     gen_mov_reg_FCC1(dst, src, fcc_offset);
1117     tcg_gen_xori_tl(dst, dst, 0x1);
1118 }
1119
1120 // !2: !(!FCC0 & FCC1)
1121 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1122                                     unsigned int fcc_offset)
1123 {
1124     gen_mov_reg_FCC0(dst, src, fcc_offset);
1125     tcg_gen_xori_tl(dst, dst, 0x1);
1126     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1127     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1128     tcg_gen_xori_tl(dst, dst, 0x1);
1129 }
1130
1131 // !3: !(FCC0 & FCC1)
1132 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1133                                     unsigned int fcc_offset)
1134 {
1135     gen_mov_reg_FCC0(dst, src, fcc_offset);
1136     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1137     tcg_gen_and_tl(dst, dst, cpu_tmp0);
1138     tcg_gen_xori_tl(dst, dst, 0x1);
1139 }
1140
1141 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1142                                target_ulong pc2, TCGv r_cond)
1143 {
1144     int l1;
1145
1146     l1 = gen_new_label();
1147
1148     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1149
1150     gen_goto_tb(dc, 0, pc1, pc1 + 4);
1151
1152     gen_set_label(l1);
1153     gen_goto_tb(dc, 1, pc2, pc2 + 4);
1154 }
1155
1156 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1157                                 target_ulong pc2, TCGv r_cond)
1158 {
1159     int l1;
1160
1161     l1 = gen_new_label();
1162
1163     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1164
1165     gen_goto_tb(dc, 0, pc2, pc1);
1166
1167     gen_set_label(l1);
1168     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1169 }
1170
1171 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1172                                       TCGv r_cond)
1173 {
1174     int l1, l2;
1175
1176     l1 = gen_new_label();
1177     l2 = gen_new_label();
1178
1179     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1180
1181     tcg_gen_movi_tl(cpu_npc, npc1);
1182     tcg_gen_br(l2);
1183
1184     gen_set_label(l1);
1185     tcg_gen_movi_tl(cpu_npc, npc2);
1186     gen_set_label(l2);
1187 }
1188
1189 /* call this function before using the condition register as it may
1190    have been set for a jump */
1191 static inline void flush_cond(DisasContext *dc, TCGv cond)
1192 {
1193     if (dc->npc == JUMP_PC) {
1194         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1195         dc->npc = DYNAMIC_PC;
1196     }
1197 }
1198
1199 static inline void save_npc(DisasContext *dc, TCGv cond)
1200 {
1201     if (dc->npc == JUMP_PC) {
1202         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1203         dc->npc = DYNAMIC_PC;
1204     } else if (dc->npc != DYNAMIC_PC) {
1205         tcg_gen_movi_tl(cpu_npc, dc->npc);
1206     }
1207 }
1208
1209 static inline void save_state(DisasContext *dc, TCGv cond)
1210 {
1211     tcg_gen_movi_tl(cpu_pc, dc->pc);
1212     save_npc(dc, cond);
1213 }
1214
1215 static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1216 {
1217     if (dc->npc == JUMP_PC) {
1218         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1219         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1220         dc->pc = DYNAMIC_PC;
1221     } else if (dc->npc == DYNAMIC_PC) {
1222         tcg_gen_mov_tl(cpu_pc, cpu_npc);
1223         dc->pc = DYNAMIC_PC;
1224     } else {
1225         dc->pc = dc->npc;
1226     }
1227 }
1228
1229 static inline void gen_op_next_insn(void)
1230 {
1231     tcg_gen_mov_tl(cpu_pc, cpu_npc);
1232     tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1233 }
1234
1235 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1236 {
1237     TCGv r_src;
1238
1239 #ifdef TARGET_SPARC64
1240     if (cc)
1241         r_src = cpu_xcc;
1242     else
1243         r_src = cpu_psr;
1244 #else
1245     r_src = cpu_psr;
1246 #endif
1247     switch (cond) {
1248     case 0x0:
1249         gen_op_eval_bn(r_dst);
1250         break;
1251     case 0x1:
1252         gen_op_eval_be(r_dst, r_src);
1253         break;
1254     case 0x2:
1255         gen_op_eval_ble(r_dst, r_src);
1256         break;
1257     case 0x3:
1258         gen_op_eval_bl(r_dst, r_src);
1259         break;
1260     case 0x4:
1261         gen_op_eval_bleu(r_dst, r_src);
1262         break;
1263     case 0x5:
1264         gen_op_eval_bcs(r_dst, r_src);
1265         break;
1266     case 0x6:
1267         gen_op_eval_bneg(r_dst, r_src);
1268         break;
1269     case 0x7:
1270         gen_op_eval_bvs(r_dst, r_src);
1271         break;
1272     case 0x8:
1273         gen_op_eval_ba(r_dst);
1274         break;
1275     case 0x9:
1276         gen_op_eval_bne(r_dst, r_src);
1277         break;
1278     case 0xa:
1279         gen_op_eval_bg(r_dst, r_src);
1280         break;
1281     case 0xb:
1282         gen_op_eval_bge(r_dst, r_src);
1283         break;
1284     case 0xc:
1285         gen_op_eval_bgu(r_dst, r_src);
1286         break;
1287     case 0xd:
1288         gen_op_eval_bcc(r_dst, r_src);
1289         break;
1290     case 0xe:
1291         gen_op_eval_bpos(r_dst, r_src);
1292         break;
1293     case 0xf:
1294         gen_op_eval_bvc(r_dst, r_src);
1295         break;
1296     }
1297 }
1298
1299 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1300 {
1301     unsigned int offset;
1302
1303     switch (cc) {
1304     default:
1305     case 0x0:
1306         offset = 0;
1307         break;
1308     case 0x1:
1309         offset = 32 - 10;
1310         break;
1311     case 0x2:
1312         offset = 34 - 10;
1313         break;
1314     case 0x3:
1315         offset = 36 - 10;
1316         break;
1317     }
1318
1319     switch (cond) {
1320     case 0x0:
1321         gen_op_eval_bn(r_dst);
1322         break;
1323     case 0x1:
1324         gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1325         break;
1326     case 0x2:
1327         gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1328         break;
1329     case 0x3:
1330         gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1331         break;
1332     case 0x4:
1333         gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1334         break;
1335     case 0x5:
1336         gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1337         break;
1338     case 0x6:
1339         gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1340         break;
1341     case 0x7:
1342         gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1343         break;
1344     case 0x8:
1345         gen_op_eval_ba(r_dst);
1346         break;
1347     case 0x9:
1348         gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1349         break;
1350     case 0xa:
1351         gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1352         break;
1353     case 0xb:
1354         gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1355         break;
1356     case 0xc:
1357         gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1358         break;
1359     case 0xd:
1360         gen_op_eval_fble(r_dst, cpu_fsr, offset);
1361         break;
1362     case 0xe:
1363         gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1364         break;
1365     case 0xf:
1366         gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1367         break;
1368     }
1369 }
1370
1371 #ifdef TARGET_SPARC64
1372 // Inverted logic
1373 static const int gen_tcg_cond_reg[8] = {
1374     -1,
1375     TCG_COND_NE,
1376     TCG_COND_GT,
1377     TCG_COND_GE,
1378     -1,
1379     TCG_COND_EQ,
1380     TCG_COND_LE,
1381     TCG_COND_LT,
1382 };
1383
1384 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1385 {
1386     int l1;
1387
1388     l1 = gen_new_label();
1389     tcg_gen_movi_tl(r_dst, 0);
1390     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1391     tcg_gen_movi_tl(r_dst, 1);
1392     gen_set_label(l1);
1393 }
1394 #endif
1395
1396 /* XXX: potentially incorrect if dynamic npc */
1397 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1398                       TCGv r_cond)
1399 {
1400     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1401     target_ulong target = dc->pc + offset;
1402
1403     if (cond == 0x0) {
1404         /* unconditional not taken */
1405         if (a) {
1406             dc->pc = dc->npc + 4;
1407             dc->npc = dc->pc + 4;
1408         } else {
1409             dc->pc = dc->npc;
1410             dc->npc = dc->pc + 4;
1411         }
1412     } else if (cond == 0x8) {
1413         /* unconditional taken */
1414         if (a) {
1415             dc->pc = target;
1416             dc->npc = dc->pc + 4;
1417         } else {
1418             dc->pc = dc->npc;
1419             dc->npc = target;
1420         }
1421     } else {
1422         flush_cond(dc, r_cond);
1423         gen_cond(r_cond, cc, cond);
1424         if (a) {
1425             gen_branch_a(dc, target, dc->npc, r_cond);
1426             dc->is_br = 1;
1427         } else {
1428             dc->pc = dc->npc;
1429             dc->jump_pc[0] = target;
1430             dc->jump_pc[1] = dc->npc + 4;
1431             dc->npc = JUMP_PC;
1432         }
1433     }
1434 }
1435
1436 /* XXX: potentially incorrect if dynamic npc */
1437 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1438                       TCGv r_cond)
1439 {
1440     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1441     target_ulong target = dc->pc + offset;
1442
1443     if (cond == 0x0) {
1444         /* unconditional not taken */
1445         if (a) {
1446             dc->pc = dc->npc + 4;
1447             dc->npc = dc->pc + 4;
1448         } else {
1449             dc->pc = dc->npc;
1450             dc->npc = dc->pc + 4;
1451         }
1452     } else if (cond == 0x8) {
1453         /* unconditional taken */
1454         if (a) {
1455             dc->pc = target;
1456             dc->npc = dc->pc + 4;
1457         } else {
1458             dc->pc = dc->npc;
1459             dc->npc = target;
1460         }
1461     } else {
1462         flush_cond(dc, r_cond);
1463         gen_fcond(r_cond, cc, cond);
1464         if (a) {
1465             gen_branch_a(dc, target, dc->npc, r_cond);
1466             dc->is_br = 1;
1467         } else {
1468             dc->pc = dc->npc;
1469             dc->jump_pc[0] = target;
1470             dc->jump_pc[1] = dc->npc + 4;
1471             dc->npc = JUMP_PC;
1472         }
1473     }
1474 }
1475
1476 #ifdef TARGET_SPARC64
1477 /* XXX: potentially incorrect if dynamic npc */
1478 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1479                           TCGv r_cond, TCGv r_reg)
1480 {
1481     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1482     target_ulong target = dc->pc + offset;
1483
1484     flush_cond(dc, r_cond);
1485     gen_cond_reg(r_cond, cond, r_reg);
1486     if (a) {
1487         gen_branch_a(dc, target, dc->npc, r_cond);
1488         dc->is_br = 1;
1489     } else {
1490         dc->pc = dc->npc;
1491         dc->jump_pc[0] = target;
1492         dc->jump_pc[1] = dc->npc + 4;
1493         dc->npc = JUMP_PC;
1494     }
1495 }
1496
1497 static GenOpFunc * const gen_fcmps[4] = {
1498     helper_fcmps,
1499     helper_fcmps_fcc1,
1500     helper_fcmps_fcc2,
1501     helper_fcmps_fcc3,
1502 };
1503
1504 static GenOpFunc * const gen_fcmpd[4] = {
1505     helper_fcmpd,
1506     helper_fcmpd_fcc1,
1507     helper_fcmpd_fcc2,
1508     helper_fcmpd_fcc3,
1509 };
1510
1511 static GenOpFunc * const gen_fcmpq[4] = {
1512     helper_fcmpq,
1513     helper_fcmpq_fcc1,
1514     helper_fcmpq_fcc2,
1515     helper_fcmpq_fcc3,
1516 };
1517
1518 static GenOpFunc * const gen_fcmpes[4] = {
1519     helper_fcmpes,
1520     helper_fcmpes_fcc1,
1521     helper_fcmpes_fcc2,
1522     helper_fcmpes_fcc3,
1523 };
1524
1525 static GenOpFunc * const gen_fcmped[4] = {
1526     helper_fcmped,
1527     helper_fcmped_fcc1,
1528     helper_fcmped_fcc2,
1529     helper_fcmped_fcc3,
1530 };
1531
1532 static GenOpFunc * const gen_fcmpeq[4] = {
1533     helper_fcmpeq,
1534     helper_fcmpeq_fcc1,
1535     helper_fcmpeq_fcc2,
1536     helper_fcmpeq_fcc3,
1537 };
1538
1539 static inline void gen_op_fcmps(int fccno)
1540 {
1541     tcg_gen_helper_0_0(gen_fcmps[fccno]);
1542 }
1543
1544 static inline void gen_op_fcmpd(int fccno)
1545 {
1546     tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1547 }
1548
1549 static inline void gen_op_fcmpq(int fccno)
1550 {
1551     tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1552 }
1553
1554 static inline void gen_op_fcmpes(int fccno)
1555 {
1556     tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1557 }
1558
1559 static inline void gen_op_fcmped(int fccno)
1560 {
1561     tcg_gen_helper_0_0(gen_fcmped[fccno]);
1562 }
1563
1564 static inline void gen_op_fcmpeq(int fccno)
1565 {
1566     tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1567 }
1568
1569 #else
1570
1571 static inline void gen_op_fcmps(int fccno)
1572 {
1573     tcg_gen_helper_0_0(helper_fcmps);
1574 }
1575
1576 static inline void gen_op_fcmpd(int fccno)
1577 {
1578     tcg_gen_helper_0_0(helper_fcmpd);
1579 }
1580
1581 static inline void gen_op_fcmpq(int fccno)
1582 {
1583     tcg_gen_helper_0_0(helper_fcmpq);
1584 }
1585
1586 static inline void gen_op_fcmpes(int fccno)
1587 {
1588     tcg_gen_helper_0_0(helper_fcmpes);
1589 }
1590
1591 static inline void gen_op_fcmped(int fccno)
1592 {
1593     tcg_gen_helper_0_0(helper_fcmped);
1594 }
1595
1596 static inline void gen_op_fcmpeq(int fccno)
1597 {
1598     tcg_gen_helper_0_0(helper_fcmpeq);
1599 }
1600 #endif
1601
1602 static inline void gen_op_fpexception_im(int fsr_flags)
1603 {
1604     TCGv r_const;
1605
1606     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1607     tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1608     r_const = tcg_const_i32(TT_FP_EXCP);
1609     tcg_gen_helper_0_1(raise_exception, r_const);
1610     tcg_temp_free(r_const);
1611 }
1612
1613 static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1614 {
1615 #if !defined(CONFIG_USER_ONLY)
1616     if (!dc->fpu_enabled) {
1617         TCGv r_const;
1618
1619         save_state(dc, r_cond);
1620         r_const = tcg_const_i32(TT_NFPU_INSN);
1621         tcg_gen_helper_0_1(raise_exception, r_const);
1622         tcg_temp_free(r_const);
1623         dc->is_br = 1;
1624         return 1;
1625     }
1626 #endif
1627     return 0;
1628 }
1629
1630 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1631 {
1632     tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1633 }
1634
1635 static inline void gen_clear_float_exceptions(void)
1636 {
1637     tcg_gen_helper_0_0(helper_clear_float_exceptions);
1638 }
1639
1640 /* asi moves */
1641 #ifdef TARGET_SPARC64
1642 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1643 {
1644     int asi, offset;
1645     TCGv r_asi;
1646
1647     if (IS_IMM) {
1648         r_asi = tcg_temp_new(TCG_TYPE_I32);
1649         offset = GET_FIELD(insn, 25, 31);
1650         tcg_gen_addi_tl(r_addr, r_addr, offset);
1651         tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1652     } else {
1653         asi = GET_FIELD(insn, 19, 26);
1654         r_asi = tcg_const_i32(asi);
1655     }
1656     return r_asi;
1657 }
1658
1659 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1660                               int sign)
1661 {
1662     TCGv r_asi, r_size, r_sign;
1663
1664     r_asi = gen_get_asi(insn, addr);
1665     r_size = tcg_const_i32(size);
1666     r_sign = tcg_const_i32(sign);
1667     tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1668     tcg_temp_free(r_sign);
1669     tcg_temp_free(r_size);
1670     tcg_temp_free(r_asi);
1671 }
1672
1673 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1674 {
1675     TCGv r_asi, r_size;
1676
1677     r_asi = gen_get_asi(insn, addr);
1678     r_size = tcg_const_i32(size);
1679     tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1680     tcg_temp_free(r_size);
1681     tcg_temp_free(r_asi);
1682 }
1683
1684 static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1685 {
1686     TCGv r_asi, r_size, r_rd;
1687
1688     r_asi = gen_get_asi(insn, addr);
1689     r_size = tcg_const_i32(size);
1690     r_rd = tcg_const_i32(rd);
1691     tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1692     tcg_temp_free(r_rd);
1693     tcg_temp_free(r_size);
1694     tcg_temp_free(r_asi);
1695 }
1696
1697 static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1698 {
1699     TCGv r_asi, r_size, r_rd;
1700
1701     r_asi = gen_get_asi(insn, addr);
1702     r_size = tcg_const_i32(size);
1703     r_rd = tcg_const_i32(rd);
1704     tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1705     tcg_temp_free(r_rd);
1706     tcg_temp_free(r_size);
1707     tcg_temp_free(r_asi);
1708 }
1709
1710 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1711 {
1712     TCGv r_asi, r_size, r_sign;
1713
1714     r_asi = gen_get_asi(insn, addr);
1715     r_size = tcg_const_i32(4);
1716     r_sign = tcg_const_i32(0);
1717     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1718     tcg_temp_free(r_sign);
1719     tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1720     tcg_temp_free(r_size);
1721     tcg_temp_free(r_asi);
1722     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1723 }
1724
1725 static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1726 {
1727     TCGv r_asi, r_rd;
1728
1729     r_asi = gen_get_asi(insn, addr);
1730     r_rd = tcg_const_i32(rd);
1731     tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd);
1732     tcg_temp_free(r_rd);
1733     tcg_temp_free(r_asi);
1734 }
1735
1736 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1737 {
1738     TCGv r_temp, r_asi, r_size;
1739
1740     r_temp = tcg_temp_new(TCG_TYPE_TL);
1741     gen_movl_reg_TN(rd + 1, r_temp);
1742     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1743                        r_temp);
1744     tcg_temp_free(r_temp);
1745     r_asi = gen_get_asi(insn, addr);
1746     r_size = tcg_const_i32(8);
1747     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1748     tcg_temp_free(r_size);
1749     tcg_temp_free(r_asi);
1750 }
1751
1752 static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1753                                int rd)
1754 {
1755     TCGv r_val1, r_asi;
1756
1757     r_val1 = tcg_temp_new(TCG_TYPE_TL);
1758     gen_movl_reg_TN(rd, r_val1);
1759     r_asi = gen_get_asi(insn, addr);
1760     tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1761     tcg_temp_free(r_asi);
1762     tcg_temp_free(r_val1);
1763 }
1764
1765 static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1766                                 int rd)
1767 {
1768     TCGv r_asi;
1769
1770     gen_movl_reg_TN(rd, cpu_tmp64);
1771     r_asi = gen_get_asi(insn, addr);
1772     tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1773     tcg_temp_free(r_asi);
1774 }
1775
1776 #elif !defined(CONFIG_USER_ONLY)
1777
1778 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1779                               int sign)
1780 {
1781     TCGv r_asi, r_size, r_sign;
1782
1783     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1784     r_size = tcg_const_i32(size);
1785     r_sign = tcg_const_i32(sign);
1786     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1787     tcg_temp_free(r_sign);
1788     tcg_temp_free(r_size);
1789     tcg_temp_free(r_asi);
1790     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1791 }
1792
1793 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1794 {
1795     TCGv r_asi, r_size;
1796
1797     tcg_gen_extu_tl_i64(cpu_tmp64, src);
1798     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1799     r_size = tcg_const_i32(size);
1800     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1801     tcg_temp_free(r_size);
1802     tcg_temp_free(r_asi);
1803 }
1804
1805 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1806 {
1807     TCGv r_asi, r_size, r_sign;
1808
1809     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1810     r_size = tcg_const_i32(4);
1811     r_sign = tcg_const_i32(0);
1812     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1813     tcg_temp_free(r_sign);
1814     tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1815     tcg_temp_free(r_size);
1816     tcg_temp_free(r_asi);
1817     tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1818 }
1819
1820 static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1821 {
1822     TCGv r_asi, r_size, r_sign;
1823
1824     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1825     r_size = tcg_const_i32(8);
1826     r_sign = tcg_const_i32(0);
1827     tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1828     tcg_temp_free(r_sign);
1829     tcg_temp_free(r_size);
1830     tcg_temp_free(r_asi);
1831     tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
1832     gen_movl_TN_reg(rd + 1, cpu_tmp0);
1833     tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1834     tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1835     gen_movl_TN_reg(rd, hi);
1836 }
1837
1838 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1839 {
1840     TCGv r_temp, r_asi, r_size;
1841
1842     r_temp = tcg_temp_new(TCG_TYPE_TL);
1843     gen_movl_reg_TN(rd + 1, r_temp);
1844     tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1845     tcg_temp_free(r_temp);
1846     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1847     r_size = tcg_const_i32(8);
1848     tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1849     tcg_temp_free(r_size);
1850     tcg_temp_free(r_asi);
1851 }
1852 #endif
1853
1854 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1855 static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1856 {
1857     TCGv r_val, r_asi, r_size;
1858
1859     gen_ld_asi(dst, addr, insn, 1, 0);
1860
1861     r_val = tcg_const_i64(0xffULL);
1862     r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1863     r_size = tcg_const_i32(1);
1864     tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1865     tcg_temp_free(r_size);
1866     tcg_temp_free(r_asi);
1867     tcg_temp_free(r_val);
1868 }
1869 #endif
1870
1871 static inline TCGv get_src1(unsigned int insn, TCGv def)
1872 {
1873     TCGv r_rs1 = def;
1874     unsigned int rs1;
1875
1876     rs1 = GET_FIELD(insn, 13, 17);
1877     if (rs1 == 0)
1878         r_rs1 = tcg_const_tl(0); // XXX how to free?
1879     else if (rs1 < 8)
1880         r_rs1 = cpu_gregs[rs1];
1881     else
1882         tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1883     return r_rs1;
1884 }
1885
1886 static inline TCGv get_src2(unsigned int insn, TCGv def)
1887 {
1888     TCGv r_rs2 = def;
1889     unsigned int rs2;
1890
1891     if (IS_IMM) { /* immediate */
1892         rs2 = GET_FIELDs(insn, 19, 31);
1893         r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1894     } else { /* register */
1895         rs2 = GET_FIELD(insn, 27, 31);
1896         if (rs2 == 0)
1897             r_rs2 = tcg_const_tl(0); // XXX how to free?
1898         else if (rs2 < 8)
1899             r_rs2 = cpu_gregs[rs2];
1900         else
1901             tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1902     }
1903     return r_rs2;
1904 }
1905
1906 #define CHECK_IU_FEATURE(dc, FEATURE)                      \
1907     if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1908         goto illegal_insn;
1909 #define CHECK_FPU_FEATURE(dc, FEATURE)                     \
1910     if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1911         goto nfpu_insn;
1912
1913 /* before an instruction, dc->pc must be static */
1914 static void disas_sparc_insn(DisasContext * dc)
1915 {
1916     unsigned int insn, opc, rs1, rs2, rd;
1917
1918     if (unlikely(loglevel & CPU_LOG_TB_OP))
1919         tcg_gen_debug_insn_start(dc->pc);
1920     insn = ldl_code(dc->pc);
1921     opc = GET_FIELD(insn, 0, 1);
1922
1923     rd = GET_FIELD(insn, 2, 6);
1924
1925     cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1926     cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
1927
1928     switch (opc) {
1929     case 0:                     /* branches/sethi */
1930         {
1931             unsigned int xop = GET_FIELD(insn, 7, 9);
1932             int32_t target;
1933             switch (xop) {
1934 #ifdef TARGET_SPARC64
1935             case 0x1:           /* V9 BPcc */
1936                 {
1937                     int cc;
1938
1939                     target = GET_FIELD_SP(insn, 0, 18);
1940                     target = sign_extend(target, 18);
1941                     target <<= 2;
1942                     cc = GET_FIELD_SP(insn, 20, 21);
1943                     if (cc == 0)
1944                         do_branch(dc, target, insn, 0, cpu_cond);
1945                     else if (cc == 2)
1946                         do_branch(dc, target, insn, 1, cpu_cond);
1947                     else
1948                         goto illegal_insn;
1949                     goto jmp_insn;
1950                 }
1951             case 0x3:           /* V9 BPr */
1952                 {
1953                     target = GET_FIELD_SP(insn, 0, 13) |
1954                         (GET_FIELD_SP(insn, 20, 21) << 14);
1955                     target = sign_extend(target, 16);
1956                     target <<= 2;
1957                     cpu_src1 = get_src1(insn, cpu_src1);
1958                     do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1959                     goto jmp_insn;
1960                 }
1961             case 0x5:           /* V9 FBPcc */
1962                 {
1963                     int cc = GET_FIELD_SP(insn, 20, 21);
1964                     if (gen_trap_ifnofpu(dc, cpu_cond))
1965                         goto jmp_insn;
1966                     target = GET_FIELD_SP(insn, 0, 18);
1967                     target = sign_extend(target, 19);
1968                     target <<= 2;
1969                     do_fbranch(dc, target, insn, cc, cpu_cond);
1970                     goto jmp_insn;
1971                 }
1972 #else
1973             case 0x7:           /* CBN+x */
1974                 {
1975                     goto ncp_insn;
1976                 }
1977 #endif
1978             case 0x2:           /* BN+x */
1979                 {
1980                     target = GET_FIELD(insn, 10, 31);
1981                     target = sign_extend(target, 22);
1982                     target <<= 2;
1983                     do_branch(dc, target, insn, 0, cpu_cond);
1984                     goto jmp_insn;
1985                 }
1986             case 0x6:           /* FBN+x */
1987                 {
1988                     if (gen_trap_ifnofpu(dc, cpu_cond))
1989                         goto jmp_insn;
1990                     target = GET_FIELD(insn, 10, 31);
1991                     target = sign_extend(target, 22);
1992                     target <<= 2;
1993                     do_fbranch(dc, target, insn, 0, cpu_cond);
1994                     goto jmp_insn;
1995                 }
1996             case 0x4:           /* SETHI */
1997                 if (rd) { // nop
1998                     uint32_t value = GET_FIELD(insn, 10, 31);
1999                     TCGv r_const;
2000
2001                     r_const = tcg_const_tl(value << 10);
2002                     gen_movl_TN_reg(rd, r_const);
2003                     tcg_temp_free(r_const);
2004                 }
2005                 break;
2006             case 0x0:           /* UNIMPL */
2007             default:
2008                 goto illegal_insn;
2009             }
2010             break;
2011         }
2012         break;
2013     case 1:
2014         /*CALL*/ {
2015             target_long target = GET_FIELDs(insn, 2, 31) << 2;
2016             TCGv r_const;
2017
2018             r_const = tcg_const_tl(dc->pc);
2019             gen_movl_TN_reg(15, r_const);
2020             tcg_temp_free(r_const);
2021             target += dc->pc;
2022             gen_mov_pc_npc(dc, cpu_cond);
2023             dc->npc = target;
2024         }
2025         goto jmp_insn;
2026     case 2:                     /* FPU & Logical Operations */
2027         {
2028             unsigned int xop = GET_FIELD(insn, 7, 12);
2029             if (xop == 0x3a) {  /* generate trap */
2030                 int cond;
2031
2032                 cpu_src1 = get_src1(insn, cpu_src1);
2033                 if (IS_IMM) {
2034                     rs2 = GET_FIELD(insn, 25, 31);
2035                     tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2036                 } else {
2037                     rs2 = GET_FIELD(insn, 27, 31);
2038                     if (rs2 != 0) {
2039                         gen_movl_reg_TN(rs2, cpu_src2);
2040                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2041                     } else
2042                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
2043                 }
2044                 cond = GET_FIELD(insn, 3, 6);
2045                 if (cond == 0x8) {
2046                     save_state(dc, cpu_cond);
2047                     tcg_gen_helper_0_1(helper_trap, cpu_dst);
2048                 } else if (cond != 0) {
2049                     TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2050 #ifdef TARGET_SPARC64
2051                     /* V9 icc/xcc */
2052                     int cc = GET_FIELD_SP(insn, 11, 12);
2053
2054                     save_state(dc, cpu_cond);
2055                     if (cc == 0)
2056                         gen_cond(r_cond, 0, cond);
2057                     else if (cc == 2)
2058                         gen_cond(r_cond, 1, cond);
2059                     else
2060                         goto illegal_insn;
2061 #else
2062                     save_state(dc, cpu_cond);
2063                     gen_cond(r_cond, 0, cond);
2064 #endif
2065                     tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2066                     tcg_temp_free(r_cond);
2067                 }
2068                 gen_op_next_insn();
2069                 tcg_gen_exit_tb(0);
2070                 dc->is_br = 1;
2071                 goto jmp_insn;
2072             } else if (xop == 0x28) {
2073                 rs1 = GET_FIELD(insn, 13, 17);
2074                 switch(rs1) {
2075                 case 0: /* rdy */
2076 #ifndef TARGET_SPARC64
2077                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2078                                        manual, rdy on the microSPARC
2079                                        II */
2080                 case 0x0f:          /* stbar in the SPARCv8 manual,
2081                                        rdy on the microSPARC II */
2082                 case 0x10 ... 0x1f: /* implementation-dependent in the
2083                                        SPARCv8 manual, rdy on the
2084                                        microSPARC II */
2085 #endif
2086                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2087                                   offsetof(CPUSPARCState, y));
2088                     gen_movl_TN_reg(rd, cpu_tmp0);
2089                     break;
2090 #ifdef TARGET_SPARC64
2091                 case 0x2: /* V9 rdccr */
2092                     tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2093                     gen_movl_TN_reg(rd, cpu_dst);
2094                     break;
2095                 case 0x3: /* V9 rdasi */
2096                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2097                                    offsetof(CPUSPARCState, asi));
2098                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2099                     gen_movl_TN_reg(rd, cpu_dst);
2100                     break;
2101                 case 0x4: /* V9 rdtick */
2102                     {
2103                         TCGv r_tickptr;
2104
2105                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2106                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2107                                        offsetof(CPUState, tick));
2108                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2109                                            r_tickptr);
2110                         tcg_temp_free(r_tickptr);
2111                         gen_movl_TN_reg(rd, cpu_dst);
2112                     }
2113                     break;
2114                 case 0x5: /* V9 rdpc */
2115                     {
2116                         TCGv r_const;
2117
2118                         r_const = tcg_const_tl(dc->pc);
2119                         gen_movl_TN_reg(rd, r_const);
2120                         tcg_temp_free(r_const);
2121                     }
2122                     break;
2123                 case 0x6: /* V9 rdfprs */
2124                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2125                                    offsetof(CPUSPARCState, fprs));
2126                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2127                     gen_movl_TN_reg(rd, cpu_dst);
2128                     break;
2129                 case 0xf: /* V9 membar */
2130                     break; /* no effect */
2131                 case 0x13: /* Graphics Status */
2132                     if (gen_trap_ifnofpu(dc, cpu_cond))
2133                         goto jmp_insn;
2134                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2135                                   offsetof(CPUSPARCState, gsr));
2136                     gen_movl_TN_reg(rd, cpu_tmp0);
2137                     break;
2138                 case 0x17: /* Tick compare */
2139                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2140                                   offsetof(CPUSPARCState, tick_cmpr));
2141                     gen_movl_TN_reg(rd, cpu_tmp0);
2142                     break;
2143                 case 0x18: /* System tick */
2144                     {
2145                         TCGv r_tickptr;
2146
2147                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2148                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2149                                        offsetof(CPUState, stick));
2150                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2151                                            r_tickptr);
2152                         tcg_temp_free(r_tickptr);
2153                         gen_movl_TN_reg(rd, cpu_dst);
2154                     }
2155                     break;
2156                 case 0x19: /* System tick compare */
2157                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2158                                   offsetof(CPUSPARCState, stick_cmpr));
2159                     gen_movl_TN_reg(rd, cpu_tmp0);
2160                     break;
2161                 case 0x10: /* Performance Control */
2162                 case 0x11: /* Performance Instrumentation Counter */
2163                 case 0x12: /* Dispatch Control */
2164                 case 0x14: /* Softint set, WO */
2165                 case 0x15: /* Softint clear, WO */
2166                 case 0x16: /* Softint write */
2167 #endif
2168                 default:
2169                     goto illegal_insn;
2170                 }
2171 #if !defined(CONFIG_USER_ONLY)
2172             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2173 #ifndef TARGET_SPARC64
2174                 if (!supervisor(dc))
2175                     goto priv_insn;
2176                 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2177 #else
2178                 CHECK_IU_FEATURE(dc, HYPV);
2179                 if (!hypervisor(dc))
2180                     goto priv_insn;
2181                 rs1 = GET_FIELD(insn, 13, 17);
2182                 switch (rs1) {
2183                 case 0: // hpstate
2184                     // gen_op_rdhpstate();
2185                     break;
2186                 case 1: // htstate
2187                     // gen_op_rdhtstate();
2188                     break;
2189                 case 3: // hintp
2190                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2191                                    offsetof(CPUSPARCState, hintp));
2192                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2193                     break;
2194                 case 5: // htba
2195                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2196                                    offsetof(CPUSPARCState, htba));
2197                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2198                     break;
2199                 case 6: // hver
2200                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2201                                    offsetof(CPUSPARCState, hver));
2202                     tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2203                     break;
2204                 case 31: // hstick_cmpr
2205                     tcg_gen_ld_tl(cpu_dst, cpu_env,
2206                                   offsetof(CPUSPARCState, hstick_cmpr));
2207                     break;
2208                 default:
2209                     goto illegal_insn;
2210                 }
2211 #endif
2212                 gen_movl_TN_reg(rd, cpu_dst);
2213                 break;
2214             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2215                 if (!supervisor(dc))
2216                     goto priv_insn;
2217 #ifdef TARGET_SPARC64
2218                 rs1 = GET_FIELD(insn, 13, 17);
2219                 switch (rs1) {
2220                 case 0: // tpc
2221                     {
2222                         TCGv r_tsptr;
2223
2224                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2225                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2226                                        offsetof(CPUState, tsptr));
2227                         tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2228                                       offsetof(trap_state, tpc));
2229                         tcg_temp_free(r_tsptr);
2230                     }
2231                     break;
2232                 case 1: // tnpc
2233                     {
2234                         TCGv r_tsptr;
2235
2236                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2237                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2238                                        offsetof(CPUState, tsptr));
2239                         tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2240                                       offsetof(trap_state, tnpc));
2241                         tcg_temp_free(r_tsptr);
2242                     }
2243                     break;
2244                 case 2: // tstate
2245                     {
2246                         TCGv r_tsptr;
2247
2248                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2249                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2250                                        offsetof(CPUState, tsptr));
2251                         tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2252                                       offsetof(trap_state, tstate));
2253                         tcg_temp_free(r_tsptr);
2254                     }
2255                     break;
2256                 case 3: // tt
2257                     {
2258                         TCGv r_tsptr;
2259
2260                         r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2261                         tcg_gen_ld_ptr(r_tsptr, cpu_env,
2262                                        offsetof(CPUState, tsptr));
2263                         tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
2264                                        offsetof(trap_state, tt));
2265                         tcg_temp_free(r_tsptr);
2266                     }
2267                     break;
2268                 case 4: // tick
2269                     {
2270                         TCGv r_tickptr;
2271
2272                         r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2273                         tcg_gen_ld_ptr(r_tickptr, cpu_env,
2274                                        offsetof(CPUState, tick));
2275                         tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
2276                                            r_tickptr);
2277                         gen_movl_TN_reg(rd, cpu_tmp0);
2278                         tcg_temp_free(r_tickptr);
2279                     }
2280                     break;
2281                 case 5: // tba
2282                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2283                                   offsetof(CPUSPARCState, tbr));
2284                     break;
2285                 case 6: // pstate
2286                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2287                                    offsetof(CPUSPARCState, pstate));
2288                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2289                     break;
2290                 case 7: // tl
2291                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2292                                    offsetof(CPUSPARCState, tl));
2293                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2294                     break;
2295                 case 8: // pil
2296                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2297                                    offsetof(CPUSPARCState, psrpil));
2298                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2299                     break;
2300                 case 9: // cwp
2301                     tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
2302                     break;
2303                 case 10: // cansave
2304                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2305                                    offsetof(CPUSPARCState, cansave));
2306                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2307                     break;
2308                 case 11: // canrestore
2309                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2310                                    offsetof(CPUSPARCState, canrestore));
2311                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2312                     break;
2313                 case 12: // cleanwin
2314                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2315                                    offsetof(CPUSPARCState, cleanwin));
2316                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2317                     break;
2318                 case 13: // otherwin
2319                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2320                                    offsetof(CPUSPARCState, otherwin));
2321                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2322                     break;
2323                 case 14: // wstate
2324                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2325                                    offsetof(CPUSPARCState, wstate));
2326                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2327                     break;
2328                 case 16: // UA2005 gl
2329                     CHECK_IU_FEATURE(dc, GL);
2330                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2331                                    offsetof(CPUSPARCState, gl));
2332                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2333                     break;
2334                 case 26: // UA2005 strand status
2335                     CHECK_IU_FEATURE(dc, HYPV);
2336                     if (!hypervisor(dc))
2337                         goto priv_insn;
2338                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2339                                    offsetof(CPUSPARCState, ssr));
2340                     tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2341                     break;
2342                 case 31: // ver
2343                     tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2344                                   offsetof(CPUSPARCState, version));
2345                     break;
2346                 case 15: // fq
2347                 default:
2348                     goto illegal_insn;
2349                 }
2350 #else
2351                 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2352                                offsetof(CPUSPARCState, wim));
2353                 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2354 #endif
2355                 gen_movl_TN_reg(rd, cpu_tmp0);
2356                 break;
2357             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2358 #ifdef TARGET_SPARC64
2359                 save_state(dc, cpu_cond);
2360                 tcg_gen_helper_0_0(helper_flushw);
2361 #else
2362                 if (!supervisor(dc))
2363                     goto priv_insn;
2364                 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr));
2365                 gen_movl_TN_reg(rd, cpu_tmp0);
2366 #endif
2367                 break;
2368 #endif
2369             } else if (xop == 0x34) {   /* FPU Operations */
2370                 if (gen_trap_ifnofpu(dc, cpu_cond))
2371                     goto jmp_insn;
2372                 gen_op_clear_ieee_excp_and_FTT();
2373                 rs1 = GET_FIELD(insn, 13, 17);
2374                 rs2 = GET_FIELD(insn, 27, 31);
2375                 xop = GET_FIELD(insn, 18, 26);
2376                 switch (xop) {
2377                     case 0x1: /* fmovs */
2378                         gen_op_load_fpr_FT0(rs2);
2379                         gen_op_store_FT0_fpr(rd);
2380                         break;
2381                     case 0x5: /* fnegs */
2382                         gen_op_load_fpr_FT1(rs2);
2383                         tcg_gen_helper_0_0(helper_fnegs);
2384                         gen_op_store_FT0_fpr(rd);
2385                         break;
2386                     case 0x9: /* fabss */
2387                         gen_op_load_fpr_FT1(rs2);
2388                         tcg_gen_helper_0_0(helper_fabss);
2389                         gen_op_store_FT0_fpr(rd);
2390                         break;
2391                     case 0x29: /* fsqrts */
2392                         CHECK_FPU_FEATURE(dc, FSQRT);
2393                         gen_op_load_fpr_FT1(rs2);
2394                         gen_clear_float_exceptions();
2395                         tcg_gen_helper_0_0(helper_fsqrts);
2396                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2397                         gen_op_store_FT0_fpr(rd);
2398                         break;
2399                     case 0x2a: /* fsqrtd */
2400                         CHECK_FPU_FEATURE(dc, FSQRT);
2401                         gen_op_load_fpr_DT1(DFPREG(rs2));
2402                         gen_clear_float_exceptions();
2403                         tcg_gen_helper_0_0(helper_fsqrtd);
2404                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2405                         gen_op_store_DT0_fpr(DFPREG(rd));
2406                         break;
2407                     case 0x2b: /* fsqrtq */
2408                         CHECK_FPU_FEATURE(dc, FLOAT128);
2409                         gen_op_load_fpr_QT1(QFPREG(rs2));
2410                         gen_clear_float_exceptions();
2411                         tcg_gen_helper_0_0(helper_fsqrtq);
2412                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2413                         gen_op_store_QT0_fpr(QFPREG(rd));
2414                         break;
2415                     case 0x41:
2416                         gen_op_load_fpr_FT0(rs1);
2417                         gen_op_load_fpr_FT1(rs2);
2418                         gen_clear_float_exceptions();
2419                         tcg_gen_helper_0_0(helper_fadds);
2420                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2421                         gen_op_store_FT0_fpr(rd);
2422                         break;
2423                     case 0x42:
2424                         gen_op_load_fpr_DT0(DFPREG(rs1));
2425                         gen_op_load_fpr_DT1(DFPREG(rs2));
2426                         gen_clear_float_exceptions();
2427                         tcg_gen_helper_0_0(helper_faddd);
2428                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2429                         gen_op_store_DT0_fpr(DFPREG(rd));
2430                         break;
2431                     case 0x43: /* faddq */
2432                         CHECK_FPU_FEATURE(dc, FLOAT128);
2433                         gen_op_load_fpr_QT0(QFPREG(rs1));
2434                         gen_op_load_fpr_QT1(QFPREG(rs2));
2435                         gen_clear_float_exceptions();
2436                         tcg_gen_helper_0_0(helper_faddq);
2437                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2438                         gen_op_store_QT0_fpr(QFPREG(rd));
2439                         break;
2440                     case 0x45:
2441                         gen_op_load_fpr_FT0(rs1);
2442                         gen_op_load_fpr_FT1(rs2);
2443                         gen_clear_float_exceptions();
2444                         tcg_gen_helper_0_0(helper_fsubs);
2445                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2446                         gen_op_store_FT0_fpr(rd);
2447                         break;
2448                     case 0x46:
2449                         gen_op_load_fpr_DT0(DFPREG(rs1));
2450                         gen_op_load_fpr_DT1(DFPREG(rs2));
2451                         gen_clear_float_exceptions();
2452                         tcg_gen_helper_0_0(helper_fsubd);
2453                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2454                         gen_op_store_DT0_fpr(DFPREG(rd));
2455                         break;
2456                     case 0x47: /* fsubq */
2457                         CHECK_FPU_FEATURE(dc, FLOAT128);
2458                         gen_op_load_fpr_QT0(QFPREG(rs1));
2459                         gen_op_load_fpr_QT1(QFPREG(rs2));
2460                         gen_clear_float_exceptions();
2461                         tcg_gen_helper_0_0(helper_fsubq);
2462                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2463                         gen_op_store_QT0_fpr(QFPREG(rd));
2464                         break;
2465                     case 0x49: /* fmuls */
2466                         CHECK_FPU_FEATURE(dc, FMUL);
2467                         gen_op_load_fpr_FT0(rs1);
2468                         gen_op_load_fpr_FT1(rs2);
2469                         gen_clear_float_exceptions();
2470                         tcg_gen_helper_0_0(helper_fmuls);
2471                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2472                         gen_op_store_FT0_fpr(rd);
2473                         break;
2474                     case 0x4a: /* fmuld */
2475                         CHECK_FPU_FEATURE(dc, FMUL);
2476                         gen_op_load_fpr_DT0(DFPREG(rs1));
2477                         gen_op_load_fpr_DT1(DFPREG(rs2));
2478                         gen_clear_float_exceptions();
2479                         tcg_gen_helper_0_0(helper_fmuld);
2480                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2481                         gen_op_store_DT0_fpr(DFPREG(rd));
2482                         break;
2483                     case 0x4b: /* fmulq */
2484                         CHECK_FPU_FEATURE(dc, FLOAT128);
2485                         CHECK_FPU_FEATURE(dc, FMUL);
2486                         gen_op_load_fpr_QT0(QFPREG(rs1));
2487                         gen_op_load_fpr_QT1(QFPREG(rs2));
2488                         gen_clear_float_exceptions();
2489                         tcg_gen_helper_0_0(helper_fmulq);
2490                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2491                         gen_op_store_QT0_fpr(QFPREG(rd));
2492                         break;
2493                     case 0x4d:
2494                         gen_op_load_fpr_FT0(rs1);
2495                         gen_op_load_fpr_FT1(rs2);
2496                         gen_clear_float_exceptions();
2497                         tcg_gen_helper_0_0(helper_fdivs);
2498                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2499                         gen_op_store_FT0_fpr(rd);
2500                         break;
2501                     case 0x4e:
2502                         gen_op_load_fpr_DT0(DFPREG(rs1));
2503                         gen_op_load_fpr_DT1(DFPREG(rs2));
2504                         gen_clear_float_exceptions();
2505                         tcg_gen_helper_0_0(helper_fdivd);
2506                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2507                         gen_op_store_DT0_fpr(DFPREG(rd));
2508                         break;
2509                     case 0x4f: /* fdivq */
2510                         CHECK_FPU_FEATURE(dc, FLOAT128);
2511                         gen_op_load_fpr_QT0(QFPREG(rs1));
2512                         gen_op_load_fpr_QT1(QFPREG(rs2));
2513                         gen_clear_float_exceptions();
2514                         tcg_gen_helper_0_0(helper_fdivq);
2515                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2516                         gen_op_store_QT0_fpr(QFPREG(rd));
2517                         break;
2518                     case 0x69:
2519                         CHECK_FPU_FEATURE(dc, FSMULD);
2520                         gen_op_load_fpr_FT0(rs1);
2521                         gen_op_load_fpr_FT1(rs2);
2522                         gen_clear_float_exceptions();
2523                         tcg_gen_helper_0_0(helper_fsmuld);
2524                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2525                         gen_op_store_DT0_fpr(DFPREG(rd));
2526                         break;
2527                     case 0x6e: /* fdmulq */
2528                         CHECK_FPU_FEATURE(dc, FLOAT128);
2529                         gen_op_load_fpr_DT0(DFPREG(rs1));
2530                         gen_op_load_fpr_DT1(DFPREG(rs2));
2531                         gen_clear_float_exceptions();
2532                         tcg_gen_helper_0_0(helper_fdmulq);
2533                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2534                         gen_op_store_QT0_fpr(QFPREG(rd));
2535                         break;
2536                     case 0xc4:
2537                         gen_op_load_fpr_FT1(rs2);
2538                         gen_clear_float_exceptions();
2539                         tcg_gen_helper_0_0(helper_fitos);
2540                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2541                         gen_op_store_FT0_fpr(rd);
2542                         break;
2543                     case 0xc6:
2544                         gen_op_load_fpr_DT1(DFPREG(rs2));
2545                         gen_clear_float_exceptions();
2546                         tcg_gen_helper_0_0(helper_fdtos);
2547                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2548                         gen_op_store_FT0_fpr(rd);
2549                         break;
2550                     case 0xc7: /* fqtos */
2551                         CHECK_FPU_FEATURE(dc, FLOAT128);
2552                         gen_op_load_fpr_QT1(QFPREG(rs2));
2553                         gen_clear_float_exceptions();
2554                         tcg_gen_helper_0_0(helper_fqtos);
2555                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2556                         gen_op_store_FT0_fpr(rd);
2557                         break;
2558                     case 0xc8:
2559                         gen_op_load_fpr_FT1(rs2);
2560                         tcg_gen_helper_0_0(helper_fitod);
2561                         gen_op_store_DT0_fpr(DFPREG(rd));
2562                         break;
2563                     case 0xc9:
2564                         gen_op_load_fpr_FT1(rs2);
2565                         tcg_gen_helper_0_0(helper_fstod);
2566                         gen_op_store_DT0_fpr(DFPREG(rd));
2567                         break;
2568                     case 0xcb: /* fqtod */
2569                         CHECK_FPU_FEATURE(dc, FLOAT128);
2570                         gen_op_load_fpr_QT1(QFPREG(rs2));
2571                         gen_clear_float_exceptions();
2572                         tcg_gen_helper_0_0(helper_fqtod);
2573                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2574                         gen_op_store_DT0_fpr(DFPREG(rd));
2575                         break;
2576                     case 0xcc: /* fitoq */
2577                         CHECK_FPU_FEATURE(dc, FLOAT128);
2578                         gen_op_load_fpr_FT1(rs2);
2579                         tcg_gen_helper_0_0(helper_fitoq);
2580                         gen_op_store_QT0_fpr(QFPREG(rd));
2581                         break;
2582                     case 0xcd: /* fstoq */
2583                         CHECK_FPU_FEATURE(dc, FLOAT128);
2584                         gen_op_load_fpr_FT1(rs2);
2585                         tcg_gen_helper_0_0(helper_fstoq);
2586                         gen_op_store_QT0_fpr(QFPREG(rd));
2587                         break;
2588                     case 0xce: /* fdtoq */
2589                         CHECK_FPU_FEATURE(dc, FLOAT128);
2590                         gen_op_load_fpr_DT1(DFPREG(rs2));
2591                         tcg_gen_helper_0_0(helper_fdtoq);
2592                         gen_op_store_QT0_fpr(QFPREG(rd));
2593                         break;
2594                     case 0xd1:
2595                         gen_op_load_fpr_FT1(rs2);
2596                         gen_clear_float_exceptions();
2597                         tcg_gen_helper_0_0(helper_fstoi);
2598                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2599                         gen_op_store_FT0_fpr(rd);
2600                         break;
2601                     case 0xd2:
2602                         gen_op_load_fpr_DT1(DFPREG(rs2));
2603                         gen_clear_float_exceptions();
2604                         tcg_gen_helper_0_0(helper_fdtoi);
2605                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2606                         gen_op_store_FT0_fpr(rd);
2607                         break;
2608                     case 0xd3: /* fqtoi */
2609                         CHECK_FPU_FEATURE(dc, FLOAT128);
2610                         gen_op_load_fpr_QT1(QFPREG(rs2));
2611                         gen_clear_float_exceptions();
2612                         tcg_gen_helper_0_0(helper_fqtoi);
2613                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2614                         gen_op_store_FT0_fpr(rd);
2615                         break;
2616 #ifdef TARGET_SPARC64
2617                     case 0x2: /* V9 fmovd */
2618                         gen_op_load_fpr_DT0(DFPREG(rs2));
2619                         gen_op_store_DT0_fpr(DFPREG(rd));
2620                         break;
2621                     case 0x3: /* V9 fmovq */
2622                         CHECK_FPU_FEATURE(dc, FLOAT128);
2623                         gen_op_load_fpr_QT0(QFPREG(rs2));
2624                         gen_op_store_QT0_fpr(QFPREG(rd));
2625                         break;
2626                     case 0x6: /* V9 fnegd */
2627                         gen_op_load_fpr_DT1(DFPREG(rs2));
2628                         tcg_gen_helper_0_0(helper_fnegd);
2629                         gen_op_store_DT0_fpr(DFPREG(rd));
2630                         break;
2631                     case 0x7: /* V9 fnegq */
2632                         CHECK_FPU_FEATURE(dc, FLOAT128);
2633                         gen_op_load_fpr_QT1(QFPREG(rs2));
2634                         tcg_gen_helper_0_0(helper_fnegq);
2635                         gen_op_store_QT0_fpr(QFPREG(rd));
2636                         break;
2637                     case 0xa: /* V9 fabsd */
2638                         gen_op_load_fpr_DT1(DFPREG(rs2));
2639                         tcg_gen_helper_0_0(helper_fabsd);
2640                         gen_op_store_DT0_fpr(DFPREG(rd));
2641                         break;
2642                     case 0xb: /* V9 fabsq */
2643                         CHECK_FPU_FEATURE(dc, FLOAT128);
2644                         gen_op_load_fpr_QT1(QFPREG(rs2));
2645                         tcg_gen_helper_0_0(helper_fabsq);
2646                         gen_op_store_QT0_fpr(QFPREG(rd));
2647                         break;
2648                     case 0x81: /* V9 fstox */
2649                         gen_op_load_fpr_FT1(rs2);
2650                         gen_clear_float_exceptions();
2651                         tcg_gen_helper_0_0(helper_fstox);
2652                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2653                         gen_op_store_DT0_fpr(DFPREG(rd));
2654                         break;
2655                     case 0x82: /* V9 fdtox */
2656                         gen_op_load_fpr_DT1(DFPREG(rs2));
2657                         gen_clear_float_exceptions();
2658                         tcg_gen_helper_0_0(helper_fdtox);
2659                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2660                         gen_op_store_DT0_fpr(DFPREG(rd));
2661                         break;
2662                     case 0x83: /* V9 fqtox */
2663                         CHECK_FPU_FEATURE(dc, FLOAT128);
2664                         gen_op_load_fpr_QT1(QFPREG(rs2));
2665                         gen_clear_float_exceptions();
2666                         tcg_gen_helper_0_0(helper_fqtox);
2667                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2668                         gen_op_store_DT0_fpr(DFPREG(rd));
2669                         break;
2670                     case 0x84: /* V9 fxtos */
2671                         gen_op_load_fpr_DT1(DFPREG(rs2));
2672                         gen_clear_float_exceptions();
2673                         tcg_gen_helper_0_0(helper_fxtos);
2674                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2675                         gen_op_store_FT0_fpr(rd);
2676                         break;
2677                     case 0x88: /* V9 fxtod */
2678                         gen_op_load_fpr_DT1(DFPREG(rs2));
2679                         gen_clear_float_exceptions();
2680                         tcg_gen_helper_0_0(helper_fxtod);
2681                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2682                         gen_op_store_DT0_fpr(DFPREG(rd));
2683                         break;
2684                     case 0x8c: /* V9 fxtoq */
2685                         CHECK_FPU_FEATURE(dc, FLOAT128);
2686                         gen_op_load_fpr_DT1(DFPREG(rs2));
2687                         gen_clear_float_exceptions();
2688                         tcg_gen_helper_0_0(helper_fxtoq);
2689                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2690                         gen_op_store_QT0_fpr(QFPREG(rd));
2691                         break;
2692 #endif
2693                     default:
2694                         goto illegal_insn;
2695                 }
2696             } else if (xop == 0x35) {   /* FPU Operations */
2697 #ifdef TARGET_SPARC64
2698                 int cond;
2699 #endif
2700                 if (gen_trap_ifnofpu(dc, cpu_cond))
2701                     goto jmp_insn;
2702                 gen_op_clear_ieee_excp_and_FTT();
2703                 rs1 = GET_FIELD(insn, 13, 17);
2704                 rs2 = GET_FIELD(insn, 27, 31);
2705                 xop = GET_FIELD(insn, 18, 26);
2706 #ifdef TARGET_SPARC64
2707                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2708                     int l1;
2709
2710                     l1 = gen_new_label();
2711                     cond = GET_FIELD_SP(insn, 14, 17);
2712                     cpu_src1 = get_src1(insn, cpu_src1);
2713                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2714                                        0, l1);
2715                     gen_op_load_fpr_FT0(rs2);
2716                     gen_op_store_FT0_fpr(rd);
2717                     gen_set_label(l1);
2718                     break;
2719                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2720                     int l1;
2721
2722                     l1 = gen_new_label();
2723                     cond = GET_FIELD_SP(insn, 14, 17);
2724                     cpu_src1 = get_src1(insn, cpu_src1);
2725                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2726                                        0, l1);
2727                     gen_op_load_fpr_DT0(DFPREG(rs2));
2728                     gen_op_store_DT0_fpr(DFPREG(rd));
2729                     gen_set_label(l1);
2730                     break;
2731                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2732                     int l1;
2733
2734                     CHECK_FPU_FEATURE(dc, FLOAT128);
2735                     l1 = gen_new_label();
2736                     cond = GET_FIELD_SP(insn, 14, 17);
2737                     cpu_src1 = get_src1(insn, cpu_src1);
2738                     tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2739                                        0, l1);
2740                     gen_op_load_fpr_QT0(QFPREG(rs2));
2741                     gen_op_store_QT0_fpr(QFPREG(rd));
2742                     gen_set_label(l1);
2743                     break;
2744                 }
2745 #endif
2746                 switch (xop) {
2747 #ifdef TARGET_SPARC64
2748 #define FMOVCC(size_FDQ, fcc)                                           \
2749                     {                                                   \
2750                         TCGv r_cond;                                    \
2751                         int l1;                                         \
2752                                                                         \
2753                         l1 = gen_new_label();                           \
2754                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2755                         cond = GET_FIELD_SP(insn, 14, 17);              \
2756                         gen_fcond(r_cond, fcc, cond);                   \
2757                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2758                                            0, l1);                      \
2759                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2760                             (glue(size_FDQ, FPREG(rs2)));               \
2761                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2762                             (glue(size_FDQ, FPREG(rd)));                \
2763                         gen_set_label(l1);                              \
2764                         tcg_temp_free(r_cond);                          \
2765                     }
2766                     case 0x001: /* V9 fmovscc %fcc0 */
2767                         FMOVCC(F, 0);
2768                         break;
2769                     case 0x002: /* V9 fmovdcc %fcc0 */
2770                         FMOVCC(D, 0);
2771                         break;
2772                     case 0x003: /* V9 fmovqcc %fcc0 */
2773                         CHECK_FPU_FEATURE(dc, FLOAT128);
2774                         FMOVCC(Q, 0);
2775                         break;
2776                     case 0x041: /* V9 fmovscc %fcc1 */
2777                         FMOVCC(F, 1);
2778                         break;
2779                     case 0x042: /* V9 fmovdcc %fcc1 */
2780                         FMOVCC(D, 1);
2781                         break;
2782                     case 0x043: /* V9 fmovqcc %fcc1 */
2783                         CHECK_FPU_FEATURE(dc, FLOAT128);
2784                         FMOVCC(Q, 1);
2785                         break;
2786                     case 0x081: /* V9 fmovscc %fcc2 */
2787                         FMOVCC(F, 2);
2788                         break;
2789                     case 0x082: /* V9 fmovdcc %fcc2 */
2790                         FMOVCC(D, 2);
2791                         break;
2792                     case 0x083: /* V9 fmovqcc %fcc2 */
2793                         CHECK_FPU_FEATURE(dc, FLOAT128);
2794                         FMOVCC(Q, 2);
2795                         break;
2796                     case 0x0c1: /* V9 fmovscc %fcc3 */
2797                         FMOVCC(F, 3);
2798                         break;
2799                     case 0x0c2: /* V9 fmovdcc %fcc3 */
2800                         FMOVCC(D, 3);
2801                         break;
2802                     case 0x0c3: /* V9 fmovqcc %fcc3 */
2803                         CHECK_FPU_FEATURE(dc, FLOAT128);
2804                         FMOVCC(Q, 3);
2805                         break;
2806 #undef FMOVCC
2807 #define FMOVCC(size_FDQ, icc)                                           \
2808                     {                                                   \
2809                         TCGv r_cond;                                    \
2810                         int l1;                                         \
2811                                                                         \
2812                         l1 = gen_new_label();                           \
2813                         r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2814                         cond = GET_FIELD_SP(insn, 14, 17);              \
2815                         gen_cond(r_cond, icc, cond);                    \
2816                         tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2817                                            0, l1);                      \
2818                         glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2819                             (glue(size_FDQ, FPREG(rs2)));               \
2820                         glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2821                             (glue(size_FDQ, FPREG(rd)));                \
2822                         gen_set_label(l1);                              \
2823                         tcg_temp_free(r_cond);                          \
2824                     }
2825
2826                     case 0x101: /* V9 fmovscc %icc */
2827                         FMOVCC(F, 0);
2828                         break;
2829                     case 0x102: /* V9 fmovdcc %icc */
2830                         FMOVCC(D, 0);
2831                     case 0x103: /* V9 fmovqcc %icc */
2832                         CHECK_FPU_FEATURE(dc, FLOAT128);
2833                         FMOVCC(Q, 0);
2834                         break;
2835                     case 0x181: /* V9 fmovscc %xcc */
2836                         FMOVCC(F, 1);
2837                         break;
2838                     case 0x182: /* V9 fmovdcc %xcc */
2839                         FMOVCC(D, 1);
2840                         break;
2841                     case 0x183: /* V9 fmovqcc %xcc */
2842                         CHECK_FPU_FEATURE(dc, FLOAT128);
2843                         FMOVCC(Q, 1);
2844                         break;
2845 #undef FMOVCC
2846 #endif
2847                     case 0x51: /* fcmps, V9 %fcc */
2848                         gen_op_load_fpr_FT0(rs1);
2849                         gen_op_load_fpr_FT1(rs2);
2850                         gen_op_fcmps(rd & 3);
2851                         break;
2852                     case 0x52: /* fcmpd, V9 %fcc */
2853                         gen_op_load_fpr_DT0(DFPREG(rs1));
2854                         gen_op_load_fpr_DT1(DFPREG(rs2));
2855                         gen_op_fcmpd(rd & 3);
2856                         break;
2857                     case 0x53: /* fcmpq, V9 %fcc */
2858                         CHECK_FPU_FEATURE(dc, FLOAT128);
2859                         gen_op_load_fpr_QT0(QFPREG(rs1));
2860                         gen_op_load_fpr_QT1(QFPREG(rs2));
2861                         gen_op_fcmpq(rd & 3);
2862                         break;
2863                     case 0x55: /* fcmpes, V9 %fcc */
2864                         gen_op_load_fpr_FT0(rs1);
2865                         gen_op_load_fpr_FT1(rs2);
2866                         gen_op_fcmpes(rd & 3);
2867                         break;
2868                     case 0x56: /* fcmped, V9 %fcc */
2869                         gen_op_load_fpr_DT0(DFPREG(rs1));
2870                         gen_op_load_fpr_DT1(DFPREG(rs2));
2871                         gen_op_fcmped(rd & 3);
2872                         break;
2873                     case 0x57: /* fcmpeq, V9 %fcc */
2874                         CHECK_FPU_FEATURE(dc, FLOAT128);
2875                         gen_op_load_fpr_QT0(QFPREG(rs1));
2876                         gen_op_load_fpr_QT1(QFPREG(rs2));
2877                         gen_op_fcmpeq(rd & 3);
2878                         break;
2879                     default:
2880                         goto illegal_insn;
2881                 }
2882             } else if (xop == 0x2) {
2883                 // clr/mov shortcut
2884
2885                 rs1 = GET_FIELD(insn, 13, 17);
2886                 if (rs1 == 0) {
2887                     // or %g0, x, y -> mov T0, x; mov y, T0
2888                     if (IS_IMM) {       /* immediate */
2889                         TCGv r_const;
2890
2891                         rs2 = GET_FIELDs(insn, 19, 31);
2892                         r_const = tcg_const_tl((int)rs2);
2893                         gen_movl_TN_reg(rd, r_const);
2894                         tcg_temp_free(r_const);
2895                     } else {            /* register */
2896                         rs2 = GET_FIELD(insn, 27, 31);
2897                         gen_movl_reg_TN(rs2, cpu_dst);
2898                         gen_movl_TN_reg(rd, cpu_dst);
2899                     }
2900                 } else {
2901                     cpu_src1 = get_src1(insn, cpu_src1);
2902                     if (IS_IMM) {       /* immediate */
2903                         rs2 = GET_FIELDs(insn, 19, 31);
2904                         tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2905                         gen_movl_TN_reg(rd, cpu_dst);
2906                     } else {            /* register */
2907                         // or x, %g0, y -> mov T1, x; mov y, T1
2908                         rs2 = GET_FIELD(insn, 27, 31);
2909                         if (rs2 != 0) {
2910                             gen_movl_reg_TN(rs2, cpu_src2);
2911                             tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2912                             gen_movl_TN_reg(rd, cpu_dst);
2913                         } else
2914                             gen_movl_TN_reg(rd, cpu_src1);
2915                     }
2916                 }
2917 #ifdef TARGET_SPARC64
2918             } else if (xop == 0x25) { /* sll, V9 sllx */
2919                 cpu_src1 = get_src1(insn, cpu_src1);
2920                 if (IS_IMM) {   /* immediate */
2921                     rs2 = GET_FIELDs(insn, 20, 31);
2922                     if (insn & (1 << 12)) {
2923                         tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2924                     } else {
2925                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2926                         tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2927                     }
2928                 } else {                /* register */
2929                     rs2 = GET_FIELD(insn, 27, 31);
2930                     gen_movl_reg_TN(rs2, cpu_src2);
2931                     if (insn & (1 << 12)) {
2932                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2933                         tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2934                     } else {
2935                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2936                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2937                         tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2938                     }
2939                 }
2940                 gen_movl_TN_reg(rd, cpu_dst);
2941             } else if (xop == 0x26) { /* srl, V9 srlx */
2942                 cpu_src1 = get_src1(insn, cpu_src1);
2943                 if (IS_IMM) {   /* immediate */
2944                     rs2 = GET_FIELDs(insn, 20, 31);
2945                     if (insn & (1 << 12)) {
2946                         tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2947                     } else {
2948                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2949                         tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2950                     }
2951                 } else {                /* register */
2952                     rs2 = GET_FIELD(insn, 27, 31);
2953                     gen_movl_reg_TN(rs2, cpu_src2);
2954                     if (insn & (1 << 12)) {
2955                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2956                         tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2957                     } else {
2958                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2959                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2960                         tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2961                     }
2962                 }
2963                 gen_movl_TN_reg(rd, cpu_dst);
2964             } else if (xop == 0x27) { /* sra, V9 srax */
2965                 cpu_src1 = get_src1(insn, cpu_src1);
2966                 if (IS_IMM) {   /* immediate */
2967                     rs2 = GET_FIELDs(insn, 20, 31);
2968                     if (insn & (1 << 12)) {
2969                         tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2970                     } else {
2971                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2972                         tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2973                         tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2974                     }
2975                 } else {                /* register */
2976                     rs2 = GET_FIELD(insn, 27, 31);
2977                     gen_movl_reg_TN(rs2, cpu_src2);
2978                     if (insn & (1 << 12)) {
2979                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2980                         tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2981                     } else {
2982                         tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2983                         tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2984                         tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2985                     }
2986                 }
2987                 gen_movl_TN_reg(rd, cpu_dst);
2988 #endif
2989             } else if (xop < 0x36) {
2990                 cpu_src1 = get_src1(insn, cpu_src1);
2991                 cpu_src2 = get_src2(insn, cpu_src2);
2992                 if (xop < 0x20) {
2993                     switch (xop & ~0x10) {
2994                     case 0x0:
2995                         if (xop & 0x10)
2996                             gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2997                         else
2998                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2999                         break;
3000                     case 0x1:
3001                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
3002                         if (xop & 0x10)
3003                             gen_op_logic_cc(cpu_dst);
3004                         break;
3005                     case 0x2:
3006                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3007                         if (xop & 0x10)
3008                             gen_op_logic_cc(cpu_dst);
3009                         break;
3010                     case 0x3:
3011                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3012                         if (xop & 0x10)
3013                             gen_op_logic_cc(cpu_dst);
3014                         break;
3015                     case 0x4:
3016                         if (xop & 0x10)
3017                             gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3018                         else
3019                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3020                         break;
3021                     case 0x5:
3022                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3023                         tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3024                         if (xop & 0x10)
3025                             gen_op_logic_cc(cpu_dst);
3026                         break;
3027                     case 0x6:
3028                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3029                         tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3030                         if (xop & 0x10)
3031                             gen_op_logic_cc(cpu_dst);
3032                         break;
3033                     case 0x7:
3034                         tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3035                         tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3036                         if (xop & 0x10)
3037                             gen_op_logic_cc(cpu_dst);
3038                         break;
3039                     case 0x8:
3040                         if (xop & 0x10)
3041                             gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3042                         else {
3043                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3044                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3045                             tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3046                         }
3047                         break;
3048 #ifdef TARGET_SPARC64
3049                     case 0x9: /* V9 mulx */
3050                         tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3051                         break;
3052 #endif
3053                     case 0xa:
3054                         CHECK_IU_FEATURE(dc, MUL);
3055                         gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3056                         if (xop & 0x10)
3057                             gen_op_logic_cc(cpu_dst);
3058                         break;
3059                     case 0xb:
3060                         CHECK_IU_FEATURE(dc, MUL);
3061                         gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3062                         if (xop & 0x10)
3063                             gen_op_logic_cc(cpu_dst);
3064                         break;
3065                     case 0xc:
3066                         if (xop & 0x10)
3067                             gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3068                         else {
3069                             gen_mov_reg_C(cpu_tmp0, cpu_psr);
3070                             tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3071                             tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3072                         }
3073                         break;
3074 #ifdef TARGET_SPARC64
3075                     case 0xd: /* V9 udivx */
3076                         tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3077                         tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3078                         gen_trap_ifdivzero_tl(cpu_cc_src2);
3079                         tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3080                         break;
3081 #endif
3082                     case 0xe:
3083                         CHECK_IU_FEATURE(dc, DIV);
3084                         tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3085                                            cpu_src2);
3086                         if (xop & 0x10)
3087                             gen_op_div_cc(cpu_dst);
3088                         break;
3089                     case 0xf:
3090                         CHECK_IU_FEATURE(dc, DIV);
3091                         tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3092                                            cpu_src2);
3093                         if (xop & 0x10)
3094                             gen_op_div_cc(cpu_dst);
3095                         break;
3096                     default:
3097                         goto illegal_insn;
3098                     }
3099                     gen_movl_TN_reg(rd, cpu_dst);
3100                 } else {
3101                     switch (xop) {
3102                     case 0x20: /* taddcc */
3103                         gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3104                         gen_movl_TN_reg(rd, cpu_dst);
3105                         break;
3106                     case 0x21: /* tsubcc */
3107                         gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3108                         gen_movl_TN_reg(rd, cpu_dst);
3109                         break;
3110                     case 0x22: /* taddcctv */
3111                         save_state(dc, cpu_cond);
3112                         gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3113                         gen_movl_TN_reg(rd, cpu_dst);
3114                         break;
3115                     case 0x23: /* tsubcctv */
3116                         save_state(dc, cpu_cond);
3117                         gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3118                         gen_movl_TN_reg(rd, cpu_dst);
3119                         break;
3120                     case 0x24: /* mulscc */
3121                         gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3122                         gen_movl_TN_reg(rd, cpu_dst);
3123                         break;
3124 #ifndef TARGET_SPARC64
3125                     case 0x25:  /* sll */
3126                         if (IS_IMM) { /* immediate */
3127                             rs2 = GET_FIELDs(insn, 20, 31);
3128                             tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3129                         } else { /* register */
3130                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3131                             tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3132                         }
3133                         gen_movl_TN_reg(rd, cpu_dst);
3134                         break;
3135                     case 0x26:  /* srl */
3136                         if (IS_IMM) { /* immediate */
3137                             rs2 = GET_FIELDs(insn, 20, 31);
3138                             tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3139                         } else { /* register */
3140                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3141                             tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3142                         }
3143                         gen_movl_TN_reg(rd, cpu_dst);
3144                         break;
3145                     case 0x27:  /* sra */
3146                         if (IS_IMM) { /* immediate */
3147                             rs2 = GET_FIELDs(insn, 20, 31);
3148                             tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3149                         } else { /* register */
3150                             tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3151                             tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3152                         }
3153                         gen_movl_TN_reg(rd, cpu_dst);
3154                         break;
3155 #endif
3156                     case 0x30:
3157                         {
3158                             switch(rd) {
3159                             case 0: /* wry */
3160                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3161                                 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3162                                               offsetof(CPUSPARCState, y));
3163                                 break;
3164 #ifndef TARGET_SPARC64
3165                             case 0x01 ... 0x0f: /* undefined in the
3166                                                    SPARCv8 manual, nop
3167                                                    on the microSPARC
3168                                                    II */
3169                             case 0x10 ... 0x1f: /* implementation-dependent
3170                                                    in the SPARCv8
3171                                                    manual, nop on the
3172                                                    microSPARC II */
3173                                 break;
3174 #else
3175                             case 0x2: /* V9 wrccr */
3176                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3177                                 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3178                                 break;
3179                             case 0x3: /* V9 wrasi */
3180                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3181                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3182                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3183                                                offsetof(CPUSPARCState, asi));
3184                                 break;
3185                             case 0x6: /* V9 wrfprs */
3186                                 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3187                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3188                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3189                                                offsetof(CPUSPARCState, fprs));
3190                                 save_state(dc, cpu_cond);
3191                                 gen_op_next_insn();
3192                                 tcg_gen_exit_tb(0);
3193                                 dc->is_br = 1;
3194                                 break;
3195                             case 0xf: /* V9 sir, nop if user */
3196 #if !defined(CONFIG_USER_ONLY)
3197                                 if (supervisor(dc))
3198                                     ; // XXX
3199 #endif
3200                                 break;
3201                             case 0x13: /* Graphics Status */
3202                                 if (gen_trap_ifnofpu(dc, cpu_cond))
3203                                     goto jmp_insn;
3204                                 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3205                                 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3206                                               offsetof(CPUSPARCState, gsr));
3207                                 break;
3208                             case 0x17: /* Tick compare */
3209 #if !defined(CONFIG_USER_ONLY)
3210                                 if (!supervisor(dc))
3211                                     goto illegal_insn;
3212 #endif
3213                                 {
3214                                     TCGv r_tickptr;
3215
3216                                     tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3217                                                    cpu_src2);
3218                                     tcg_gen_st_tl(cpu_tmp0, cpu_env,
3219                                                   offsetof(CPUSPARCState,
3220                                                            tick_cmpr));
3221                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3222                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3223                                                    offsetof(CPUState, tick));
3224                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3225                                                        r_tickptr, cpu_tmp0);
3226                                     tcg_temp_free(r_tickptr);
3227                                 }
3228                                 break;
3229                             case 0x18: /* System tick */
3230 #if !defined(CONFIG_USER_ONLY)
3231                                 if (!supervisor(dc))
3232                                     goto illegal_insn;
3233 #endif
3234                                 {
3235                                     TCGv r_tickptr;
3236
3237                                     tcg_gen_xor_tl(cpu_dst, cpu_src1,
3238                                                    cpu_src2);
3239                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3240                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3241                                                    offsetof(CPUState, stick));
3242                                     tcg_gen_helper_0_2(helper_tick_set_count,
3243                                                        r_tickptr, cpu_dst);
3244                                     tcg_temp_free(r_tickptr);
3245                                 }
3246                                 break;
3247                             case 0x19: /* System tick compare */
3248 #if !defined(CONFIG_USER_ONLY)
3249                                 if (!supervisor(dc))
3250                                     goto illegal_insn;
3251 #endif
3252                                 {
3253                                     TCGv r_tickptr;
3254
3255                                     tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3256                                                    cpu_src2);
3257                                     tcg_gen_st_tl(cpu_tmp0, cpu_env,
3258                                                   offsetof(CPUSPARCState,
3259                                                            stick_cmpr));
3260                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3261                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3262                                                    offsetof(CPUState, stick));
3263                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3264                                                        r_tickptr, cpu_tmp0);
3265                                     tcg_temp_free(r_tickptr);
3266                                 }
3267                                 break;
3268
3269                             case 0x10: /* Performance Control */
3270                             case 0x11: /* Performance Instrumentation
3271                                           Counter */
3272                             case 0x12: /* Dispatch Control */
3273                             case 0x14: /* Softint set */
3274                             case 0x15: /* Softint clear */
3275                             case 0x16: /* Softint write */
3276 #endif
3277                             default:
3278                                 goto illegal_insn;
3279                             }
3280                         }
3281                         break;
3282 #if !defined(CONFIG_USER_ONLY)
3283                     case 0x31: /* wrpsr, V9 saved, restored */
3284                         {
3285                             if (!supervisor(dc))
3286                                 goto priv_insn;
3287 #ifdef TARGET_SPARC64
3288                             switch (rd) {
3289                             case 0:
3290                                 tcg_gen_helper_0_0(helper_saved);
3291                                 break;
3292                             case 1:
3293                                 tcg_gen_helper_0_0(helper_restored);
3294                                 break;
3295                             case 2: /* UA2005 allclean */
3296                             case 3: /* UA2005 otherw */
3297                             case 4: /* UA2005 normalw */
3298                             case 5: /* UA2005 invalw */
3299                                 // XXX
3300                             default:
3301                                 goto illegal_insn;
3302                             }
3303 #else
3304                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3305                             tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3306                             save_state(dc, cpu_cond);
3307                             gen_op_next_insn();
3308                             tcg_gen_exit_tb(0);
3309                             dc->is_br = 1;
3310 #endif
3311                         }
3312                         break;
3313                     case 0x32: /* wrwim, V9 wrpr */
3314                         {
3315                             if (!supervisor(dc))
3316                                 goto priv_insn;
3317                             tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3318 #ifdef TARGET_SPARC64
3319                             switch (rd) {
3320                             case 0: // tpc
3321                                 {
3322                                     TCGv r_tsptr;
3323
3324                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3325                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3326                                                    offsetof(CPUState, tsptr));
3327                                     tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3328                                                   offsetof(trap_state, tpc));
3329                                     tcg_temp_free(r_tsptr);
3330                                 }
3331                                 break;
3332                             case 1: // tnpc
3333                                 {
3334                                     TCGv r_tsptr;
3335
3336                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3337                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3338                                                    offsetof(CPUState, tsptr));
3339                                     tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3340                                                   offsetof(trap_state, tnpc));
3341                                     tcg_temp_free(r_tsptr);
3342                                 }
3343                                 break;
3344                             case 2: // tstate
3345                                 {
3346                                     TCGv r_tsptr;
3347
3348                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3349                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3350                                                    offsetof(CPUState, tsptr));
3351                                     tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3352                                                   offsetof(trap_state,
3353                                                            tstate));
3354                                     tcg_temp_free(r_tsptr);
3355                                 }
3356                                 break;
3357                             case 3: // tt
3358                                 {
3359                                     TCGv r_tsptr;
3360
3361                                     r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3362                                     tcg_gen_ld_ptr(r_tsptr, cpu_env,
3363                                                    offsetof(CPUState, tsptr));
3364                                     tcg_gen_st_i32(cpu_tmp0, r_tsptr,
3365                                                    offsetof(trap_state, tt));
3366                                     tcg_temp_free(r_tsptr);
3367                                 }
3368                                 break;
3369                             case 4: // tick
3370                                 {
3371                                     TCGv r_tickptr;
3372
3373                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3374                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3375                                                    offsetof(CPUState, tick));
3376                                     tcg_gen_helper_0_2(helper_tick_set_count,
3377                                                        r_tickptr, cpu_tmp0);
3378                                     tcg_temp_free(r_tickptr);
3379                                 }
3380                                 break;
3381                             case 5: // tba
3382                                 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3383                                               offsetof(CPUSPARCState, tbr));
3384                                 break;
3385                             case 6: // pstate
3386                                 save_state(dc, cpu_cond);
3387                                 tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
3388                                 gen_op_next_insn();
3389                                 tcg_gen_exit_tb(0);
3390                                 dc->is_br = 1;
3391                                 break;
3392                             case 7: // tl
3393                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3394                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3395                                                offsetof(CPUSPARCState, tl));
3396                                 break;
3397                             case 8: // pil
3398                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3399                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3400                                                offsetof(CPUSPARCState,
3401                                                         psrpil));
3402                                 break;
3403                             case 9: // cwp
3404                                 tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
3405                                 break;
3406                             case 10: // cansave
3407                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3408                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3409                                                offsetof(CPUSPARCState,
3410                                                         cansave));
3411                                 break;
3412                             case 11: // canrestore
3413                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3414                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3415                                                offsetof(CPUSPARCState,
3416                                                         canrestore));
3417                                 break;
3418                             case 12: // cleanwin
3419                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3420                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3421                                                offsetof(CPUSPARCState,
3422                                                         cleanwin));
3423                                 break;
3424                             case 13: // otherwin
3425                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3426                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3427                                                offsetof(CPUSPARCState,
3428                                                         otherwin));
3429                                 break;
3430                             case 14: // wstate
3431                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3432                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3433                                                offsetof(CPUSPARCState,
3434                                                         wstate));
3435                                 break;
3436                             case 16: // UA2005 gl
3437                                 CHECK_IU_FEATURE(dc, GL);
3438                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3439                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3440                                                offsetof(CPUSPARCState, gl));
3441                                 break;
3442                             case 26: // UA2005 strand status
3443                                 CHECK_IU_FEATURE(dc, HYPV);
3444                                 if (!hypervisor(dc))
3445                                     goto priv_insn;
3446                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3447                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3448                                                offsetof(CPUSPARCState, ssr));
3449                                 break;
3450                             default:
3451                                 goto illegal_insn;
3452                             }
3453 #else
3454                             tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3455                             tcg_gen_st_i32(cpu_tmp32, cpu_env,
3456                                            offsetof(CPUSPARCState, wim));
3457 #endif
3458                         }
3459                         break;
3460                     case 0x33: /* wrtbr, UA2005 wrhpr */
3461                         {
3462 #ifndef TARGET_SPARC64
3463                             if (!supervisor(dc))
3464                                 goto priv_insn;
3465                             tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3466                             tcg_gen_st_tl(cpu_tmp0, cpu_env,
3467                                           offsetof(CPUSPARCState, tbr));
3468 #else
3469                             CHECK_IU_FEATURE(dc, HYPV);
3470                             if (!hypervisor(dc))
3471                                 goto priv_insn;
3472                             tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3473                             switch (rd) {
3474                             case 0: // hpstate
3475                                 // XXX gen_op_wrhpstate();
3476                                 save_state(dc, cpu_cond);
3477                                 gen_op_next_insn();
3478                                 tcg_gen_exit_tb(0);
3479                                 dc->is_br = 1;
3480                                 break;
3481                             case 1: // htstate
3482                                 // XXX gen_op_wrhtstate();
3483                                 break;
3484                             case 3: // hintp
3485                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3486                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3487                                                offsetof(CPUSPARCState, hintp));
3488                                 break;
3489                             case 5: // htba
3490                                 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3491                                 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3492                                                offsetof(CPUSPARCState, htba));
3493                                 break;
3494                             case 31: // hstick_cmpr
3495                                 {
3496                                     TCGv r_tickptr;
3497
3498                                     tcg_gen_st_tl(cpu_tmp0, cpu_env,
3499                                                   offsetof(CPUSPARCState,
3500                                                            hstick_cmpr));
3501                                     r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3502                                     tcg_gen_ld_ptr(r_tickptr, cpu_env,
3503                                                    offsetof(CPUState, hstick));
3504                                     tcg_gen_helper_0_2(helper_tick_set_limit,
3505                                                        r_tickptr, cpu_tmp0);
3506                                     tcg_temp_free(r_tickptr);
3507                                 }
3508                                 break;
3509                             case 6: // hver readonly
3510                             default:
3511                                 goto illegal_insn;
3512                             }
3513 #endif
3514                         }
3515                         break;
3516 #endif
3517 #ifdef TARGET_SPARC64
3518                     case 0x2c: /* V9 movcc */
3519                         {
3520                             int cc = GET_FIELD_SP(insn, 11, 12);
3521                             int cond = GET_FIELD_SP(insn, 14, 17);
3522                             TCGv r_cond;
3523                             int l1;
3524
3525                             r_cond = tcg_temp_new(TCG_TYPE_TL);
3526                             if (insn & (1 << 18)) {
3527                                 if (cc == 0)
3528                                     gen_cond(r_cond, 0, cond);
3529                                 else if (cc == 2)
3530                                     gen_cond(r_cond, 1, cond);
3531                                 else
3532                                     goto illegal_insn;
3533                             } else {
3534                                 gen_fcond(r_cond, cc, cond);
3535                             }
3536
3537                             l1 = gen_new_label();
3538
3539                             tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3540                             if (IS_IMM) {       /* immediate */
3541                                 TCGv r_const;
3542
3543                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
3544                                 r_const = tcg_const_tl((int)rs2);
3545                                 gen_movl_TN_reg(rd, r_const);
3546                                 tcg_temp_free(r_const);
3547                             } else {
3548                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3549                                 gen_movl_reg_TN(rs2, cpu_tmp0);
3550                                 gen_movl_TN_reg(rd, cpu_tmp0);
3551                             }
3552                             gen_set_label(l1);
3553                             tcg_temp_free(r_cond);
3554                             break;
3555                         }
3556                     case 0x2d: /* V9 sdivx */
3557                         gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3558                         gen_movl_TN_reg(rd, cpu_dst);
3559                         break;
3560                     case 0x2e: /* V9 popc */
3561                         {
3562                             cpu_src2 = get_src2(insn, cpu_src2);
3563                             tcg_gen_helper_1_1(helper_popc, cpu_dst,
3564                                                cpu_src2);
3565                             gen_movl_TN_reg(rd, cpu_dst);
3566                         }
3567                     case 0x2f: /* V9 movr */
3568                         {
3569                             int cond = GET_FIELD_SP(insn, 10, 12);
3570                             int l1;
3571
3572                             cpu_src1 = get_src1(insn, cpu_src1);
3573
3574                             l1 = gen_new_label();
3575
3576                             tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3577                                               cpu_src1, 0, l1);
3578                             if (IS_IMM) {       /* immediate */
3579                                 TCGv r_const;
3580
3581                                 rs2 = GET_FIELD_SPs(insn, 0, 9);
3582                                 r_const = tcg_const_tl((int)rs2);
3583                                 gen_movl_TN_reg(rd, r_const);
3584                                 tcg_temp_free(r_const);
3585                             } else {
3586                                 rs2 = GET_FIELD_SP(insn, 0, 4);
3587                                 gen_movl_reg_TN(rs2, cpu_tmp0);
3588                                 gen_movl_TN_reg(rd, cpu_tmp0);
3589                             }
3590                             gen_set_label(l1);
3591                             break;
3592                         }
3593 #endif
3594                     default:
3595                         goto illegal_insn;
3596                     }
3597                 }
3598             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3599 #ifdef TARGET_SPARC64
3600                 int opf = GET_FIELD_SP(insn, 5, 13);
3601                 rs1 = GET_FIELD(insn, 13, 17);
3602                 rs2 = GET_FIELD(insn, 27, 31);
3603                 if (gen_trap_ifnofpu(dc, cpu_cond))
3604                     goto jmp_insn;
3605
3606                 switch (opf) {
3607                 case 0x000: /* VIS I edge8cc */
3608                 case 0x001: /* VIS II edge8n */
3609                 case 0x002: /* VIS I edge8lcc */
3610                 case 0x003: /* VIS II edge8ln */
3611                 case 0x004: /* VIS I edge16cc */
3612                 case 0x005: /* VIS II edge16n */
3613                 case 0x006: /* VIS I edge16lcc */
3614                 case 0x007: /* VIS II edge16ln */
3615                 case 0x008: /* VIS I edge32cc */
3616                 case 0x009: /* VIS II edge32n */
3617                 case 0x00a: /* VIS I edge32lcc */
3618                 case 0x00b: /* VIS II edge32ln */
3619                     // XXX
3620                     goto illegal_insn;
3621                 case 0x010: /* VIS I array8 */
3622                     CHECK_FPU_FEATURE(dc, VIS1);
3623                     cpu_src1 = get_src1(insn, cpu_src1);
3624                     gen_movl_reg_TN(rs2, cpu_src2);
3625                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3626                                        cpu_src2);
3627                     gen_movl_TN_reg(rd, cpu_dst);
3628                     break;
3629                 case 0x012: /* VIS I array16 */
3630                     CHECK_FPU_FEATURE(dc, VIS1);
3631                     cpu_src1 = get_src1(insn, cpu_src1);
3632                     gen_movl_reg_TN(rs2, cpu_src2);
3633                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3634                                        cpu_src2);
3635                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3636                     gen_movl_TN_reg(rd, cpu_dst);
3637                     break;
3638                 case 0x014: /* VIS I array32 */
3639                     CHECK_FPU_FEATURE(dc, VIS1);
3640                     cpu_src1 = get_src1(insn, cpu_src1);
3641                     gen_movl_reg_TN(rs2, cpu_src2);
3642                     tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3643                                        cpu_src2);
3644                     tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3645                     gen_movl_TN_reg(rd, cpu_dst);
3646                     break;
3647                 case 0x018: /* VIS I alignaddr */
3648                     CHECK_FPU_FEATURE(dc, VIS1);
3649                     cpu_src1 = get_src1(insn, cpu_src1);
3650                     gen_movl_reg_TN(rs2, cpu_src2);
3651                     tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3652                                        cpu_src2);
3653                     gen_movl_TN_reg(rd, cpu_dst);
3654                     break;
3655                 case 0x019: /* VIS II bmask */
3656                 case 0x01a: /* VIS I alignaddrl */
3657                     // XXX
3658                     goto illegal_insn;
3659                 case 0x020: /* VIS I fcmple16 */
3660                     CHECK_FPU_FEATURE(dc, VIS1);
3661                     gen_op_load_fpr_DT0(DFPREG(rs1));
3662                     gen_op_load_fpr_DT1(DFPREG(rs2));
3663                     tcg_gen_helper_0_0(helper_fcmple16);
3664                     gen_op_store_DT0_fpr(DFPREG(rd));
3665                     break;
3666                 case 0x022: /* VIS I fcmpne16 */
3667                     CHECK_FPU_FEATURE(dc, VIS1);
3668                     gen_op_load_fpr_DT0(DFPREG(rs1));
3669                     gen_op_load_fpr_DT1(DFPREG(rs2));
3670                     tcg_gen_helper_0_0(helper_fcmpne16);
3671                     gen_op_store_DT0_fpr(DFPREG(rd));
3672                     break;
3673                 case 0x024: /* VIS I fcmple32 */
3674                     CHECK_FPU_FEATURE(dc, VIS1);
3675                     gen_op_load_fpr_DT0(DFPREG(rs1));
3676                     gen_op_load_fpr_DT1(DFPREG(rs2));
3677                     tcg_gen_helper_0_0(helper_fcmple32);
3678                     gen_op_store_DT0_fpr(DFPREG(rd));
3679                     break;
3680                 case 0x026: /* VIS I fcmpne32 */
3681                     CHECK_FPU_FEATURE(dc, VIS1);
3682                     gen_op_load_fpr_DT0(DFPREG(rs1));
3683                     gen_op_load_fpr_DT1(DFPREG(rs2));
3684                     tcg_gen_helper_0_0(helper_fcmpne32);
3685                     gen_op_store_DT0_fpr(DFPREG(rd));
3686                     break;
3687                 case 0x028: /* VIS I fcmpgt16 */
3688                     CHECK_FPU_FEATURE(dc, VIS1);
3689                     gen_op_load_fpr_DT0(DFPREG(rs1));
3690                     gen_op_load_fpr_DT1(DFPREG(rs2));
3691                     tcg_gen_helper_0_0(helper_fcmpgt16);
3692                     gen_op_store_DT0_fpr(DFPREG(rd));
3693                     break;
3694                 case 0x02a: /* VIS I fcmpeq16 */
3695                     CHECK_FPU_FEATURE(dc, VIS1);
3696                     gen_op_load_fpr_DT0(DFPREG(rs1));
3697                     gen_op_load_fpr_DT1(DFPREG(rs2));
3698                     tcg_gen_helper_0_0(helper_fcmpeq16);
3699                     gen_op_store_DT0_fpr(DFPREG(rd));
3700                     break;
3701                 case 0x02c: /* VIS I fcmpgt32 */
3702                     CHECK_FPU_FEATURE(dc, VIS1);
3703                     gen_op_load_fpr_DT0(DFPREG(rs1));
3704                     gen_op_load_fpr_DT1(DFPREG(rs2));
3705                     tcg_gen_helper_0_0(helper_fcmpgt32);
3706                     gen_op_store_DT0_fpr(DFPREG(rd));
3707                     break;
3708                 case 0x02e: /* VIS I fcmpeq32 */
3709                     CHECK_FPU_FEATURE(dc, VIS1);
3710                     gen_op_load_fpr_DT0(DFPREG(rs1));
3711                     gen_op_load_fpr_DT1(DFPREG(rs2));
3712                     tcg_gen_helper_0_0(helper_fcmpeq32);
3713                     gen_op_store_DT0_fpr(DFPREG(rd));
3714                     break;
3715                 case 0x031: /* VIS I fmul8x16 */
3716                     CHECK_FPU_FEATURE(dc, VIS1);
3717                     gen_op_load_fpr_DT0(DFPREG(rs1));
3718                     gen_op_load_fpr_DT1(DFPREG(rs2));
3719                     tcg_gen_helper_0_0(helper_fmul8x16);
3720                     gen_op_store_DT0_fpr(DFPREG(rd));
3721                     break;
3722                 case 0x033: /* VIS I fmul8x16au */
3723                     CHECK_FPU_FEATURE(dc, VIS1);
3724                     gen_op_load_fpr_DT0(DFPREG(rs1));
3725                     gen_op_load_fpr_DT1(DFPREG(rs2));
3726                     tcg_gen_helper_0_0(helper_fmul8x16au);
3727                     gen_op_store_DT0_fpr(DFPREG(rd));
3728                     break;
3729                 case 0x035: /* VIS I fmul8x16al */
3730                     CHECK_FPU_FEATURE(dc, VIS1);
3731                     gen_op_load_fpr_DT0(DFPREG(rs1));
3732                     gen_op_load_fpr_DT1(DFPREG(rs2));
3733                     tcg_gen_helper_0_0(helper_fmul8x16al);
3734                     gen_op_store_DT0_fpr(DFPREG(rd));
3735                     break;
3736                 case 0x036: /* VIS I fmul8sux16 */
3737                     CHECK_FPU_FEATURE(dc, VIS1);
3738                     gen_op_load_fpr_DT0(DFPREG(rs1));
3739                     gen_op_load_fpr_DT1(DFPREG(rs2));
3740                     tcg_gen_helper_0_0(helper_fmul8sux16);
3741                     gen_op_store_DT0_fpr(DFPREG(rd));
3742                     break;
3743                 case 0x037: /* VIS I fmul8ulx16 */
3744                     CHECK_FPU_FEATURE(dc, VIS1);
3745                     gen_op_load_fpr_DT0(DFPREG(rs1));
3746                     gen_op_load_fpr_DT1(DFPREG(rs2));
3747                     tcg_gen_helper_0_0(helper_fmul8ulx16);
3748                     gen_op_store_DT0_fpr(DFPREG(rd));
3749                     break;
3750                 case 0x038: /* VIS I fmuld8sux16 */
3751                     CHECK_FPU_FEATURE(dc, VIS1);
3752                     gen_op_load_fpr_DT0(DFPREG(rs1));
3753                     gen_op_load_fpr_DT1(DFPREG(rs2));
3754                     tcg_gen_helper_0_0(helper_fmuld8sux16);
3755                     gen_op_store_DT0_fpr(DFPREG(rd));
3756                     break;
3757                 case 0x039: /* VIS I fmuld8ulx16 */
3758                     CHECK_FPU_FEATURE(dc, VIS1);
3759                     gen_op_load_fpr_DT0(DFPREG(rs1));
3760                     gen_op_load_fpr_DT1(DFPREG(rs2));
3761                     tcg_gen_helper_0_0(helper_fmuld8ulx16);
3762                     gen_op_store_DT0_fpr(DFPREG(rd));
3763                     break;
3764                 case 0x03a: /* VIS I fpack32 */
3765                 case 0x03b: /* VIS I fpack16 */
3766                 case 0x03d: /* VIS I fpackfix */
3767                 case 0x03e: /* VIS I pdist */
3768                     // XXX
3769                     goto illegal_insn;
3770                 case 0x048: /* VIS I faligndata */
3771                     CHECK_FPU_FEATURE(dc, VIS1);
3772                     gen_op_load_fpr_DT0(DFPREG(rs1));
3773                     gen_op_load_fpr_DT1(DFPREG(rs2));
3774                     tcg_gen_helper_0_0(helper_faligndata);
3775                     gen_op_store_DT0_fpr(DFPREG(rd));
3776                     break;
3777                 case 0x04b: /* VIS I fpmerge */
3778                     CHECK_FPU_FEATURE(dc, VIS1);
3779                     gen_op_load_fpr_DT0(DFPREG(rs1));
3780                     gen_op_load_fpr_DT1(DFPREG(rs2));
3781                     tcg_gen_helper_0_0(helper_fpmerge);
3782                     gen_op_store_DT0_fpr(DFPREG(rd));
3783                     break;
3784                 case 0x04c: /* VIS II bshuffle */
3785                     // XXX
3786                     goto illegal_insn;
3787                 case 0x04d: /* VIS I fexpand */
3788                     CHECK_FPU_FEATURE(dc, VIS1);
3789                     gen_op_load_fpr_DT0(DFPREG(rs1));
3790                     gen_op_load_fpr_DT1(DFPREG(rs2));
3791                     tcg_gen_helper_0_0(helper_fexpand);
3792                     gen_op_store_DT0_fpr(DFPREG(rd));
3793                     break;
3794                 case 0x050: /* VIS I fpadd16 */
3795                     CHECK_FPU_FEATURE(dc, VIS1);
3796                     gen_op_load_fpr_DT0(DFPREG(rs1));
3797                     gen_op_load_fpr_DT1(DFPREG(rs2));
3798                     tcg_gen_helper_0_0(helper_fpadd16);
3799                     gen_op_store_DT0_fpr(DFPREG(rd));
3800                     break;
3801                 case 0x051: /* VIS I fpadd16s */
3802                     CHECK_FPU_FEATURE(dc, VIS1);
3803                     gen_op_load_fpr_FT0(rs1);
3804                     gen_op_load_fpr_FT1(rs2);
3805                     tcg_gen_helper_0_0(helper_fpadd16s);
3806                     gen_op_store_FT0_fpr(rd);
3807                     break;
3808                 case 0x052: /* VIS I fpadd32 */
3809                     CHECK_FPU_FEATURE(dc, VIS1);
3810                     gen_op_load_fpr_DT0(DFPREG(rs1));
3811                     gen_op_load_fpr_DT1(DFPREG(rs2));
3812                     tcg_gen_helper_0_0(helper_fpadd32);
3813                     gen_op_store_DT0_fpr(DFPREG(rd));
3814                     break;
3815                 case 0x053: /* VIS I fpadd32s */
3816                     CHECK_FPU_FEATURE(dc, VIS1);
3817                     gen_op_load_fpr_FT0(rs1);
3818                     gen_op_load_fpr_FT1(rs2);
3819                     tcg_gen_helper_0_0(helper_fpadd32s);
3820                     gen_op_store_FT0_fpr(rd);
3821                     break;
3822                 case 0x054: /* VIS I fpsub16 */
3823                     CHECK_FPU_FEATURE(dc, VIS1);
3824                     gen_op_load_fpr_DT0(DFPREG(rs1));
3825                     gen_op_load_fpr_DT1(DFPREG(rs2));
3826                     tcg_gen_helper_0_0(helper_fpsub16);
3827                     gen_op_store_DT0_fpr(DFPREG(rd));
3828                     break;
3829                 case 0x055: /* VIS I fpsub16s */
3830                     CHECK_FPU_FEATURE(dc, VIS1);
3831                     gen_op_load_fpr_FT0(rs1);
3832                     gen_op_load_fpr_FT1(rs2);
3833                     tcg_gen_helper_0_0(helper_fpsub16s);
3834                     gen_op_store_FT0_fpr(rd);
3835                     break;
3836                 case 0x056: /* VIS I fpsub32 */
3837                     CHECK_FPU_FEATURE(dc, VIS1);
3838                     gen_op_load_fpr_DT0(DFPREG(rs1));
3839                     gen_op_load_fpr_DT1(DFPREG(rs2));
3840                     tcg_gen_helper_0_0(helper_fpadd32);
3841                     gen_op_store_DT0_fpr(DFPREG(rd));
3842                     break;
3843                 case 0x057: /* VIS I fpsub32s */
3844                     CHECK_FPU_FEATURE(dc, VIS1);
3845                     gen_op_load_fpr_FT0(rs1);
3846                     gen_op_load_fpr_FT1(rs2);
3847                     tcg_gen_helper_0_0(helper_fpsub32s);
3848                     gen_op_store_FT0_fpr(rd);
3849                     break;
3850                 case 0x060: /* VIS I fzero */
3851                     CHECK_FPU_FEATURE(dc, VIS1);
3852                     tcg_gen_helper_0_0(helper_movl_DT0_0);
3853                     gen_op_store_DT0_fpr(DFPREG(rd));
3854                     break;
3855                 case 0x061: /* VIS I fzeros */
3856                     CHECK_FPU_FEATURE(dc, VIS1);
3857                     tcg_gen_helper_0_0(helper_movl_FT0_0);
3858                     gen_op_store_FT0_fpr(rd);
3859                     break;
3860                 case 0x062: /* VIS I fnor */
3861                     CHECK_FPU_FEATURE(dc, VIS1);
3862                     gen_op_load_fpr_DT0(DFPREG(rs1));
3863                     gen_op_load_fpr_DT1(DFPREG(rs2));
3864                     tcg_gen_helper_0_0(helper_fnor);
3865                     gen_op_store_DT0_fpr(DFPREG(rd));
3866                     break;
3867                 case 0x063: /* VIS I fnors */
3868                     CHECK_FPU_FEATURE(dc, VIS1);
3869                     gen_op_load_fpr_FT0(rs1);
3870                     gen_op_load_fpr_FT1(rs2);
3871                     tcg_gen_helper_0_0(helper_fnors);
3872                     gen_op_store_FT0_fpr(rd);
3873                     break;
3874                 case 0x064: /* VIS I fandnot2 */
3875                     CHECK_FPU_FEATURE(dc, VIS1);
3876                     gen_op_load_fpr_DT1(DFPREG(rs1));
3877                     gen_op_load_fpr_DT0(DFPREG(rs2));
3878                     tcg_gen_helper_0_0(helper_fandnot);
3879                     gen_op_store_DT0_fpr(DFPREG(rd));
3880                     break;
3881                 case 0x065: /* VIS I fandnot2s */
3882                     CHECK_FPU_FEATURE(dc, VIS1);
3883                     gen_op_load_fpr_FT1(rs1);
3884                     gen_op_load_fpr_FT0(rs2);
3885                     tcg_gen_helper_0_0(helper_fandnots);
3886                     gen_op_store_FT0_fpr(rd);
3887                     break;
3888                 case 0x066: /* VIS I fnot2 */
3889                     CHECK_FPU_FEATURE(dc, VIS1);
3890                     gen_op_load_fpr_DT1(DFPREG(rs2));
3891                     tcg_gen_helper_0_0(helper_fnot);
3892                     gen_op_store_DT0_fpr(DFPREG(rd));
3893                     break;
3894                 case 0x067: /* VIS I fnot2s */
3895                     CHECK_FPU_FEATURE(dc, VIS1);
3896                     gen_op_load_fpr_FT1(rs2);
3897                     tcg_gen_helper_0_0(helper_fnot);
3898                     gen_op_store_FT0_fpr(rd);
3899                     break;
3900                 case 0x068: /* VIS I fandnot1 */
3901                     CHECK_FPU_FEATURE(dc, VIS1);
3902                     gen_op_load_fpr_DT0(DFPREG(rs1));
3903                     gen_op_load_fpr_DT1(DFPREG(rs2));
3904                     tcg_gen_helper_0_0(helper_fandnot);
3905                     gen_op_store_DT0_fpr(DFPREG(rd));
3906                     break;
3907                 case 0x069: /* VIS I fandnot1s */
3908                     CHECK_FPU_FEATURE(dc, VIS1);
3909                     gen_op_load_fpr_FT0(rs1);
3910                     gen_op_load_fpr_FT1(rs2);
3911                     tcg_gen_helper_0_0(helper_fandnots);
3912                     gen_op_store_FT0_fpr(rd);
3913                     break;
3914                 case 0x06a: /* VIS I fnot1 */
3915                     CHECK_FPU_FEATURE(dc, VIS1);
3916                     gen_op_load_fpr_DT1(DFPREG(rs1));
3917                     tcg_gen_helper_0_0(helper_fnot);
3918                     gen_op_store_DT0_fpr(DFPREG(rd));
3919                     break;
3920                 case 0x06b: /* VIS I fnot1s */
3921                     CHECK_FPU_FEATURE(dc, VIS1);
3922                     gen_op_load_fpr_FT1(rs1);
3923                     tcg_gen_helper_0_0(helper_fnot);
3924                     gen_op_store_FT0_fpr(rd);
3925                     break;
3926                 case 0x06c: /* VIS I fxor */
3927                     CHECK_FPU_FEATURE(dc, VIS1);
3928                     gen_op_load_fpr_DT0(DFPREG(rs1));
3929                     gen_op_load_fpr_DT1(DFPREG(rs2));
3930                     tcg_gen_helper_0_0(helper_fxor);
3931                     gen_op_store_DT0_fpr(DFPREG(rd));
3932                     break;
3933                 case 0x06d: /* VIS I fxors */
3934                     CHECK_FPU_FEATURE(dc, VIS1);
3935                     gen_op_load_fpr_FT0(rs1);
3936                     gen_op_load_fpr_FT1(rs2);
3937                     tcg_gen_helper_0_0(helper_fxors);
3938                     gen_op_store_FT0_fpr(rd);
3939                     break;
3940                 case 0x06e: /* VIS I fnand */
3941                     CHECK_FPU_FEATURE(dc, VIS1);
3942                     gen_op_load_fpr_DT0(DFPREG(rs1));
3943                     gen_op_load_fpr_DT1(DFPREG(rs2));
3944                     tcg_gen_helper_0_0(helper_fnand);
3945                     gen_op_store_DT0_fpr(DFPREG(rd));
3946                     break;
3947                 case 0x06f: /* VIS I fnands */
3948                     CHECK_FPU_FEATURE(dc, VIS1);
3949                     gen_op_load_fpr_FT0(rs1);
3950                     gen_op_load_fpr_FT1(rs2);
3951                     tcg_gen_helper_0_0(helper_fnands);
3952                     gen_op_store_FT0_fpr(rd);
3953                     break;
3954                 case 0x070: /* VIS I fand */
3955                     CHECK_FPU_FEATURE(dc, VIS1);
3956                     gen_op_load_fpr_DT0(DFPREG(rs1));
3957                     gen_op_load_fpr_DT1(DFPREG(rs2));
3958                     tcg_gen_helper_0_0(helper_fand);
3959                     gen_op_store_DT0_fpr(DFPREG(rd));
3960                     break;
3961                 case 0x071: /* VIS I fands */
3962                     CHECK_FPU_FEATURE(dc, VIS1);
3963                     gen_op_load_fpr_FT0(rs1);
3964                     gen_op_load_fpr_FT1(rs2);
3965                     tcg_gen_helper_0_0(helper_fands);
3966                     gen_op_store_FT0_fpr(rd);
3967                     break;
3968                 case 0x072: /* VIS I fxnor */
3969                     CHECK_FPU_FEATURE(dc, VIS1);
3970                     gen_op_load_fpr_DT0(DFPREG(rs1));
3971                     gen_op_load_fpr_DT1(DFPREG(rs2));
3972                     tcg_gen_helper_0_0(helper_fxnor);
3973                     gen_op_store_DT0_fpr(DFPREG(rd));
3974                     break;
3975                 case 0x073: /* VIS I fxnors */
3976                     CHECK_FPU_FEATURE(dc, VIS1);
3977                     gen_op_load_fpr_FT0(rs1);
3978                     gen_op_load_fpr_FT1(rs2);
3979                     tcg_gen_helper_0_0(helper_fxnors);
3980                     gen_op_store_FT0_fpr(rd);
3981                     break;
3982                 case 0x074: /* VIS I fsrc1 */
3983                     CHECK_FPU_FEATURE(dc, VIS1);
3984                     gen_op_load_fpr_DT0(DFPREG(rs1));
3985                     gen_op_store_DT0_fpr(DFPREG(rd));
3986                     break;
3987                 case 0x075: /* VIS I fsrc1s */
3988                     CHECK_FPU_FEATURE(dc, VIS1);
3989                     gen_op_load_fpr_FT0(rs1);
3990                     gen_op_store_FT0_fpr(rd);
3991                     break;
3992                 case 0x076: /* VIS I fornot2 */
3993                     CHECK_FPU_FEATURE(dc, VIS1);
3994                     gen_op_load_fpr_DT1(DFPREG(rs1));
3995                     gen_op_load_fpr_DT0(DFPREG(rs2));
3996                     tcg_gen_helper_0_0(helper_fornot);
3997                     gen_op_store_DT0_fpr(DFPREG(rd));
3998                     break;
3999                 case 0x077: /* VIS I fornot2s */
4000                     CHECK_FPU_FEATURE(dc, VIS1);
4001                     gen_op_load_fpr_FT1(rs1);
4002                     gen_op_load_fpr_FT0(rs2);
4003                     tcg_gen_helper_0_0(helper_fornots);
4004                     gen_op_store_FT0_fpr(rd);
4005                     break;
4006                 case 0x078: /* VIS I fsrc2 */
4007                     CHECK_FPU_FEATURE(dc, VIS1);
4008                     gen_op_load_fpr_DT0(DFPREG(rs2));
4009                     gen_op_store_DT0_fpr(DFPREG(rd));
4010                     break;
4011                 case 0x079: /* VIS I fsrc2s */
4012                     CHECK_FPU_FEATURE(dc, VIS1);
4013                     gen_op_load_fpr_FT0(rs2);
4014                     gen_op_store_FT0_fpr(rd);
4015                     break;
4016                 case 0x07a: /* VIS I fornot1 */
4017                     CHECK_FPU_FEATURE(dc, VIS1);
4018                     gen_op_load_fpr_DT0(DFPREG(rs1));
4019                     gen_op_load_fpr_DT1(DFPREG(rs2));
4020                     tcg_gen_helper_0_0(helper_fornot);
4021                     gen_op_store_DT0_fpr(DFPREG(rd));
4022                     break;
4023                 case 0x07b: /* VIS I fornot1s */
4024                     CHECK_FPU_FEATURE(dc, VIS1);
4025                     gen_op_load_fpr_FT0(rs1);
4026                     gen_op_load_fpr_FT1(rs2);
4027                     tcg_gen_helper_0_0(helper_fornots);
4028                     gen_op_store_FT0_fpr(rd);
4029                     break;
4030                 case 0x07c: /* VIS I for */
4031                     CHECK_FPU_FEATURE(dc, VIS1);
4032                     gen_op_load_fpr_DT0(DFPREG(rs1));
4033                     gen_op_load_fpr_DT1(DFPREG(rs2));
4034                     tcg_gen_helper_0_0(helper_for);
4035                     gen_op_store_DT0_fpr(DFPREG(rd));
4036                     break;
4037                 case 0x07d: /* VIS I fors */
4038                     CHECK_FPU_FEATURE(dc, VIS1);
4039                     gen_op_load_fpr_FT0(rs1);
4040                     gen_op_load_fpr_FT1(rs2);
4041                     tcg_gen_helper_0_0(helper_fors);
4042                     gen_op_store_FT0_fpr(rd);
4043                     break;
4044                 case 0x07e: /* VIS I fone */
4045                     CHECK_FPU_FEATURE(dc, VIS1);
4046                     tcg_gen_helper_0_0(helper_movl_DT0_1);
4047                     gen_op_store_DT0_fpr(DFPREG(rd));
4048                     break;
4049                 case 0x07f: /* VIS I fones */
4050                     CHECK_FPU_FEATURE(dc, VIS1);
4051                     tcg_gen_helper_0_0(helper_movl_FT0_1);
4052                     gen_op_store_FT0_fpr(rd);
4053                     break;
4054                 case 0x080: /* VIS I shutdown */
4055                 case 0x081: /* VIS II siam */
4056                     // XXX
4057                     goto illegal_insn;
4058                 default:
4059                     goto illegal_insn;
4060                 }
4061 #else
4062                 goto ncp_insn;
4063 #endif
4064             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4065 #ifdef TARGET_SPARC64
4066                 goto illegal_insn;
4067 #else
4068                 goto ncp_insn;
4069 #endif
4070 #ifdef TARGET_SPARC64
4071             } else if (xop == 0x39) { /* V9 return */
4072                 TCGv r_const;
4073
4074                 save_state(dc, cpu_cond);
4075                 cpu_src1 = get_src1(insn, cpu_src1);
4076                 if (IS_IMM) {   /* immediate */
4077                     rs2 = GET_FIELDs(insn, 19, 31);
4078                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4079                 } else {                /* register */
4080                     rs2 = GET_FIELD(insn, 27, 31);
4081                     if (rs2) {
4082                         gen_movl_reg_TN(rs2, cpu_src2);
4083                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4084                     } else
4085                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
4086                 }
4087                 tcg_gen_helper_0_0(helper_restore);
4088                 gen_mov_pc_npc(dc, cpu_cond);
4089                 r_const = tcg_const_i32(3);
4090                 tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4091                 tcg_temp_free(r_const);
4092                 tcg_gen_mov_tl(cpu_npc, cpu_dst);
4093                 dc->npc = DYNAMIC_PC;
4094                 goto jmp_insn;
4095 #endif
4096             } else {
4097                 cpu_src1 = get_src1(insn, cpu_src1);
4098                 if (IS_IMM) {   /* immediate */
4099                     rs2 = GET_FIELDs(insn, 19, 31);
4100                     tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4101                 } else {                /* register */
4102                     rs2 = GET_FIELD(insn, 27, 31);
4103                     if (rs2) {
4104                         gen_movl_reg_TN(rs2, cpu_src2);
4105                         tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4106                     } else
4107                         tcg_gen_mov_tl(cpu_dst, cpu_src1);
4108                 }
4109                 switch (xop) {
4110                 case 0x38:      /* jmpl */
4111                     {
4112                         TCGv r_const;
4113
4114                         r_const = tcg_const_tl(dc->pc);
4115                         gen_movl_TN_reg(rd, r_const);
4116                         tcg_temp_free(r_const);
4117                         gen_mov_pc_npc(dc, cpu_cond);
4118                         r_const = tcg_const_i32(3);
4119                         tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4120                                            r_const);
4121                         tcg_temp_free(r_const);
4122                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
4123                         dc->npc = DYNAMIC_PC;
4124                     }
4125                     goto jmp_insn;
4126 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4127                 case 0x39:      /* rett, V9 return */
4128                     {
4129                         TCGv r_const;
4130
4131                         if (!supervisor(dc))
4132                             goto priv_insn;
4133                         gen_mov_pc_npc(dc, cpu_cond);
4134                         r_const = tcg_const_i32(3);
4135                         tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4136                                            r_const);
4137                         tcg_temp_free(r_const);
4138                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
4139                         dc->npc = DYNAMIC_PC;
4140                         tcg_gen_helper_0_0(helper_rett);
4141                     }
4142                     goto jmp_insn;
4143 #endif
4144                 case 0x3b: /* flush */
4145                     if (!((dc)->features & CPU_FEATURE_FLUSH))
4146                         goto unimp_flush;
4147                     tcg_gen_helper_0_1(helper_flush, cpu_dst);
4148                     break;
4149                 case 0x3c:      /* save */
4150                     save_state(dc, cpu_cond);
4151                     tcg_gen_helper_0_0(helper_save);
4152                     gen_movl_TN_reg(rd, cpu_dst);
4153                     break;
4154                 case 0x3d:      /* restore */
4155                     save_state(dc, cpu_cond);
4156                     tcg_gen_helper_0_0(helper_restore);
4157                     gen_movl_TN_reg(rd, cpu_dst);
4158                     break;
4159 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4160                 case 0x3e:      /* V9 done/retry */
4161                     {
4162                         switch (rd) {
4163                         case 0:
4164                             if (!supervisor(dc))
4165                                 goto priv_insn;
4166                             dc->npc = DYNAMIC_PC;
4167                             dc->pc = DYNAMIC_PC;
4168                             tcg_gen_helper_0_0(helper_done);
4169                             goto jmp_insn;
4170                         case 1:
4171                             if (!supervisor(dc))
4172                                 goto priv_insn;
4173                             dc->npc = DYNAMIC_PC;
4174                             dc->pc = DYNAMIC_PC;
4175                             tcg_gen_helper_0_0(helper_retry);
4176                             goto jmp_insn;
4177                         default:
4178                             goto illegal_insn;
4179                         }
4180                     }
4181                     break;
4182 #endif
4183                 default:
4184                     goto illegal_insn;
4185                 }
4186             }
4187             break;
4188         }
4189         break;
4190     case 3:                     /* load/store instructions */
4191         {
4192             unsigned int xop = GET_FIELD(insn, 7, 12);
4193
4194             cpu_src1 = get_src1(insn, cpu_src1);
4195             if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
4196                 rs2 = GET_FIELD(insn, 27, 31);
4197                 gen_movl_reg_TN(rs2, cpu_src2);
4198                 tcg_gen_mov_tl(cpu_addr, cpu_src1);
4199             } else if (IS_IMM) {     /* immediate */
4200                 rs2 = GET_FIELDs(insn, 19, 31);
4201                 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4202             } else {            /* register */
4203                 rs2 = GET_FIELD(insn, 27, 31);
4204                 if (rs2 != 0) {
4205                     gen_movl_reg_TN(rs2, cpu_src2);
4206                     tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4207                 } else
4208                     tcg_gen_mov_tl(cpu_addr, cpu_src1);
4209             }
4210             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4211                 (xop > 0x17 && xop <= 0x1d ) ||
4212                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4213                 switch (xop) {
4214                 case 0x0:       /* load unsigned word */
4215                     gen_address_mask(dc, cpu_addr);
4216                     tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4217                     break;
4218                 case 0x1:       /* load unsigned byte */
4219                     gen_address_mask(dc, cpu_addr);
4220                     tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4221                     break;
4222                 case 0x2:       /* load unsigned halfword */
4223                     gen_address_mask(dc, cpu_addr);
4224                     tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4225                     break;
4226                 case 0x3:       /* load double word */
4227                     if (rd & 1)
4228                         goto illegal_insn;
4229                     else {
4230                         TCGv r_const;
4231
4232                         save_state(dc, cpu_cond);
4233                         r_const = tcg_const_i32(7);
4234                         tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4235                                            r_const); // XXX remove
4236                         tcg_temp_free(r_const);
4237                         gen_address_mask(dc, cpu_addr);
4238                         tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4239                         tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4240                         tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4241                         gen_movl_TN_reg(rd + 1, cpu_tmp0);
4242                         tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4243                         tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4244                         tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4245                     }
4246                     break;
4247                 case 0x9:       /* load signed byte */
4248                     gen_address_mask(dc, cpu_addr);
4249                     tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4250                     break;
4251                 case 0xa:       /* load signed halfword */
4252                     gen_address_mask(dc, cpu_addr);
4253                     tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4254                     break;
4255                 case 0xd:       /* ldstub -- XXX: should be atomically */
4256                     {
4257                         TCGv r_const;
4258
4259                         gen_address_mask(dc, cpu_addr);
4260                         tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4261                         r_const = tcg_const_tl(0xff);
4262                         tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4263                         tcg_temp_free(r_const);
4264                     }
4265                     break;
4266                 case 0x0f:      /* swap register with memory. Also
4267                                    atomically */
4268                     CHECK_IU_FEATURE(dc, SWAP);
4269                     gen_movl_reg_TN(rd, cpu_val);
4270                     gen_address_mask(dc, cpu_addr);
4271                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4272                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4273                     tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4274                     break;
4275 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4276                 case 0x10:      /* load word alternate */
4277 #ifndef TARGET_SPARC64
4278                     if (IS_IMM)
4279                         goto illegal_insn;
4280                     if (!supervisor(dc))
4281                         goto priv_insn;
4282 #endif
4283                     save_state(dc, cpu_cond);
4284                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4285                     break;
4286                 case 0x11:      /* load unsigned byte alternate */
4287 #ifndef TARGET_SPARC64
4288                     if (IS_IMM)
4289                         goto illegal_insn;
4290                     if (!supervisor(dc))
4291                         goto priv_insn;
4292 #endif
4293                     save_state(dc, cpu_cond);
4294                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4295                     break;
4296                 case 0x12:      /* load unsigned halfword alternate */
4297 #ifndef TARGET_SPARC64
4298                     if (IS_IMM)
4299                         goto illegal_insn;
4300                     if (!supervisor(dc))
4301                         goto priv_insn;
4302 #endif
4303                     save_state(dc, cpu_cond);
4304                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4305                     break;
4306                 case 0x13:      /* load double word alternate */
4307 #ifndef TARGET_SPARC64
4308                     if (IS_IMM)
4309                         goto illegal_insn;
4310                     if (!supervisor(dc))
4311                         goto priv_insn;
4312 #endif
4313                     if (rd & 1)
4314                         goto illegal_insn;
4315                     save_state(dc, cpu_cond);
4316                     gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
4317                     goto skip_move;
4318                 case 0x19:      /* load signed byte alternate */
4319 #ifndef TARGET_SPARC64
4320                     if (IS_IMM)
4321                         goto illegal_insn;
4322                     if (!supervisor(dc))
4323                         goto priv_insn;
4324 #endif
4325                     save_state(dc, cpu_cond);
4326                     gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4327                     break;
4328                 case 0x1a:      /* load signed halfword alternate */
4329 #ifndef TARGET_SPARC64
4330                     if (IS_IMM)
4331                         goto illegal_insn;
4332                     if (!supervisor(dc))
4333                         goto priv_insn;
4334 #endif
4335                     save_state(dc, cpu_cond);
4336                     gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4337                     break;
4338                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
4339 #ifndef TARGET_SPARC64
4340                     if (IS_IMM)
4341                         goto illegal_insn;
4342                     if (!supervisor(dc))
4343                         goto priv_insn;
4344 #endif
4345                     save_state(dc, cpu_cond);
4346                     gen_ldstub_asi(cpu_val, cpu_addr, insn);
4347                     break;
4348                 case 0x1f:      /* swap reg with alt. memory. Also
4349                                    atomically */
4350                     CHECK_IU_FEATURE(dc, SWAP);
4351 #ifndef TARGET_SPARC64
4352                     if (IS_IMM)
4353                         goto illegal_insn;
4354                     if (!supervisor(dc))
4355                         goto priv_insn;
4356 #endif
4357                     save_state(dc, cpu_cond);
4358                     gen_movl_reg_TN(rd, cpu_val);
4359                     gen_swap_asi(cpu_val, cpu_addr, insn);
4360                     break;
4361
4362 #ifndef TARGET_SPARC64
4363                 case 0x30: /* ldc */
4364                 case 0x31: /* ldcsr */
4365                 case 0x33: /* lddc */
4366                     goto ncp_insn;
4367 #endif
4368 #endif
4369 #ifdef TARGET_SPARC64
4370                 case 0x08: /* V9 ldsw */
4371                     gen_address_mask(dc, cpu_addr);
4372                     tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4373                     break;
4374                 case 0x0b: /* V9 ldx */
4375                     gen_address_mask(dc, cpu_addr);
4376                     tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4377                     break;
4378                 case 0x18: /* V9 ldswa */
4379                     save_state(dc, cpu_cond);
4380                     gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4381                     break;
4382                 case 0x1b: /* V9 ldxa */
4383                     save_state(dc, cpu_cond);
4384                     gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4385                     break;
4386                 case 0x2d: /* V9 prefetch, no effect */
4387                     goto skip_move;
4388                 case 0x30: /* V9 ldfa */
4389                     save_state(dc, cpu_cond);
4390                     gen_ldf_asi(cpu_addr, insn, 4, rd);
4391                     goto skip_move;
4392                 case 0x33: /* V9 lddfa */
4393                     save_state(dc, cpu_cond);
4394                     gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4395                     goto skip_move;
4396                 case 0x3d: /* V9 prefetcha, no effect */
4397                     goto skip_move;
4398                 case 0x32: /* V9 ldqfa */
4399                     CHECK_FPU_FEATURE(dc, FLOAT128);
4400                     save_state(dc, cpu_cond);
4401                     gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4402                     goto skip_move;
4403 #endif
4404                 default:
4405                     goto illegal_insn;
4406                 }
4407                 gen_movl_TN_reg(rd, cpu_val);
4408 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4409             skip_move: ;
4410 #endif
4411             } else if (xop >= 0x20 && xop < 0x24) {
4412                 if (gen_trap_ifnofpu(dc, cpu_cond))
4413                     goto jmp_insn;
4414                 save_state(dc, cpu_cond);
4415                 switch (xop) {
4416                 case 0x20:      /* load fpreg */
4417                     gen_address_mask(dc, cpu_addr);
4418                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4419                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4420                                    offsetof(CPUState, fpr[rd]));
4421                     break;
4422                 case 0x21:      /* load fsr */
4423                     gen_address_mask(dc, cpu_addr);
4424                     tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4425                     tcg_gen_st_i32(cpu_tmp32, cpu_env,
4426                                    offsetof(CPUState, ft0));
4427                     tcg_gen_helper_0_0(helper_ldfsr);
4428                     break;
4429                 case 0x22:      /* load quad fpreg */
4430                     {
4431                         TCGv r_const;
4432
4433                         CHECK_FPU_FEATURE(dc, FLOAT128);
4434                         r_const = tcg_const_i32(dc->mem_idx);
4435                         tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4436                         tcg_temp_free(r_const);
4437                         gen_op_store_QT0_fpr(QFPREG(rd));
4438                     }
4439                     break;
4440                 case 0x23:      /* load double fpreg */
4441                     {
4442                         TCGv r_const;
4443
4444                         r_const = tcg_const_i32(dc->mem_idx);
4445                         tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4446                         tcg_temp_free(r_const);
4447                         gen_op_store_DT0_fpr(DFPREG(rd));
4448                     }
4449                     break;
4450                 default:
4451                     goto illegal_insn;
4452                 }
4453             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4454                        xop == 0xe || xop == 0x1e) {
4455                 gen_movl_reg_TN(rd, cpu_val);
4456                 switch (xop) {
4457                 case 0x4: /* store word */
4458                     gen_address_mask(dc, cpu_addr);
4459                     tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4460                     break;
4461                 case 0x5: /* store byte */
4462                     gen_address_mask(dc, cpu_addr);
4463                     tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4464                     break;
4465                 case 0x6: /* store halfword */
4466                     gen_address_mask(dc, cpu_addr);
4467                     tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4468                     break;
4469                 case 0x7: /* store double word */
4470                     if (rd & 1)
4471                         goto illegal_insn;
4472                     else {
4473                         TCGv r_low, r_const;
4474
4475                         save_state(dc, cpu_cond);
4476                         gen_address_mask(dc, cpu_addr);
4477                         r_const = tcg_const_i32(7);
4478                         tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4479                                            r_const); // XXX remove
4480                         tcg_temp_free(r_const);
4481                         r_low = tcg_temp_new(TCG_TYPE_TL);
4482                         gen_movl_reg_TN(rd + 1, r_low);
4483                         tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4484                                            r_low);
4485                         tcg_temp_free(r_low);
4486                         tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4487                     }
4488                     break;
4489 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4490                 case 0x14: /* store word alternate */
4491 #ifndef TARGET_SPARC64
4492                     if (IS_IMM)
4493                         goto illegal_insn;
4494                     if (!supervisor(dc))
4495                         goto priv_insn;
4496 #endif
4497                     save_state(dc, cpu_cond);
4498                     gen_st_asi(cpu_val, cpu_addr, insn, 4);
4499                     break;
4500                 case 0x15: /* store byte alternate */
4501 #ifndef TARGET_SPARC64
4502                     if (IS_IMM)
4503                         goto illegal_insn;
4504                     if (!supervisor(dc))
4505                         goto priv_insn;
4506 #endif
4507                     save_state(dc, cpu_cond);
4508                     gen_st_asi(cpu_val, cpu_addr, insn, 1);
4509                     break;
4510                 case 0x16: /* store halfword alternate */
4511 #ifndef TARGET_SPARC64
4512                     if (IS_IMM)
4513                         goto illegal_insn;
4514                     if (!supervisor(dc))
4515                         goto priv_insn;
4516 #endif
4517                     save_state(dc, cpu_cond);
4518                     gen_st_asi(cpu_val, cpu_addr, insn, 2);
4519                     break;
4520                 case 0x17: /* store double word alternate */
4521 #ifndef TARGET_SPARC64
4522                     if (IS_IMM)
4523                         goto illegal_insn;
4524                     if (!supervisor(dc))
4525                         goto priv_insn;
4526 #endif
4527                     if (rd & 1)
4528                         goto illegal_insn;
4529                     else {
4530                         save_state(dc, cpu_cond);
4531                         gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4532                     }
4533                     break;
4534 #endif
4535 #ifdef TARGET_SPARC64
4536                 case 0x0e: /* V9 stx */
4537                     gen_address_mask(dc, cpu_addr);
4538                     tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4539                     break;
4540                 case 0x1e: /* V9 stxa */
4541                     save_state(dc, cpu_cond);
4542                     gen_st_asi(cpu_val, cpu_addr, insn, 8);
4543                     break;
4544 #endif
4545                 default:
4546                     goto illegal_insn;
4547                 }
4548             } else if (xop > 0x23 && xop < 0x28) {
4549                 if (gen_trap_ifnofpu(dc, cpu_cond))
4550                     goto jmp_insn;
4551                 save_state(dc, cpu_cond);
4552                 switch (xop) {
4553                 case 0x24: /* store fpreg */
4554                     gen_address_mask(dc, cpu_addr);
4555                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4556                                    offsetof(CPUState, fpr[rd]));
4557                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4558                     break;
4559                 case 0x25: /* stfsr, V9 stxfsr */
4560                     gen_address_mask(dc, cpu_addr);
4561                     tcg_gen_helper_0_0(helper_stfsr);
4562                     tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4563                                    offsetof(CPUState, ft0));
4564                     tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4565                     break;
4566                 case 0x26:
4567 #ifdef TARGET_SPARC64
4568                     /* V9 stqf, store quad fpreg */
4569                     {
4570                         TCGv r_const;
4571
4572                         CHECK_FPU_FEATURE(dc, FLOAT128);
4573                         gen_op_load_fpr_QT0(QFPREG(rd));
4574                         r_const = tcg_const_i32(dc->mem_idx);
4575                         tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4576                         tcg_temp_free(r_const);
4577                     }
4578                     break;
4579 #else /* !TARGET_SPARC64 */
4580                     /* stdfq, store floating point queue */
4581 #if defined(CONFIG_USER_ONLY)
4582                     goto illegal_insn;
4583 #else
4584                     if (!supervisor(dc))
4585                         goto priv_insn;
4586                     if (gen_trap_ifnofpu(dc, cpu_cond))
4587                         goto jmp_insn;
4588                     goto nfq_insn;
4589 #endif
4590 #endif
4591                 case 0x27: /* store double fpreg */
4592                     {
4593                         TCGv r_const;
4594
4595                         gen_op_load_fpr_DT0(DFPREG(rd));
4596                         r_const = tcg_const_i32(dc->mem_idx);
4597                         tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4598                         tcg_temp_free(r_const);
4599                     }
4600                     break;
4601                 default:
4602                     goto illegal_insn;
4603                 }
4604             } else if (xop > 0x33 && xop < 0x3f) {
4605                 save_state(dc, cpu_cond);
4606                 switch (xop) {
4607 #ifdef TARGET_SPARC64
4608                 case 0x34: /* V9 stfa */
4609                     gen_op_load_fpr_FT0(rd);
4610                     gen_stf_asi(cpu_addr, insn, 4, rd);
4611                     break;
4612                 case 0x36: /* V9 stqfa */
4613                     {
4614                         TCGv r_const;
4615
4616                         CHECK_FPU_FEATURE(dc, FLOAT128);
4617                         r_const = tcg_const_i32(7);
4618                         tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4619                                            r_const);
4620                         tcg_temp_free(r_const);
4621                         gen_op_load_fpr_QT0(QFPREG(rd));
4622                         gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4623                     }
4624                     break;
4625                 case 0x37: /* V9 stdfa */
4626                     gen_op_load_fpr_DT0(DFPREG(rd));
4627                     gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4628                     break;
4629                 case 0x3c: /* V9 casa */
4630                     gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4631                     gen_movl_TN_reg(rd, cpu_val);
4632                     break;
4633                 case 0x3e: /* V9 casxa */
4634                     gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4635                     gen_movl_TN_reg(rd, cpu_val);
4636                     break;
4637 #else
4638                 case 0x34: /* stc */
4639                 case 0x35: /* stcsr */
4640                 case 0x36: /* stdcq */
4641                 case 0x37: /* stdc */
4642                     goto ncp_insn;
4643 #endif
4644                 default:
4645                     goto illegal_insn;
4646                 }
4647             }
4648             else
4649                 goto illegal_insn;
4650         }
4651         break;
4652     }
4653     /* default case for non jump instructions */
4654     if (dc->npc == DYNAMIC_PC) {
4655         dc->pc = DYNAMIC_PC;
4656         gen_op_next_insn();
4657     } else if (dc->npc == JUMP_PC) {
4658         /* we can do a static jump */
4659         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4660         dc->is_br = 1;
4661     } else {
4662         dc->pc = dc->npc;
4663         dc->npc = dc->npc + 4;
4664     }
4665  jmp_insn:
4666     return;
4667  illegal_insn:
4668     {
4669         TCGv r_const;
4670
4671         save_state(dc, cpu_cond);
4672         r_const = tcg_const_i32(TT_ILL_INSN);
4673         tcg_gen_helper_0_1(raise_exception, r_const);
4674         tcg_temp_free(r_const);
4675         dc->is_br = 1;
4676     }
4677     return;
4678  unimp_flush:
4679     {
4680         TCGv r_const;
4681
4682         save_state(dc, cpu_cond);
4683         r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4684         tcg_gen_helper_0_1(raise_exception, r_const);
4685         tcg_temp_free(r_const);
4686         dc->is_br = 1;
4687     }
4688     return;
4689 #if !defined(CONFIG_USER_ONLY)
4690  priv_insn:
4691     {
4692         TCGv r_const;
4693
4694         save_state(dc, cpu_cond);
4695         r_const = tcg_const_i32(TT_PRIV_INSN);
4696         tcg_gen_helper_0_1(raise_exception, r_const);
4697         tcg_temp_free(r_const);
4698         dc->is_br = 1;
4699     }
4700     return;
4701 #endif
4702  nfpu_insn:
4703     save_state(dc, cpu_cond);
4704     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4705     dc->is_br = 1;
4706     return;
4707 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4708  nfq_insn:
4709     save_state(dc, cpu_cond);
4710     gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4711     dc->is_br = 1;
4712     return;
4713 #endif
4714 #ifndef TARGET_SPARC64
4715  ncp_insn:
4716     {
4717         TCGv r_const;
4718
4719         save_state(dc, cpu_cond);
4720         r_const = tcg_const_i32(TT_NCP_INSN);
4721         tcg_gen_helper_0_1(raise_exception, r_const);
4722         tcg_temp_free(r_const);
4723         dc->is_br = 1;
4724     }
4725     return;
4726 #endif
4727 }
4728
4729 static inline void gen_intermediate_code_internal(TranslationBlock * tb,
4730                                                   int spc, CPUSPARCState *env)
4731 {
4732     target_ulong pc_start, last_pc;
4733     uint16_t *gen_opc_end;
4734     DisasContext dc1, *dc = &dc1;
4735     int j, lj = -1;
4736     int num_insns;
4737     int max_insns;
4738
4739     memset(dc, 0, sizeof(DisasContext));
4740     dc->tb = tb;
4741     pc_start = tb->pc;
4742     dc->pc = pc_start;
4743     last_pc = dc->pc;
4744     dc->npc = (target_ulong) tb->cs_base;
4745     dc->mem_idx = cpu_mmu_index(env);
4746     dc->features = env->features;
4747     if ((dc->features & CPU_FEATURE_FLOAT)) {
4748         dc->fpu_enabled = cpu_fpu_enabled(env);
4749 #if defined(CONFIG_USER_ONLY)
4750         dc->features |= CPU_FEATURE_FLOAT128;
4751 #endif
4752     } else
4753         dc->fpu_enabled = 0;
4754 #ifdef TARGET_SPARC64
4755     dc->address_mask_32bit = env->pstate & PS_AM;
4756 #endif
4757     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4758
4759     cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4760     cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4761     cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4762
4763     cpu_dst = tcg_temp_local_new(TCG_TYPE_TL);
4764
4765     // loads and stores
4766     cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
4767     cpu_addr = tcg_temp_local_new(TCG_TYPE_TL);
4768
4769     num_insns = 0;
4770     max_insns = tb->cflags & CF_COUNT_MASK;
4771     if (max_insns == 0)
4772         max_insns = CF_COUNT_MASK;
4773     gen_icount_start();
4774     do {
4775         if (env->nb_breakpoints > 0) {
4776             for(j = 0; j < env->nb_breakpoints; j++) {
4777                 if (env->breakpoints[j] == dc->pc) {
4778                     if (dc->pc != pc_start)
4779                         save_state(dc, cpu_cond);
4780                     tcg_gen_helper_0_0(helper_debug);
4781                     tcg_gen_exit_tb(0);
4782                     dc->is_br = 1;
4783                     goto exit_gen_loop;
4784                 }
4785             }
4786         }
4787         if (spc) {
4788             if (loglevel > 0)
4789                 fprintf(logfile, "Search PC...\n");
4790             j = gen_opc_ptr - gen_opc_buf;
4791             if (lj < j) {
4792                 lj++;
4793                 while (lj < j)
4794                     gen_opc_instr_start[lj++] = 0;
4795                 gen_opc_pc[lj] = dc->pc;
4796                 gen_opc_npc[lj] = dc->npc;
4797                 gen_opc_instr_start[lj] = 1;
4798                 gen_opc_icount[lj] = num_insns;
4799             }
4800         }
4801         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
4802             gen_io_start();
4803         last_pc = dc->pc;
4804         disas_sparc_insn(dc);
4805         num_insns++;
4806
4807         if (dc->is_br)
4808             break;
4809         /* if the next PC is different, we abort now */
4810         if (dc->pc != (last_pc + 4))
4811             break;
4812         /* if we reach a page boundary, we stop generation so that the
4813            PC of a TT_TFAULT exception is always in the right page */
4814         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4815             break;
4816         /* if single step mode, we generate only one instruction and
4817            generate an exception */
4818         if (env->singlestep_enabled) {
4819             tcg_gen_movi_tl(cpu_pc, dc->pc);
4820             tcg_gen_exit_tb(0);
4821             break;
4822         }
4823     } while ((gen_opc_ptr < gen_opc_end) &&
4824              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
4825              num_insns < max_insns);
4826
4827  exit_gen_loop:
4828     tcg_temp_free(cpu_addr);
4829     tcg_temp_free(cpu_val);
4830     tcg_temp_free(cpu_dst);
4831     tcg_temp_free(cpu_tmp64);
4832     tcg_temp_free(cpu_tmp32);
4833     tcg_temp_free(cpu_tmp0);
4834     if (tb->cflags & CF_LAST_IO)
4835         gen_io_end();
4836     if (!dc->is_br) {
4837         if (dc->pc != DYNAMIC_PC &&
4838             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4839             /* static PC and NPC: we can use direct chaining */
4840             gen_goto_tb(dc, 0, dc->pc, dc->npc);
4841         } else {
4842             if (dc->pc != DYNAMIC_PC)
4843                 tcg_gen_movi_tl(cpu_pc, dc->pc);
4844             save_npc(dc, cpu_cond);
4845             tcg_gen_exit_tb(0);
4846         }
4847     }
4848     gen_icount_end(tb, num_insns);
4849     *gen_opc_ptr = INDEX_op_end;
4850     if (spc) {
4851         j = gen_opc_ptr - gen_opc_buf;
4852         lj++;
4853         while (lj <= j)
4854             gen_opc_instr_start[lj++] = 0;
4855 #if 0
4856         if (loglevel > 0) {
4857             page_dump(logfile);
4858         }
4859 #endif
4860         gen_opc_jump_pc[0] = dc->jump_pc[0];
4861         gen_opc_jump_pc[1] = dc->jump_pc[1];
4862     } else {
4863         tb->size = last_pc + 4 - pc_start;
4864         tb->icount = num_insns;
4865     }
4866 #ifdef DEBUG_DISAS
4867     if (loglevel & CPU_LOG_TB_IN_ASM) {
4868         fprintf(logfile, "--------------\n");
4869         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4870         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4871         fprintf(logfile, "\n");
4872     }
4873 #endif
4874 }
4875
4876 void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4877 {
4878     gen_intermediate_code_internal(tb, 0, env);
4879 }
4880
4881 void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4882 {
4883     gen_intermediate_code_internal(tb, 1, env);
4884 }
4885
4886 void gen_intermediate_code_init(CPUSPARCState *env)
4887 {
4888     unsigned int i;
4889     static int inited;
4890     static const char * const gregnames[8] = {
4891         NULL, // g0 not used
4892         "g1",
4893         "g2",
4894         "g3",
4895         "g4",
4896         "g5",
4897         "g6",
4898         "g7",
4899     };
4900
4901     /* init various static tables */
4902     if (!inited) {
4903         inited = 1;
4904
4905         cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4906         cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4907                                          offsetof(CPUState, regwptr),
4908                                          "regwptr");
4909 #ifdef TARGET_SPARC64
4910         cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4911                                      TCG_AREG0, offsetof(CPUState, xcc),
4912                                      "xcc");
4913 #endif
4914         cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4915                                       TCG_AREG0, offsetof(CPUState, cond),
4916                                       "cond");
4917         cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4918                                         TCG_AREG0, offsetof(CPUState, cc_src),
4919                                         "cc_src");
4920         cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4921                                          offsetof(CPUState, cc_src2),
4922                                          "cc_src2");
4923         cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4924                                         TCG_AREG0, offsetof(CPUState, cc_dst),
4925                                         "cc_dst");
4926         cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4927                                      TCG_AREG0, offsetof(CPUState, psr),
4928                                      "psr");
4929         cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4930                                      TCG_AREG0, offsetof(CPUState, fsr),
4931                                      "fsr");
4932         cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4933                                     TCG_AREG0, offsetof(CPUState, pc),
4934                                     "pc");
4935         cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4936                                     TCG_AREG0, offsetof(CPUState, npc),
4937                                     "npc");
4938         for (i = 1; i < 8; i++)
4939             cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4940                                               offsetof(CPUState, gregs[i]),
4941                                               gregnames[i]);
4942         /* register helpers */
4943
4944 #undef DEF_HELPER
4945 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4946 #include "helper.h"
4947     }
4948 }
4949
4950 void gen_pc_load(CPUState *env, TranslationBlock *tb,
4951                 unsigned long searched_pc, int pc_pos, void *puc)
4952 {
4953     target_ulong npc;
4954     env->pc = gen_opc_pc[pc_pos];
4955     npc = gen_opc_npc[pc_pos];
4956     if (npc == 1) {
4957         /* dynamic NPC: already stored */
4958     } else if (npc == 2) {
4959         target_ulong t2 = (target_ulong)(unsigned long)puc;
4960         /* jump PC: use T2 and the jump targets of the translation */
4961         if (t2)
4962             env->npc = gen_opc_jump_pc[0];
4963         else
4964             env->npc = gen_opc_jump_pc[1];
4965     } else {
4966         env->npc = npc;
4967     }
4968 }