2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 static const int tcg_target_reg_alloc_order[] = {
65 static const int tcg_target_call_iarg_regs[6] = {
74 static const int tcg_target_call_oarg_regs[2] = {
79 static uint8_t *tb_ret_addr;
81 static void patch_reloc(uint8_t *code_ptr, int type,
82 tcg_target_long value, tcg_target_long addend)
87 if (value != (uint32_t)value)
89 *(uint32_t *)code_ptr = value;
92 if (value != (int32_t)value)
94 *(uint32_t *)code_ptr = value;
97 value -= (long)code_ptr;
98 if (value != (int32_t)value)
100 *(uint32_t *)code_ptr = value;
107 /* maximum number of register used for input function arguments */
108 static inline int tcg_target_get_call_iarg_regs_count(int flags)
113 /* parse target specific constraints */
114 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
121 ct->ct |= TCG_CT_REG;
122 tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
125 ct->ct |= TCG_CT_REG;
126 tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
129 ct->ct |= TCG_CT_REG;
130 tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
133 ct->ct |= TCG_CT_REG;
134 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
137 ct->ct |= TCG_CT_REG;
138 tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
141 ct->ct |= TCG_CT_REG;
142 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
145 ct->ct |= TCG_CT_REG;
146 tcg_regset_set32(ct->u.regs, 0, 0xf);
149 ct->ct |= TCG_CT_REG;
150 tcg_regset_set32(ct->u.regs, 0, 0xffff);
152 case 'L': /* qemu_ld/st constraint */
153 ct->ct |= TCG_CT_REG;
154 tcg_regset_set32(ct->u.regs, 0, 0xffff);
155 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
156 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
159 ct->ct |= TCG_CT_CONST_S32;
162 ct->ct |= TCG_CT_CONST_U32;
172 /* test if a constant matches the constraint */
173 static inline int tcg_target_const_match(tcg_target_long val,
174 const TCGArgConstraint *arg_ct)
178 if (ct & TCG_CT_CONST)
180 else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
182 else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
221 #define P_EXT 0x100 /* 0x0f opcode prefix */
222 #define P_REXW 0x200 /* set rex.w = 1 */
223 #define P_REXB 0x400 /* force rex use for byte registers */
225 static const uint8_t tcg_cond_to_jcc[10] = {
226 [TCG_COND_EQ] = JCC_JE,
227 [TCG_COND_NE] = JCC_JNE,
228 [TCG_COND_LT] = JCC_JL,
229 [TCG_COND_GE] = JCC_JGE,
230 [TCG_COND_LE] = JCC_JLE,
231 [TCG_COND_GT] = JCC_JG,
232 [TCG_COND_LTU] = JCC_JB,
233 [TCG_COND_GEU] = JCC_JAE,
234 [TCG_COND_LEU] = JCC_JBE,
235 [TCG_COND_GTU] = JCC_JA,
238 static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
241 rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) |
242 ((x >> 2) & 2) | ((rm >> 3) & 1);
243 if (rex || (opc & P_REXB)) {
244 tcg_out8(s, rex | 0x40);
248 tcg_out8(s, opc & 0xff);
251 static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
253 tcg_out_opc(s, opc, r, rm, 0);
254 tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
257 /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
258 static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
259 tcg_target_long offset)
263 tcg_out_opc(s, opc, r, 0, 0);
264 val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
265 if (val == (int32_t)val) {
267 tcg_out8(s, 0x05 | ((r & 7) << 3));
269 } else if (offset == (int32_t)offset) {
270 tcg_out8(s, 0x04 | ((r & 7) << 3));
271 tcg_out8(s, 0x25); /* sib */
272 tcg_out32(s, offset);
276 } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
277 tcg_out_opc(s, opc, r, rm, 0);
278 if ((rm & 7) == TCG_REG_RSP) {
279 tcg_out8(s, 0x04 | ((r & 7) << 3));
282 tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
284 } else if ((int8_t)offset == offset) {
285 tcg_out_opc(s, opc, r, rm, 0);
286 if ((rm & 7) == TCG_REG_RSP) {
287 tcg_out8(s, 0x44 | ((r & 7) << 3));
290 tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
294 tcg_out_opc(s, opc, r, rm, 0);
295 if ((rm & 7) == TCG_REG_RSP) {
296 tcg_out8(s, 0x84 | ((r & 7) << 3));
299 tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
301 tcg_out32(s, offset);
305 #if defined(CONFIG_SOFTMMU)
306 /* XXX: incomplete. index must be different from ESP */
307 static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
308 int index, int shift,
309 tcg_target_long offset)
314 if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
316 } else if (offset == (int8_t)offset) {
318 } else if (offset == (int32_t)offset) {
324 tcg_out_opc(s, opc, r, rm, 0);
325 if ((rm & 7) == TCG_REG_RSP) {
326 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
327 tcg_out8(s, 0x04 | (rm & 7));
329 tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
332 tcg_out_opc(s, opc, r, rm, index);
333 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
334 tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
338 } else if (mod == 0x80) {
339 tcg_out32(s, offset);
344 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
346 tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
349 static inline void tcg_out_movi(TCGContext *s, TCGType type,
350 int ret, tcg_target_long arg)
353 tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
354 } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
355 tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
357 } else if (arg == (int32_t)arg) {
358 tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
361 tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
363 tcg_out32(s, arg >> 32);
367 static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
368 int arg1, tcg_target_long arg2)
370 if (type == TCG_TYPE_I32)
371 tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
373 tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
376 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
377 int arg1, tcg_target_long arg2)
379 if (type == TCG_TYPE_I32)
380 tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
382 tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
385 static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
387 if (val == (int8_t)val) {
388 tcg_out_modrm(s, 0x83, c, r0);
390 } else if (c == ARITH_AND && val == 0xffu) {
392 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0);
393 } else if (c == ARITH_AND && val == 0xffffu) {
395 tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
397 tcg_out_modrm(s, 0x81, c, r0);
402 static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
404 if (val == (int8_t)val) {
405 tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
407 } else if (c == ARITH_AND && val == 0xffu) {
409 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
410 } else if (c == ARITH_AND && val == 0xffffu) {
412 tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
413 } else if (c == ARITH_AND && val == 0xffffffffu) {
414 /* 32-bit mov zero extends */
415 tcg_out_modrm(s, 0x8b, r0, r0);
416 } else if (val == (int32_t)val) {
417 tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
419 } else if (c == ARITH_AND && val == (uint32_t)val) {
420 tcg_out_modrm(s, 0x81, c, r0);
427 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
430 tgen_arithi64(s, ARITH_ADD, reg, val);
433 static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
436 TCGLabel *l = &s->labels[label_index];
439 val = l->u.value - (tcg_target_long)s->code_ptr;
441 if ((int8_t)val1 == val1) {
445 tcg_out8(s, 0x70 + opc);
450 tcg_out32(s, val - 5);
453 tcg_out8(s, 0x80 + opc);
454 tcg_out32(s, val - 6);
462 tcg_out8(s, 0x80 + opc);
464 tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
469 static void tcg_out_brcond(TCGContext *s, int cond,
470 TCGArg arg1, TCGArg arg2, int const_arg2,
471 int label_index, int rexw)
476 tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
479 tgen_arithi64(s, ARITH_CMP, arg1, arg2);
481 tgen_arithi32(s, ARITH_CMP, arg1, arg2);
484 tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
486 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
489 #if defined(CONFIG_SOFTMMU)
491 #include "../../softmmu_defs.h"
493 static void *qemu_ld_helpers[4] = {
500 static void *qemu_st_helpers[4] = {
508 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
511 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
512 #if defined(CONFIG_SOFTMMU)
513 uint8_t *label1_ptr, *label2_ptr;
524 #if TARGET_LONG_BITS == 32
529 #if defined(CONFIG_SOFTMMU)
531 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
534 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
536 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
537 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
539 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
540 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
542 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
543 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
545 /* lea offset(r1, env), r1 */
546 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
547 offsetof(CPUState, tlb_table[mem_index][0].addr_read));
550 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
553 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
556 tcg_out8(s, 0x70 + JCC_JE);
557 label1_ptr = s->code_ptr;
560 /* XXX: move that code at the end of the TB */
561 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
563 tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
564 (tcg_target_long)s->code_ptr - 4);
569 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
573 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
577 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
581 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
585 tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
590 tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
593 tcg_out_mov(s, data_reg, TCG_REG_RAX);
599 label2_ptr = s->code_ptr;
603 *label1_ptr = s->code_ptr - label1_ptr - 1;
606 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
607 offsetof(CPUTLBEntry, addr_read));
608 #elif defined(CONFIG_USE_GUEST_BASE)
610 * Add guest_base to all loads.
612 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg); /* movq addr_reg, r0 */
613 tcg_out_addi(s, r0, GUEST_BASE); /* addq $GUEST_BASE, r0 */
618 #ifdef TARGET_WORDS_BIGENDIAN
626 tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0);
630 tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, 0);
634 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
636 /* rolw $8, data_reg */
638 tcg_out_modrm(s, 0xc1, 0, data_reg);
645 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
646 /* rolw $8, data_reg */
648 tcg_out_modrm(s, 0xc1, 0, data_reg);
651 /* movswX data_reg, data_reg */
652 tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
655 tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, 0);
659 /* movl (r0), data_reg */
660 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
663 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
668 /* movl (r0), data_reg */
669 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
671 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
673 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
676 tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, 0);
680 /* movq (r0), data_reg */
681 tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, 0);
684 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
691 #if defined(CONFIG_SOFTMMU)
693 *label2_ptr = s->code_ptr - label2_ptr - 1;
697 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
700 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
701 #if defined(CONFIG_SOFTMMU)
702 uint8_t *label1_ptr, *label2_ptr;
714 #if TARGET_LONG_BITS == 32
719 #if defined(CONFIG_SOFTMMU)
721 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
724 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
726 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
727 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
729 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
730 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
732 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
733 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
735 /* lea offset(r1, env), r1 */
736 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
737 offsetof(CPUState, tlb_table[mem_index][0].addr_write));
740 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
743 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
746 tcg_out8(s, 0x70 + JCC_JE);
747 label1_ptr = s->code_ptr;
750 /* XXX: move that code at the end of the TB */
754 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg);
758 tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
762 tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
766 tcg_out_mov(s, TCG_REG_RSI, data_reg);
769 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
771 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
772 (tcg_target_long)s->code_ptr - 4);
776 label2_ptr = s->code_ptr;
780 *label1_ptr = s->code_ptr - label1_ptr - 1;
783 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
784 offsetof(CPUTLBEntry, addr_write));
785 #elif defined(CONFIG_USE_GUEST_BASE)
787 * Add guest_base to all stores.
789 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg); /* movq addr_reg, r0 */
790 tcg_out_addi(s, r0, GUEST_BASE); /* addq $GUEST_BASE, r0 */
795 #ifdef TARGET_WORDS_BIGENDIAN
803 tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, 0);
807 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
808 tcg_out8(s, 0x66); /* rolw $8, %ecx */
809 tcg_out_modrm(s, 0xc1, 0, r1);
815 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
819 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
821 tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
825 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
829 tcg_out_mov(s, r1, data_reg);
831 tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
835 tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, 0);
841 #if defined(CONFIG_SOFTMMU)
843 *label2_ptr = s->code_ptr - label2_ptr - 1;
847 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
848 const int *const_args)
853 case INDEX_op_exit_tb:
854 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
855 tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
856 tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
858 case INDEX_op_goto_tb:
859 if (s->tb_jmp_offset) {
860 /* direct jump method */
861 tcg_out8(s, 0xe9); /* jmp im */
862 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
865 /* indirect jump method */
867 tcg_out_modrm_offset(s, 0xff, 4, -1,
868 (tcg_target_long)(s->tb_next +
871 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
876 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
878 tcg_out_modrm(s, 0xff, 2, args[0]);
884 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
886 tcg_out_modrm(s, 0xff, 4, args[0]);
890 tcg_out_jxx(s, JCC_JMP, args[0]);
892 case INDEX_op_movi_i32:
893 tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
895 case INDEX_op_movi_i64:
896 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
898 case INDEX_op_ld8u_i32:
899 case INDEX_op_ld8u_i64:
901 tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
903 case INDEX_op_ld8s_i32:
905 tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
907 case INDEX_op_ld8s_i64:
909 tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
911 case INDEX_op_ld16u_i32:
912 case INDEX_op_ld16u_i64:
914 tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
916 case INDEX_op_ld16s_i32:
918 tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
920 case INDEX_op_ld16s_i64:
922 tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
924 case INDEX_op_ld_i32:
925 case INDEX_op_ld32u_i64:
927 tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
929 case INDEX_op_ld32s_i64:
931 tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
933 case INDEX_op_ld_i64:
935 tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
938 case INDEX_op_st8_i32:
939 case INDEX_op_st8_i64:
941 tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]);
943 case INDEX_op_st16_i32:
944 case INDEX_op_st16_i64:
947 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
949 case INDEX_op_st_i32:
950 case INDEX_op_st32_i64:
952 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
954 case INDEX_op_st_i64:
956 tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
959 case INDEX_op_sub_i32:
962 case INDEX_op_and_i32:
965 case INDEX_op_or_i32:
968 case INDEX_op_xor_i32:
971 case INDEX_op_add_i32:
975 tgen_arithi32(s, c, args[0], args[2]);
977 tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
981 case INDEX_op_sub_i64:
984 case INDEX_op_and_i64:
987 case INDEX_op_or_i64:
990 case INDEX_op_xor_i64:
993 case INDEX_op_add_i64:
997 tgen_arithi64(s, c, args[0], args[2]);
999 tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
1003 case INDEX_op_mul_i32:
1004 if (const_args[2]) {
1007 if (val == (int8_t)val) {
1008 tcg_out_modrm(s, 0x6b, args[0], args[0]);
1011 tcg_out_modrm(s, 0x69, args[0], args[0]);
1015 tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
1018 case INDEX_op_mul_i64:
1019 if (const_args[2]) {
1022 if (val == (int8_t)val) {
1023 tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
1026 tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
1030 tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
1033 case INDEX_op_div2_i32:
1034 tcg_out_modrm(s, 0xf7, 7, args[4]);
1036 case INDEX_op_divu2_i32:
1037 tcg_out_modrm(s, 0xf7, 6, args[4]);
1039 case INDEX_op_div2_i64:
1040 tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
1042 case INDEX_op_divu2_i64:
1043 tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
1046 case INDEX_op_shl_i32:
1049 if (const_args[2]) {
1051 tcg_out_modrm(s, 0xd1, c, args[0]);
1053 tcg_out_modrm(s, 0xc1, c, args[0]);
1054 tcg_out8(s, args[2]);
1057 tcg_out_modrm(s, 0xd3, c, args[0]);
1060 case INDEX_op_shr_i32:
1063 case INDEX_op_sar_i32:
1066 case INDEX_op_rotl_i32:
1069 case INDEX_op_rotr_i32:
1073 case INDEX_op_shl_i64:
1076 if (const_args[2]) {
1078 tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
1080 tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
1081 tcg_out8(s, args[2]);
1084 tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
1087 case INDEX_op_shr_i64:
1090 case INDEX_op_sar_i64:
1093 case INDEX_op_rotl_i64:
1096 case INDEX_op_rotr_i64:
1100 case INDEX_op_brcond_i32:
1101 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1104 case INDEX_op_brcond_i64:
1105 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1109 case INDEX_op_bswap16_i32:
1110 case INDEX_op_bswap16_i64:
1112 tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]);
1115 case INDEX_op_bswap32_i32:
1116 case INDEX_op_bswap32_i64:
1117 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
1119 case INDEX_op_bswap64_i64:
1120 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
1123 case INDEX_op_neg_i32:
1124 tcg_out_modrm(s, 0xf7, 3, args[0]);
1126 case INDEX_op_neg_i64:
1127 tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
1130 case INDEX_op_not_i32:
1131 tcg_out_modrm(s, 0xf7, 2, args[0]);
1133 case INDEX_op_not_i64:
1134 tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]);
1137 case INDEX_op_ext8s_i32:
1138 tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]);
1140 case INDEX_op_ext16s_i32:
1141 tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
1143 case INDEX_op_ext8s_i64:
1144 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]);
1146 case INDEX_op_ext16s_i64:
1147 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]);
1149 case INDEX_op_ext32s_i64:
1150 tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
1153 case INDEX_op_qemu_ld8u:
1154 tcg_out_qemu_ld(s, args, 0);
1156 case INDEX_op_qemu_ld8s:
1157 tcg_out_qemu_ld(s, args, 0 | 4);
1159 case INDEX_op_qemu_ld16u:
1160 tcg_out_qemu_ld(s, args, 1);
1162 case INDEX_op_qemu_ld16s:
1163 tcg_out_qemu_ld(s, args, 1 | 4);
1165 case INDEX_op_qemu_ld32u:
1166 tcg_out_qemu_ld(s, args, 2);
1168 case INDEX_op_qemu_ld32s:
1169 tcg_out_qemu_ld(s, args, 2 | 4);
1171 case INDEX_op_qemu_ld64:
1172 tcg_out_qemu_ld(s, args, 3);
1175 case INDEX_op_qemu_st8:
1176 tcg_out_qemu_st(s, args, 0);
1178 case INDEX_op_qemu_st16:
1179 tcg_out_qemu_st(s, args, 1);
1181 case INDEX_op_qemu_st32:
1182 tcg_out_qemu_st(s, args, 2);
1184 case INDEX_op_qemu_st64:
1185 tcg_out_qemu_st(s, args, 3);
1193 static int tcg_target_callee_save_regs[] = {
1198 /* TCG_REG_R14, */ /* currently used for the global env, so no
1203 static inline void tcg_out_push(TCGContext *s, int reg)
1205 tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
1208 static inline void tcg_out_pop(TCGContext *s, int reg)
1210 tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
1213 /* Generate global QEMU prologue and epilogue code */
1214 void tcg_target_qemu_prologue(TCGContext *s)
1216 int i, frame_size, push_size, stack_addend;
1219 /* save all callee saved registers */
1220 for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1221 tcg_out_push(s, tcg_target_callee_save_regs[i]);
1224 /* reserve some stack space */
1225 push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
1226 frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1227 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1228 ~(TCG_TARGET_STACK_ALIGN - 1);
1229 stack_addend = frame_size - push_size;
1230 tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
1232 tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */
1235 tb_ret_addr = s->code_ptr;
1236 tcg_out_addi(s, TCG_REG_RSP, stack_addend);
1237 for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1238 tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1240 tcg_out8(s, 0xc3); /* ret */
1243 static const TCGTargetOpDef x86_64_op_defs[] = {
1244 { INDEX_op_exit_tb, { } },
1245 { INDEX_op_goto_tb, { } },
1246 { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
1247 { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
1248 { INDEX_op_br, { } },
1250 { INDEX_op_mov_i32, { "r", "r" } },
1251 { INDEX_op_movi_i32, { "r" } },
1252 { INDEX_op_ld8u_i32, { "r", "r" } },
1253 { INDEX_op_ld8s_i32, { "r", "r" } },
1254 { INDEX_op_ld16u_i32, { "r", "r" } },
1255 { INDEX_op_ld16s_i32, { "r", "r" } },
1256 { INDEX_op_ld_i32, { "r", "r" } },
1257 { INDEX_op_st8_i32, { "r", "r" } },
1258 { INDEX_op_st16_i32, { "r", "r" } },
1259 { INDEX_op_st_i32, { "r", "r" } },
1261 { INDEX_op_add_i32, { "r", "0", "ri" } },
1262 { INDEX_op_mul_i32, { "r", "0", "ri" } },
1263 { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1264 { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1265 { INDEX_op_sub_i32, { "r", "0", "ri" } },
1266 { INDEX_op_and_i32, { "r", "0", "ri" } },
1267 { INDEX_op_or_i32, { "r", "0", "ri" } },
1268 { INDEX_op_xor_i32, { "r", "0", "ri" } },
1270 { INDEX_op_shl_i32, { "r", "0", "ci" } },
1271 { INDEX_op_shr_i32, { "r", "0", "ci" } },
1272 { INDEX_op_sar_i32, { "r", "0", "ci" } },
1273 { INDEX_op_rotl_i32, { "r", "0", "ci" } },
1274 { INDEX_op_rotr_i32, { "r", "0", "ci" } },
1276 { INDEX_op_brcond_i32, { "r", "ri" } },
1278 { INDEX_op_mov_i64, { "r", "r" } },
1279 { INDEX_op_movi_i64, { "r" } },
1280 { INDEX_op_ld8u_i64, { "r", "r" } },
1281 { INDEX_op_ld8s_i64, { "r", "r" } },
1282 { INDEX_op_ld16u_i64, { "r", "r" } },
1283 { INDEX_op_ld16s_i64, { "r", "r" } },
1284 { INDEX_op_ld32u_i64, { "r", "r" } },
1285 { INDEX_op_ld32s_i64, { "r", "r" } },
1286 { INDEX_op_ld_i64, { "r", "r" } },
1287 { INDEX_op_st8_i64, { "r", "r" } },
1288 { INDEX_op_st16_i64, { "r", "r" } },
1289 { INDEX_op_st32_i64, { "r", "r" } },
1290 { INDEX_op_st_i64, { "r", "r" } },
1292 { INDEX_op_add_i64, { "r", "0", "re" } },
1293 { INDEX_op_mul_i64, { "r", "0", "re" } },
1294 { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
1295 { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
1296 { INDEX_op_sub_i64, { "r", "0", "re" } },
1297 { INDEX_op_and_i64, { "r", "0", "reZ" } },
1298 { INDEX_op_or_i64, { "r", "0", "re" } },
1299 { INDEX_op_xor_i64, { "r", "0", "re" } },
1301 { INDEX_op_shl_i64, { "r", "0", "ci" } },
1302 { INDEX_op_shr_i64, { "r", "0", "ci" } },
1303 { INDEX_op_sar_i64, { "r", "0", "ci" } },
1304 { INDEX_op_rotl_i64, { "r", "0", "ci" } },
1305 { INDEX_op_rotr_i64, { "r", "0", "ci" } },
1307 { INDEX_op_brcond_i64, { "r", "re" } },
1309 { INDEX_op_bswap16_i32, { "r", "0" } },
1310 { INDEX_op_bswap16_i64, { "r", "0" } },
1311 { INDEX_op_bswap32_i32, { "r", "0" } },
1312 { INDEX_op_bswap32_i64, { "r", "0" } },
1313 { INDEX_op_bswap64_i64, { "r", "0" } },
1315 { INDEX_op_neg_i32, { "r", "0" } },
1316 { INDEX_op_neg_i64, { "r", "0" } },
1318 { INDEX_op_not_i32, { "r", "0" } },
1319 { INDEX_op_not_i64, { "r", "0" } },
1321 { INDEX_op_ext8s_i32, { "r", "r"} },
1322 { INDEX_op_ext16s_i32, { "r", "r"} },
1323 { INDEX_op_ext8s_i64, { "r", "r"} },
1324 { INDEX_op_ext16s_i64, { "r", "r"} },
1325 { INDEX_op_ext32s_i64, { "r", "r"} },
1327 { INDEX_op_qemu_ld8u, { "r", "L" } },
1328 { INDEX_op_qemu_ld8s, { "r", "L" } },
1329 { INDEX_op_qemu_ld16u, { "r", "L" } },
1330 { INDEX_op_qemu_ld16s, { "r", "L" } },
1331 { INDEX_op_qemu_ld32u, { "r", "L" } },
1332 { INDEX_op_qemu_ld32s, { "r", "L" } },
1333 { INDEX_op_qemu_ld64, { "r", "L" } },
1335 { INDEX_op_qemu_st8, { "L", "L" } },
1336 { INDEX_op_qemu_st16, { "L", "L" } },
1337 { INDEX_op_qemu_st32, { "L", "L" } },
1338 { INDEX_op_qemu_st64, { "L", "L", "L" } },
1343 void tcg_target_init(TCGContext *s)
1346 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1349 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1350 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
1351 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1352 (1 << TCG_REG_RDI) |
1353 (1 << TCG_REG_RSI) |
1354 (1 << TCG_REG_RDX) |
1355 (1 << TCG_REG_RCX) |
1358 (1 << TCG_REG_RAX) |
1359 (1 << TCG_REG_R10) |
1360 (1 << TCG_REG_R11));
1362 tcg_regset_clear(s->reserved_regs);
1363 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
1365 tcg_add_target_add_op_defs(x86_64_op_defs);