2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
43 int tcg_target_reg_alloc_order[] = {
62 const int tcg_target_call_iarg_regs[6] = {
71 const int tcg_target_call_oarg_regs[2] = {
76 static uint8_t *tb_ret_addr;
78 static void patch_reloc(uint8_t *code_ptr, int type,
79 tcg_target_long value, tcg_target_long addend)
84 if (value != (uint32_t)value)
86 *(uint32_t *)code_ptr = value;
89 if (value != (int32_t)value)
91 *(uint32_t *)code_ptr = value;
94 value -= (long)code_ptr;
95 if (value != (int32_t)value)
97 *(uint32_t *)code_ptr = value;
104 /* maximum number of register used for input function arguments */
105 static inline int tcg_target_get_call_iarg_regs_count(int flags)
110 /* parse target specific constraints */
111 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
118 ct->ct |= TCG_CT_REG;
119 tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
122 ct->ct |= TCG_CT_REG;
123 tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
126 ct->ct |= TCG_CT_REG;
127 tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
130 ct->ct |= TCG_CT_REG;
131 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
134 ct->ct |= TCG_CT_REG;
135 tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
138 ct->ct |= TCG_CT_REG;
139 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
142 ct->ct |= TCG_CT_REG;
143 tcg_regset_set32(ct->u.regs, 0, 0xf);
146 ct->ct |= TCG_CT_REG;
147 tcg_regset_set32(ct->u.regs, 0, 0xffff);
149 case 'L': /* qemu_ld/st constraint */
150 ct->ct |= TCG_CT_REG;
151 tcg_regset_set32(ct->u.regs, 0, 0xffff);
152 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
153 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
156 ct->ct |= TCG_CT_CONST_S32;
159 ct->ct |= TCG_CT_CONST_U32;
169 /* test if a constant matches the constraint */
170 static inline int tcg_target_const_match(tcg_target_long val,
171 const TCGArgConstraint *arg_ct)
175 if (ct & TCG_CT_CONST)
177 else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
179 else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
216 #define P_EXT 0x100 /* 0x0f opcode prefix */
217 #define P_REXW 0x200 /* set rex.w = 1 */
218 #define P_REXB 0x400 /* force rex use for byte registers */
220 static const uint8_t tcg_cond_to_jcc[10] = {
221 [TCG_COND_EQ] = JCC_JE,
222 [TCG_COND_NE] = JCC_JNE,
223 [TCG_COND_LT] = JCC_JL,
224 [TCG_COND_GE] = JCC_JGE,
225 [TCG_COND_LE] = JCC_JLE,
226 [TCG_COND_GT] = JCC_JG,
227 [TCG_COND_LTU] = JCC_JB,
228 [TCG_COND_GEU] = JCC_JAE,
229 [TCG_COND_LEU] = JCC_JBE,
230 [TCG_COND_GTU] = JCC_JA,
233 static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
236 rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) |
237 ((x >> 2) & 2) | ((rm >> 3) & 1);
238 if (rex || (opc & P_REXB)) {
239 tcg_out8(s, rex | 0x40);
246 static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
248 tcg_out_opc(s, opc, r, rm, 0);
249 tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
252 /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
253 static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
254 tcg_target_long offset)
258 tcg_out_opc(s, opc, r, 0, 0);
259 val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
260 if (val == (int32_t)val) {
262 tcg_out8(s, 0x05 | ((r & 7) << 3));
264 } else if (offset == (int32_t)offset) {
265 tcg_out8(s, 0x04 | ((r & 7) << 3));
266 tcg_out8(s, 0x25); /* sib */
267 tcg_out32(s, offset);
271 } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
272 tcg_out_opc(s, opc, r, rm, 0);
273 if ((rm & 7) == TCG_REG_RSP) {
274 tcg_out8(s, 0x04 | ((r & 7) << 3));
277 tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
279 } else if ((int8_t)offset == offset) {
280 tcg_out_opc(s, opc, r, rm, 0);
281 if ((rm & 7) == TCG_REG_RSP) {
282 tcg_out8(s, 0x44 | ((r & 7) << 3));
285 tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
289 tcg_out_opc(s, opc, r, rm, 0);
290 if ((rm & 7) == TCG_REG_RSP) {
291 tcg_out8(s, 0x84 | ((r & 7) << 3));
294 tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
296 tcg_out32(s, offset);
300 #if defined(CONFIG_SOFTMMU)
301 /* XXX: incomplete. index must be different from ESP */
302 static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
303 int index, int shift,
304 tcg_target_long offset)
309 if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
311 } else if (offset == (int8_t)offset) {
313 } else if (offset == (int32_t)offset) {
319 tcg_out_opc(s, opc, r, rm, 0);
320 if ((rm & 7) == TCG_REG_RSP) {
321 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
322 tcg_out8(s, 0x04 | (rm & 7));
324 tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
327 tcg_out_opc(s, opc, r, rm, index);
328 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
329 tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
333 } else if (mod == 0x80) {
334 tcg_out32(s, offset);
339 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
341 tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
344 static inline void tcg_out_movi(TCGContext *s, TCGType type,
345 int ret, tcg_target_long arg)
348 tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
349 } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
350 tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
352 } else if (arg == (int32_t)arg) {
353 tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
356 tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
358 tcg_out32(s, arg >> 32);
362 static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
363 int arg1, tcg_target_long arg2)
365 if (type == TCG_TYPE_I32)
366 tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
368 tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
371 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
372 int arg1, tcg_target_long arg2)
374 if (type == TCG_TYPE_I32)
375 tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
377 tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
380 static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
382 if (val == (int8_t)val) {
383 tcg_out_modrm(s, 0x83, c, r0);
385 } else if (c == ARITH_AND && val == 0xffu) {
387 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0);
388 } else if (c == ARITH_AND && val == 0xffffu) {
390 tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
392 tcg_out_modrm(s, 0x81, c, r0);
397 static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
399 if (val == (int8_t)val) {
400 tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
402 } else if (c == ARITH_AND && val == 0xffu) {
404 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
405 } else if (c == ARITH_AND && val == 0xffffu) {
407 tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
408 } else if (c == ARITH_AND && val == 0xffffffffu) {
409 /* 32-bit mov zero extends */
410 tcg_out_modrm(s, 0x8b, r0, r0);
411 } else if (val == (int32_t)val) {
412 tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
414 } else if (c == ARITH_AND && val == (uint32_t)val) {
415 tcg_out_modrm(s, 0x81, c, r0);
422 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
425 tgen_arithi64(s, ARITH_ADD, reg, val);
428 static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
431 TCGLabel *l = &s->labels[label_index];
434 val = l->u.value - (tcg_target_long)s->code_ptr;
436 if ((int8_t)val1 == val1) {
440 tcg_out8(s, 0x70 + opc);
445 tcg_out32(s, val - 5);
448 tcg_out8(s, 0x80 + opc);
449 tcg_out32(s, val - 6);
457 tcg_out8(s, 0x80 + opc);
459 tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
464 static void tcg_out_brcond(TCGContext *s, int cond,
465 TCGArg arg1, TCGArg arg2, int const_arg2,
466 int label_index, int rexw)
471 tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
474 tgen_arithi64(s, ARITH_CMP, arg1, arg2);
476 tgen_arithi32(s, ARITH_CMP, arg1, arg2);
479 tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
481 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
484 #if defined(CONFIG_SOFTMMU)
486 #include "../../softmmu_defs.h"
488 static void *qemu_ld_helpers[4] = {
495 static void *qemu_st_helpers[4] = {
503 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
506 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
507 #if defined(CONFIG_SOFTMMU)
508 uint8_t *label1_ptr, *label2_ptr;
519 #if TARGET_LONG_BITS == 32
524 #if defined(CONFIG_SOFTMMU)
526 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
529 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
531 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
532 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
534 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
535 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
537 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
538 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
540 /* lea offset(r1, env), r1 */
541 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
542 offsetof(CPUState, tlb_table[mem_index][0].addr_read));
545 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
548 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
551 tcg_out8(s, 0x70 + JCC_JE);
552 label1_ptr = s->code_ptr;
555 /* XXX: move that code at the end of the TB */
556 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
558 tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
559 (tcg_target_long)s->code_ptr - 4);
564 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
568 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
572 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
579 tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
582 tcg_out_mov(s, data_reg, TCG_REG_RAX);
588 label2_ptr = s->code_ptr;
592 *label1_ptr = s->code_ptr - label1_ptr - 1;
595 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
596 offsetof(CPUTLBEntry, addr_read));
601 #ifdef TARGET_WORDS_BIGENDIAN
609 tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0);
613 tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, 0);
617 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
619 /* rolw $8, data_reg */
621 tcg_out_modrm(s, 0xc1, 0, data_reg);
628 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
629 /* rolw $8, data_reg */
631 tcg_out_modrm(s, 0xc1, 0, data_reg);
634 /* movswX data_reg, data_reg */
635 tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
638 tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, 0);
642 /* movl (r0), data_reg */
643 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
646 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
651 /* movl (r0), data_reg */
652 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
654 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
656 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
659 tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, 0);
663 /* movq (r0), data_reg */
664 tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, 0);
667 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
674 #if defined(CONFIG_SOFTMMU)
676 *label2_ptr = s->code_ptr - label2_ptr - 1;
680 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
683 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
684 #if defined(CONFIG_SOFTMMU)
685 uint8_t *label1_ptr, *label2_ptr;
697 #if TARGET_LONG_BITS == 32
702 #if defined(CONFIG_SOFTMMU)
704 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
707 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
709 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
710 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
712 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
713 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
715 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
716 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
718 /* lea offset(r1, env), r1 */
719 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
720 offsetof(CPUState, tlb_table[mem_index][0].addr_write));
723 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
726 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
729 tcg_out8(s, 0x70 + JCC_JE);
730 label1_ptr = s->code_ptr;
733 /* XXX: move that code at the end of the TB */
737 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg);
741 tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
745 tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
749 tcg_out_mov(s, TCG_REG_RSI, data_reg);
752 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
754 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
755 (tcg_target_long)s->code_ptr - 4);
759 label2_ptr = s->code_ptr;
763 *label1_ptr = s->code_ptr - label1_ptr - 1;
766 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
767 offsetof(CPUTLBEntry, addr_write));
772 #ifdef TARGET_WORDS_BIGENDIAN
780 tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, 0);
784 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
785 tcg_out8(s, 0x66); /* rolw $8, %ecx */
786 tcg_out_modrm(s, 0xc1, 0, r1);
792 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
796 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
798 tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
802 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
806 tcg_out_mov(s, r1, data_reg);
808 tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
812 tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, 0);
818 #if defined(CONFIG_SOFTMMU)
820 *label2_ptr = s->code_ptr - label2_ptr - 1;
824 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
825 const int *const_args)
830 case INDEX_op_exit_tb:
831 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
832 tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
833 tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
835 case INDEX_op_goto_tb:
836 if (s->tb_jmp_offset) {
837 /* direct jump method */
838 tcg_out8(s, 0xe9); /* jmp im */
839 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
842 /* indirect jump method */
844 tcg_out_modrm_offset(s, 0xff, 4, -1,
845 (tcg_target_long)(s->tb_next +
848 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
853 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
855 tcg_out_modrm(s, 0xff, 2, args[0]);
861 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
863 tcg_out_modrm(s, 0xff, 4, args[0]);
867 tcg_out_jxx(s, JCC_JMP, args[0]);
869 case INDEX_op_movi_i32:
870 tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
872 case INDEX_op_movi_i64:
873 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
875 case INDEX_op_ld8u_i32:
876 case INDEX_op_ld8u_i64:
878 tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
880 case INDEX_op_ld8s_i32:
882 tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
884 case INDEX_op_ld8s_i64:
886 tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
888 case INDEX_op_ld16u_i32:
889 case INDEX_op_ld16u_i64:
891 tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
893 case INDEX_op_ld16s_i32:
895 tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
897 case INDEX_op_ld16s_i64:
899 tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
901 case INDEX_op_ld_i32:
902 case INDEX_op_ld32u_i64:
904 tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
906 case INDEX_op_ld32s_i64:
908 tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
910 case INDEX_op_ld_i64:
912 tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
915 case INDEX_op_st8_i32:
916 case INDEX_op_st8_i64:
918 tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]);
920 case INDEX_op_st16_i32:
921 case INDEX_op_st16_i64:
924 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
926 case INDEX_op_st_i32:
927 case INDEX_op_st32_i64:
929 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
931 case INDEX_op_st_i64:
933 tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
936 case INDEX_op_sub_i32:
939 case INDEX_op_and_i32:
942 case INDEX_op_or_i32:
945 case INDEX_op_xor_i32:
948 case INDEX_op_add_i32:
952 tgen_arithi32(s, c, args[0], args[2]);
954 tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
958 case INDEX_op_sub_i64:
961 case INDEX_op_and_i64:
964 case INDEX_op_or_i64:
967 case INDEX_op_xor_i64:
970 case INDEX_op_add_i64:
974 tgen_arithi64(s, c, args[0], args[2]);
976 tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
980 case INDEX_op_mul_i32:
984 if (val == (int8_t)val) {
985 tcg_out_modrm(s, 0x6b, args[0], args[0]);
988 tcg_out_modrm(s, 0x69, args[0], args[0]);
992 tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
995 case INDEX_op_mul_i64:
999 if (val == (int8_t)val) {
1000 tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
1003 tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
1007 tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
1010 case INDEX_op_div2_i32:
1011 tcg_out_modrm(s, 0xf7, 7, args[4]);
1013 case INDEX_op_divu2_i32:
1014 tcg_out_modrm(s, 0xf7, 6, args[4]);
1016 case INDEX_op_div2_i64:
1017 tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
1019 case INDEX_op_divu2_i64:
1020 tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
1023 case INDEX_op_shl_i32:
1026 if (const_args[2]) {
1028 tcg_out_modrm(s, 0xd1, c, args[0]);
1030 tcg_out_modrm(s, 0xc1, c, args[0]);
1031 tcg_out8(s, args[2]);
1034 tcg_out_modrm(s, 0xd3, c, args[0]);
1037 case INDEX_op_shr_i32:
1040 case INDEX_op_sar_i32:
1044 case INDEX_op_shl_i64:
1047 if (const_args[2]) {
1049 tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
1051 tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
1052 tcg_out8(s, args[2]);
1055 tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
1058 case INDEX_op_shr_i64:
1061 case INDEX_op_sar_i64:
1065 case INDEX_op_brcond_i32:
1066 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1069 case INDEX_op_brcond_i64:
1070 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1074 case INDEX_op_bswap_i32:
1075 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
1077 case INDEX_op_bswap_i64:
1078 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
1081 case INDEX_op_neg_i32:
1082 tcg_out_modrm(s, 0xf7, 3, args[0]);
1084 case INDEX_op_neg_i64:
1085 tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
1088 case INDEX_op_ext8s_i32:
1089 tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]);
1091 case INDEX_op_ext16s_i32:
1092 tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
1094 case INDEX_op_ext8s_i64:
1095 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]);
1097 case INDEX_op_ext16s_i64:
1098 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]);
1100 case INDEX_op_ext32s_i64:
1101 tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
1104 case INDEX_op_qemu_ld8u:
1105 tcg_out_qemu_ld(s, args, 0);
1107 case INDEX_op_qemu_ld8s:
1108 tcg_out_qemu_ld(s, args, 0 | 4);
1110 case INDEX_op_qemu_ld16u:
1111 tcg_out_qemu_ld(s, args, 1);
1113 case INDEX_op_qemu_ld16s:
1114 tcg_out_qemu_ld(s, args, 1 | 4);
1116 case INDEX_op_qemu_ld32u:
1117 tcg_out_qemu_ld(s, args, 2);
1119 case INDEX_op_qemu_ld32s:
1120 tcg_out_qemu_ld(s, args, 2 | 4);
1122 case INDEX_op_qemu_ld64:
1123 tcg_out_qemu_ld(s, args, 3);
1126 case INDEX_op_qemu_st8:
1127 tcg_out_qemu_st(s, args, 0);
1129 case INDEX_op_qemu_st16:
1130 tcg_out_qemu_st(s, args, 1);
1132 case INDEX_op_qemu_st32:
1133 tcg_out_qemu_st(s, args, 2);
1135 case INDEX_op_qemu_st64:
1136 tcg_out_qemu_st(s, args, 3);
1144 static int tcg_target_callee_save_regs[] = {
1149 /* TCG_REG_R14, */ /* currently used for the global env, so no
1154 static inline void tcg_out_push(TCGContext *s, int reg)
1156 tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
1159 static inline void tcg_out_pop(TCGContext *s, int reg)
1161 tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
1164 /* Generate global QEMU prologue and epilogue code */
1165 void tcg_target_qemu_prologue(TCGContext *s)
1167 int i, frame_size, push_size, stack_addend;
1170 /* save all callee saved registers */
1171 for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1172 tcg_out_push(s, tcg_target_callee_save_regs[i]);
1175 /* reserve some stack space */
1176 push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
1177 frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1178 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1179 ~(TCG_TARGET_STACK_ALIGN - 1);
1180 stack_addend = frame_size - push_size;
1181 tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
1183 tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */
1186 tb_ret_addr = s->code_ptr;
1187 tcg_out_addi(s, TCG_REG_RSP, stack_addend);
1188 for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1189 tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1191 tcg_out8(s, 0xc3); /* ret */
1194 static const TCGTargetOpDef x86_64_op_defs[] = {
1195 { INDEX_op_exit_tb, { } },
1196 { INDEX_op_goto_tb, { } },
1197 { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
1198 { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
1199 { INDEX_op_br, { } },
1201 { INDEX_op_mov_i32, { "r", "r" } },
1202 { INDEX_op_movi_i32, { "r" } },
1203 { INDEX_op_ld8u_i32, { "r", "r" } },
1204 { INDEX_op_ld8s_i32, { "r", "r" } },
1205 { INDEX_op_ld16u_i32, { "r", "r" } },
1206 { INDEX_op_ld16s_i32, { "r", "r" } },
1207 { INDEX_op_ld_i32, { "r", "r" } },
1208 { INDEX_op_st8_i32, { "r", "r" } },
1209 { INDEX_op_st16_i32, { "r", "r" } },
1210 { INDEX_op_st_i32, { "r", "r" } },
1212 { INDEX_op_add_i32, { "r", "0", "ri" } },
1213 { INDEX_op_mul_i32, { "r", "0", "ri" } },
1214 { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1215 { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1216 { INDEX_op_sub_i32, { "r", "0", "ri" } },
1217 { INDEX_op_and_i32, { "r", "0", "ri" } },
1218 { INDEX_op_or_i32, { "r", "0", "ri" } },
1219 { INDEX_op_xor_i32, { "r", "0", "ri" } },
1221 { INDEX_op_shl_i32, { "r", "0", "ci" } },
1222 { INDEX_op_shr_i32, { "r", "0", "ci" } },
1223 { INDEX_op_sar_i32, { "r", "0", "ci" } },
1225 { INDEX_op_brcond_i32, { "r", "ri" } },
1227 { INDEX_op_mov_i64, { "r", "r" } },
1228 { INDEX_op_movi_i64, { "r" } },
1229 { INDEX_op_ld8u_i64, { "r", "r" } },
1230 { INDEX_op_ld8s_i64, { "r", "r" } },
1231 { INDEX_op_ld16u_i64, { "r", "r" } },
1232 { INDEX_op_ld16s_i64, { "r", "r" } },
1233 { INDEX_op_ld32u_i64, { "r", "r" } },
1234 { INDEX_op_ld32s_i64, { "r", "r" } },
1235 { INDEX_op_ld_i64, { "r", "r" } },
1236 { INDEX_op_st8_i64, { "r", "r" } },
1237 { INDEX_op_st16_i64, { "r", "r" } },
1238 { INDEX_op_st32_i64, { "r", "r" } },
1239 { INDEX_op_st_i64, { "r", "r" } },
1241 { INDEX_op_add_i64, { "r", "0", "re" } },
1242 { INDEX_op_mul_i64, { "r", "0", "re" } },
1243 { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
1244 { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
1245 { INDEX_op_sub_i64, { "r", "0", "re" } },
1246 { INDEX_op_and_i64, { "r", "0", "reZ" } },
1247 { INDEX_op_or_i64, { "r", "0", "re" } },
1248 { INDEX_op_xor_i64, { "r", "0", "re" } },
1250 { INDEX_op_shl_i64, { "r", "0", "ci" } },
1251 { INDEX_op_shr_i64, { "r", "0", "ci" } },
1252 { INDEX_op_sar_i64, { "r", "0", "ci" } },
1254 { INDEX_op_brcond_i64, { "r", "re" } },
1256 { INDEX_op_bswap_i32, { "r", "0" } },
1257 { INDEX_op_bswap_i64, { "r", "0" } },
1259 { INDEX_op_neg_i32, { "r", "0" } },
1260 { INDEX_op_neg_i64, { "r", "0" } },
1262 { INDEX_op_ext8s_i32, { "r", "r"} },
1263 { INDEX_op_ext16s_i32, { "r", "r"} },
1264 { INDEX_op_ext8s_i64, { "r", "r"} },
1265 { INDEX_op_ext16s_i64, { "r", "r"} },
1266 { INDEX_op_ext32s_i64, { "r", "r"} },
1268 { INDEX_op_qemu_ld8u, { "r", "L" } },
1269 { INDEX_op_qemu_ld8s, { "r", "L" } },
1270 { INDEX_op_qemu_ld16u, { "r", "L" } },
1271 { INDEX_op_qemu_ld16s, { "r", "L" } },
1272 { INDEX_op_qemu_ld32u, { "r", "L" } },
1273 { INDEX_op_qemu_ld32s, { "r", "L" } },
1274 { INDEX_op_qemu_ld64, { "r", "L" } },
1276 { INDEX_op_qemu_st8, { "L", "L" } },
1277 { INDEX_op_qemu_st16, { "L", "L" } },
1278 { INDEX_op_qemu_st32, { "L", "L" } },
1279 { INDEX_op_qemu_st64, { "L", "L", "L" } },
1284 void tcg_target_init(TCGContext *s)
1287 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1290 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1291 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
1292 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1293 (1 << TCG_REG_RDI) |
1294 (1 << TCG_REG_RSI) |
1295 (1 << TCG_REG_RDX) |
1296 (1 << TCG_REG_RCX) |
1299 (1 << TCG_REG_RAX) |
1300 (1 << TCG_REG_R10) |
1301 (1 << TCG_REG_R11));
1303 tcg_regset_clear(s->reserved_regs);
1304 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
1306 tcg_add_target_add_op_defs(x86_64_op_defs);