2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 static const int tcg_target_reg_alloc_order[] = {
64 static const int tcg_target_call_iarg_regs[6] = {
73 static const int tcg_target_call_oarg_regs[2] = {
78 static uint8_t *tb_ret_addr;
80 static void patch_reloc(uint8_t *code_ptr, int type,
81 tcg_target_long value, tcg_target_long addend)
86 if (value != (uint32_t)value)
88 *(uint32_t *)code_ptr = value;
91 if (value != (int32_t)value)
93 *(uint32_t *)code_ptr = value;
96 value -= (long)code_ptr;
97 if (value != (int32_t)value)
99 *(uint32_t *)code_ptr = value;
106 /* maximum number of register used for input function arguments */
107 static inline int tcg_target_get_call_iarg_regs_count(int flags)
112 /* parse target specific constraints */
113 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
120 ct->ct |= TCG_CT_REG;
121 tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
124 ct->ct |= TCG_CT_REG;
125 tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
128 ct->ct |= TCG_CT_REG;
129 tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
132 ct->ct |= TCG_CT_REG;
133 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
136 ct->ct |= TCG_CT_REG;
137 tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
140 ct->ct |= TCG_CT_REG;
141 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
144 ct->ct |= TCG_CT_REG;
145 tcg_regset_set32(ct->u.regs, 0, 0xf);
148 ct->ct |= TCG_CT_REG;
149 tcg_regset_set32(ct->u.regs, 0, 0xffff);
151 case 'L': /* qemu_ld/st constraint */
152 ct->ct |= TCG_CT_REG;
153 tcg_regset_set32(ct->u.regs, 0, 0xffff);
154 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
155 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
158 ct->ct |= TCG_CT_CONST_S32;
161 ct->ct |= TCG_CT_CONST_U32;
171 /* test if a constant matches the constraint */
172 static inline int tcg_target_const_match(tcg_target_long val,
173 const TCGArgConstraint *arg_ct)
177 if (ct & TCG_CT_CONST)
179 else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
181 else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
220 #define P_EXT 0x100 /* 0x0f opcode prefix */
221 #define P_REXW 0x200 /* set rex.w = 1 */
222 #define P_REXB 0x400 /* force rex use for byte registers */
224 static const uint8_t tcg_cond_to_jcc[10] = {
225 [TCG_COND_EQ] = JCC_JE,
226 [TCG_COND_NE] = JCC_JNE,
227 [TCG_COND_LT] = JCC_JL,
228 [TCG_COND_GE] = JCC_JGE,
229 [TCG_COND_LE] = JCC_JLE,
230 [TCG_COND_GT] = JCC_JG,
231 [TCG_COND_LTU] = JCC_JB,
232 [TCG_COND_GEU] = JCC_JAE,
233 [TCG_COND_LEU] = JCC_JBE,
234 [TCG_COND_GTU] = JCC_JA,
237 static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
240 rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) |
241 ((x >> 2) & 2) | ((rm >> 3) & 1);
242 if (rex || (opc & P_REXB)) {
243 tcg_out8(s, rex | 0x40);
247 tcg_out8(s, opc & 0xff);
250 static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
252 tcg_out_opc(s, opc, r, rm, 0);
253 tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
256 /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
257 static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
258 tcg_target_long offset)
262 tcg_out_opc(s, opc, r, 0, 0);
263 val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
264 if (val == (int32_t)val) {
266 tcg_out8(s, 0x05 | ((r & 7) << 3));
268 } else if (offset == (int32_t)offset) {
269 tcg_out8(s, 0x04 | ((r & 7) << 3));
270 tcg_out8(s, 0x25); /* sib */
271 tcg_out32(s, offset);
275 } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
276 tcg_out_opc(s, opc, r, rm, 0);
277 if ((rm & 7) == TCG_REG_RSP) {
278 tcg_out8(s, 0x04 | ((r & 7) << 3));
281 tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
283 } else if ((int8_t)offset == offset) {
284 tcg_out_opc(s, opc, r, rm, 0);
285 if ((rm & 7) == TCG_REG_RSP) {
286 tcg_out8(s, 0x44 | ((r & 7) << 3));
289 tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
293 tcg_out_opc(s, opc, r, rm, 0);
294 if ((rm & 7) == TCG_REG_RSP) {
295 tcg_out8(s, 0x84 | ((r & 7) << 3));
298 tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
300 tcg_out32(s, offset);
304 #if defined(CONFIG_SOFTMMU)
305 /* XXX: incomplete. index must be different from ESP */
306 static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
307 int index, int shift,
308 tcg_target_long offset)
313 if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
315 } else if (offset == (int8_t)offset) {
317 } else if (offset == (int32_t)offset) {
323 tcg_out_opc(s, opc, r, rm, 0);
324 if ((rm & 7) == TCG_REG_RSP) {
325 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
326 tcg_out8(s, 0x04 | (rm & 7));
328 tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
331 tcg_out_opc(s, opc, r, rm, index);
332 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
333 tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
337 } else if (mod == 0x80) {
338 tcg_out32(s, offset);
343 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
345 tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
348 static inline void tcg_out_movi(TCGContext *s, TCGType type,
349 int ret, tcg_target_long arg)
352 tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
353 } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
354 tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
356 } else if (arg == (int32_t)arg) {
357 tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
360 tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
362 tcg_out32(s, arg >> 32);
366 static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
367 int arg1, tcg_target_long arg2)
369 if (type == TCG_TYPE_I32)
370 tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
372 tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
375 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
376 int arg1, tcg_target_long arg2)
378 if (type == TCG_TYPE_I32)
379 tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
381 tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
384 static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
386 if (val == (int8_t)val) {
387 tcg_out_modrm(s, 0x83, c, r0);
389 } else if (c == ARITH_AND && val == 0xffu) {
391 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0);
392 } else if (c == ARITH_AND && val == 0xffffu) {
394 tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
396 tcg_out_modrm(s, 0x81, c, r0);
401 static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
403 if (val == (int8_t)val) {
404 tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
406 } else if (c == ARITH_AND && val == 0xffu) {
408 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
409 } else if (c == ARITH_AND && val == 0xffffu) {
411 tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
412 } else if (c == ARITH_AND && val == 0xffffffffu) {
413 /* 32-bit mov zero extends */
414 tcg_out_modrm(s, 0x8b, r0, r0);
415 } else if (val == (int32_t)val) {
416 tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
418 } else if (c == ARITH_AND && val == (uint32_t)val) {
419 tcg_out_modrm(s, 0x81, c, r0);
426 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
429 tgen_arithi64(s, ARITH_ADD, reg, val);
432 static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
435 TCGLabel *l = &s->labels[label_index];
438 val = l->u.value - (tcg_target_long)s->code_ptr;
440 if ((int8_t)val1 == val1) {
444 tcg_out8(s, 0x70 + opc);
449 tcg_out32(s, val - 5);
452 tcg_out8(s, 0x80 + opc);
453 tcg_out32(s, val - 6);
461 tcg_out8(s, 0x80 + opc);
463 tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
468 static void tcg_out_brcond(TCGContext *s, int cond,
469 TCGArg arg1, TCGArg arg2, int const_arg2,
470 int label_index, int rexw)
475 tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
478 tgen_arithi64(s, ARITH_CMP, arg1, arg2);
480 tgen_arithi32(s, ARITH_CMP, arg1, arg2);
483 tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
485 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
488 #if defined(CONFIG_SOFTMMU)
490 #include "../../softmmu_defs.h"
492 static void *qemu_ld_helpers[4] = {
499 static void *qemu_st_helpers[4] = {
507 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
510 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
511 #if defined(CONFIG_SOFTMMU)
512 uint8_t *label1_ptr, *label2_ptr;
523 #if TARGET_LONG_BITS == 32
528 #if defined(CONFIG_SOFTMMU)
530 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
533 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
535 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
536 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
538 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
539 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
541 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
542 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
544 /* lea offset(r1, env), r1 */
545 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
546 offsetof(CPUState, tlb_table[mem_index][0].addr_read));
549 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
552 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
555 tcg_out8(s, 0x70 + JCC_JE);
556 label1_ptr = s->code_ptr;
559 /* XXX: move that code at the end of the TB */
560 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
562 tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
563 (tcg_target_long)s->code_ptr - 4);
568 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
572 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
576 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
580 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
584 tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
589 tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
592 tcg_out_mov(s, data_reg, TCG_REG_RAX);
598 label2_ptr = s->code_ptr;
602 *label1_ptr = s->code_ptr - label1_ptr - 1;
605 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
606 offsetof(CPUTLBEntry, addr_read));
611 #ifdef TARGET_WORDS_BIGENDIAN
619 tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0);
623 tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, 0);
627 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
629 /* rolw $8, data_reg */
631 tcg_out_modrm(s, 0xc1, 0, data_reg);
638 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
639 /* rolw $8, data_reg */
641 tcg_out_modrm(s, 0xc1, 0, data_reg);
644 /* movswX data_reg, data_reg */
645 tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
648 tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, 0);
652 /* movl (r0), data_reg */
653 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
656 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
661 /* movl (r0), data_reg */
662 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
664 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
666 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
669 tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, 0);
673 /* movq (r0), data_reg */
674 tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, 0);
677 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
684 #if defined(CONFIG_SOFTMMU)
686 *label2_ptr = s->code_ptr - label2_ptr - 1;
690 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
693 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
694 #if defined(CONFIG_SOFTMMU)
695 uint8_t *label1_ptr, *label2_ptr;
707 #if TARGET_LONG_BITS == 32
712 #if defined(CONFIG_SOFTMMU)
714 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
717 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
719 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
720 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
722 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
723 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
725 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
726 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
728 /* lea offset(r1, env), r1 */
729 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
730 offsetof(CPUState, tlb_table[mem_index][0].addr_write));
733 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
736 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
739 tcg_out8(s, 0x70 + JCC_JE);
740 label1_ptr = s->code_ptr;
743 /* XXX: move that code at the end of the TB */
747 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg);
751 tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
755 tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
759 tcg_out_mov(s, TCG_REG_RSI, data_reg);
762 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
764 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
765 (tcg_target_long)s->code_ptr - 4);
769 label2_ptr = s->code_ptr;
773 *label1_ptr = s->code_ptr - label1_ptr - 1;
776 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
777 offsetof(CPUTLBEntry, addr_write));
782 #ifdef TARGET_WORDS_BIGENDIAN
790 tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, 0);
794 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
795 tcg_out8(s, 0x66); /* rolw $8, %ecx */
796 tcg_out_modrm(s, 0xc1, 0, r1);
802 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
806 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
808 tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
812 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
816 tcg_out_mov(s, r1, data_reg);
818 tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
822 tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, 0);
828 #if defined(CONFIG_SOFTMMU)
830 *label2_ptr = s->code_ptr - label2_ptr - 1;
834 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
835 const int *const_args)
840 case INDEX_op_exit_tb:
841 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
842 tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
843 tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
845 case INDEX_op_goto_tb:
846 if (s->tb_jmp_offset) {
847 /* direct jump method */
848 tcg_out8(s, 0xe9); /* jmp im */
849 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
852 /* indirect jump method */
854 tcg_out_modrm_offset(s, 0xff, 4, -1,
855 (tcg_target_long)(s->tb_next +
858 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
863 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
865 tcg_out_modrm(s, 0xff, 2, args[0]);
871 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
873 tcg_out_modrm(s, 0xff, 4, args[0]);
877 tcg_out_jxx(s, JCC_JMP, args[0]);
879 case INDEX_op_movi_i32:
880 tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
882 case INDEX_op_movi_i64:
883 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
885 case INDEX_op_ld8u_i32:
886 case INDEX_op_ld8u_i64:
888 tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
890 case INDEX_op_ld8s_i32:
892 tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
894 case INDEX_op_ld8s_i64:
896 tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
898 case INDEX_op_ld16u_i32:
899 case INDEX_op_ld16u_i64:
901 tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
903 case INDEX_op_ld16s_i32:
905 tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
907 case INDEX_op_ld16s_i64:
909 tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
911 case INDEX_op_ld_i32:
912 case INDEX_op_ld32u_i64:
914 tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
916 case INDEX_op_ld32s_i64:
918 tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
920 case INDEX_op_ld_i64:
922 tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
925 case INDEX_op_st8_i32:
926 case INDEX_op_st8_i64:
928 tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]);
930 case INDEX_op_st16_i32:
931 case INDEX_op_st16_i64:
934 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
936 case INDEX_op_st_i32:
937 case INDEX_op_st32_i64:
939 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
941 case INDEX_op_st_i64:
943 tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
946 case INDEX_op_sub_i32:
949 case INDEX_op_and_i32:
952 case INDEX_op_or_i32:
955 case INDEX_op_xor_i32:
958 case INDEX_op_add_i32:
962 tgen_arithi32(s, c, args[0], args[2]);
964 tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
968 case INDEX_op_sub_i64:
971 case INDEX_op_and_i64:
974 case INDEX_op_or_i64:
977 case INDEX_op_xor_i64:
980 case INDEX_op_add_i64:
984 tgen_arithi64(s, c, args[0], args[2]);
986 tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
990 case INDEX_op_mul_i32:
994 if (val == (int8_t)val) {
995 tcg_out_modrm(s, 0x6b, args[0], args[0]);
998 tcg_out_modrm(s, 0x69, args[0], args[0]);
1002 tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
1005 case INDEX_op_mul_i64:
1006 if (const_args[2]) {
1009 if (val == (int8_t)val) {
1010 tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
1013 tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
1017 tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
1020 case INDEX_op_div2_i32:
1021 tcg_out_modrm(s, 0xf7, 7, args[4]);
1023 case INDEX_op_divu2_i32:
1024 tcg_out_modrm(s, 0xf7, 6, args[4]);
1026 case INDEX_op_div2_i64:
1027 tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
1029 case INDEX_op_divu2_i64:
1030 tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
1033 case INDEX_op_shl_i32:
1036 if (const_args[2]) {
1038 tcg_out_modrm(s, 0xd1, c, args[0]);
1040 tcg_out_modrm(s, 0xc1, c, args[0]);
1041 tcg_out8(s, args[2]);
1044 tcg_out_modrm(s, 0xd3, c, args[0]);
1047 case INDEX_op_shr_i32:
1050 case INDEX_op_sar_i32:
1053 case INDEX_op_rotl_i32:
1056 case INDEX_op_rotr_i32:
1060 case INDEX_op_shl_i64:
1063 if (const_args[2]) {
1065 tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
1067 tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
1068 tcg_out8(s, args[2]);
1071 tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
1074 case INDEX_op_shr_i64:
1077 case INDEX_op_sar_i64:
1080 case INDEX_op_rotl_i64:
1083 case INDEX_op_rotr_i64:
1087 case INDEX_op_brcond_i32:
1088 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1091 case INDEX_op_brcond_i64:
1092 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1096 case INDEX_op_bswap16_i32:
1097 case INDEX_op_bswap16_i64:
1099 tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]);
1102 case INDEX_op_bswap32_i32:
1103 case INDEX_op_bswap32_i64:
1104 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
1106 case INDEX_op_bswap64_i64:
1107 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
1110 case INDEX_op_neg_i32:
1111 tcg_out_modrm(s, 0xf7, 3, args[0]);
1113 case INDEX_op_neg_i64:
1114 tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
1117 case INDEX_op_not_i32:
1118 tcg_out_modrm(s, 0xf7, 2, args[0]);
1120 case INDEX_op_not_i64:
1121 tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]);
1124 case INDEX_op_ext8s_i32:
1125 tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]);
1127 case INDEX_op_ext16s_i32:
1128 tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
1130 case INDEX_op_ext8s_i64:
1131 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]);
1133 case INDEX_op_ext16s_i64:
1134 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]);
1136 case INDEX_op_ext32s_i64:
1137 tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
1140 case INDEX_op_qemu_ld8u:
1141 tcg_out_qemu_ld(s, args, 0);
1143 case INDEX_op_qemu_ld8s:
1144 tcg_out_qemu_ld(s, args, 0 | 4);
1146 case INDEX_op_qemu_ld16u:
1147 tcg_out_qemu_ld(s, args, 1);
1149 case INDEX_op_qemu_ld16s:
1150 tcg_out_qemu_ld(s, args, 1 | 4);
1152 case INDEX_op_qemu_ld32u:
1153 tcg_out_qemu_ld(s, args, 2);
1155 case INDEX_op_qemu_ld32s:
1156 tcg_out_qemu_ld(s, args, 2 | 4);
1158 case INDEX_op_qemu_ld64:
1159 tcg_out_qemu_ld(s, args, 3);
1162 case INDEX_op_qemu_st8:
1163 tcg_out_qemu_st(s, args, 0);
1165 case INDEX_op_qemu_st16:
1166 tcg_out_qemu_st(s, args, 1);
1168 case INDEX_op_qemu_st32:
1169 tcg_out_qemu_st(s, args, 2);
1171 case INDEX_op_qemu_st64:
1172 tcg_out_qemu_st(s, args, 3);
1180 static int tcg_target_callee_save_regs[] = {
1185 /* TCG_REG_R14, */ /* currently used for the global env, so no
1190 static inline void tcg_out_push(TCGContext *s, int reg)
1192 tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
1195 static inline void tcg_out_pop(TCGContext *s, int reg)
1197 tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
1200 /* Generate global QEMU prologue and epilogue code */
1201 void tcg_target_qemu_prologue(TCGContext *s)
1203 int i, frame_size, push_size, stack_addend;
1206 /* save all callee saved registers */
1207 for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1208 tcg_out_push(s, tcg_target_callee_save_regs[i]);
1211 /* reserve some stack space */
1212 push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
1213 frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1214 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1215 ~(TCG_TARGET_STACK_ALIGN - 1);
1216 stack_addend = frame_size - push_size;
1217 tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
1219 tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */
1222 tb_ret_addr = s->code_ptr;
1223 tcg_out_addi(s, TCG_REG_RSP, stack_addend);
1224 for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1225 tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1227 tcg_out8(s, 0xc3); /* ret */
1230 static const TCGTargetOpDef x86_64_op_defs[] = {
1231 { INDEX_op_exit_tb, { } },
1232 { INDEX_op_goto_tb, { } },
1233 { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
1234 { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
1235 { INDEX_op_br, { } },
1237 { INDEX_op_mov_i32, { "r", "r" } },
1238 { INDEX_op_movi_i32, { "r" } },
1239 { INDEX_op_ld8u_i32, { "r", "r" } },
1240 { INDEX_op_ld8s_i32, { "r", "r" } },
1241 { INDEX_op_ld16u_i32, { "r", "r" } },
1242 { INDEX_op_ld16s_i32, { "r", "r" } },
1243 { INDEX_op_ld_i32, { "r", "r" } },
1244 { INDEX_op_st8_i32, { "r", "r" } },
1245 { INDEX_op_st16_i32, { "r", "r" } },
1246 { INDEX_op_st_i32, { "r", "r" } },
1248 { INDEX_op_add_i32, { "r", "0", "ri" } },
1249 { INDEX_op_mul_i32, { "r", "0", "ri" } },
1250 { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1251 { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1252 { INDEX_op_sub_i32, { "r", "0", "ri" } },
1253 { INDEX_op_and_i32, { "r", "0", "ri" } },
1254 { INDEX_op_or_i32, { "r", "0", "ri" } },
1255 { INDEX_op_xor_i32, { "r", "0", "ri" } },
1257 { INDEX_op_shl_i32, { "r", "0", "ci" } },
1258 { INDEX_op_shr_i32, { "r", "0", "ci" } },
1259 { INDEX_op_sar_i32, { "r", "0", "ci" } },
1260 { INDEX_op_rotl_i32, { "r", "0", "ci" } },
1261 { INDEX_op_rotr_i32, { "r", "0", "ci" } },
1263 { INDEX_op_brcond_i32, { "r", "ri" } },
1265 { INDEX_op_mov_i64, { "r", "r" } },
1266 { INDEX_op_movi_i64, { "r" } },
1267 { INDEX_op_ld8u_i64, { "r", "r" } },
1268 { INDEX_op_ld8s_i64, { "r", "r" } },
1269 { INDEX_op_ld16u_i64, { "r", "r" } },
1270 { INDEX_op_ld16s_i64, { "r", "r" } },
1271 { INDEX_op_ld32u_i64, { "r", "r" } },
1272 { INDEX_op_ld32s_i64, { "r", "r" } },
1273 { INDEX_op_ld_i64, { "r", "r" } },
1274 { INDEX_op_st8_i64, { "r", "r" } },
1275 { INDEX_op_st16_i64, { "r", "r" } },
1276 { INDEX_op_st32_i64, { "r", "r" } },
1277 { INDEX_op_st_i64, { "r", "r" } },
1279 { INDEX_op_add_i64, { "r", "0", "re" } },
1280 { INDEX_op_mul_i64, { "r", "0", "re" } },
1281 { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
1282 { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
1283 { INDEX_op_sub_i64, { "r", "0", "re" } },
1284 { INDEX_op_and_i64, { "r", "0", "reZ" } },
1285 { INDEX_op_or_i64, { "r", "0", "re" } },
1286 { INDEX_op_xor_i64, { "r", "0", "re" } },
1288 { INDEX_op_shl_i64, { "r", "0", "ci" } },
1289 { INDEX_op_shr_i64, { "r", "0", "ci" } },
1290 { INDEX_op_sar_i64, { "r", "0", "ci" } },
1291 { INDEX_op_rotl_i64, { "r", "0", "ci" } },
1292 { INDEX_op_rotr_i64, { "r", "0", "ci" } },
1294 { INDEX_op_brcond_i64, { "r", "re" } },
1296 { INDEX_op_bswap16_i32, { "r", "0" } },
1297 { INDEX_op_bswap16_i64, { "r", "0" } },
1298 { INDEX_op_bswap32_i32, { "r", "0" } },
1299 { INDEX_op_bswap32_i64, { "r", "0" } },
1300 { INDEX_op_bswap64_i64, { "r", "0" } },
1302 { INDEX_op_neg_i32, { "r", "0" } },
1303 { INDEX_op_neg_i64, { "r", "0" } },
1305 { INDEX_op_not_i32, { "r", "0" } },
1306 { INDEX_op_not_i64, { "r", "0" } },
1308 { INDEX_op_ext8s_i32, { "r", "r"} },
1309 { INDEX_op_ext16s_i32, { "r", "r"} },
1310 { INDEX_op_ext8s_i64, { "r", "r"} },
1311 { INDEX_op_ext16s_i64, { "r", "r"} },
1312 { INDEX_op_ext32s_i64, { "r", "r"} },
1314 { INDEX_op_qemu_ld8u, { "r", "L" } },
1315 { INDEX_op_qemu_ld8s, { "r", "L" } },
1316 { INDEX_op_qemu_ld16u, { "r", "L" } },
1317 { INDEX_op_qemu_ld16s, { "r", "L" } },
1318 { INDEX_op_qemu_ld32u, { "r", "L" } },
1319 { INDEX_op_qemu_ld32s, { "r", "L" } },
1320 { INDEX_op_qemu_ld64, { "r", "L" } },
1322 { INDEX_op_qemu_st8, { "L", "L" } },
1323 { INDEX_op_qemu_st16, { "L", "L" } },
1324 { INDEX_op_qemu_st32, { "L", "L" } },
1325 { INDEX_op_qemu_st64, { "L", "L", "L" } },
1330 void tcg_target_init(TCGContext *s)
1333 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1336 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1337 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
1338 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1339 (1 << TCG_REG_RDI) |
1340 (1 << TCG_REG_RSI) |
1341 (1 << TCG_REG_RDX) |
1342 (1 << TCG_REG_RCX) |
1345 (1 << TCG_REG_RAX) |
1346 (1 << TCG_REG_R10) |
1347 (1 << TCG_REG_R11));
1349 tcg_regset_clear(s->reserved_regs);
1350 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
1352 tcg_add_target_add_op_defs(x86_64_op_defs);