2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 static const int tcg_target_reg_alloc_order[] = {
64 static const int tcg_target_call_iarg_regs[6] = {
73 static const int tcg_target_call_oarg_regs[2] = {
78 static uint8_t *tb_ret_addr;
80 static void patch_reloc(uint8_t *code_ptr, int type,
81 tcg_target_long value, tcg_target_long addend)
86 if (value != (uint32_t)value)
88 *(uint32_t *)code_ptr = value;
91 if (value != (int32_t)value)
93 *(uint32_t *)code_ptr = value;
96 value -= (long)code_ptr;
97 if (value != (int32_t)value)
99 *(uint32_t *)code_ptr = value;
106 /* maximum number of register used for input function arguments */
107 static inline int tcg_target_get_call_iarg_regs_count(int flags)
112 /* parse target specific constraints */
113 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
120 ct->ct |= TCG_CT_REG;
121 tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
124 ct->ct |= TCG_CT_REG;
125 tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
128 ct->ct |= TCG_CT_REG;
129 tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
132 ct->ct |= TCG_CT_REG;
133 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
136 ct->ct |= TCG_CT_REG;
137 tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
140 ct->ct |= TCG_CT_REG;
141 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
144 ct->ct |= TCG_CT_REG;
145 tcg_regset_set32(ct->u.regs, 0, 0xf);
148 ct->ct |= TCG_CT_REG;
149 tcg_regset_set32(ct->u.regs, 0, 0xffff);
151 case 'L': /* qemu_ld/st constraint */
152 ct->ct |= TCG_CT_REG;
153 tcg_regset_set32(ct->u.regs, 0, 0xffff);
154 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
155 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
158 ct->ct |= TCG_CT_CONST_S32;
161 ct->ct |= TCG_CT_CONST_U32;
171 /* test if a constant matches the constraint */
172 static inline int tcg_target_const_match(tcg_target_long val,
173 const TCGArgConstraint *arg_ct)
177 if (ct & TCG_CT_CONST)
179 else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
181 else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
220 #define P_EXT 0x100 /* 0x0f opcode prefix */
221 #define P_REXW 0x200 /* set rex.w = 1 */
222 #define P_REXB 0x400 /* force rex use for byte registers */
224 static const uint8_t tcg_cond_to_jcc[10] = {
225 [TCG_COND_EQ] = JCC_JE,
226 [TCG_COND_NE] = JCC_JNE,
227 [TCG_COND_LT] = JCC_JL,
228 [TCG_COND_GE] = JCC_JGE,
229 [TCG_COND_LE] = JCC_JLE,
230 [TCG_COND_GT] = JCC_JG,
231 [TCG_COND_LTU] = JCC_JB,
232 [TCG_COND_GEU] = JCC_JAE,
233 [TCG_COND_LEU] = JCC_JBE,
234 [TCG_COND_GTU] = JCC_JA,
237 static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
240 rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) |
241 ((x >> 2) & 2) | ((rm >> 3) & 1);
242 if (rex || (opc & P_REXB)) {
243 tcg_out8(s, rex | 0x40);
247 tcg_out8(s, opc & 0xff);
250 static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
252 tcg_out_opc(s, opc, r, rm, 0);
253 tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
256 /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
257 static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
258 tcg_target_long offset)
262 tcg_out_opc(s, opc, r, 0, 0);
263 val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
264 if (val == (int32_t)val) {
266 tcg_out8(s, 0x05 | ((r & 7) << 3));
268 } else if (offset == (int32_t)offset) {
269 tcg_out8(s, 0x04 | ((r & 7) << 3));
270 tcg_out8(s, 0x25); /* sib */
271 tcg_out32(s, offset);
275 } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
276 tcg_out_opc(s, opc, r, rm, 0);
277 if ((rm & 7) == TCG_REG_RSP) {
278 tcg_out8(s, 0x04 | ((r & 7) << 3));
281 tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
283 } else if ((int8_t)offset == offset) {
284 tcg_out_opc(s, opc, r, rm, 0);
285 if ((rm & 7) == TCG_REG_RSP) {
286 tcg_out8(s, 0x44 | ((r & 7) << 3));
289 tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
293 tcg_out_opc(s, opc, r, rm, 0);
294 if ((rm & 7) == TCG_REG_RSP) {
295 tcg_out8(s, 0x84 | ((r & 7) << 3));
298 tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
300 tcg_out32(s, offset);
304 #if defined(CONFIG_SOFTMMU)
305 /* XXX: incomplete. index must be different from ESP */
306 static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
307 int index, int shift,
308 tcg_target_long offset)
313 if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
315 } else if (offset == (int8_t)offset) {
317 } else if (offset == (int32_t)offset) {
323 tcg_out_opc(s, opc, r, rm, 0);
324 if ((rm & 7) == TCG_REG_RSP) {
325 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
326 tcg_out8(s, 0x04 | (rm & 7));
328 tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
331 tcg_out_opc(s, opc, r, rm, index);
332 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
333 tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
337 } else if (mod == 0x80) {
338 tcg_out32(s, offset);
343 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
345 tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
348 static inline void tcg_out_movi(TCGContext *s, TCGType type,
349 int ret, tcg_target_long arg)
352 tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
353 } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
354 tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
356 } else if (arg == (int32_t)arg) {
357 tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
360 tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
362 tcg_out32(s, arg >> 32);
366 static void tcg_out_goto(TCGContext *s, int call, uint8_t *target)
370 disp = target - s->code_ptr - 5;
371 if (disp == (target - s->code_ptr - 5)) {
372 tcg_out8(s, call ? 0xe8 : 0xe9);
375 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R10, (tcg_target_long) target);
376 tcg_out_modrm(s, 0xff, call ? 2 : 4, TCG_REG_R10);
380 static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
381 int arg1, tcg_target_long arg2)
383 if (type == TCG_TYPE_I32)
384 tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
386 tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
389 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
390 int arg1, tcg_target_long arg2)
392 if (type == TCG_TYPE_I32)
393 tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
395 tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
398 static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
400 if (val == (int8_t)val) {
401 tcg_out_modrm(s, 0x83, c, r0);
403 } else if (c == ARITH_AND && val == 0xffu) {
405 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0);
406 } else if (c == ARITH_AND && val == 0xffffu) {
408 tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
410 tcg_out_modrm(s, 0x81, c, r0);
415 static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
417 if (val == (int8_t)val) {
418 tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
420 } else if (c == ARITH_AND && val == 0xffu) {
422 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
423 } else if (c == ARITH_AND && val == 0xffffu) {
425 tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
426 } else if (c == ARITH_AND && val == 0xffffffffu) {
427 /* 32-bit mov zero extends */
428 tcg_out_modrm(s, 0x8b, r0, r0);
429 } else if (val == (int32_t)val) {
430 tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
432 } else if (c == ARITH_AND && val == (uint32_t)val) {
433 tcg_out_modrm(s, 0x81, c, r0);
440 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
443 tgen_arithi64(s, ARITH_ADD, reg, val);
446 static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
449 TCGLabel *l = &s->labels[label_index];
452 val = l->u.value - (tcg_target_long)s->code_ptr;
454 if ((int8_t)val1 == val1) {
458 tcg_out8(s, 0x70 + opc);
463 tcg_out32(s, val - 5);
466 tcg_out8(s, 0x80 + opc);
467 tcg_out32(s, val - 6);
475 tcg_out8(s, 0x80 + opc);
477 tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
482 static void tcg_out_brcond(TCGContext *s, int cond,
483 TCGArg arg1, TCGArg arg2, int const_arg2,
484 int label_index, int rexw)
489 tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
492 tgen_arithi64(s, ARITH_CMP, arg1, arg2);
494 tgen_arithi32(s, ARITH_CMP, arg1, arg2);
497 tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
499 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
502 #if defined(CONFIG_SOFTMMU)
504 #include "../../softmmu_defs.h"
506 static void *qemu_ld_helpers[4] = {
513 static void *qemu_st_helpers[4] = {
521 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
524 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
526 #if defined(CONFIG_SOFTMMU)
527 uint8_t *label1_ptr, *label2_ptr;
538 #if TARGET_LONG_BITS == 32
543 #if defined(CONFIG_SOFTMMU)
545 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
548 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
550 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
551 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
553 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
554 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
556 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
557 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
559 /* lea offset(r1, env), r1 */
560 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
561 offsetof(CPUState, tlb_table[mem_index][0].addr_read));
564 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
567 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
570 tcg_out8(s, 0x70 + JCC_JE);
571 label1_ptr = s->code_ptr;
574 /* XXX: move that code at the end of the TB */
575 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
576 tcg_out_goto(s, 1, qemu_ld_helpers[s_bits]);
581 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
585 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
589 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
593 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
597 tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
602 tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
605 tcg_out_mov(s, data_reg, TCG_REG_RAX);
611 label2_ptr = s->code_ptr;
615 *label1_ptr = s->code_ptr - label1_ptr - 1;
618 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
619 offsetof(CPUTLBEntry, addr_read));
622 if (GUEST_BASE == (int32_t)GUEST_BASE) {
627 /* movq $GUEST_BASE, r0 */
628 tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0);
629 tcg_out32(s, GUEST_BASE);
630 tcg_out32(s, GUEST_BASE >> 32);
631 /* addq addr_reg, r0 */
632 tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
636 #ifdef TARGET_WORDS_BIGENDIAN
644 tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, offset);
648 tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, offset);
652 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
654 /* rolw $8, data_reg */
656 tcg_out_modrm(s, 0xc1, 0, data_reg);
663 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
664 /* rolw $8, data_reg */
666 tcg_out_modrm(s, 0xc1, 0, data_reg);
669 /* movswX data_reg, data_reg */
670 tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
673 tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, offset);
677 /* movl (r0), data_reg */
678 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
681 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
686 /* movl (r0), data_reg */
687 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
689 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
691 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
694 tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, offset);
698 /* movq (r0), data_reg */
699 tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, offset);
702 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
709 #if defined(CONFIG_SOFTMMU)
711 *label2_ptr = s->code_ptr - label2_ptr - 1;
715 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
718 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
720 #if defined(CONFIG_SOFTMMU)
721 uint8_t *label1_ptr, *label2_ptr;
733 #if TARGET_LONG_BITS == 32
738 #if defined(CONFIG_SOFTMMU)
740 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
743 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
745 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
746 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
748 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
749 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
751 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
752 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
754 /* lea offset(r1, env), r1 */
755 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
756 offsetof(CPUState, tlb_table[mem_index][0].addr_write));
759 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
762 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
765 tcg_out8(s, 0x70 + JCC_JE);
766 label1_ptr = s->code_ptr;
769 /* XXX: move that code at the end of the TB */
773 tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg);
777 tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
781 tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
785 tcg_out_mov(s, TCG_REG_RSI, data_reg);
788 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
789 tcg_out_goto(s, 1, qemu_st_helpers[s_bits]);
793 label2_ptr = s->code_ptr;
797 *label1_ptr = s->code_ptr - label1_ptr - 1;
800 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
801 offsetof(CPUTLBEntry, addr_write));
804 if (GUEST_BASE == (int32_t)GUEST_BASE) {
809 /* movq $GUEST_BASE, r0 */
810 tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0);
811 tcg_out32(s, GUEST_BASE);
812 tcg_out32(s, GUEST_BASE >> 32);
813 /* addq addr_reg, r0 */
814 tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
818 #ifdef TARGET_WORDS_BIGENDIAN
826 tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, offset);
830 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
831 tcg_out8(s, 0x66); /* rolw $8, %ecx */
832 tcg_out_modrm(s, 0xc1, 0, r1);
838 tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
842 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
844 tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
848 tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
852 tcg_out_mov(s, r1, data_reg);
854 tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
858 tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, offset);
864 #if defined(CONFIG_SOFTMMU)
866 *label2_ptr = s->code_ptr - label2_ptr - 1;
870 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
871 const int *const_args)
876 case INDEX_op_exit_tb:
877 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
878 tcg_out_goto(s, 0, tb_ret_addr);
880 case INDEX_op_goto_tb:
881 if (s->tb_jmp_offset) {
882 /* direct jump method */
883 tcg_out8(s, 0xe9); /* jmp im */
884 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
887 /* indirect jump method */
889 tcg_out_modrm_offset(s, 0xff, 4, -1,
890 (tcg_target_long)(s->tb_next +
893 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
897 tcg_out_goto(s, 1, (void *) args[0]);
899 tcg_out_modrm(s, 0xff, 2, args[0]);
904 tcg_out_goto(s, 0, (void *) args[0]);
906 tcg_out_modrm(s, 0xff, 4, args[0]);
910 tcg_out_jxx(s, JCC_JMP, args[0]);
912 case INDEX_op_movi_i32:
913 tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
915 case INDEX_op_movi_i64:
916 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
918 case INDEX_op_ld8u_i32:
919 case INDEX_op_ld8u_i64:
921 tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
923 case INDEX_op_ld8s_i32:
925 tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
927 case INDEX_op_ld8s_i64:
929 tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
931 case INDEX_op_ld16u_i32:
932 case INDEX_op_ld16u_i64:
934 tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
936 case INDEX_op_ld16s_i32:
938 tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
940 case INDEX_op_ld16s_i64:
942 tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
944 case INDEX_op_ld_i32:
945 case INDEX_op_ld32u_i64:
947 tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
949 case INDEX_op_ld32s_i64:
951 tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
953 case INDEX_op_ld_i64:
955 tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
958 case INDEX_op_st8_i32:
959 case INDEX_op_st8_i64:
961 tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]);
963 case INDEX_op_st16_i32:
964 case INDEX_op_st16_i64:
967 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
969 case INDEX_op_st_i32:
970 case INDEX_op_st32_i64:
972 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
974 case INDEX_op_st_i64:
976 tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
979 case INDEX_op_sub_i32:
982 case INDEX_op_and_i32:
985 case INDEX_op_or_i32:
988 case INDEX_op_xor_i32:
991 case INDEX_op_add_i32:
995 tgen_arithi32(s, c, args[0], args[2]);
997 tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
1001 case INDEX_op_sub_i64:
1004 case INDEX_op_and_i64:
1007 case INDEX_op_or_i64:
1010 case INDEX_op_xor_i64:
1013 case INDEX_op_add_i64:
1016 if (const_args[2]) {
1017 tgen_arithi64(s, c, args[0], args[2]);
1019 tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
1023 case INDEX_op_mul_i32:
1024 if (const_args[2]) {
1027 if (val == (int8_t)val) {
1028 tcg_out_modrm(s, 0x6b, args[0], args[0]);
1031 tcg_out_modrm(s, 0x69, args[0], args[0]);
1035 tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
1038 case INDEX_op_mul_i64:
1039 if (const_args[2]) {
1042 if (val == (int8_t)val) {
1043 tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
1046 tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
1050 tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
1053 case INDEX_op_div2_i32:
1054 tcg_out_modrm(s, 0xf7, 7, args[4]);
1056 case INDEX_op_divu2_i32:
1057 tcg_out_modrm(s, 0xf7, 6, args[4]);
1059 case INDEX_op_div2_i64:
1060 tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
1062 case INDEX_op_divu2_i64:
1063 tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
1066 case INDEX_op_shl_i32:
1069 if (const_args[2]) {
1071 tcg_out_modrm(s, 0xd1, c, args[0]);
1073 tcg_out_modrm(s, 0xc1, c, args[0]);
1074 tcg_out8(s, args[2]);
1077 tcg_out_modrm(s, 0xd3, c, args[0]);
1080 case INDEX_op_shr_i32:
1083 case INDEX_op_sar_i32:
1086 case INDEX_op_rotl_i32:
1089 case INDEX_op_rotr_i32:
1093 case INDEX_op_shl_i64:
1096 if (const_args[2]) {
1098 tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
1100 tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
1101 tcg_out8(s, args[2]);
1104 tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
1107 case INDEX_op_shr_i64:
1110 case INDEX_op_sar_i64:
1113 case INDEX_op_rotl_i64:
1116 case INDEX_op_rotr_i64:
1120 case INDEX_op_brcond_i32:
1121 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1124 case INDEX_op_brcond_i64:
1125 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1129 case INDEX_op_bswap16_i32:
1130 case INDEX_op_bswap16_i64:
1132 tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]);
1135 case INDEX_op_bswap32_i32:
1136 case INDEX_op_bswap32_i64:
1137 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
1139 case INDEX_op_bswap64_i64:
1140 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
1143 case INDEX_op_neg_i32:
1144 tcg_out_modrm(s, 0xf7, 3, args[0]);
1146 case INDEX_op_neg_i64:
1147 tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
1150 case INDEX_op_not_i32:
1151 tcg_out_modrm(s, 0xf7, 2, args[0]);
1153 case INDEX_op_not_i64:
1154 tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]);
1157 case INDEX_op_ext8s_i32:
1158 tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]);
1160 case INDEX_op_ext16s_i32:
1161 tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
1163 case INDEX_op_ext8s_i64:
1164 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]);
1166 case INDEX_op_ext16s_i64:
1167 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]);
1169 case INDEX_op_ext32s_i64:
1170 tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
1173 case INDEX_op_qemu_ld8u:
1174 tcg_out_qemu_ld(s, args, 0);
1176 case INDEX_op_qemu_ld8s:
1177 tcg_out_qemu_ld(s, args, 0 | 4);
1179 case INDEX_op_qemu_ld16u:
1180 tcg_out_qemu_ld(s, args, 1);
1182 case INDEX_op_qemu_ld16s:
1183 tcg_out_qemu_ld(s, args, 1 | 4);
1185 case INDEX_op_qemu_ld32u:
1186 tcg_out_qemu_ld(s, args, 2);
1188 case INDEX_op_qemu_ld32s:
1189 tcg_out_qemu_ld(s, args, 2 | 4);
1191 case INDEX_op_qemu_ld64:
1192 tcg_out_qemu_ld(s, args, 3);
1195 case INDEX_op_qemu_st8:
1196 tcg_out_qemu_st(s, args, 0);
1198 case INDEX_op_qemu_st16:
1199 tcg_out_qemu_st(s, args, 1);
1201 case INDEX_op_qemu_st32:
1202 tcg_out_qemu_st(s, args, 2);
1204 case INDEX_op_qemu_st64:
1205 tcg_out_qemu_st(s, args, 3);
1213 static int tcg_target_callee_save_regs[] = {
1218 /* TCG_REG_R14, */ /* currently used for the global env, so no
1223 static inline void tcg_out_push(TCGContext *s, int reg)
1225 tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
1228 static inline void tcg_out_pop(TCGContext *s, int reg)
1230 tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
1233 /* Generate global QEMU prologue and epilogue code */
1234 void tcg_target_qemu_prologue(TCGContext *s)
1236 int i, frame_size, push_size, stack_addend;
1239 /* save all callee saved registers */
1240 for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1241 tcg_out_push(s, tcg_target_callee_save_regs[i]);
1244 /* reserve some stack space */
1245 push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
1246 frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1247 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1248 ~(TCG_TARGET_STACK_ALIGN - 1);
1249 stack_addend = frame_size - push_size;
1250 tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
1252 tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */
1255 tb_ret_addr = s->code_ptr;
1256 tcg_out_addi(s, TCG_REG_RSP, stack_addend);
1257 for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1258 tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1260 tcg_out8(s, 0xc3); /* ret */
1263 static const TCGTargetOpDef x86_64_op_defs[] = {
1264 { INDEX_op_exit_tb, { } },
1265 { INDEX_op_goto_tb, { } },
1266 { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
1267 { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
1268 { INDEX_op_br, { } },
1270 { INDEX_op_mov_i32, { "r", "r" } },
1271 { INDEX_op_movi_i32, { "r" } },
1272 { INDEX_op_ld8u_i32, { "r", "r" } },
1273 { INDEX_op_ld8s_i32, { "r", "r" } },
1274 { INDEX_op_ld16u_i32, { "r", "r" } },
1275 { INDEX_op_ld16s_i32, { "r", "r" } },
1276 { INDEX_op_ld_i32, { "r", "r" } },
1277 { INDEX_op_st8_i32, { "r", "r" } },
1278 { INDEX_op_st16_i32, { "r", "r" } },
1279 { INDEX_op_st_i32, { "r", "r" } },
1281 { INDEX_op_add_i32, { "r", "0", "ri" } },
1282 { INDEX_op_mul_i32, { "r", "0", "ri" } },
1283 { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1284 { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1285 { INDEX_op_sub_i32, { "r", "0", "ri" } },
1286 { INDEX_op_and_i32, { "r", "0", "ri" } },
1287 { INDEX_op_or_i32, { "r", "0", "ri" } },
1288 { INDEX_op_xor_i32, { "r", "0", "ri" } },
1290 { INDEX_op_shl_i32, { "r", "0", "ci" } },
1291 { INDEX_op_shr_i32, { "r", "0", "ci" } },
1292 { INDEX_op_sar_i32, { "r", "0", "ci" } },
1293 { INDEX_op_rotl_i32, { "r", "0", "ci" } },
1294 { INDEX_op_rotr_i32, { "r", "0", "ci" } },
1296 { INDEX_op_brcond_i32, { "r", "ri" } },
1298 { INDEX_op_mov_i64, { "r", "r" } },
1299 { INDEX_op_movi_i64, { "r" } },
1300 { INDEX_op_ld8u_i64, { "r", "r" } },
1301 { INDEX_op_ld8s_i64, { "r", "r" } },
1302 { INDEX_op_ld16u_i64, { "r", "r" } },
1303 { INDEX_op_ld16s_i64, { "r", "r" } },
1304 { INDEX_op_ld32u_i64, { "r", "r" } },
1305 { INDEX_op_ld32s_i64, { "r", "r" } },
1306 { INDEX_op_ld_i64, { "r", "r" } },
1307 { INDEX_op_st8_i64, { "r", "r" } },
1308 { INDEX_op_st16_i64, { "r", "r" } },
1309 { INDEX_op_st32_i64, { "r", "r" } },
1310 { INDEX_op_st_i64, { "r", "r" } },
1312 { INDEX_op_add_i64, { "r", "0", "re" } },
1313 { INDEX_op_mul_i64, { "r", "0", "re" } },
1314 { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
1315 { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
1316 { INDEX_op_sub_i64, { "r", "0", "re" } },
1317 { INDEX_op_and_i64, { "r", "0", "reZ" } },
1318 { INDEX_op_or_i64, { "r", "0", "re" } },
1319 { INDEX_op_xor_i64, { "r", "0", "re" } },
1321 { INDEX_op_shl_i64, { "r", "0", "ci" } },
1322 { INDEX_op_shr_i64, { "r", "0", "ci" } },
1323 { INDEX_op_sar_i64, { "r", "0", "ci" } },
1324 { INDEX_op_rotl_i64, { "r", "0", "ci" } },
1325 { INDEX_op_rotr_i64, { "r", "0", "ci" } },
1327 { INDEX_op_brcond_i64, { "r", "re" } },
1329 { INDEX_op_bswap16_i32, { "r", "0" } },
1330 { INDEX_op_bswap16_i64, { "r", "0" } },
1331 { INDEX_op_bswap32_i32, { "r", "0" } },
1332 { INDEX_op_bswap32_i64, { "r", "0" } },
1333 { INDEX_op_bswap64_i64, { "r", "0" } },
1335 { INDEX_op_neg_i32, { "r", "0" } },
1336 { INDEX_op_neg_i64, { "r", "0" } },
1338 { INDEX_op_not_i32, { "r", "0" } },
1339 { INDEX_op_not_i64, { "r", "0" } },
1341 { INDEX_op_ext8s_i32, { "r", "r"} },
1342 { INDEX_op_ext16s_i32, { "r", "r"} },
1343 { INDEX_op_ext8s_i64, { "r", "r"} },
1344 { INDEX_op_ext16s_i64, { "r", "r"} },
1345 { INDEX_op_ext32s_i64, { "r", "r"} },
1347 { INDEX_op_qemu_ld8u, { "r", "L" } },
1348 { INDEX_op_qemu_ld8s, { "r", "L" } },
1349 { INDEX_op_qemu_ld16u, { "r", "L" } },
1350 { INDEX_op_qemu_ld16s, { "r", "L" } },
1351 { INDEX_op_qemu_ld32u, { "r", "L" } },
1352 { INDEX_op_qemu_ld32s, { "r", "L" } },
1353 { INDEX_op_qemu_ld64, { "r", "L" } },
1355 { INDEX_op_qemu_st8, { "L", "L" } },
1356 { INDEX_op_qemu_st16, { "L", "L" } },
1357 { INDEX_op_qemu_st32, { "L", "L" } },
1358 { INDEX_op_qemu_st64, { "L", "L", "L" } },
1363 void tcg_target_init(TCGContext *s)
1366 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1369 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1370 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
1371 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1372 (1 << TCG_REG_RDI) |
1373 (1 << TCG_REG_RSI) |
1374 (1 << TCG_REG_RDX) |
1375 (1 << TCG_REG_RCX) |
1378 (1 << TCG_REG_RAX) |
1379 (1 << TCG_REG_R10) |
1380 (1 << TCG_REG_R11));
1382 tcg_regset_clear(s->reserved_regs);
1383 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
1385 tcg_add_target_add_op_defs(x86_64_op_defs);