2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
43 int tcg_target_reg_alloc_order[TCG_TARGET_NB_REGS] = {
62 const int tcg_target_call_iarg_regs[6] = {
71 const int tcg_target_call_oarg_regs[2] = {
76 static void patch_reloc(uint8_t *code_ptr, int type,
77 tcg_target_long value)
81 if (value != (uint32_t)value)
83 *(uint32_t *)code_ptr = value;
86 if (value != (int32_t)value)
88 *(uint32_t *)code_ptr = value;
91 value -= (long)code_ptr;
92 if (value != (int32_t)value)
94 *(uint32_t *)code_ptr = value;
101 /* maximum number of register used for input function arguments */
102 static inline int tcg_target_get_call_iarg_regs_count(int flags)
107 /* parse target specific constraints */
108 int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
115 ct->ct |= TCG_CT_REG;
116 tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
119 ct->ct |= TCG_CT_REG;
120 tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
123 ct->ct |= TCG_CT_REG;
124 tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
127 ct->ct |= TCG_CT_REG;
128 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
131 ct->ct |= TCG_CT_REG;
132 tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
135 ct->ct |= TCG_CT_REG;
136 tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
139 ct->ct |= TCG_CT_REG;
140 tcg_regset_set32(ct->u.regs, 0, 0xf);
143 ct->ct |= TCG_CT_REG;
144 tcg_regset_set32(ct->u.regs, 0, 0xffff);
146 case 'L': /* qemu_ld/st constraint */
147 ct->ct |= TCG_CT_REG;
148 tcg_regset_set32(ct->u.regs, 0, 0xffff);
149 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
150 tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
153 ct->ct |= TCG_CT_CONST_S32;
156 ct->ct |= TCG_CT_CONST_U32;
166 /* test if a constant matches the constraint */
167 static inline int tcg_target_const_match(tcg_target_long val,
168 const TCGArgConstraint *arg_ct)
172 if (ct & TCG_CT_CONST)
174 else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
176 else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
213 #define P_EXT 0x100 /* 0x0f opcode prefix */
214 #define P_REXW 0x200 /* set rex.w = 1 */
215 #define P_REX 0x400 /* force rex usage */
217 static const uint8_t tcg_cond_to_jcc[10] = {
218 [TCG_COND_EQ] = JCC_JE,
219 [TCG_COND_NE] = JCC_JNE,
220 [TCG_COND_LT] = JCC_JL,
221 [TCG_COND_GE] = JCC_JGE,
222 [TCG_COND_LE] = JCC_JLE,
223 [TCG_COND_GT] = JCC_JG,
224 [TCG_COND_LTU] = JCC_JB,
225 [TCG_COND_GEU] = JCC_JAE,
226 [TCG_COND_LEU] = JCC_JBE,
227 [TCG_COND_GTU] = JCC_JA,
230 static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
233 rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) |
234 ((x >> 2) & 2) | ((rm >> 3) & 1);
235 if (rex || (opc & P_REX)) {
236 tcg_out8(s, rex | 0x40);
243 static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
245 tcg_out_opc(s, opc, r, rm, 0);
246 tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
249 /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
250 static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
251 tcg_target_long offset)
255 tcg_out_opc(s, opc, r, 0, 0);
256 val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
257 if (val == (int32_t)val) {
259 tcg_out8(s, 0x05 | ((r & 7) << 3));
261 } else if (offset == (int32_t)offset) {
262 tcg_out8(s, 0x04 | ((r & 7) << 3));
263 tcg_out8(s, 0x25); /* sib */
264 tcg_out32(s, offset);
268 } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
269 tcg_out_opc(s, opc, r, rm, 0);
270 if ((rm & 7) == TCG_REG_RSP) {
271 tcg_out8(s, 0x04 | ((r & 7) << 3));
274 tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
276 } else if ((int8_t)offset == offset) {
277 tcg_out_opc(s, opc, r, rm, 0);
278 if ((rm & 7) == TCG_REG_RSP) {
279 tcg_out8(s, 0x44 | ((r & 7) << 3));
282 tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
286 tcg_out_opc(s, opc, r, rm, 0);
287 if ((rm & 7) == TCG_REG_RSP) {
288 tcg_out8(s, 0x84 | ((r & 7) << 3));
291 tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
293 tcg_out32(s, offset);
297 /* XXX: incomplete. index must be different from ESP */
298 static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
299 int index, int shift,
300 tcg_target_long offset)
305 if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
307 } else if (offset == (int8_t)offset) {
309 } else if (offset == (int32_t)offset) {
315 tcg_out_opc(s, opc, r, rm, 0);
316 if ((rm & 7) == TCG_REG_RSP) {
317 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
318 tcg_out8(s, 0x04 | (rm & 7));
320 tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
323 tcg_out_opc(s, opc, r, rm, index);
324 tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
325 tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
329 } else if (mod == 0x80) {
330 tcg_out32(s, offset);
334 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
336 tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
339 static inline void tcg_out_movi(TCGContext *s, TCGType type,
340 int ret, tcg_target_long arg)
343 tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
344 } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
345 tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
347 } else if (arg == (int32_t)arg) {
348 tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
351 tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
353 tcg_out32(s, arg >> 32);
357 static inline void tcg_out_ld(TCGContext *s, int ret,
358 int arg1, tcg_target_long arg2)
360 tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
363 static inline void tcg_out_st(TCGContext *s, int arg,
364 int arg1, tcg_target_long arg2)
366 tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
369 static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
371 if (val == (int8_t)val) {
372 tcg_out_modrm(s, 0x83, c, r0);
375 tcg_out_modrm(s, 0x81, c, r0);
380 static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
382 if (val == (int8_t)val) {
383 tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
385 } else if (val == (int32_t)val) {
386 tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
388 } else if (c == ARITH_AND && val == (uint32_t)val) {
389 tcg_out_modrm(s, 0x81, c, r0);
396 void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
399 tgen_arithi64(s, ARITH_ADD, reg, val);
402 static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
405 TCGLabel *l = &s->labels[label_index];
408 val = l->u.value - (tcg_target_long)s->code_ptr;
410 if ((int8_t)val1 == val1) {
414 tcg_out8(s, 0x70 + opc);
419 tcg_out32(s, val - 5);
422 tcg_out8(s, 0x80 + opc);
423 tcg_out32(s, val - 6);
431 tcg_out8(s, 0x80 + opc);
433 tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
438 static void tcg_out_brcond(TCGContext *s, int cond,
439 TCGArg arg1, TCGArg arg2, int const_arg2,
440 int label_index, int rexw)
463 tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
464 tcg_out_jxx(s, c, label_index);
468 tgen_arithi64(s, ARITH_CMP, arg1, arg2);
470 tgen_arithi32(s, ARITH_CMP, arg1, arg2);
471 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
474 tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
475 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
479 #if defined(CONFIG_SOFTMMU)
480 extern void __ldb_mmu(void);
481 extern void __ldw_mmu(void);
482 extern void __ldl_mmu(void);
483 extern void __ldq_mmu(void);
485 extern void __stb_mmu(void);
486 extern void __stw_mmu(void);
487 extern void __stl_mmu(void);
488 extern void __stq_mmu(void);
491 static void *qemu_ld_helpers[4] = {
498 static void *qemu_st_helpers[4] = {
506 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
509 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
510 #if defined(CONFIG_SOFTMMU)
511 uint8_t *label1_ptr, *label2_ptr;
522 #if TARGET_LONG_BITS == 32
527 #if defined(CONFIG_SOFTMMU)
529 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
532 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
534 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
535 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
537 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
538 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
540 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
541 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
543 /* lea offset(r1, env), r1 */
544 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
545 offsetof(CPUState, tlb_table[mem_index][0].addr_read));
548 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
551 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
554 tcg_out8(s, 0x70 + JCC_JE);
555 label1_ptr = s->code_ptr;
558 /* XXX: move that code at the end of the TB */
559 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
561 tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
562 (tcg_target_long)s->code_ptr - 4);
567 tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
571 tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
575 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
582 tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
585 tcg_out_mov(s, data_reg, TCG_REG_RAX);
591 label2_ptr = s->code_ptr;
595 *label1_ptr = s->code_ptr - label1_ptr - 1;
598 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
599 offsetof(CPUTLBEntry, addr_read));
604 #ifdef TARGET_WORDS_BIGENDIAN
612 tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0);
616 tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, 0);
620 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
622 /* rolw $8, data_reg */
624 tcg_out_modrm(s, 0xc1, 0, data_reg);
631 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
632 /* rolw $8, data_reg */
634 tcg_out_modrm(s, 0xc1, 0, data_reg);
637 /* movswX data_reg, data_reg */
638 tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
641 tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, 0);
645 /* movl (r0), data_reg */
646 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
649 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
654 /* movl (r0), data_reg */
655 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
657 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
659 tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
662 tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, 0);
666 /* movq (r0), data_reg */
667 tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, 0);
670 tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
677 #if defined(CONFIG_SOFTMMU)
679 *label2_ptr = s->code_ptr - label2_ptr - 1;
683 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
686 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
687 #if defined(CONFIG_SOFTMMU)
688 uint8_t *label1_ptr, *label2_ptr;
700 #if TARGET_LONG_BITS == 32
705 #if defined(CONFIG_SOFTMMU)
707 tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
710 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
712 tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
713 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
715 tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
716 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
718 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
719 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
721 /* lea offset(r1, env), r1 */
722 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
723 offsetof(CPUState, tlb_table[mem_index][0].addr_write));
726 tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
729 tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
732 tcg_out8(s, 0x70 + JCC_JE);
733 label1_ptr = s->code_ptr;
736 /* XXX: move that code at the end of the TB */
740 tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_RSI, data_reg);
744 tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
748 tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
752 tcg_out_mov(s, TCG_REG_RSI, data_reg);
755 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
757 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
758 (tcg_target_long)s->code_ptr - 4);
762 label2_ptr = s->code_ptr;
766 *label1_ptr = s->code_ptr - label1_ptr - 1;
769 tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
770 offsetof(CPUTLBEntry, addr_write));
775 #ifdef TARGET_WORDS_BIGENDIAN
783 tcg_out_modrm_offset(s, 0x88 | P_REX, data_reg, r0, 0);
787 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
788 tcg_out8(s, 0x66); /* rolw $8, %ecx */
789 tcg_out_modrm(s, 0xc1, 0, r1);
795 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
799 tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
801 tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
805 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
809 tcg_out_mov(s, r1, data_reg);
811 tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
815 tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, 0);
821 #if defined(CONFIG_SOFTMMU)
823 *label2_ptr = s->code_ptr - label2_ptr - 1;
827 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
828 const int *const_args)
833 case INDEX_op_exit_tb:
834 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
835 tcg_out8(s, 0xc3); /* ret */
837 case INDEX_op_goto_tb:
838 if (s->tb_jmp_offset) {
839 /* direct jump method */
840 tcg_out8(s, 0xe9); /* jmp im */
841 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
844 /* indirect jump method */
846 tcg_out_modrm_offset(s, 0xff, 4, -1,
847 (tcg_target_long)(s->tb_next +
850 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
855 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
857 tcg_out_modrm(s, 0xff, 2, args[0]);
863 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
865 tcg_out_modrm(s, 0xff, 4, args[0]);
869 tcg_out_jxx(s, JCC_JMP, args[0]);
871 case INDEX_op_movi_i32:
872 tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
874 case INDEX_op_movi_i64:
875 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
877 case INDEX_op_ld8u_i32:
878 case INDEX_op_ld8u_i64:
880 tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
882 case INDEX_op_ld8s_i32:
884 tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
886 case INDEX_op_ld8s_i64:
888 tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
890 case INDEX_op_ld16u_i32:
891 case INDEX_op_ld16u_i64:
893 tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
895 case INDEX_op_ld16s_i32:
897 tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
899 case INDEX_op_ld16s_i64:
901 tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
903 case INDEX_op_ld_i32:
904 case INDEX_op_ld32u_i64:
906 tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
908 case INDEX_op_ld32s_i64:
910 tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
912 case INDEX_op_ld_i64:
914 tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
917 case INDEX_op_st8_i32:
918 case INDEX_op_st8_i64:
920 tcg_out_modrm_offset(s, 0x88 | P_REX, args[0], args[1], args[2]);
922 case INDEX_op_st16_i32:
923 case INDEX_op_st16_i64:
926 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
928 case INDEX_op_st_i32:
929 case INDEX_op_st32_i64:
931 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
933 case INDEX_op_st_i64:
935 tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
938 case INDEX_op_sub_i32:
941 case INDEX_op_and_i32:
944 case INDEX_op_or_i32:
947 case INDEX_op_xor_i32:
950 case INDEX_op_add_i32:
954 tgen_arithi32(s, c, args[0], args[2]);
956 tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
960 case INDEX_op_sub_i64:
963 case INDEX_op_and_i64:
966 case INDEX_op_or_i64:
969 case INDEX_op_xor_i64:
972 case INDEX_op_add_i64:
976 tgen_arithi64(s, c, args[0], args[2]);
978 tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
982 case INDEX_op_mul_i32:
986 if (val == (int8_t)val) {
987 tcg_out_modrm(s, 0x6b, args[0], args[0]);
990 tcg_out_modrm(s, 0x69, args[0], args[0]);
994 tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
997 case INDEX_op_mul_i64:
1001 if (val == (int8_t)val) {
1002 tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
1005 tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
1009 tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
1012 case INDEX_op_div2_i32:
1013 tcg_out_modrm(s, 0xf7, 7, args[4]);
1015 case INDEX_op_divu2_i32:
1016 tcg_out_modrm(s, 0xf7, 6, args[4]);
1018 case INDEX_op_div2_i64:
1019 tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
1021 case INDEX_op_divu2_i64:
1022 tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
1025 case INDEX_op_shl_i32:
1028 if (const_args[2]) {
1030 tcg_out_modrm(s, 0xd1, c, args[0]);
1032 tcg_out_modrm(s, 0xc1, c, args[0]);
1033 tcg_out8(s, args[2]);
1036 tcg_out_modrm(s, 0xd3, c, args[0]);
1039 case INDEX_op_shr_i32:
1042 case INDEX_op_sar_i32:
1046 case INDEX_op_shl_i64:
1049 if (const_args[2]) {
1051 tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
1053 tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
1054 tcg_out8(s, args[2]);
1057 tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
1060 case INDEX_op_shr_i64:
1063 case INDEX_op_sar_i64:
1067 case INDEX_op_brcond_i32:
1068 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1071 case INDEX_op_brcond_i64:
1072 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1076 case INDEX_op_bswap_i32:
1077 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
1079 case INDEX_op_bswap_i64:
1080 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
1083 case INDEX_op_qemu_ld8u:
1084 tcg_out_qemu_ld(s, args, 0);
1086 case INDEX_op_qemu_ld8s:
1087 tcg_out_qemu_ld(s, args, 0 | 4);
1089 case INDEX_op_qemu_ld16u:
1090 tcg_out_qemu_ld(s, args, 1);
1092 case INDEX_op_qemu_ld16s:
1093 tcg_out_qemu_ld(s, args, 1 | 4);
1095 case INDEX_op_qemu_ld32u:
1096 tcg_out_qemu_ld(s, args, 2);
1098 case INDEX_op_qemu_ld32s:
1099 tcg_out_qemu_ld(s, args, 2 | 4);
1101 case INDEX_op_qemu_ld64:
1102 tcg_out_qemu_ld(s, args, 3);
1105 case INDEX_op_qemu_st8:
1106 tcg_out_qemu_st(s, args, 0);
1108 case INDEX_op_qemu_st16:
1109 tcg_out_qemu_st(s, args, 1);
1111 case INDEX_op_qemu_st32:
1112 tcg_out_qemu_st(s, args, 2);
1114 case INDEX_op_qemu_st64:
1115 tcg_out_qemu_st(s, args, 3);
1123 static const TCGTargetOpDef x86_64_op_defs[] = {
1124 { INDEX_op_exit_tb, { } },
1125 { INDEX_op_goto_tb, { } },
1126 { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
1127 { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
1128 { INDEX_op_br, { } },
1130 { INDEX_op_mov_i32, { "r", "r" } },
1131 { INDEX_op_movi_i32, { "r" } },
1132 { INDEX_op_ld8u_i32, { "r", "r" } },
1133 { INDEX_op_ld8s_i32, { "r", "r" } },
1134 { INDEX_op_ld16u_i32, { "r", "r" } },
1135 { INDEX_op_ld16s_i32, { "r", "r" } },
1136 { INDEX_op_ld_i32, { "r", "r" } },
1137 { INDEX_op_st8_i32, { "r", "r" } },
1138 { INDEX_op_st16_i32, { "r", "r" } },
1139 { INDEX_op_st_i32, { "r", "r" } },
1141 { INDEX_op_add_i32, { "r", "0", "ri" } },
1142 { INDEX_op_mul_i32, { "r", "0", "ri" } },
1143 { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1144 { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1145 { INDEX_op_sub_i32, { "r", "0", "ri" } },
1146 { INDEX_op_and_i32, { "r", "0", "ri" } },
1147 { INDEX_op_or_i32, { "r", "0", "ri" } },
1148 { INDEX_op_xor_i32, { "r", "0", "ri" } },
1150 { INDEX_op_shl_i32, { "r", "0", "ci" } },
1151 { INDEX_op_shr_i32, { "r", "0", "ci" } },
1152 { INDEX_op_sar_i32, { "r", "0", "ci" } },
1154 { INDEX_op_brcond_i32, { "r", "ri" } },
1156 { INDEX_op_mov_i64, { "r", "r" } },
1157 { INDEX_op_movi_i64, { "r" } },
1158 { INDEX_op_ld8u_i64, { "r", "r" } },
1159 { INDEX_op_ld8s_i64, { "r", "r" } },
1160 { INDEX_op_ld16u_i64, { "r", "r" } },
1161 { INDEX_op_ld16s_i64, { "r", "r" } },
1162 { INDEX_op_ld32u_i64, { "r", "r" } },
1163 { INDEX_op_ld32s_i64, { "r", "r" } },
1164 { INDEX_op_ld_i64, { "r", "r" } },
1165 { INDEX_op_st8_i64, { "r", "r" } },
1166 { INDEX_op_st16_i64, { "r", "r" } },
1167 { INDEX_op_st32_i64, { "r", "r" } },
1168 { INDEX_op_st_i64, { "r", "r" } },
1170 { INDEX_op_add_i64, { "r", "0", "re" } },
1171 { INDEX_op_mul_i64, { "r", "0", "re" } },
1172 { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
1173 { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
1174 { INDEX_op_sub_i64, { "r", "0", "re" } },
1175 { INDEX_op_and_i64, { "r", "0", "reZ" } },
1176 { INDEX_op_or_i64, { "r", "0", "re" } },
1177 { INDEX_op_xor_i64, { "r", "0", "re" } },
1179 { INDEX_op_shl_i64, { "r", "0", "ci" } },
1180 { INDEX_op_shr_i64, { "r", "0", "ci" } },
1181 { INDEX_op_sar_i64, { "r", "0", "ci" } },
1183 { INDEX_op_brcond_i64, { "r", "re" } },
1185 { INDEX_op_bswap_i32, { "r", "0" } },
1186 { INDEX_op_bswap_i64, { "r", "0" } },
1188 { INDEX_op_qemu_ld8u, { "r", "L" } },
1189 { INDEX_op_qemu_ld8s, { "r", "L" } },
1190 { INDEX_op_qemu_ld16u, { "r", "L" } },
1191 { INDEX_op_qemu_ld16s, { "r", "L" } },
1192 { INDEX_op_qemu_ld32u, { "r", "L" } },
1193 { INDEX_op_qemu_ld32s, { "r", "L" } },
1194 { INDEX_op_qemu_ld64, { "r", "L" } },
1196 { INDEX_op_qemu_st8, { "L", "L" } },
1197 { INDEX_op_qemu_st16, { "L", "L" } },
1198 { INDEX_op_qemu_st32, { "L", "L" } },
1199 { INDEX_op_qemu_st64, { "L", "L", "L" } },
1204 void tcg_target_init(TCGContext *s)
1206 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1207 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
1208 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1209 (1 << TCG_REG_RDI) |
1210 (1 << TCG_REG_RSI) |
1211 (1 << TCG_REG_RDX) |
1212 (1 << TCG_REG_RCX) |
1215 (1 << TCG_REG_RAX) |
1216 (1 << TCG_REG_R10) |
1217 (1 << TCG_REG_R11));
1219 tcg_regset_clear(s->reserved_regs);
1220 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
1221 /* XXX: will be suppresed when proper global TB entry code will be
1223 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RBX);
1224 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RBP);
1226 tcg_add_target_add_op_defs(x86_64_op_defs);