2 * QEMU System Emulator header
4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 /* we put basic includes here to avoid repeating them in device drivers */
49 #define ENOMEDIUM ENODEV
55 #define lseek _lseeki64
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
61 static inline char *realpath(const char *path, char *resolved_path)
63 _fullpath(resolved_path, path, _MAX_PATH);
75 /* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77 #include "config-host.h"
84 #include "audio/audio.h"
87 #endif /* !defined(QEMU_TOOL) */
90 #define xglue(x, y) x ## y
91 #define glue(x, y) xglue(x, y)
92 #define stringify(s) tostring(s)
93 #define tostring(s) #s
98 #define __builtin_expect(x, n) (x)
101 #define likely(x) __builtin_expect(!!(x), 1)
102 #define unlikely(x) __builtin_expect(!!(x), 0)
106 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
109 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
112 #ifndef always_inline
113 #if (__GNUC__ < 3) || defined(__APPLE__)
114 #define always_inline inline
116 #define always_inline __attribute__ (( always_inline )) inline
121 void pstrcpy(char *buf, int buf_size, const char *str);
122 char *pstrcat(char *buf, int buf_size, const char *s);
123 int strstart(const char *str, const char *val, const char **ptr);
124 int stristart(const char *str, const char *val, const char **ptr);
127 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
129 void hw_error(const char *fmt, ...);
131 extern const char *bios_dir;
132 extern const char *bios_name;
134 extern int vm_running;
135 extern const char *qemu_name;
137 typedef struct vm_change_state_entry VMChangeStateEntry;
138 typedef void VMChangeStateHandler(void *opaque, int running);
139 typedef void VMStopHandler(void *opaque, int reason);
141 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
143 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
145 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
146 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
149 void vm_stop(int reason);
151 typedef void QEMUResetHandler(void *opaque);
153 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
154 void qemu_system_reset_request(void);
155 void qemu_system_shutdown_request(void);
156 void qemu_system_powerdown_request(void);
157 #if !defined(TARGET_SPARC)
158 // Please implement a power failure function to signal the OS
159 #define qemu_system_powerdown() do{}while(0)
161 void qemu_system_powerdown(void);
164 void main_loop_wait(int timeout);
167 extern int bios_size;
169 extern int cirrus_vga_enabled;
170 extern int vmsvga_enabled;
171 extern int graphic_width;
172 extern int graphic_height;
173 extern int graphic_depth;
174 extern const char *keyboard_layout;
175 extern int kqemu_allowed;
176 extern int win2k_install_hack;
178 extern int usb_enabled;
180 extern int cursor_hide;
181 extern int graphic_rotate;
183 extern int semihosting_enabled;
184 extern int autostart;
185 extern int old_param;
186 extern const char *bootp_filename;
188 #define MAX_OPTION_ROMS 16
189 extern const char *option_rom[MAX_OPTION_ROMS];
190 extern int nb_option_roms;
193 #define MAX_PROM_ENVS 128
194 extern const char *prom_envs[MAX_PROM_ENVS];
195 extern unsigned int nb_prom_envs;
198 /* XXX: make it dynamic */
199 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
200 #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
201 #define BIOS_SIZE ((512 + 32) * 1024)
202 #elif defined(TARGET_MIPS)
203 #define BIOS_SIZE (4 * 1024 * 1024)
206 /* keyboard/mouse support */
208 #define MOUSE_EVENT_LBUTTON 0x01
209 #define MOUSE_EVENT_RBUTTON 0x02
210 #define MOUSE_EVENT_MBUTTON 0x04
212 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
213 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
215 typedef struct QEMUPutMouseEntry {
216 QEMUPutMouseEvent *qemu_put_mouse_event;
217 void *qemu_put_mouse_event_opaque;
218 int qemu_put_mouse_event_absolute;
219 char *qemu_put_mouse_event_name;
221 /* used internally by qemu for handling mice */
222 struct QEMUPutMouseEntry *next;
225 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
226 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
227 void *opaque, int absolute,
229 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
231 void kbd_put_keycode(int keycode);
232 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
233 int kbd_mouse_is_absolute(void);
235 void do_info_mice(void);
236 void do_mouse_set(int index);
238 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
240 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
241 #define QEMU_KEY_BACKSPACE 0x007f
242 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
243 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
244 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
245 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
246 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
247 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
248 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
249 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
250 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
252 #define QEMU_KEY_CTRL_UP 0xe400
253 #define QEMU_KEY_CTRL_DOWN 0xe401
254 #define QEMU_KEY_CTRL_LEFT 0xe402
255 #define QEMU_KEY_CTRL_RIGHT 0xe403
256 #define QEMU_KEY_CTRL_HOME 0xe404
257 #define QEMU_KEY_CTRL_END 0xe405
258 #define QEMU_KEY_CTRL_PAGEUP 0xe406
259 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
261 void kbd_put_keysym(int keysym);
263 /* async I/O support */
265 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
266 typedef int IOCanRWHandler(void *opaque);
267 typedef void IOHandler(void *opaque);
269 int qemu_set_fd_handler2(int fd,
270 IOCanRWHandler *fd_read_poll,
274 int qemu_set_fd_handler(int fd,
279 /* Polling handling */
281 /* return TRUE if no sleep should be done afterwards */
282 typedef int PollingFunc(void *opaque);
284 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
285 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
288 /* Wait objects handling */
289 typedef void WaitObjectFunc(void *opaque);
291 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
292 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
295 typedef struct QEMUBH QEMUBH;
297 /* character device */
299 #define CHR_EVENT_BREAK 0 /* serial break char */
300 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
301 #define CHR_EVENT_RESET 2 /* new connection established */
304 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
310 } QEMUSerialSetParams;
312 #define CHR_IOCTL_SERIAL_SET_BREAK 2
314 #define CHR_IOCTL_PP_READ_DATA 3
315 #define CHR_IOCTL_PP_WRITE_DATA 4
316 #define CHR_IOCTL_PP_READ_CONTROL 5
317 #define CHR_IOCTL_PP_WRITE_CONTROL 6
318 #define CHR_IOCTL_PP_READ_STATUS 7
319 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
320 #define CHR_IOCTL_PP_EPP_READ 9
321 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
322 #define CHR_IOCTL_PP_EPP_WRITE 11
324 typedef void IOEventHandler(void *opaque, int event);
326 typedef struct CharDriverState {
327 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
328 void (*chr_update_read_handler)(struct CharDriverState *s);
329 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
330 IOEventHandler *chr_event;
331 IOCanRWHandler *chr_can_read;
332 IOReadHandler *chr_read;
333 void *handler_opaque;
334 void (*chr_send_event)(struct CharDriverState *chr, int event);
335 void (*chr_close)(struct CharDriverState *chr);
341 CharDriverState *qemu_chr_open(const char *filename);
342 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
343 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
344 void qemu_chr_send_event(CharDriverState *s, int event);
345 void qemu_chr_add_handlers(CharDriverState *s,
346 IOCanRWHandler *fd_can_read,
347 IOReadHandler *fd_read,
348 IOEventHandler *fd_event,
350 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
351 void qemu_chr_reset(CharDriverState *s);
352 int qemu_chr_can_read(CharDriverState *s);
353 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
357 typedef struct DisplayState DisplayState;
358 typedef struct TextConsole TextConsole;
360 typedef void (*vga_hw_update_ptr)(void *);
361 typedef void (*vga_hw_invalidate_ptr)(void *);
362 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
364 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
365 vga_hw_invalidate_ptr invalidate,
366 vga_hw_screen_dump_ptr screen_dump,
368 void vga_hw_update(void);
369 void vga_hw_invalidate(void);
370 void vga_hw_screen_dump(const char *filename);
372 int is_graphic_console(void);
373 CharDriverState *text_console_init(DisplayState *ds, const char *p);
374 void console_select(unsigned int index);
378 #define MAX_SERIAL_PORTS 4
380 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
384 #define MAX_PARALLEL_PORTS 3
386 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
388 struct ParallelIOArg {
395 typedef struct VLANClientState VLANClientState;
397 struct VLANClientState {
398 IOReadHandler *fd_read;
399 /* Packets may still be sent if this returns zero. It's used to
400 rate-limit the slirp code. */
401 IOCanRWHandler *fd_can_read;
403 struct VLANClientState *next;
404 struct VLANState *vlan;
408 typedef struct VLANState {
410 VLANClientState *first_client;
411 struct VLANState *next;
412 unsigned int nb_guest_devs, nb_host_devs;
415 VLANState *qemu_find_vlan(int id);
416 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
417 IOReadHandler *fd_read,
418 IOCanRWHandler *fd_can_read,
420 int qemu_can_send_packet(VLANClientState *vc);
421 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
422 void qemu_handler_true(void *opaque);
424 void do_info_network(void);
427 int tap_win32_init(VLANState *vlan, const char *ifname);
433 typedef struct NICInfo {
440 extern NICInfo nd_table[MAX_NICS];
443 void do_info_slirp(void);
447 typedef struct QEMUClock QEMUClock;
448 typedef struct QEMUTimer QEMUTimer;
449 typedef void QEMUTimerCB(void *opaque);
451 /* The real time clock should be used only for stuff which does not
452 change the virtual machine state, as it is run even if the virtual
453 machine is stopped. The real time clock has a frequency of 1000
455 extern QEMUClock *rt_clock;
457 /* The virtual clock is only run during the emulation. It is stopped
458 when the virtual machine is stopped. Virtual timers use a high
459 precision clock, usually cpu cycles (use ticks_per_sec). */
460 extern QEMUClock *vm_clock;
462 int64_t qemu_get_clock(QEMUClock *clock);
464 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
465 void qemu_free_timer(QEMUTimer *ts);
466 void qemu_del_timer(QEMUTimer *ts);
467 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
468 int qemu_timer_pending(QEMUTimer *ts);
470 extern int64_t ticks_per_sec;
472 int64_t cpu_get_ticks(void);
473 void cpu_enable_ticks(void);
474 void cpu_disable_ticks(void);
478 typedef struct QEMUFile QEMUFile;
480 QEMUFile *qemu_fopen(const char *filename, const char *mode);
481 void qemu_fflush(QEMUFile *f);
482 void qemu_fclose(QEMUFile *f);
483 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
484 void qemu_put_byte(QEMUFile *f, int v);
485 void qemu_put_be16(QEMUFile *f, unsigned int v);
486 void qemu_put_be32(QEMUFile *f, unsigned int v);
487 void qemu_put_be64(QEMUFile *f, uint64_t v);
488 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
489 int qemu_get_byte(QEMUFile *f);
490 unsigned int qemu_get_be16(QEMUFile *f);
491 unsigned int qemu_get_be32(QEMUFile *f);
492 uint64_t qemu_get_be64(QEMUFile *f);
494 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
496 qemu_put_be64(f, *pv);
499 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
501 qemu_put_be32(f, *pv);
504 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
506 qemu_put_be16(f, *pv);
509 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
511 qemu_put_byte(f, *pv);
514 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
516 *pv = qemu_get_be64(f);
519 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
521 *pv = qemu_get_be32(f);
524 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
526 *pv = qemu_get_be16(f);
529 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
531 *pv = qemu_get_byte(f);
534 #if TARGET_LONG_BITS == 64
535 #define qemu_put_betl qemu_put_be64
536 #define qemu_get_betl qemu_get_be64
537 #define qemu_put_betls qemu_put_be64s
538 #define qemu_get_betls qemu_get_be64s
540 #define qemu_put_betl qemu_put_be32
541 #define qemu_get_betl qemu_get_be32
542 #define qemu_put_betls qemu_put_be32s
543 #define qemu_get_betls qemu_get_be32s
546 int64_t qemu_ftell(QEMUFile *f);
547 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
549 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
550 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
552 int register_savevm(const char *idstr,
555 SaveStateHandler *save_state,
556 LoadStateHandler *load_state,
558 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
559 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
561 void cpu_save(QEMUFile *f, void *opaque);
562 int cpu_load(QEMUFile *f, void *opaque, int version_id);
564 void do_savevm(const char *name);
565 void do_loadvm(const char *name);
566 void do_delvm(const char *name);
567 void do_info_snapshots(void);
570 typedef void QEMUBHFunc(void *opaque);
572 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
573 void qemu_bh_schedule(QEMUBH *bh);
574 void qemu_bh_cancel(QEMUBH *bh);
575 void qemu_bh_delete(QEMUBH *bh);
576 int qemu_bh_poll(void);
579 typedef struct BlockDriverState BlockDriverState;
580 typedef struct BlockDriver BlockDriver;
582 extern BlockDriver bdrv_raw;
583 extern BlockDriver bdrv_host_device;
584 extern BlockDriver bdrv_cow;
585 extern BlockDriver bdrv_qcow;
586 extern BlockDriver bdrv_vmdk;
587 extern BlockDriver bdrv_cloop;
588 extern BlockDriver bdrv_dmg;
589 extern BlockDriver bdrv_bochs;
590 extern BlockDriver bdrv_vpc;
591 extern BlockDriver bdrv_vvfat;
592 extern BlockDriver bdrv_qcow2;
593 extern BlockDriver bdrv_parallels;
595 typedef struct BlockDriverInfo {
596 /* in bytes, 0 if irrelevant */
598 /* offset at which the VM state can be saved (0 if not possible) */
599 int64_t vm_state_offset;
602 typedef struct QEMUSnapshotInfo {
603 char id_str[128]; /* unique snapshot id */
604 /* the following fields are informative. They are not needed for
605 the consistency of the snapshot */
606 char name[256]; /* user choosen name */
607 uint32_t vm_state_size; /* VM state info size */
608 uint32_t date_sec; /* UTC date of the snapshot */
610 uint64_t vm_clock_nsec; /* VM clock relative to boot */
613 #define BDRV_O_RDONLY 0x0000
614 #define BDRV_O_RDWR 0x0002
615 #define BDRV_O_ACCESS 0x0003
616 #define BDRV_O_CREAT 0x0004 /* create an empty file */
617 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
618 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
619 use a disk image format on top of
623 void bdrv_init(void);
624 BlockDriver *bdrv_find_format(const char *format_name);
625 int bdrv_create(BlockDriver *drv,
626 const char *filename, int64_t size_in_sectors,
627 const char *backing_file, int flags);
628 BlockDriverState *bdrv_new(const char *device_name);
629 void bdrv_delete(BlockDriverState *bs);
630 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
631 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
632 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
634 void bdrv_close(BlockDriverState *bs);
635 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
636 uint8_t *buf, int nb_sectors);
637 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
638 const uint8_t *buf, int nb_sectors);
639 int bdrv_pread(BlockDriverState *bs, int64_t offset,
640 void *buf, int count);
641 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
642 const void *buf, int count);
643 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
644 int64_t bdrv_getlength(BlockDriverState *bs);
645 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
646 int bdrv_commit(BlockDriverState *bs);
647 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
648 /* async block I/O */
649 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
650 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
652 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
653 uint8_t *buf, int nb_sectors,
654 BlockDriverCompletionFunc *cb, void *opaque);
655 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
656 const uint8_t *buf, int nb_sectors,
657 BlockDriverCompletionFunc *cb, void *opaque);
658 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
660 void qemu_aio_init(void);
661 void qemu_aio_poll(void);
662 void qemu_aio_flush(void);
663 void qemu_aio_wait_start(void);
664 void qemu_aio_wait(void);
665 void qemu_aio_wait_end(void);
667 int qemu_key_check(BlockDriverState *bs, const char *name);
669 /* Ensure contents are flushed to disk. */
670 void bdrv_flush(BlockDriverState *bs);
672 #define BDRV_TYPE_HD 0
673 #define BDRV_TYPE_CDROM 1
674 #define BDRV_TYPE_FLOPPY 2
675 #define BIOS_ATA_TRANSLATION_AUTO 0
676 #define BIOS_ATA_TRANSLATION_NONE 1
677 #define BIOS_ATA_TRANSLATION_LBA 2
678 #define BIOS_ATA_TRANSLATION_LARGE 3
679 #define BIOS_ATA_TRANSLATION_RECHS 4
681 void bdrv_set_geometry_hint(BlockDriverState *bs,
682 int cyls, int heads, int secs);
683 void bdrv_set_type_hint(BlockDriverState *bs, int type);
684 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
685 void bdrv_get_geometry_hint(BlockDriverState *bs,
686 int *pcyls, int *pheads, int *psecs);
687 int bdrv_get_type_hint(BlockDriverState *bs);
688 int bdrv_get_translation_hint(BlockDriverState *bs);
689 int bdrv_is_removable(BlockDriverState *bs);
690 int bdrv_is_read_only(BlockDriverState *bs);
691 int bdrv_is_inserted(BlockDriverState *bs);
692 int bdrv_media_changed(BlockDriverState *bs);
693 int bdrv_is_locked(BlockDriverState *bs);
694 void bdrv_set_locked(BlockDriverState *bs, int locked);
695 void bdrv_eject(BlockDriverState *bs, int eject_flag);
696 void bdrv_set_change_cb(BlockDriverState *bs,
697 void (*change_cb)(void *opaque), void *opaque);
698 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
699 void bdrv_info(void);
700 BlockDriverState *bdrv_find(const char *name);
701 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
702 int bdrv_is_encrypted(BlockDriverState *bs);
703 int bdrv_set_key(BlockDriverState *bs, const char *key);
704 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
706 const char *bdrv_get_device_name(BlockDriverState *bs);
707 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
708 const uint8_t *buf, int nb_sectors);
709 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
711 void bdrv_get_backing_filename(BlockDriverState *bs,
712 char *filename, int filename_size);
713 int bdrv_snapshot_create(BlockDriverState *bs,
714 QEMUSnapshotInfo *sn_info);
715 int bdrv_snapshot_goto(BlockDriverState *bs,
716 const char *snapshot_id);
717 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
718 int bdrv_snapshot_list(BlockDriverState *bs,
719 QEMUSnapshotInfo **psn_info);
720 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
722 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
723 int path_is_absolute(const char *path);
724 void path_combine(char *dest, int dest_size,
725 const char *base_path,
726 const char *filename);
730 typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
732 DisplayState *ds, const char **fd_filename, int snapshot,
733 const char *kernel_filename, const char *kernel_cmdline,
734 const char *initrd_filename, const char *cpu_model);
736 typedef struct QEMUMachine {
739 QEMUMachineInitFunc *init;
740 struct QEMUMachine *next;
743 int qemu_register_machine(QEMUMachine *m);
745 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
751 extern target_phys_addr_t isa_mem_base;
753 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
754 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
756 int register_ioport_read(int start, int length, int size,
757 IOPortReadFunc *func, void *opaque);
758 int register_ioport_write(int start, int length, int size,
759 IOPortWriteFunc *func, void *opaque);
760 void isa_unassign_ioport(int start, int length);
762 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
766 extern target_phys_addr_t pci_mem_base;
768 typedef struct PCIBus PCIBus;
769 typedef struct PCIDevice PCIDevice;
771 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
772 uint32_t address, uint32_t data, int len);
773 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
774 uint32_t address, int len);
775 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
776 uint32_t addr, uint32_t size, int type);
778 #define PCI_ADDRESS_SPACE_MEM 0x00
779 #define PCI_ADDRESS_SPACE_IO 0x01
780 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
782 typedef struct PCIIORegion {
783 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
786 PCIMapIORegionFunc *map_func;
789 #define PCI_ROM_SLOT 6
790 #define PCI_NUM_REGIONS 7
792 #define PCI_DEVICES_MAX 64
794 #define PCI_VENDOR_ID 0x00 /* 16 bits */
795 #define PCI_DEVICE_ID 0x02 /* 16 bits */
796 #define PCI_COMMAND 0x04 /* 16 bits */
797 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
798 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
799 #define PCI_CLASS_DEVICE 0x0a /* Device class */
800 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
801 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
802 #define PCI_MIN_GNT 0x3e /* 8 bits */
803 #define PCI_MAX_LAT 0x3f /* 8 bits */
806 /* PCI config space */
809 /* the following fields are read only */
813 PCIIORegion io_regions[PCI_NUM_REGIONS];
815 /* do not access the following fields */
816 PCIConfigReadFunc *config_read;
817 PCIConfigWriteFunc *config_write;
818 /* ??? This is a PC-specific hack, and should be removed. */
821 /* IRQ objects for the INTA-INTD pins. */
824 /* Current IRQ levels. Used internally by the generic PCI code. */
828 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
829 int instance_size, int devfn,
830 PCIConfigReadFunc *config_read,
831 PCIConfigWriteFunc *config_write);
833 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
834 uint32_t size, int type,
835 PCIMapIORegionFunc *map_func);
837 uint32_t pci_default_read_config(PCIDevice *d,
838 uint32_t address, int len);
839 void pci_default_write_config(PCIDevice *d,
840 uint32_t address, uint32_t val, int len);
841 void pci_device_save(PCIDevice *s, QEMUFile *f);
842 int pci_device_load(PCIDevice *s, QEMUFile *f);
844 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
845 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
846 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
847 qemu_irq *pic, int devfn_min, int nirq);
849 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
850 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
851 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
852 int pci_bus_num(PCIBus *s);
853 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
856 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
857 pci_map_irq_fn map_irq, const char *name);
860 PCIBus *pci_prep_init(qemu_irq *pic);
863 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
866 PCIBus *pci_pmac_init(qemu_irq *pic);
869 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
872 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
875 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
876 void i440fx_set_smm(PCIDevice *d, int val);
877 int piix3_init(PCIBus *bus, int devfn);
878 void i440fx_init_memory_mappings(PCIDevice *d);
880 int piix4_init(PCIBus *bus, int devfn);
883 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
885 OPENPIC_OUTPUT_INT = 0, /* IRQ */
886 OPENPIC_OUTPUT_CINT, /* critical IRQ */
887 OPENPIC_OUTPUT_MCK, /* Machine check event */
888 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
889 OPENPIC_OUTPUT_RESET, /* Core reset event */
892 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
893 qemu_irq **irqs, qemu_irq irq_out);
896 qemu_irq *heathrow_pic_init(int *pmem_index);
899 PCIBus *pci_gt64120_init(qemu_irq *pic);
908 int (*init_isa) (AudioState *s, qemu_irq *pic);
909 int (*init_pci) (PCIBus *bus, AudioState *s);
913 extern struct soundhw soundhw[];
919 #define VGA_RAM_SIZE (8192 * 1024)
921 #define VGA_RAM_SIZE (9 * 1024 * 1024)
924 struct DisplayState {
928 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
932 QEMUTimer *gui_timer;
934 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
935 void (*dpy_resize)(struct DisplayState *s, int w, int h);
936 void (*dpy_refresh)(struct DisplayState *s);
937 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
938 int dst_x, int dst_y, int w, int h);
939 void (*dpy_fill)(struct DisplayState *s, int x, int y,
940 int w, int h, uint32_t c);
941 void (*mouse_set)(int x, int y, int on);
942 void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
943 uint8_t *image, uint8_t *mask);
946 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
948 s->dpy_update(s, x, y, w, h);
951 static inline void dpy_resize(DisplayState *s, int w, int h)
953 s->dpy_resize(s, w, h);
956 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
957 unsigned long vga_ram_offset, int vga_ram_size);
958 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
959 unsigned long vga_ram_offset, int vga_ram_size,
960 unsigned long vga_bios_offset, int vga_bios_size);
961 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
962 unsigned long vga_ram_offset, int vga_ram_size,
963 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
967 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
968 unsigned long vga_ram_offset, int vga_ram_size);
969 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
970 unsigned long vga_ram_offset, int vga_ram_size);
973 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
974 unsigned long vga_ram_offset, int vga_ram_size);
977 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
980 void cocoa_display_init(DisplayState *ds, int full_screen);
983 void vnc_display_init(DisplayState *ds);
984 void vnc_display_close(DisplayState *ds);
985 int vnc_display_open(DisplayState *ds, const char *display);
986 int vnc_display_password(DisplayState *ds, const char *password);
987 void do_info_vnc(void);
990 extern uint8_t _translate_keycode(const int key);
995 extern BlockDriverState *bs_table[MAX_DISKS + 1];
996 extern BlockDriverState *sd_bdrv;
997 extern BlockDriverState *mtd_bdrv;
999 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
1000 BlockDriverState *hd0, BlockDriverState *hd1);
1001 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
1002 int secondary_ide_enabled);
1003 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1005 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1007 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
1010 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1011 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1014 typedef struct ds1225y_t ds1225y_t;
1015 ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1018 int es1370_init (PCIBus *bus, AudioState *s);
1021 int SB16_init (AudioState *s, qemu_irq *pic);
1024 int Adlib_init (AudioState *s, qemu_irq *pic);
1027 int GUS_init (AudioState *s, qemu_irq *pic);
1030 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1031 int DMA_get_channel_mode (int nchan);
1032 int DMA_read_memory (int nchan, void *buf, int pos, int size);
1033 int DMA_write_memory (int nchan, void *buf, int pos, int size);
1034 void DMA_hold_DREQ (int nchan);
1035 void DMA_release_DREQ (int nchan);
1036 void DMA_schedule(int nchan);
1037 void DMA_run (void);
1038 void DMA_init (int high_page_enable);
1039 void DMA_register_channel (int nchan,
1040 DMA_transfer_handler transfer_handler,
1044 extern BlockDriverState *fd_table[MAX_FD];
1046 typedef struct fdctrl_t fdctrl_t;
1048 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1049 target_phys_addr_t io_base,
1050 BlockDriverState **fds);
1051 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1055 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1056 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1057 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1061 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1062 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1066 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1070 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1071 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1072 qemu_irq irq, qemu_irq *reset);
1075 void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
1078 void *vmmouse_init(void *m);
1082 void vmport_init(CPUState *env);
1083 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1088 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1089 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1090 target_phys_addr_t base, int it_shift);
1094 typedef struct RTCState RTCState;
1096 RTCState *rtc_init(int base, qemu_irq irq);
1097 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1098 void rtc_set_memory(RTCState *s, int addr, int val);
1099 void rtc_set_date(RTCState *s, const struct tm *tm);
1103 typedef struct SerialState SerialState;
1104 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1105 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1106 qemu_irq irq, CharDriverState *chr,
1108 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1109 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1110 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1111 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1112 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1113 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1117 typedef struct ParallelState ParallelState;
1118 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1119 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1123 typedef struct PicState2 PicState2;
1124 extern PicState2 *isa_pic;
1125 void pic_set_irq(int irq, int level);
1126 void pic_set_irq_new(void *opaque, int irq, int level);
1127 qemu_irq *i8259_init(qemu_irq parent_irq);
1128 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1129 void *alt_irq_opaque);
1130 int pic_read_irq(PicState2 *s);
1131 void pic_update_irq(PicState2 *s);
1132 uint32_t pic_intack_read(PicState2 *s);
1133 void pic_info(void);
1134 void irq_info(void);
1137 typedef struct IOAPICState IOAPICState;
1139 int apic_init(CPUState *env);
1140 int apic_accept_pic_intr(CPUState *env);
1141 int apic_get_interrupt(CPUState *env);
1142 IOAPICState *ioapic_init(void);
1143 void ioapic_set_irq(void *opaque, int vector, int level);
1147 #define PIT_FREQ 1193182
1149 typedef struct PITState PITState;
1151 PITState *pit_init(int base, qemu_irq irq);
1152 void pit_set_gate(PITState *pit, int channel, int val);
1153 int pit_get_gate(PITState *pit, int channel);
1154 int pit_get_initial_count(PITState *pit, int channel);
1155 int pit_get_mode(PITState *pit, int channel);
1156 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1159 extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1162 void pcspk_init(PITState *);
1163 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1167 #include "hw/smbus.h"
1170 extern int acpi_enabled;
1171 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1172 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1173 void acpi_bios_init(void);
1176 extern QEMUMachine bareetraxfs_machine;
1179 extern QEMUMachine pc_machine;
1180 extern QEMUMachine isapc_machine;
1181 extern int fd_bootchk;
1183 void ioport_set_a20(int enable);
1184 int ioport_get_a20(void);
1187 extern QEMUMachine prep_machine;
1188 extern QEMUMachine core99_machine;
1189 extern QEMUMachine heathrow_machine;
1190 extern QEMUMachine ref405ep_machine;
1191 extern QEMUMachine taihu_machine;
1194 extern QEMUMachine mips_machine;
1197 extern QEMUMachine mips_malta_machine;
1200 extern QEMUMachine mips_pica61_machine;
1202 /* mips_mipssim.c */
1203 extern QEMUMachine mips_mipssim_machine;
1206 extern void cpu_mips_irq_init_cpu(CPUState *env);
1209 extern void cpu_mips_clock_init(CPUState *);
1210 extern void cpu_mips_irqctrl_init (void);
1213 extern QEMUMachine shix_machine;
1216 extern QEMUMachine r2d_machine;
1219 /* PowerPC hardware exceptions management helpers */
1220 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1221 typedef struct clk_setup_t clk_setup_t;
1222 struct clk_setup_t {
1226 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1228 if (clk->cb != NULL)
1229 (*clk->cb)(clk->opaque, freq);
1232 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1233 /* Embedded PowerPC DCR management */
1234 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1235 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1236 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1237 int (*dcr_write_error)(int dcrn));
1238 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1239 dcr_read_cb drc_read, dcr_write_cb dcr_write);
1240 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1241 /* Embedded PowerPC reset */
1242 void ppc40x_core_reset (CPUState *env);
1243 void ppc40x_chip_reset (CPUState *env);
1244 void ppc40x_system_reset (CPUState *env);
1246 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1248 extern CPUWriteMemoryFunc *PPC_io_write[];
1249 extern CPUReadMemoryFunc *PPC_io_read[];
1250 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1253 extern QEMUMachine ss5_machine, ss10_machine;
1256 void *iommu_init(target_phys_addr_t addr);
1257 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1258 uint8_t *buf, int len, int is_write);
1259 static inline void sparc_iommu_memory_read(void *opaque,
1260 target_phys_addr_t addr,
1261 uint8_t *buf, int len)
1263 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1266 static inline void sparc_iommu_memory_write(void *opaque,
1267 target_phys_addr_t addr,
1268 uint8_t *buf, int len)
1270 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1274 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1275 unsigned long vram_offset, int vram_size, int width, int height,
1278 /* slavio_intctl.c */
1279 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1280 const uint32_t *intbit_to_level,
1281 qemu_irq **irq, qemu_irq **cpu_irq,
1282 qemu_irq **parent_irq, unsigned int cputimer);
1283 void slavio_pic_info(void *opaque);
1284 void slavio_irq_info(void *opaque);
1287 int get_image_size(const char *filename);
1288 int load_image(const char *filename, uint8_t *addr);
1289 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1290 uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1291 int load_aout(const char *filename, uint8_t *addr);
1292 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1294 /* slavio_timer.c */
1295 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
1296 qemu_irq *cpu_irqs);
1298 /* slavio_serial.c */
1299 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1300 CharDriverState *chr1, CharDriverState *chr2);
1301 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1304 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1306 void slavio_set_power_fail(void *opaque, int power_failing);
1309 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1310 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1311 void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1314 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1315 void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1316 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1317 uint8_t *buf, int len, int do_bswap);
1318 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1319 uint8_t *buf, int len, int do_bswap);
1320 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1321 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1324 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1327 extern QEMUMachine sun4u_machine;
1330 #include "hw/m48t59.h"
1332 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1333 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1334 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1335 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1336 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1337 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1338 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1339 const unsigned char *str, uint32_t max);
1340 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1341 void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1342 uint32_t start, uint32_t count);
1343 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1344 const unsigned char *arch,
1345 uint32_t RAM_size, int boot_device,
1346 uint32_t kernel_image, uint32_t kernel_size,
1347 const char *cmdline,
1348 uint32_t initrd_image, uint32_t initrd_size,
1349 uint32_t NVRAM_image,
1350 int width, int height, int depth);
1354 #define MAX_ADB_DEVICES 16
1356 #define ADB_MAX_OUT_LEN 16
1358 typedef struct ADBDevice ADBDevice;
1360 /* buf = NULL means polling */
1361 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1362 const uint8_t *buf, int len);
1363 typedef int ADBDeviceReset(ADBDevice *d);
1366 struct ADBBusState *bus;
1369 ADBDeviceRequest *devreq;
1370 ADBDeviceReset *devreset;
1374 typedef struct ADBBusState {
1375 ADBDevice devices[MAX_ADB_DEVICES];
1380 int adb_request(ADBBusState *s, uint8_t *buf_out,
1381 const uint8_t *buf, int len);
1382 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1384 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1385 ADBDeviceRequest *devreq,
1386 ADBDeviceReset *devreset,
1388 void adb_kbd_init(ADBBusState *bus);
1389 void adb_mouse_init(ADBBusState *bus);
1393 extern ADBBusState adb_bus;
1394 int cuda_init(qemu_irq irq);
1398 /* usb ports of the VM */
1400 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1401 usb_attachfn attach);
1403 #define VM_USB_HUB_SIZE 8
1405 void do_usb_add(const char *devname);
1406 void do_usb_del(const char *devname);
1407 void usb_info(void);
1411 SCSI_REASON_DONE, /* Command complete. */
1412 SCSI_REASON_DATA /* Transfer complete, more data required. */
1415 typedef struct SCSIDevice SCSIDevice;
1416 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1419 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1421 scsi_completionfn completion,
1423 void scsi_disk_destroy(SCSIDevice *s);
1425 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1426 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1427 layer the completion routine may be called directly by
1428 scsi_{read,write}_data. */
1429 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1430 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1431 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1432 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1435 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1436 void *lsi_scsi_init(PCIBus *bus, int devfn);
1438 /* integratorcp.c */
1439 extern QEMUMachine integratorcp_machine;
1442 extern QEMUMachine versatilepb_machine;
1443 extern QEMUMachine versatileab_machine;
1446 extern QEMUMachine realview_machine;
1449 extern QEMUMachine akitapda_machine;
1450 extern QEMUMachine spitzpda_machine;
1451 extern QEMUMachine borzoipda_machine;
1452 extern QEMUMachine terrierpda_machine;
1455 extern QEMUMachine palmte_machine;
1458 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1459 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1460 void ps2_write_mouse(void *, int val);
1461 void ps2_write_keyboard(void *, int val);
1462 uint32_t ps2_read_data(void *);
1463 void ps2_queue(void *, int b);
1464 void ps2_keyboard_set_translation(void *opaque, int mode);
1465 void ps2_mouse_fake_event(void *opaque);
1468 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1471 void pl031_init(uint32_t base, qemu_irq irq);
1474 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1477 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1480 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1483 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1486 void pl181_init(uint32_t base, BlockDriverState *bd,
1487 qemu_irq irq0, qemu_irq irq1);
1490 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1493 void sp804_init(uint32_t base, qemu_irq irq);
1494 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1497 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1500 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1504 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1505 const char *kernel_cmdline, const char *initrd_filename,
1506 int board_id, target_phys_addr_t loader_start);
1511 struct SH7750State *sh7750_init(CPUState * cpu);
1514 /* The callback will be triggered if any of the designated lines change */
1515 uint16_t portamask_trigger;
1516 uint16_t portbmask_trigger;
1517 /* Return 0 if no action was taken */
1518 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1519 uint16_t * periph_pdtra,
1520 uint16_t * periph_portdira,
1521 uint16_t * periph_pdtrb,
1522 uint16_t * periph_portdirb);
1525 int sh7750_register_io_device(struct SH7750State *s,
1526 sh7750_io_device * device);
1528 #define TMU012_FEAT_TOCR (1 << 0)
1529 #define TMU012_FEAT_3CHAN (1 << 1)
1530 #define TMU012_FEAT_EXTCLK (1 << 2)
1531 void tmu012_init(uint32_t base, int feat, uint32_t freq);
1534 #define SH_SERIAL_FEAT_SCIF (1 << 0)
1535 void sh_serial_init (target_phys_addr_t base, int feat,
1536 uint32_t freq, CharDriverState *chr);
1539 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1541 /* NOR flash devices */
1542 #define MAX_PFLASH 4
1543 extern BlockDriverState *pflash_table[MAX_PFLASH];
1544 typedef struct pflash_t pflash_t;
1546 pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1547 BlockDriverState *bs,
1548 uint32_t sector_len, int nb_blocs, int width,
1549 uint16_t id0, uint16_t id1,
1550 uint16_t id2, uint16_t id3);
1553 struct nand_flash_s;
1554 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1555 void nand_done(struct nand_flash_s *s);
1556 void nand_setpins(struct nand_flash_s *s,
1557 int cle, int ale, int ce, int wp, int gnd);
1558 void nand_getpins(struct nand_flash_s *s, int *rb);
1559 void nand_setio(struct nand_flash_s *s, uint8_t value);
1560 uint8_t nand_getio(struct nand_flash_s *s);
1562 #define NAND_MFR_TOSHIBA 0x98
1563 #define NAND_MFR_SAMSUNG 0xec
1564 #define NAND_MFR_FUJITSU 0x04
1565 #define NAND_MFR_NATIONAL 0x8f
1566 #define NAND_MFR_RENESAS 0x07
1567 #define NAND_MFR_STMICRO 0x20
1568 #define NAND_MFR_HYNIX 0xad
1569 #define NAND_MFR_MICRON 0x2c
1572 struct ecc_state_s {
1573 uint8_t cp; /* Column parity */
1574 uint16_t lp[2]; /* Line parity */
1578 uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1579 void ecc_reset(struct ecc_state_s *s);
1580 void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1581 void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1584 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1587 struct ads7846_state_s;
1588 uint32_t ads7846_read(void *opaque);
1589 void ads7846_write(void *opaque, uint32_t value);
1590 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1594 uint32_t max111x_read(void *opaque);
1595 void max111x_write(void *opaque, uint32_t value);
1596 struct max111x_s *max1110_init(qemu_irq cb);
1597 struct max111x_s *max1111_init(qemu_irq cb);
1598 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1600 /* PCMCIA/Cardbus */
1602 struct pcmcia_socket_s {
1605 const char *slot_string;
1606 const char *card_string;
1609 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1610 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1611 void pcmcia_info(void);
1613 struct pcmcia_card_s {
1615 struct pcmcia_socket_s *slot;
1616 int (*attach)(void *state);
1617 int (*detach)(void *state);
1621 /* Only valid if attached */
1622 uint8_t (*attr_read)(void *state, uint32_t address);
1623 void (*attr_write)(void *state, uint32_t address, uint8_t value);
1624 uint16_t (*common_read)(void *state, uint32_t address);
1625 void (*common_write)(void *state, uint32_t address, uint16_t value);
1626 uint16_t (*io_read)(void *state, uint32_t address);
1627 void (*io_write)(void *state, uint32_t address, uint16_t value);
1630 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1631 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1632 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1633 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1634 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1635 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1636 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1637 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1638 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1639 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1640 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1641 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1642 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1643 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1644 #define CISTPL_END 0xff /* Tuple End */
1645 #define CISTPL_ENDMARK 0xff
1648 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1651 typedef struct ptimer_state ptimer_state;
1652 typedef void (*ptimer_cb)(void *opaque);
1654 ptimer_state *ptimer_init(QEMUBH *bh);
1655 void ptimer_set_period(ptimer_state *s, int64_t period);
1656 void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1657 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1658 uint64_t ptimer_get_count(ptimer_state *s);
1659 void ptimer_set_count(ptimer_state *s, uint64_t count);
1660 void ptimer_run(ptimer_state *s, int oneshot);
1661 void ptimer_stop(ptimer_state *s);
1662 void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1663 void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1667 #include "hw/omap.h"
1670 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1671 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1672 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1673 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1674 CharDriverState *chr);
1677 qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1680 void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1683 qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1686 extern QEMUMachine an5206_machine;
1689 extern QEMUMachine mcf5208evb_machine;
1691 #include "gdbstub.h"
1693 #endif /* defined(QEMU_TOOL) */
1696 void monitor_init(CharDriverState *hd, int show_banner);
1697 void term_puts(const char *str);
1698 void term_vprintf(const char *fmt, va_list ap);
1699 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1700 void term_print_filename(const char *filename);
1701 void term_flush(void);
1702 void term_print_help(void);
1703 void monitor_readline(const char *prompt, int is_password,
1704 char *buf, int buf_size);
1707 typedef void ReadLineFunc(void *opaque, const char *str);
1709 extern int completion_index;
1710 void add_completion(const char *str);
1711 void readline_handle_byte(int ch);
1712 void readline_find_completion(const char *cmdline);
1713 const char *readline_get_history(unsigned int index);
1714 void readline_start(const char *prompt, int is_password,
1715 ReadLineFunc *readline_func, void *opaque);
1717 void kqemu_record_dump(void);