+
+void monitor_disas(Monitor *mon, CPUState *env,
+ target_ulong pc, int nb_insn, int is_physical, int flags)
+{
+ int count, i;
+ struct disassemble_info disasm_info;
+ int (*print_insn)(bfd_vma pc, disassemble_info *info);
+
+ INIT_DISASSEMBLE_INFO(disasm_info, (FILE *)mon, monitor_fprintf);
+
+ monitor_disas_env = env;
+ monitor_disas_is_physical = is_physical;
+ disasm_info.read_memory_func = monitor_read_memory;
+
+ disasm_info.buffer_vma = pc;
+
+#ifdef TARGET_WORDS_BIGENDIAN
+ disasm_info.endian = BFD_ENDIAN_BIG;
+#else
+ disasm_info.endian = BFD_ENDIAN_LITTLE;
+#endif
+#if defined(TARGET_I386)
+ if (flags == 2)
+ disasm_info.mach = bfd_mach_x86_64;
+ else if (flags == 1)
+ disasm_info.mach = bfd_mach_i386_i8086;
+ else
+ disasm_info.mach = bfd_mach_i386_i386;
+ print_insn = print_insn_i386;
+#elif defined(TARGET_ARM)
+ print_insn = print_insn_arm;
+#elif defined(TARGET_ALPHA)
+ print_insn = print_insn_alpha;
+#elif defined(TARGET_SPARC)
+ print_insn = print_insn_sparc;
+#ifdef TARGET_SPARC64
+ disasm_info.mach = bfd_mach_sparc_v9b;
+#endif
+#elif defined(TARGET_PPC)
+#ifdef TARGET_PPC64
+ disasm_info.mach = bfd_mach_ppc64;
+#else
+ disasm_info.mach = bfd_mach_ppc;
+#endif
+ print_insn = print_insn_ppc;
+#elif defined(TARGET_M68K)
+ print_insn = print_insn_m68k;
+#elif defined(TARGET_MIPS)
+#ifdef TARGET_WORDS_BIGENDIAN
+ print_insn = print_insn_big_mips;
+#else
+ print_insn = print_insn_little_mips;
+#endif
+#else
+ monitor_printf(mon, "0x" TARGET_FMT_lx
+ ": Asm output not supported on this arch\n", pc);
+ return;
+#endif
+
+ for(i = 0; i < nb_insn; i++) {
+ monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc);
+ count = print_insn(pc, &disasm_info);
+ monitor_printf(mon, "\n");
+ if (count < 0)
+ break;
+ pc += count;
+ }
+}
+#endif