Make MIPS MT implementation more cache friendly.

[qemu] / gdbstub.c

diff --git a/gdbstub.c b/gdbstub.c
index 64f4a9f..f110d1e 100644 (file)
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -610,17 +610,17 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
     ptr = mem_buf;
     for (i = 0; i < 32; i++)
       {
-        *(target_ulong *)ptr = tswapl(env->gpr[i][env->current_tc]);
+        *(target_ulong *)ptr = tswapl(env->gpr[env->current_tc][i]);
         ptr += sizeof(target_ulong);
       }
 
     *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status);
     ptr += sizeof(target_ulong);
 
-    *(target_ulong *)ptr = tswapl(env->LO[0][env->current_tc]);
+    *(target_ulong *)ptr = tswapl(env->LO[env->current_tc][0]);
     ptr += sizeof(target_ulong);
 
-    *(target_ulong *)ptr = tswapl(env->HI[0][env->current_tc]);
+    *(target_ulong *)ptr = tswapl(env->HI[env->current_tc][0]);
     ptr += sizeof(target_ulong);
 
     *(target_ulong *)ptr = tswapl(env->CP0_BadVAddr);
@@ -687,17 +687,17 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
     ptr = mem_buf;
     for (i = 0; i < 32; i++)
       {
-        env->gpr[i][env->current_tc] = tswapl(*(target_ulong *)ptr);
+        env->gpr[env->current_tc][i] = tswapl(*(target_ulong *)ptr);
         ptr += sizeof(target_ulong);
       }
 
     env->CP0_Status = tswapl(*(target_ulong *)ptr);
     ptr += sizeof(target_ulong);
 
-    env->LO[0][env->current_tc] = tswapl(*(target_ulong *)ptr);
+    env->LO[env->current_tc][0] = tswapl(*(target_ulong *)ptr);
     ptr += sizeof(target_ulong);
 
-    env->HI[0][env->current_tc] = tswapl(*(target_ulong *)ptr);
+    env->HI[env->current_tc][0] = tswapl(*(target_ulong *)ptr);
     ptr += sizeof(target_ulong);
 
     env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr);