*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
*/
#include "hw.h"
#include "pc.h"
#include "sysemu.h"
#include "i2c.h"
#include "smbus.h"
+#include "kvm.h"
//#define DEBUG
uint8_t smb_data[32];
uint8_t smb_index;
qemu_irq irq;
- int64_t pmtmr;
} PIIX4PMState;
+#define RSM_STS (1 << 15)
+#define PWRBTN_STS (1 << 8)
#define RTC_EN (1 << 10)
#define PWRBTN_EN (1 << 8)
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
-#define TIMER_OVERFLOW_CNT (1 << 23)
-#define TIMER_MASK 0xffffffLL
#define SCI_EN (1 << 0)
#define SMBHSTDAT1 0x06
#define SMBBLKDAT 0x07
-PIIX4PMState *pm_state;
-
-static void update_pmtmr(PIIX4PMState *s)
-{
- int64_t pmtmr;
-
- pmtmr = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec)
- & TIMER_MASK;
-
- if (!(s->pmsts & TMROF_EN)) {
- if ((pmtmr ^ s->pmtmr) & TIMER_OVERFLOW_CNT) {
- s->pmsts |= TMROF_EN;
- if (s->pmen & TMROF_EN)
- qemu_set_irq(s->irq, 1);
- } else {
- /* Calculate when the timer will neet to set
- * the overflow bit again */
- uint64_t delta = TIMER_OVERFLOW_CNT -
- (pmtmr & (TIMER_OVERFLOW_CNT - 1));
-
- delta = muldiv64(delta, ticks_per_sec, PM_FREQ);
- qemu_mod_timer(s->tmr_timer, qemu_get_clock(vm_clock) + delta);
- }
- }
-
- s->pmtmr = pmtmr;
-}
+static PIIX4PMState *pm_state;
static uint32_t get_pmtmr(PIIX4PMState *s)
{
- update_pmtmr(s);
- return s->pmtmr & TIMER_MASK;
+ uint32_t d;
+ d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
+ return d & 0xffffff;
}
-
static int get_pmsts(PIIX4PMState *s)
{
- /* Just increase the accurancy by double computing the timer value */
- update_pmtmr(s);
-
+ int64_t d;
+ int pmsts;
+ pmsts = s->pmsts;
+ d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
+ if (d >= s->tmr_overflow_time)
+ s->pmsts |= TMROF_EN;
return s->pmsts;
}
static void pm_update_sci(PIIX4PMState *s)
{
- int sci_level;
-
- sci_level = (((s->pmsts & s->pmen) &
- (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
- if (!sci_level)
- qemu_set_irq(s->irq, sci_level);
+ int sci_level, pmsts;
+ int64_t expire_time;
+
+ pmsts = get_pmsts(s);
+ sci_level = (((pmsts & s->pmen) &
+ (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
+ qemu_set_irq(s->irq, sci_level);
+ /* schedule a timer interruption if needed */
+ if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
+ expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
+ qemu_mod_timer(s->tmr_timer, expire_time);
+ } else {
+ qemu_del_timer(s->tmr_timer);
+ }
}
static void pm_tmr_timer(void *opaque)
{
PIIX4PMState *s = opaque;
- update_pmtmr(s);
+ pm_update_sci(s);
}
static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
addr &= 0x3f;
switch(addr) {
case 0x00:
- s->pmsts &= ~val;
- update_pmtmr(s);
- pm_update_sci(s);
+ {
+ int64_t d;
+ int pmsts;
+ pmsts = get_pmsts(s);
+ if (pmsts & val & TMROF_EN) {
+ /* if TMRSTS is reset, then compute the new overflow time */
+ d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
+ s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
+ }
+ s->pmsts &= ~val;
+ pm_update_sci(s);
+ }
break;
case 0x02:
s->pmen = val;
s->pmcntrl = val & ~(SUS_EN);
if (val & SUS_EN) {
/* change suspend type */
- sus_typ = (val >> 10) & 3;
+ sus_typ = (val >> 10) & 7;
switch(sus_typ) {
case 0: /* soft power off */
qemu_system_shutdown_request();
break;
+ case 1:
+ /* RSM_STS should be set on resume. Pretend that resume
+ was caused by power button */
+ s->pmsts |= (RSM_STS | PWRBTN_STS);
+ qemu_system_reset_request();
+#if defined(TARGET_I386)
+ cmos_set_s3_resume();
+#endif
default:
break;
}
return 0;
}
+static void piix4_reset(void *opaque)
+{
+ PIIX4PMState *s = opaque;
+ uint8_t *pci_conf = s->dev.config;
+
+ pci_conf[0x58] = 0;
+ pci_conf[0x59] = 0;
+ pci_conf[0x5a] = 0;
+ pci_conf[0x5b] = 0;
+}
+
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq)
{
devfn, NULL, pm_write_config);
pm_state = s;
pci_conf = s->dev.config;
- pci_conf[0x00] = 0x86;
- pci_conf[0x01] = 0x80;
- pci_conf[0x02] = 0x13;
- pci_conf[0x03] = 0x71;
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
pci_conf[0x06] = 0x80;
pci_conf[0x07] = 0x02;
pci_conf[0x08] = 0x03; // revision number
pci_conf[0x09] = 0x00;
- pci_conf[0x0a] = 0x80; // other bridge device
- pci_conf[0x0b] = 0x06; // bridge device
+ pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
pci_conf[0x0e] = 0x00; // header_type
pci_conf[0x3d] = 0x01; // interrupt pin 1
register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
+ if (kvm_enabled()) {
+ /* Mark SMM as already inited to prevent SMM from running. KVM does not
+ * support SMM mode. */
+ pci_conf[0x5B] = 0x02;
+ }
+
/* XXX: which specification is used ? The i82731AB has different
mappings */
pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
s->smbus = i2c_init_bus();
s->irq = sci_irq;
+ qemu_register_reset(piix4_reset, s);
+
return s->smbus;
}
#if defined(TARGET_I386)
void qemu_system_powerdown(void)
{
- if(pm_state->pmen & PWRBTN_EN) {
+ if (!pm_state) {
+ qemu_system_shutdown_request();
+ } else if (pm_state->pmen & PWRBTN_EN) {
pm_state->pmsts |= PWRBTN_EN;
pm_update_sci(pm_state);
}
}
#endif
+
+#define GPE_BASE 0xafe0
+#define PCI_BASE 0xae00
+#define PCI_EJ_BASE 0xae08
+
+struct gpe_regs {
+ uint16_t sts; /* status */
+ uint16_t en; /* enabled */
+};
+
+struct pci_status {
+ uint32_t up;
+ uint32_t down;
+};
+
+static struct gpe_regs gpe;
+static struct pci_status pci0_status;
+
+static uint32_t gpe_readb(void *opaque, uint32_t addr)
+{
+ uint32_t val = 0;
+ struct gpe_regs *g = opaque;
+ switch (addr) {
+ case GPE_BASE:
+ val = g->sts & 0xFF;
+ break;
+ case GPE_BASE + 1:
+ val = (g->sts >> 8) & 0xFF;
+ break;
+ case GPE_BASE + 2:
+ val = g->en & 0xFF;
+ break;
+ case GPE_BASE + 3:
+ val = (g->en >> 8) & 0xFF;
+ break;
+ default:
+ break;
+ }
+
+#if defined(DEBUG)
+ printf("gpe read %lx == %lx\n", addr, val);
+#endif
+ return val;
+}
+
+static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ struct gpe_regs *g = opaque;
+ switch (addr) {
+ case GPE_BASE:
+ g->sts = (g->sts & ~0xFFFF) | (val & 0xFFFF);
+ break;
+ case GPE_BASE + 1:
+ g->sts = (g->sts & 0xFFFF) | (val << 8);
+ break;
+ case GPE_BASE + 2:
+ g->en = (g->en & ~0xFFFF) | (val & 0xFFFF);
+ break;
+ case GPE_BASE + 3:
+ g->en = (g->en & 0xFFFF) | (val << 8);
+ break;
+ default:
+ break;
+ }
+
+#if defined(DEBUG)
+ printf("gpe write %lx <== %d\n", addr, val);
+#endif
+}
+
+static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
+{
+ uint32_t val = 0;
+ struct pci_status *g = opaque;
+ switch (addr) {
+ case PCI_BASE:
+ val = g->up;
+ break;
+ case PCI_BASE + 4:
+ val = g->down;
+ break;
+ default:
+ break;
+ }
+
+#if defined(DEBUG)
+ printf("pcihotplug read %lx == %lx\n", addr, val);
+#endif
+ return val;
+}
+
+static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ struct pci_status *g = opaque;
+ switch (addr) {
+ case PCI_BASE:
+ g->up = val;
+ break;
+ case PCI_BASE + 4:
+ g->down = val;
+ break;
+ }
+
+#if defined(DEBUG)
+ printf("pcihotplug write %lx <== %d\n", addr, val);
+#endif
+}
+
+static uint32_t pciej_read(void *opaque, uint32_t addr)
+{
+#if defined(DEBUG)
+ printf("pciej read %lx == %lx\n", addr, val);
+#endif
+ return 0;
+}
+
+static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
+{
+#if defined (TARGET_I386)
+ int slot = ffs(val) - 1;
+
+ pci_device_hot_remove_success(0, slot);
+#endif
+
+#if defined(DEBUG)
+ printf("pciej write %lx <== %d\n", addr, val);
+#endif
+}
+
+void qemu_system_hot_add_init(void)
+{
+ register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
+ register_ioport_read(GPE_BASE, 4, 1, gpe_readb, &gpe);
+
+ register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
+ register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status);
+
+ register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
+ register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, NULL);
+}
+
+static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
+{
+ g->sts |= 2;
+ g->en |= 2;
+ p->up |= (1 << slot);
+}
+
+static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
+{
+ g->sts |= 2;
+ g->en |= 2;
+ p->down |= (1 << slot);
+}
+
+void qemu_system_device_hot_add(int bus, int slot, int state)
+{
+ qemu_set_irq(pm_state->irq, 1);
+ pci0_status.up = 0;
+ pci0_status.down = 0;
+ if (state)
+ enable_device(&pci0_status, &gpe, slot);
+ else
+ disable_device(&pci0_status, &gpe, slot);
+ qemu_set_irq(pm_state->irq, 0);
+}
projects / qemu / blobdiff