* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
+
#include "hw.h"
-#include "block.h"
#include "scsi-disk.h"
-#include "sun4m.h"
-/* FIXME: Only needed for MAX_DISKS, which is probably wrong. */
-#include "sysemu.h"
+#include "scsi.h"
/* debug ESP card */
//#define DEBUG_ESP
#define DPRINTF(fmt, args...) \
do { printf("ESP: " fmt , ##args); } while (0)
#else
-#define DPRINTF(fmt, args...)
+#define DPRINTF(fmt, args...) do {} while (0)
#endif
-#define ESP_MASK 0x3f
#define ESP_REGS 16
-#define ESP_SIZE (ESP_REGS * 4)
#define TI_BUFSZ 32
typedef struct ESPState ESPState;
struct ESPState {
+ uint32_t it_shift;
qemu_irq irq;
uint8_t rregs[ESP_REGS];
uint8_t wregs[ESP_REGS];
int32_t ti_size;
uint32_t ti_rptr, ti_wptr;
uint8_t ti_buf[TI_BUFSZ];
- int sense;
- int dma;
+ uint32_t sense;
+ uint32_t dma;
SCSIDevice *scsi_dev[ESP_MAX_DEVS];
SCSIDevice *current_dev;
uint8_t cmdbuf[TI_BUFSZ];
- int cmdlen;
- int do_cmd;
+ uint32_t cmdlen;
+ uint32_t do_cmd;
/* The amount of data left in the current DMA transfer. */
uint32_t dma_left;
uint32_t dma_counter;
uint8_t *async_buf;
uint32_t async_len;
+
+ espdma_memory_read_write dma_memory_read;
+ espdma_memory_read_write dma_memory_write;
void *dma_opaque;
};
#define STAT_TC 0x10
#define STAT_PE 0x20
#define STAT_GE 0x40
-#define STAT_IN 0x80
+#define STAT_INT 0x80
#define INTR_FC 0x08
#define INTR_BS 0x10
#define TCHI_FAS100A 0x4
-static int get_cmd(ESPState *s, uint8_t *buf)
+static void esp_raise_irq(ESPState *s)
+{
+ if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
+ s->rregs[ESP_RSTAT] |= STAT_INT;
+ qemu_irq_raise(s->irq);
+ }
+}
+
+static void esp_lower_irq(ESPState *s)
+{
+ if (s->rregs[ESP_RSTAT] & STAT_INT) {
+ s->rregs[ESP_RSTAT] &= ~STAT_INT;
+ qemu_irq_lower(s->irq);
+ }
+}
+
+static uint32_t get_cmd(ESPState *s, uint8_t *buf)
{
uint32_t dmalen;
int target;
target = s->wregs[ESP_WBUSID] & 7;
DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
if (s->dma) {
- espdma_memory_read(s->dma_opaque, buf, dmalen);
+ s->dma_memory_read(s->dma_opaque, buf, dmalen);
} else {
buf[0] = 0;
memcpy(&buf[1], s->ti_buf, dmalen);
if (s->current_dev) {
/* Started a new command before the old one finished. Cancel it. */
- scsi_cancel_io(s->current_dev, 0);
+ s->current_dev->cancel_io(s->current_dev, 0);
s->async_len = 0;
}
if (target >= ESP_MAX_DEVS || !s->scsi_dev[target]) {
// No such drive
- s->rregs[ESP_RSTAT] = STAT_IN;
+ s->rregs[ESP_RSTAT] = 0;
s->rregs[ESP_RINTR] = INTR_DC;
s->rregs[ESP_RSEQ] = SEQ_0;
- qemu_irq_raise(s->irq);
+ esp_raise_irq(s);
return 0;
}
s->current_dev = s->scsi_dev[target];
DPRINTF("do_cmd: busid 0x%x\n", buf[0]);
lun = buf[0] & 7;
- datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun);
+ datalen = s->current_dev->send_command(s->current_dev, 0, &buf[1], lun);
s->ti_size = datalen;
if (datalen != 0) {
- s->rregs[ESP_RSTAT] = STAT_IN | STAT_TC;
+ s->rregs[ESP_RSTAT] = STAT_TC;
s->dma_left = 0;
s->dma_counter = 0;
if (datalen > 0) {
s->rregs[ESP_RSTAT] |= STAT_DI;
- scsi_read_data(s->current_dev, 0);
+ s->current_dev->read_data(s->current_dev, 0);
} else {
s->rregs[ESP_RSTAT] |= STAT_DO;
- scsi_write_data(s->current_dev, 0);
+ s->current_dev->write_data(s->current_dev, 0);
}
}
s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
s->rregs[ESP_RSEQ] = SEQ_CD;
- qemu_irq_raise(s->irq);
+ esp_raise_irq(s);
}
static void handle_satn(ESPState *s)
if (s->cmdlen) {
DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
s->do_cmd = 1;
- s->rregs[ESP_RSTAT] = STAT_IN | STAT_TC | STAT_CD;
+ s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
s->rregs[ESP_RSEQ] = SEQ_CD;
- qemu_irq_raise(s->irq);
+ esp_raise_irq(s);
}
}
s->ti_buf[0] = s->sense;
s->ti_buf[1] = 0;
if (s->dma) {
- espdma_memory_write(s->dma_opaque, s->ti_buf, 2);
- s->rregs[ESP_RSTAT] = STAT_IN | STAT_TC | STAT_ST;
+ s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
+ s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
s->rregs[ESP_RSEQ] = SEQ_CD;
} else {
s->ti_wptr = 0;
s->rregs[ESP_RFLAGS] = 2;
}
- qemu_irq_raise(s->irq);
+ esp_raise_irq(s);
}
static void esp_dma_done(ESPState *s)
{
- s->rregs[ESP_RSTAT] |= STAT_IN | STAT_TC;
+ s->rregs[ESP_RSTAT] |= STAT_TC;
s->rregs[ESP_RINTR] = INTR_BS;
s->rregs[ESP_RSEQ] = 0;
s->rregs[ESP_RFLAGS] = 0;
s->rregs[ESP_TCLO] = 0;
s->rregs[ESP_TCMID] = 0;
- qemu_irq_raise(s->irq);
+ esp_raise_irq(s);
}
static void esp_do_dma(ESPState *s)
len = s->dma_left;
if (s->do_cmd) {
DPRINTF("command len %d + %d\n", s->cmdlen, len);
- espdma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
+ s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
s->ti_size = 0;
s->cmdlen = 0;
s->do_cmd = 0;
len = s->async_len;
}
if (to_device) {
- espdma_memory_read(s->dma_opaque, s->async_buf, len);
+ s->dma_memory_read(s->dma_opaque, s->async_buf, len);
} else {
- espdma_memory_write(s->dma_opaque, s->async_buf, len);
+ s->dma_memory_write(s->dma_opaque, s->async_buf, len);
}
s->dma_left -= len;
s->async_buf += len;
if (s->async_len == 0) {
if (to_device) {
// ti_size is negative
- scsi_write_data(s->current_dev, 0);
+ s->current_dev->write_data(s->current_dev, 0);
} else {
- scsi_read_data(s->current_dev, 0);
+ s->current_dev->read_data(s->current_dev, 0);
/* If there is still data to be read from the device then
complete the DMA operation immeriately. Otherwise defer
until the scsi layer has completed. */
} else {
DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
s->async_len = arg;
- s->async_buf = scsi_get_buf(s->current_dev, 0);
+ s->async_buf = s->current_dev->get_buf(s->current_dev, 0);
if (s->dma_left) {
esp_do_dma(s);
} else if (s->dma_counter != 0 && s->ti_size <= 0) {
{
ESPState *s = opaque;
+ esp_lower_irq(s);
+
memset(s->rregs, 0, ESP_REGS);
memset(s->wregs, 0, ESP_REGS);
s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
ESPState *s = opaque;
uint32_t saddr;
- saddr = (addr & ESP_MASK) >> 2;
+ saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
switch (saddr) {
case ESP_FIFO:
} else {
s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
}
- qemu_irq_raise(s->irq);
+ esp_raise_irq(s);
}
if (s->ti_size == 0) {
s->ti_rptr = 0;
break;
case ESP_RINTR:
// Clear interrupt/error status bits
- s->rregs[ESP_RSTAT] &= ~(STAT_IN | STAT_GE | STAT_PE);
- qemu_irq_lower(s->irq);
+ s->rregs[ESP_RSTAT] &= ~(STAT_GE | STAT_PE);
+ esp_lower_irq(s);
break;
default:
break;
ESPState *s = opaque;
uint32_t saddr;
- saddr = (addr & ESP_MASK) >> 2;
+ saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
val);
switch (saddr) {
//s->ti_size = 0;
s->rregs[ESP_RINTR] = INTR_FC;
s->rregs[ESP_RSEQ] = 0;
+ s->rregs[ESP_RFLAGS] = 0;
break;
case CMD_RESET:
DPRINTF("Chip reset (%2.2x)\n", val);
DPRINTF("Bus reset (%2.2x)\n", val);
s->rregs[ESP_RINTR] = INTR_RST;
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
- qemu_irq_raise(s->irq);
+ esp_raise_irq(s);
}
break;
case CMD_TI:
static CPUReadMemoryFunc *esp_mem_read[3] = {
esp_mem_readb,
- esp_mem_readb,
- esp_mem_readb,
+ NULL,
+ NULL,
};
static CPUWriteMemoryFunc *esp_mem_write[3] = {
esp_mem_writeb,
- esp_mem_writeb,
- esp_mem_writeb,
+ NULL,
+ NULL,
};
static void esp_save(QEMUFile *f, void *opaque)
qemu_put_buffer(f, s->rregs, ESP_REGS);
qemu_put_buffer(f, s->wregs, ESP_REGS);
- qemu_put_be32s(f, &s->ti_size);
+ qemu_put_be32s(f, (uint32_t *)&s->ti_size);
qemu_put_be32s(f, &s->ti_rptr);
qemu_put_be32s(f, &s->ti_wptr);
qemu_put_buffer(f, s->ti_buf, TI_BUFSZ);
qemu_get_buffer(f, s->rregs, ESP_REGS);
qemu_get_buffer(f, s->wregs, ESP_REGS);
- qemu_get_be32s(f, &s->ti_size);
+ qemu_get_be32s(f, (uint32_t *)&s->ti_size);
qemu_get_be32s(f, &s->ti_rptr);
qemu_get_be32s(f, &s->ti_wptr);
qemu_get_buffer(f, s->ti_buf, TI_BUFSZ);
}
if (s->scsi_dev[id]) {
DPRINTF("Destroying device %d\n", id);
- scsi_disk_destroy(s->scsi_dev[id]);
+ s->scsi_dev[id]->destroy(s->scsi_dev[id]);
}
DPRINTF("Attaching block device %d\n", id);
/* Command queueing is not implemented. */
- s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
+ s->scsi_dev[id] = scsi_generic_init(bd, 0, esp_command_complete, s);
+ if (s->scsi_dev[id] == NULL)
+ s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
}
-void *esp_init(target_phys_addr_t espaddr,
+void *esp_init(target_phys_addr_t espaddr, int it_shift,
+ espdma_memory_read_write dma_memory_read,
+ espdma_memory_read_write dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset)
{
ESPState *s;
return NULL;
s->irq = irq;
+ s->it_shift = it_shift;
+ s->dma_memory_read = dma_memory_read;
+ s->dma_memory_write = dma_memory_write;
s->dma_opaque = dma_opaque;
esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
- cpu_register_physical_memory(espaddr, ESP_SIZE, esp_io_memory);
+ cpu_register_physical_memory(espaddr, ESP_REGS << it_shift, esp_io_memory);
esp_reset(s);
projects / qemu / blobdiff