* The controller is used in Sun4m systems in a slightly different
* way. There are changes in DOR register and DMA is not available.
*/
+
#include "hw.h"
#include "fdc.h"
#include "block.h"
#include "qemu-timer.h"
#include "isa.h"
+#include "sysbus.h"
+#include "qdev-addr.h"
/********************************************************/
/* debug Floppy devices */
//#define DEBUG_FLOPPY
#ifdef DEBUG_FLOPPY
-#define FLOPPY_DPRINTF(fmt, args...) \
-do { printf("FLOPPY: " fmt , ##args); } while (0)
+#define FLOPPY_DPRINTF(fmt, ...) \
+ do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
#else
-#define FLOPPY_DPRINTF(fmt, args...)
+#define FLOPPY_DPRINTF(fmt, ...)
#endif
-#define FLOPPY_ERROR(fmt, args...) \
-do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ##args); } while (0)
+#define FLOPPY_ERROR(fmt, ...) \
+ do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
/********************************************************/
/* Floppy drive emulation */
+#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
+#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
+
/* Will always be a fixed parameter for us */
-#define FD_SECTOR_LEN 512
-#define FD_SECTOR_SC 2 /* Sector size code */
+#define FD_SECTOR_LEN 512
+#define FD_SECTOR_SC 2 /* Sector size code */
+#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
/* Floppy disk drive emulation */
typedef enum fdisk_type_t {
/* HW */
qemu_irq irq;
int dma_chann;
- target_phys_addr_t io_base;
/* Controller state */
QEMUTimer *result_timer;
uint8_t sra;
uint8_t srb;
uint8_t dor;
+ uint8_t dor_vmstate; /* only used as temp during vmstate */
uint8_t tdr;
uint8_t dsr;
uint8_t msr;
uint8_t status2;
/* Command FIFO */
uint8_t *fifo;
+ int32_t fifo_size;
uint32_t data_pos;
uint32_t data_len;
uint8_t data_state;
/* Sun4m quirks? */
int sun4m;
/* Floppy drives */
+ uint8_t num_floppies;
fdrive_t drives[MAX_FD];
+ int reset_sensei;
};
+typedef struct fdctrl_sysbus_t {
+ SysBusDevice busdev;
+ struct fdctrl_t state;
+} fdctrl_sysbus_t;
+
+typedef struct fdctrl_isabus_t {
+ ISADevice busdev;
+ struct fdctrl_t state;
+} fdctrl_isabus_t;
+
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
{
fdctrl_t *fdctrl = opaque;
uint32_t retval;
- switch (reg & 0x07) {
+ switch (reg) {
case FD_REG_SRA:
retval = fdctrl_read_statusA(fdctrl);
break;
FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
- switch (reg & 0x07) {
+ switch (reg) {
case FD_REG_DOR:
fdctrl_write_dor(fdctrl, value);
break;
}
}
+static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
+{
+ return fdctrl_read(opaque, reg & 7);
+}
+
+static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
+{
+ fdctrl_write(opaque, reg & 7, value);
+}
+
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
{
return fdctrl_read(opaque, (uint32_t)reg);
fdctrl_write(opaque, (uint32_t)reg, value);
}
-static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
+static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
fdctrl_read_mem,
fdctrl_read_mem,
fdctrl_read_mem,
};
-static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
+static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
fdctrl_write_mem,
fdctrl_write_mem,
fdctrl_write_mem,
};
-static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
+static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
fdctrl_read_mem,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
+static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
fdctrl_write_mem,
NULL,
NULL,
};
-static void fd_save (QEMUFile *f, fdrive_t *fd)
-{
- qemu_put_8s(f, &fd->head);
- qemu_put_8s(f, &fd->track);
- qemu_put_8s(f, &fd->sect);
-}
+static const VMStateDescription vmstate_fdrive = {
+ .name = "fdrive",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT8(head, fdrive_t),
+ VMSTATE_UINT8(track, fdrive_t),
+ VMSTATE_UINT8(sect, fdrive_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
-static void fdc_save (QEMUFile *f, void *opaque)
+static void fdc_pre_save(const void *opaque)
{
- fdctrl_t *s = opaque;
- uint8_t tmp;
- int i;
+ fdctrl_t *s = (void *)opaque;
- /* Controller state */
- qemu_put_8s(f, &s->sra);
- qemu_put_8s(f, &s->srb);
- qemu_put_8s(f, &s->tdr);
- qemu_put_8s(f, &s->dsr);
- qemu_put_8s(f, &s->msr);
- qemu_put_8s(f, &s->status0);
- qemu_put_8s(f, &s->status1);
- qemu_put_8s(f, &s->status2);
- qemu_put_8s(f, &s->cur_drv);
- /* Command FIFO */
- qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
- qemu_put_be32s(f, &s->data_pos);
- qemu_put_be32s(f, &s->data_len);
- qemu_put_8s(f, &s->data_state);
- qemu_put_8s(f, &s->data_dir);
- qemu_put_8s(f, &s->eot);
- /* States kept only to be returned back */
- qemu_put_8s(f, &s->timer0);
- qemu_put_8s(f, &s->timer1);
- qemu_put_8s(f, &s->precomp_trk);
- qemu_put_8s(f, &s->config);
- qemu_put_8s(f, &s->lock);
- qemu_put_8s(f, &s->pwrd);
-
- tmp = MAX_FD;
- qemu_put_8s(f, &tmp);
- for (i = 0; i < MAX_FD; i++)
- fd_save(f, &s->drives[i]);
+ s->dor_vmstate = s->dor | GET_CUR_DRV(s);
}
-static int fd_load (QEMUFile *f, fdrive_t *fd)
+static int fdc_post_load(void *opaque)
{
- qemu_get_8s(f, &fd->head);
- qemu_get_8s(f, &fd->track);
- qemu_get_8s(f, &fd->sect);
+ fdctrl_t *s = opaque;
+ SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
+ s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
return 0;
}
-static int fdc_load (QEMUFile *f, void *opaque, int version_id)
-{
- fdctrl_t *s = opaque;
- int i, ret = 0;
- uint8_t n;
-
- if (version_id != 2)
- return -EINVAL;
-
- /* Controller state */
- qemu_get_8s(f, &s->sra);
- qemu_get_8s(f, &s->srb);
- qemu_get_8s(f, &s->tdr);
- qemu_get_8s(f, &s->dsr);
- qemu_get_8s(f, &s->msr);
- qemu_get_8s(f, &s->status0);
- qemu_get_8s(f, &s->status1);
- qemu_get_8s(f, &s->status2);
- qemu_get_8s(f, &s->cur_drv);
- /* Command FIFO */
- qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
- qemu_get_be32s(f, &s->data_pos);
- qemu_get_be32s(f, &s->data_len);
- qemu_get_8s(f, &s->data_state);
- qemu_get_8s(f, &s->data_dir);
- qemu_get_8s(f, &s->eot);
- /* States kept only to be returned back */
- qemu_get_8s(f, &s->timer0);
- qemu_get_8s(f, &s->timer1);
- qemu_get_8s(f, &s->precomp_trk);
- qemu_get_8s(f, &s->config);
- qemu_get_8s(f, &s->lock);
- qemu_get_8s(f, &s->pwrd);
- qemu_get_8s(f, &n);
-
- if (n > MAX_FD)
- return -EINVAL;
-
- for (i = 0; i < n; i++) {
- ret = fd_load(f, &s->drives[i]);
- if (ret != 0)
- break;
+static const VMStateDescription vmstate_fdc = {
+ .name = "fdc",
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .minimum_version_id_old = 2,
+ .pre_save = fdc_pre_save,
+ .post_load = fdc_post_load,
+ .fields = (VMStateField []) {
+ /* Controller State */
+ VMSTATE_UINT8(sra, fdctrl_t),
+ VMSTATE_UINT8(srb, fdctrl_t),
+ VMSTATE_UINT8(dor_vmstate, fdctrl_t),
+ VMSTATE_UINT8(tdr, fdctrl_t),
+ VMSTATE_UINT8(dsr, fdctrl_t),
+ VMSTATE_UINT8(msr, fdctrl_t),
+ VMSTATE_UINT8(status0, fdctrl_t),
+ VMSTATE_UINT8(status1, fdctrl_t),
+ VMSTATE_UINT8(status2, fdctrl_t),
+ /* Command FIFO */
+ VMSTATE_VARRAY(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8),
+ VMSTATE_UINT32(data_pos, fdctrl_t),
+ VMSTATE_UINT32(data_len, fdctrl_t),
+ VMSTATE_UINT8(data_state, fdctrl_t),
+ VMSTATE_UINT8(data_dir, fdctrl_t),
+ VMSTATE_UINT8(eot, fdctrl_t),
+ /* States kept only to be returned back */
+ VMSTATE_UINT8(timer0, fdctrl_t),
+ VMSTATE_UINT8(timer1, fdctrl_t),
+ VMSTATE_UINT8(precomp_trk, fdctrl_t),
+ VMSTATE_UINT8(config, fdctrl_t),
+ VMSTATE_UINT8(lock, fdctrl_t),
+ VMSTATE_UINT8(pwrd, fdctrl_t),
+ VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t),
+ VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1,
+ vmstate_fdrive, fdrive_t),
+ VMSTATE_END_OF_LIST()
}
-
- return ret;
-}
+};
static void fdctrl_external_reset(void *opaque)
{
qemu_set_irq(fdctrl->irq, 1);
fdctrl->sra |= FD_SRA_INTPEND;
}
+ fdctrl->reset_sensei = 0;
fdctrl->status0 = status0;
FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
}
fdctrl_reset_fifo(fdctrl);
if (do_irq) {
fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
+ fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
}
}
cur_drv = get_cur_drv(fdctrl);
FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
status0, status1, status2,
- status0 | (cur_drv->head << 2) | fdctrl->cur_drv);
- fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | fdctrl->cur_drv;
+ status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
+ fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
fdctrl->fifo[1] = status1;
fdctrl->fifo[2] = status2;
fdctrl->fifo[3] = cur_drv->track;
uint8_t kh, kt, ks;
int did_seek = 0;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
kt = fdctrl->fifo[2];
kh = fdctrl->fifo[3];
ks = fdctrl->fifo[4];
FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
- fdctrl->cur_drv, kh, kt, ks,
+ GET_CUR_DRV(fdctrl), kh, kt, ks,
_fd_sector(kh, kt, ks, cur_drv->last_sect));
switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
case 2:
} else {
int tmp;
fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
- tmp = (cur_drv->last_sect - ks + 1);
+ tmp = (fdctrl->fifo[6] - ks + 1);
if (fdctrl->fifo[0] & 0x80)
- tmp += cur_drv->last_sect;
+ tmp += fdctrl->fifo[6];
fdctrl->data_len *= tmp;
}
fdctrl->eot = fdctrl->fifo[6];
len = FD_SECTOR_LEN - rel_pos;
FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
"(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
- fdctrl->data_len, fdctrl->cur_drv, cur_drv->head,
+ fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
fd_sector(cur_drv) * FD_SECTOR_LEN);
if (fdctrl->data_dir != FD_DIR_WRITE ||
fdrive_t *cur_drv;
uint8_t kh, kt, ks;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
kt = fdctrl->fifo[6];
kh = fdctrl->fifo[7];
ks = fdctrl->fifo[8];
FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
- fdctrl->cur_drv, kh, kt, ks,
+ GET_CUR_DRV(fdctrl), kh, kt, ks,
_fd_sector(kh, kt, ks, cur_drv->last_sect));
switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
case 2:
/* XXX: should set main status register to busy */
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
qemu_mod_timer(fdctrl->result_timer,
- qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
+ qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
}
static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
{
fdrive_t *cur_drv;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
fdctrl->data_state |= FD_STATE_FORMAT;
if (fdctrl->fifo[0] & 0x80)
{
fdrive_t *cur_drv;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
/* 1 Byte status back */
fdctrl->fifo[0] = (cur_drv->ro << 6) |
(cur_drv->track == 0 ? 0x10 : 0x00) |
(cur_drv->head << 2) |
- fdctrl->cur_drv |
+ GET_CUR_DRV(fdctrl) |
0x28;
fdctrl_set_fifo(fdctrl, 1, 0);
}
{
fdrive_t *cur_drv;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
fd_recalibrate(cur_drv);
fdctrl_reset_fifo(fdctrl);
{
fdrive_t *cur_drv = get_cur_drv(fdctrl);
-#if 0
- fdctrl->fifo[0] =
- fdctrl->status0 | (cur_drv->head << 2) | fdctrl->cur_drv;
-#else
- /* XXX: status0 handling is broken for read/write
- commands, so we do this hack. It should be suppressed
- ASAP */
- fdctrl->fifo[0] =
- FD_SR0_SEEK | (cur_drv->head << 2) | fdctrl->cur_drv;
-#endif
+ if(fdctrl->reset_sensei > 0) {
+ fdctrl->fifo[0] =
+ FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
+ fdctrl->reset_sensei--;
+ } else {
+ /* XXX: status0 handling is broken for read/write
+ commands, so we do this hack. It should be suppressed
+ ASAP */
+ fdctrl->fifo[0] =
+ FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
+ }
+
fdctrl->fifo[1] = cur_drv->track;
fdctrl_set_fifo(fdctrl, 2, 0);
fdctrl_reset_irq(fdctrl);
{
fdrive_t *cur_drv;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
fdctrl_reset_fifo(fdctrl);
if (fdctrl->fifo[2] > cur_drv->max_track) {
} else if (fdctrl->data_len > 7) {
/* ERROR */
fdctrl->fifo[0] = 0x80 |
- (cur_drv->head << 2) | fdctrl->cur_drv;
+ (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
fdctrl_set_fifo(fdctrl, 1, 1);
}
}
{
fdrive_t *cur_drv;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
cur_drv->track = cur_drv->max_track - 1;
{
fdrive_t *cur_drv;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[2] > cur_drv->track) {
cur_drv->track = 0;
/* Is it write command time ? */
if (fdctrl->msr & FD_MSR_NONDMA) {
/* FIFO data write */
- fdctrl->fifo[fdctrl->data_pos++] = value;
- if (fdctrl->data_pos % FD_SECTOR_LEN == (FD_SECTOR_LEN - 1) ||
+ pos = fdctrl->data_pos++;
+ pos %= FD_SECTOR_LEN;
+ fdctrl->fifo[pos] = value;
+ if (pos == FD_SECTOR_LEN - 1 ||
fdctrl->data_pos == fdctrl->data_len) {
cur_drv = get_cur_drv(fdctrl);
if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
}
/* Init functions */
-static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
- target_phys_addr_t io_base,
- BlockDriverState **fds)
+static void fdctrl_connect_drives(fdctrl_t *fdctrl, BlockDriverState **fds)
+{
+ unsigned int i;
+
+ for (i = 0; i < MAX_FD; i++) {
+ fd_init(&fdctrl->drives[i], fds[i]);
+ fd_revalidate(&fdctrl->drives[i]);
+ }
+}
+
+fdctrl_t *fdctrl_init_isa(BlockDriverState **fds)
+{
+ fdctrl_t *fdctrl;
+ ISADevice *dev;
+ int dma_chann = 2;
+
+ dev = isa_create_simple("isa-fdc");
+ fdctrl = &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state);
+
+ fdctrl->dma_chann = dma_chann;
+ DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
+
+ fdctrl_connect_drives(fdctrl, fds);
+
+ return fdctrl;
+}
+
+fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
+ target_phys_addr_t mmio_base,
+ BlockDriverState **fds)
{
fdctrl_t *fdctrl;
+ DeviceState *dev;
+ fdctrl_sysbus_t *sys;
+
+ dev = qdev_create(NULL, "sysbus-fdc");
+ qdev_init(dev);
+ sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
+ fdctrl = &sys->state;
+ sysbus_connect_irq(&sys->busdev, 0, irq);
+ sysbus_mmio_map(&sys->busdev, 0, mmio_base);
+
+ fdctrl->dma_chann = dma_chann;
+ DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
+ fdctrl_connect_drives(fdctrl, fds);
+
+ return fdctrl;
+}
+
+fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
+ BlockDriverState **fds, qemu_irq *fdc_tc)
+{
+ DeviceState *dev;
+ fdctrl_sysbus_t *sys;
+ fdctrl_t *fdctrl;
+
+ dev = qdev_create(NULL, "SUNW,fdtwo");
+ qdev_init(dev);
+ sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
+ fdctrl = &sys->state;
+ sysbus_connect_irq(&sys->busdev, 0, irq);
+ sysbus_mmio_map(&sys->busdev, 0, io_base);
+ *fdc_tc = qdev_get_gpio_in(dev, 0);
+
+ fdctrl->dma_chann = -1;
+
+ fdctrl_connect_drives(fdctrl, fds);
+
+ return fdctrl;
+}
+
+static int fdctrl_init_common(fdctrl_t *fdctrl)
+{
int i, j;
+ static int command_tables_inited = 0;
/* Fill 'command_to_handler' lookup table */
- for (i = sizeof(handlers)/sizeof(handlers[0]) - 1; i >= 0; i--) {
- for (j = 0; j < sizeof(command_to_handler); j++) {
- if ((j & handlers[i].mask) == handlers[i].value)
- command_to_handler[j] = i;
+ if (!command_tables_inited) {
+ command_tables_inited = 1;
+ for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
+ for (j = 0; j < sizeof(command_to_handler); j++) {
+ if ((j & handlers[i].mask) == handlers[i].value) {
+ command_to_handler[j] = i;
+ }
+ }
}
}
FLOPPY_DPRINTF("init controller\n");
- fdctrl = qemu_mallocz(sizeof(fdctrl_t));
- if (!fdctrl)
- return NULL;
fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
- if (fdctrl->fifo == NULL) {
- qemu_free(fdctrl);
- return NULL;
- }
+ fdctrl->fifo_size = 512;
fdctrl->result_timer = qemu_new_timer(vm_clock,
fdctrl_result_timer, fdctrl);
fdctrl->version = 0x90; /* Intel 82078 controller */
- fdctrl->irq = irq;
- fdctrl->dma_chann = dma_chann;
- fdctrl->io_base = io_base;
fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
- if (fdctrl->dma_chann != -1) {
- DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
- }
- for (i = 0; i < MAX_FD; i++) {
- fd_init(&fdctrl->drives[i], fds[i]);
- }
+ fdctrl->num_floppies = MAX_FD;
+
fdctrl_external_reset(fdctrl);
- register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
+ vmstate_register(-1, &vmstate_fdc, fdctrl);
qemu_register_reset(fdctrl_external_reset, fdctrl);
- for (i = 0; i < MAX_FD; i++) {
- fd_revalidate(&fdctrl->drives[i]);
- }
-
- return fdctrl;
+ return 0;
}
-fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
- target_phys_addr_t io_base,
- BlockDriverState **fds)
+static int isabus_fdc_init1(ISADevice *dev)
{
- fdctrl_t *fdctrl;
- int io_mem;
+ fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev);
+ fdctrl_t *fdctrl = &isa->state;
+ int iobase = 0x3f0;
+ int isairq = 6;
- fdctrl = fdctrl_init_common(irq, dma_chann, io_base, fds);
+ register_ioport_read(iobase + 0x01, 5, 1,
+ &fdctrl_read_port, fdctrl);
+ register_ioport_read(iobase + 0x07, 1, 1,
+ &fdctrl_read_port, fdctrl);
+ register_ioport_write(iobase + 0x01, 5, 1,
+ &fdctrl_write_port, fdctrl);
+ register_ioport_write(iobase + 0x07, 1, 1,
+ &fdctrl_write_port, fdctrl);
+ isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
- fdctrl->sun4m = 0;
- if (mem_mapped) {
- io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write,
- fdctrl);
- cpu_register_physical_memory(io_base, 0x08, io_mem);
- } else {
- register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read,
- fdctrl);
- register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read,
- fdctrl);
- register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write,
- fdctrl);
- register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
- fdctrl);
- }
+ return fdctrl_init_common(fdctrl);
+}
- return fdctrl;
+static int sysbus_fdc_init1(SysBusDevice *dev)
+{
+ fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
+ int io;
+
+ io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
+ sysbus_init_mmio(dev, 0x08, io);
+ sysbus_init_irq(dev, &fdctrl->irq);
+ qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
+
+ return fdctrl_init_common(fdctrl);
}
-fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
- BlockDriverState **fds, qemu_irq *fdc_tc)
+static int sun4m_fdc_init1(SysBusDevice *dev)
{
- fdctrl_t *fdctrl;
- int io_mem;
+ fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
+ int io;
+
+ io = cpu_register_io_memory(fdctrl_mem_read_strict,
+ fdctrl_mem_write_strict, fdctrl);
+ sysbus_init_mmio(dev, 0x08, io);
+ sysbus_init_irq(dev, &fdctrl->irq);
+ qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
- fdctrl = fdctrl_init_common(irq, -1, io_base, fds);
fdctrl->sun4m = 1;
- io_mem = cpu_register_io_memory(0, fdctrl_mem_read_strict,
- fdctrl_mem_write_strict,
- fdctrl);
- cpu_register_physical_memory(io_base, 0x08, io_mem);
- *fdc_tc = *qemu_allocate_irqs(fdctrl_handle_tc, fdctrl, 1);
+ return fdctrl_init_common(fdctrl);
+}
- return fdctrl;
+static ISADeviceInfo isa_fdc_info = {
+ .init = isabus_fdc_init1,
+ .qdev.name = "isa-fdc",
+ .qdev.size = sizeof(fdctrl_isabus_t),
+};
+
+static SysBusDeviceInfo sysbus_fdc_info = {
+ .init = sysbus_fdc_init1,
+ .qdev.name = "sysbus-fdc",
+ .qdev.size = sizeof(fdctrl_sysbus_t),
+};
+
+static SysBusDeviceInfo sun4m_fdc_info = {
+ .init = sun4m_fdc_init1,
+ .qdev.name = "SUNW,fdtwo",
+ .qdev.size = sizeof(fdctrl_sysbus_t),
+};
+
+static void fdc_register_devices(void)
+{
+ isa_qdev_register(&isa_fdc_info);
+ sysbus_register_withprop(&sysbus_fdc_info);
+ sysbus_register_withprop(&sun4m_fdc_info);
}
+
+device_init(fdc_register_devices)
projects / qemu / blobdiff