vmstate: Add pre/post_save() hooks

[qemu] / hw / m48t59.c

diff --git a/hw/m48t59.c b/hw/m48t59.c
index b781f50..0fcf4f8 100644 (file)
--- a/hw/m48t59.c
+++ b/hw/m48t59.c
@@ -23,16 +23,16 @@
  */
 #include "hw.h"
 #include "nvram.h"
-#include "isa.h"
 #include "qemu-timer.h"
 #include "sysemu.h"
+#include "sysbus.h"
 
 //#define DEBUG_NVRAM
 
 #if defined(DEBUG_NVRAM)
-#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
+#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
 #else
-#define NVRAM_PRINTF(fmt, args...) do { } while (0)
+#define NVRAM_PRINTF(fmt, ...) do { } while (0)
 #endif
 
 /*
@@ -41,14 +41,13 @@
  * PPC platform there is also a nvram lock function.
  */
 struct m48t59_t {
+    SysBusDevice busdev;
     /* Model parameters */
-    int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
+    uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
     /* Hardware parameters */
     qemu_irq IRQ;
-    int mem_index;
-    target_phys_addr_t mem_base;
     uint32_t io_base;
-    uint16_t size;
+    uint32_t size;
     /* RTC management */
     time_t   time_offset;
     time_t   stop_time;
@@ -514,7 +513,6 @@ static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
 {
     m48t59_t *NVRAM = opaque;
 
-    addr -= NVRAM->mem_base;
     m48t59_write(NVRAM, addr, value & 0xff);
 }
 
@@ -522,7 +520,6 @@ static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 {
     m48t59_t *NVRAM = opaque;
 
-    addr -= NVRAM->mem_base;
     m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
     m48t59_write(NVRAM, addr + 1, value & 0xff);
 }
@@ -531,7 +528,6 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 {
     m48t59_t *NVRAM = opaque;
 
-    addr -= NVRAM->mem_base;
     m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
     m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
     m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
@@ -543,7 +539,6 @@ static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
     m48t59_t *NVRAM = opaque;
     uint32_t retval;
 
-    addr -= NVRAM->mem_base;
     retval = m48t59_read(NVRAM, addr);
     return retval;
 }
@@ -553,7 +548,6 @@ static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
     m48t59_t *NVRAM = opaque;
     uint32_t retval;
 
-    addr -= NVRAM->mem_base;
     retval = m48t59_read(NVRAM, addr) << 8;
     retval |= m48t59_read(NVRAM, addr + 1);
     return retval;
@@ -564,7 +558,6 @@ static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
     m48t59_t *NVRAM = opaque;
     uint32_t retval;
 
-    addr -= NVRAM->mem_base;
     retval = m48t59_read(NVRAM, addr) << 24;
     retval |= m48t59_read(NVRAM, addr + 1) << 16;
     retval |= m48t59_read(NVRAM, addr + 2) << 8;
@@ -572,13 +565,13 @@ static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
     return retval;
 }
 
-static CPUWriteMemoryFunc *nvram_write[] = {
+static CPUWriteMemoryFunc * const nvram_write[] = {
     &nvram_writeb,
     &nvram_writew,
     &nvram_writel,
 };
 
-static CPUReadMemoryFunc *nvram_read[] = {
+static CPUReadMemoryFunc * const nvram_read[] = {
     &nvram_readb,
     &nvram_readw,
     &nvram_readl,
@@ -611,6 +604,8 @@ static void m48t59_reset(void *opaque)
 {
     m48t59_t *NVRAM = opaque;
 
+    NVRAM->addr = 0;
+    NVRAM->lock = 0;
     if (NVRAM->alrm_timer != NULL)
         qemu_del_timer(NVRAM->alrm_timer);
 
@@ -623,41 +618,67 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
                        uint32_t io_base, uint16_t size,
                        int type)
 {
-    m48t59_t *s;
-    target_phys_addr_t save_base;
-
-    s = qemu_mallocz(sizeof(m48t59_t));
-    if (!s)
-       return NULL;
-    s->buffer = qemu_mallocz(size);
-    if (!s->buffer) {
-        qemu_free(s);
-        return NULL;
-    }
-    s->IRQ = IRQ;
-    s->size = size;
-    s->mem_base = mem_base;
-    s->io_base = io_base;
-    s->addr = 0;
-    s->type = type;
+    DeviceState *dev;
+    SysBusDevice *s;
+    m48t59_t *d;
+
+    dev = qdev_create(NULL, "m48t59");
+    qdev_prop_set_uint32(dev, "type", type);
+    qdev_prop_set_uint32(dev, "size", size);
+    qdev_prop_set_uint32(dev, "io_base", io_base);
+    qdev_init(dev);
+    s = sysbus_from_qdev(dev);
+    sysbus_connect_irq(s, 0, IRQ);
     if (io_base != 0) {
         register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
         register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
     }
     if (mem_base != 0) {
-        s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
-        cpu_register_physical_memory(mem_base, size, s->mem_index);
+        sysbus_mmio_map(s, 0, mem_base);
     }
-    if (type == 59) {
+
+    d = FROM_SYSBUS(m48t59_t, s);
+
+    return d;
+}
+
+static int m48t59_init1(SysBusDevice *dev)
+{
+    m48t59_t *s = FROM_SYSBUS(m48t59_t, dev);
+    int mem_index;
+
+    s->buffer = qemu_mallocz(s->size);
+    sysbus_init_irq(dev, &s->IRQ);
+
+    mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
+    sysbus_init_mmio(dev, s->size, mem_index);
+
+    if (s->type == 59) {
         s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
         s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
     }
-    s->lock = 0;
     qemu_get_timedate(&s->alarm, 0);
 
     qemu_register_reset(m48t59_reset, s);
-    save_base = mem_base ? mem_base : io_base;
-    register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);
+    register_savevm("m48t59", -1, 1, m48t59_save, m48t59_load, s);
+    return 0;
+}
 
-    return s;
+static SysBusDeviceInfo m48t59_info = {
+    .init = m48t59_init1,
+    .qdev.name  = "m48t59",
+    .qdev.size  = sizeof(m48t59_t),
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_UINT32("size",    m48t59_t, size,    -1),
+        DEFINE_PROP_UINT32("type",    m48t59_t, type,    -1),
+        DEFINE_PROP_HEX32( "io_base", m48t59_t, io_base,  0),
+        DEFINE_PROP_END_OF_LIST(),
+    }
+};
+
+static void m48t59_register_devices(void)
+{
+    sysbus_register_withprop(&m48t59_info);
 }
+
+device_init(m48t59_register_devices)