qemu_irq_lower(s->irq);
}
-static void m5208_timer_write(m5208_timer_state *s, int offset,
+static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
+ m5208_timer_state *s = (m5208_timer_state *)opaque;
int prescale;
int limit;
switch (offset) {
case 4:
break;
default:
- /* Should never happen. */
- abort();
+ hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);
+ break;
}
m5208_timer_update(s);
}
m5208_timer_update(s);
}
-typedef struct {
- m5208_timer_state timer[2];
-} m5208_sys_state;
+static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
+{
+ m5208_timer_state *s = (m5208_timer_state *)opaque;
+ switch (addr) {
+ case 0:
+ return s->pcsr;
+ case 2:
+ return s->pmr;
+ case 4:
+ return ptimer_get_count(s->timer);
+ default:
+ hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
+ return 0;
+ }
+}
+
+static CPUReadMemoryFunc * const m5208_timer_readfn[] = {
+ m5208_timer_read,
+ m5208_timer_read,
+ m5208_timer_read
+};
+
+static CPUWriteMemoryFunc * const m5208_timer_writefn[] = {
+ m5208_timer_write,
+ m5208_timer_write,
+ m5208_timer_write
+};
static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
{
- m5208_sys_state *s = (m5208_sys_state *)opaque;
switch (addr) {
- /* PIT0 */
- case 0xfc080000:
- return s->timer[0].pcsr;
- case 0xfc080002:
- return s->timer[0].pmr;
- case 0xfc080004:
- return ptimer_get_count(s->timer[0].timer);
- /* PIT1 */
- case 0xfc084000:
- return s->timer[1].pcsr;
- case 0xfc084002:
- return s->timer[1].pmr;
- case 0xfc084004:
- return ptimer_get_count(s->timer[1].timer);
-
- /* SDRAM Controller. */
- case 0xfc0a8110: /* SDCS0 */
+ case 0x110: /* SDCS0 */
{
int n;
for (n = 0; n < 32; n++) {
}
return (n - 1) | 0x40000000;
}
- case 0xfc0a8114: /* SDCS1 */
+ case 0x114: /* SDCS1 */
return 0;
default:
- cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x\n",
- (int)addr);
+ hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
return 0;
}
}
static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- m5208_sys_state *s = (m5208_sys_state *)opaque;
- switch (addr) {
- /* PIT0 */
- case 0xfc080000:
- case 0xfc080002:
- case 0xfc080004:
- m5208_timer_write(&s->timer[0], addr & 0xf, value);
- return;
- /* PIT1 */
- case 0xfc084000:
- case 0xfc084002:
- case 0xfc084004:
- m5208_timer_write(&s->timer[1], addr & 0xf, value);
- return;
- default:
- cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
- (int)addr);
- break;
- }
+ hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
}
-static CPUReadMemoryFunc *m5208_sys_readfn[] = {
+static CPUReadMemoryFunc * const m5208_sys_readfn[] = {
m5208_sys_read,
m5208_sys_read,
m5208_sys_read
};
-static CPUWriteMemoryFunc *m5208_sys_writefn[] = {
+static CPUWriteMemoryFunc * const m5208_sys_writefn[] = {
m5208_sys_write,
m5208_sys_write,
m5208_sys_write
static void mcf5208_sys_init(qemu_irq *pic)
{
int iomemtype;
- m5208_sys_state *s;
+ m5208_timer_state *s;
QEMUBH *bh;
int i;
- s = (m5208_sys_state *)qemu_mallocz(sizeof(m5208_sys_state));
- iomemtype = cpu_register_io_memory(0, m5208_sys_readfn,
- m5208_sys_writefn, s);
+ iomemtype = cpu_register_io_memory(m5208_sys_readfn,
+ m5208_sys_writefn, NULL);
/* SDRAMC. */
cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
/* Timers. */
for (i = 0; i < 2; i++) {
- bh = qemu_bh_new(m5208_timer_trigger, &s->timer[i]);
- s->timer[i].timer = ptimer_init(bh);
+ s = (m5208_timer_state *)qemu_mallocz(sizeof(m5208_timer_state));
+ bh = qemu_bh_new(m5208_timer_trigger, s);
+ s->timer = ptimer_init(bh);
+ iomemtype = cpu_register_io_memory(m5208_timer_readfn,
+ m5208_timer_writefn, s);
cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
iomemtype);
- s->timer[i].irq = pic[4 + i];
+ s->irq = pic[4 + i];
}
}
-static void mcf5208evb_init(int ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+static void mcf5208evb_init(ram_addr_t ram_size,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
env->vbr = 0;
/* TODO: Configure BARs. */
- /* DRAM at 0x20000000 */
+ /* DRAM at 0x40000000 */
cpu_register_physical_memory(0x40000000, ram_size,
qemu_ram_alloc(ram_size) | IO_MEM_RAM);
fprintf(stderr, "Too many NICs\n");
exit(1);
}
- if (nd_table[0].vlan) {
- if (nd_table[0].model == NULL
- || strcmp(nd_table[0].model, "mcf_fec") == 0) {
- mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36);
- } else if (strcmp(nd_table[0].model, "?") == 0) {
- fprintf(stderr, "qemu: Supported NICs: mcf_fec\n");
- exit (1);
- } else {
- fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
- exit (1);
- }
- }
+ if (nd_table[0].vlan)
+ mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36);
/* 0xfc000000 SCM. */
/* 0xfc004000 XBS. */
kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL);
entry = elf_entry;
if (kernel_size < 0) {
- kernel_size = load_uboot(kernel_filename, &entry, NULL);
+ kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
}
if (kernel_size < 0) {
- kernel_size = load_image(kernel_filename, phys_ram_base);
- entry = 0x20000000;
+ kernel_size = load_image_targphys(kernel_filename, 0x40000000,
+ ram_size);
+ entry = 0x40000000;
}
if (kernel_size < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
env->pc = entry;
}
-QEMUMachine mcf5208evb_machine = {
- "mcf5208evb",
- "MCF5206EVB",
- mcf5208evb_init,
+static QEMUMachine mcf5208evb_machine = {
+ .name = "mcf5208evb",
+ .desc = "MCF5206EVB",
+ .init = mcf5208evb_init,
+ .is_default = 1,
};
+
+static void mcf5208evb_machine_init(void)
+{
+ qemu_register_machine(&mcf5208evb_machine);
+}
+
+machine_init(mcf5208evb_machine_init);
projects / qemu / blobdiff