qdev scsi bus infrastructure

[qemu] / hw / mipsnet.c

diff --git a/hw/mipsnet.c b/hw/mipsnet.c
index 5a74ad9..e842984 100644 (file)
--- a/hw/mipsnet.c
+++ b/hw/mipsnet.c
@@ -11,7 +11,6 @@
 /* MIPSnet register offsets */
 
 #define MIPSNET_DEV_ID         0x00
-# define MIPSNET_DEV_ID_STRING "MIPSNET0"
 #define MIPSNET_BUSY           0x08
 #define MIPSNET_RX_DATA_COUNT  0x0c
 #define MIPSNET_TX_DATA_COUNT  0x10
@@ -34,9 +33,9 @@ typedef struct MIPSnetState {
     uint32_t intctl;
     uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
     uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
+    int io_base;
     qemu_irq irq;
     VLANClientState *vc;
-    NICInfo *nd;
 } MIPSnetState;
 
 static void mipsnet_reset(MIPSnetState *s)
@@ -105,15 +104,14 @@ static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr)
 {
     MIPSnetState *s = opaque;
     int ret = 0;
-    const char *devid = MIPSNET_DEV_ID_STRING;
 
     addr &= 0x3f;
     switch (addr) {
     case MIPSNET_DEV_ID:
-       ret = *((uint32_t *)&devid);
+       ret = be32_to_cpu(0x4d495053);          /* MIPS */
         break;
     case MIPSNET_DEV_ID + 4:
-       ret = *((uint32_t *)(&devid + 4));
+       ret = be32_to_cpu(0x4e455430);          /* NET0 */
         break;
     case MIPSNET_BUSY:
        ret = s->busy;
@@ -234,13 +232,24 @@ static int mipsnet_load(QEMUFile *f, void *opaque, int version_id)
     return 0;
 }
 
+static void mipsnet_cleanup(VLANClientState *vc)
+{
+    MIPSnetState *s = vc->opaque;
+
+    unregister_savevm("mipsnet", s);
+
+    isa_unassign_ioport(s->io_base, 36);
+
+    qemu_free(s);
+}
+
 void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
 {
     MIPSnetState *s;
 
+    qemu_check_nic_model(nd, "mipsnet");
+
     s = qemu_mallocz(sizeof(MIPSnetState));
-    if (!s)
-        return;
 
     register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
     register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
@@ -249,23 +258,17 @@ void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
     register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
     register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
 
+    s->io_base = base;
     s->irq = irq;
-    s->nd = nd;
     if (nd && nd->vlan) {
-        s->vc = qemu_new_vlan_client(nd->vlan, mipsnet_receive,
-                                     mipsnet_can_receive, s);
+        s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
+                                     mipsnet_receive, mipsnet_can_receive,
+                                     mipsnet_cleanup, s);
     } else {
         s->vc = NULL;
     }
 
-    snprintf(s->vc->info_str, sizeof(s->vc->info_str),
-             "mipsnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
-              s->nd->macaddr[0],
-              s->nd->macaddr[1],
-              s->nd->macaddr[2],
-              s->nd->macaddr[3],
-              s->nd->macaddr[4],
-              s->nd->macaddr[5]);
+    qemu_format_nic_info_str(s->vc, nd->macaddr);
 
     mipsnet_reset(s);
     register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);