struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
struct omap_target_agent_s;
-struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);
target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
int iotype);
+target_phys_addr_t omap_l4_base(struct omap_target_agent_s *ta, int region);
+uint32_t omap_l4_size(struct omap_target_agent_s *ta, int region);
# define l4_register_io_memory cpu_register_io_memory
struct omap_intr_handler_s;
qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
struct omap_mpu_state_s *mpu);
-struct omap3_prm_s;
-struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,
- qemu_irq mpu_int, qemu_irq iva_int,
- struct omap_mpu_state_s *mpu);
-
-struct omap3_cm_s;
-struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,
- qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
- struct omap_mpu_state_s *mpu);
-
struct omap_sysctl_s;
struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
omap_clk iclk, struct omap_mpu_state_s *mpu);
target_phys_addr_t base, qemu_irq irq);
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
void (*base_upd)(void *opaque, target_phys_addr_t new),
- void (*unmap)(void *opaque), void *opaque,
- struct nand_flash_s *nand_s);
+ void (*unmap)(void *opaque), void *opaque, int devicetype);
/*
* Common IRQ numbers for level 1 interrupt handler
#define OMAP_INT_3XXX_BENCH 3 /* MPU emulation */
#define OMAP_INT_3XXX_MCBSP2_ST_IRQ 4 /* Sidetone MCBSP2 overflow */
#define OMAP_INT_3XXX_MCBSP3_ST_IRQ 5 /* Sidetone MCBSP3 overflow */
-/* IRQ6 is reserved */
+#define OMAP_INT_3XXX_SSM_ABORT_IRQ 6
#define OMAP_INT_3XXX_SYS_NIRQ 7 /* External source (active low) */
-/* IRQ8 is reserved */
+#define OMAP_INT_3XXX_D2D_FW_IRQ 8
#define OMAP_INT_3XXX_SMX_DBG_IRQ 9 /* L3 interconnect error for debug */
#define OMAP_INT_3XXX_SMX_APP_IRQ 10 /* L3 interconnect error for application */
#define OMAP_INT_3XXX_PRCM_MPU_IRQ 11 /* PRCM module IRQ */
#define OMAP_INT_3XXX_GPIO4_MPU_IRQ 32 /* GPIO module 4 */
#define OMAP_INT_3XXX_GPIO5_MPU_IRQ 33 /* GPIO module 5 */
#define OMAP_INT_3XXX_GPIO6_MPU_IRQ 34 /* GPIO module 6 */
-/* IRQ35 is reserved */
+#define OMAP_INT_3XXX_USIM_IRQ 35
#define OMAP_INT_3XXX_WDT3_IRQ 36 /* Watchdog timer module 3 overflow */
#define OMAP_INT_3XXX_GPT1_IRQ 37 /* General-purpose timer module 1 */
#define OMAP_INT_3XXX_GPT2_IRQ 38 /* General-purpose timer module 2 */
#define OMAP_INT_3XXX_GPT9_IRQ 45 /* General-purpose timer module 9 */
#define OMAP_INT_3XXX_GPT10_IRQ 46 /* General-purpose timer module 10 */
#define OMAP_INT_3XXX_GPT11_IRQ 47 /* General-purpose timer module 11 */
-#define OMAP_INT_3XXX_SPI4_IRQ 48 /* MCSPI module 4 */
-/* IRQ49 is reserved */
-/* IRQ50 is reserved */
-/* IRQ51 is reserved */
-/* IRQ52 is reserved */
+#define OMAP_INT_3XXX_MCSPI4_IRQ 48 /* MCSPI module 4 */
+#define OMAP_INT_3XXX_SHA1MD52_IRQ 49
+#define OMAP_INT_3XXX_FPKA_READY 50
+#define OMAP_INT_3XXX_SHA1MD51_IRQ 51
+#define OMAP_INT_3XXX_RNG_IRQ 52
#define OMAP_INT_3XXX_MG_IRQ 53
#define OMAP_INT_3XXX_MCBSP4_IRQ_TX 54 /* MCBSP module 4 transmit */
#define OMAP_INT_3XXX_MCBSP4_IRQ_RX 55 /* MCBSP module 4 receive */
#define OMAP_INT_3XXX_I2C3_IRQ 61 /* I2C module 3 */
#define OMAP_INT_3XXX_MCBSP2_IRQ_TX 62 /* MCBSP module 2 transmit */
#define OMAP_INT_3XXX_MCBSP2_IRQ_RX 63 /* MCBSP module 2 receive */
-/* IRQ64 is reserved */
+#define OMAP_INT_3XXX_FPKA_ERROR 64
#define OMAP_INT_3XXX_MCSPI1_IRQ 65 /* MCSPI module 1 */
#define OMAP_INT_3XXX_MCSPI2_IRQ 66 /* MCSPI module 2 */
/* IRQ67 is reserved */
struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk);
+struct soc_dma_s *omap3_dma4_init(struct omap_target_agent_s *ta,
+ struct omap_mpu_state_s *mpu,
+ qemu_irq *irqs, int chans,
+ omap_clk iclk, omap_clk fclk);
void omap_dma_reset(struct soc_dma_s *s);
struct dma_irq_map {
int dual;
int current_frame;
- ram_addr_t phys_framebuffer[2];
+ target_phys_addr_t phys_framebuffer[2];
qemu_irq irq;
struct omap_mpu_state_s *mpu;
} *omap_dma_get_lcdch(struct soc_dma_s *s);
#define OMAP3XXX_DMA_SPI1_TX2 39
#define OMAP3XXX_DMA_SPI1_RX2 40
#define OMAP3XXX_DMA_SPI1_TX3 41
-#define OMAP3XXX_DMA_SPI1_RX4 42
+#define OMAP3XXX_DMA_SPI1_RX3 42
#define OMAP3XXX_DMA_SPI2_TX0 43
#define OMAP3XXX_DMA_SPI2_RX0 44
#define OMAP3XXX_DMA_SPI2_TX1 45
#define OMAP3XXX_DMA_MMC1_RX 62
#define OMAP3XXX_DMA_MS 63
#define OMAP3XXX_DMA_EXT_DMAREQ3 64
-
+#define OMAP3XXX_DMA_AES2_TX 65
+#define OMAP3XXX_DMA_AES2_RX 66
+#define OMAP3XXX_DMA_DES2_TX 67
+#define OMAP3XXX_DMA_DES2_RX 68
+#define OMAP3XXX_DMA_SHA1MD5_RX 69
#define OMAP3XXX_DMA_SPI4_TX0 70
#define OMAP3XXX_DMA_SPI4_RX0 71
#define OMAP3XXX_DMA_DSS0 72
#define OMAP3XXX_DMA_MMC3_TX 77
#define OMAP3XXX_DMA_MMC3_RX 78
+#define OMAP3XXX_DMA_USIM_TX 79
+#define OMAP3XXX_DMA_USIM_RX 80
/* omap[123].c */
struct omap_gpif_s *omap3_gpif_init(void);
void omap3_gpio_init(struct omap_mpu_state_s *mpu,
struct omap_gpif_s *s, struct omap_target_agent_s *ta,
- qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int module_index);
+ qemu_irq irq, omap_clk *fclk, omap_clk iclk, int module_index);
qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);
void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);
void omap_uwire_attach(struct omap_uwire_s *s,
struct uwire_slave_s *slave, int chipselect);
-struct omap_mcspi_s;
-struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
- qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
-void omap_mcspi_attach(struct omap_mcspi_s *s,
- uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
- int chipselect);
-
struct omap_rtc_s;
struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
qemu_irq *irq, omap_clk clk);
void omap_i2c_reset(struct omap_i2c_s *s);
i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
+/* omap_spi.c */
+struct omap_mcspi_s;
+struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta,
+ struct omap_mpu_state_s *mpu,
+ int chnum, qemu_irq irq, qemu_irq *drq,
+ omap_clk fclk, omap_clk iclk);
+void omap_mcspi_attach(struct omap_mcspi_s *s,
+ uint32_t (*txrx)(void *opaque, uint32_t, int),
+ void *opaque, int chipselect);
+void omap_mcspi_reset(struct omap_mcspi_s *s);
+
/* omap3_usb.c */
struct omap3_hsusb_s;
struct omap3_hsusb_s *omap3_hsusb_init(struct omap_target_agent_s *otg_ta,
qemu_irq ehci_irq,
qemu_irq tll_irq);
+/* usb-ohci.c */
+int usb_ohci_init_omap(target_phys_addr_t base, uint32_t region_size,
+ int num_ports, qemu_irq irq);
+
+
# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
# define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
struct omap_gpif_s *gpif;
- struct omap_mcspi_s *mcspi[2];
+ struct omap_mcspi_s *mcspi[4];
struct omap_dss_s *dss;
/* omap3.c */
struct omap_mpu_state_s *omap3530_mpu_init(unsigned long sdram_size,
- const char *core);
+ CharDriverState *chr_uart1,
+ CharDriverState *chr_uart2,
+ CharDriverState *chr_uart3);
void omap3_set_mem_type(struct omap_mpu_state_s *s, int bootfrom);
/* omap3_boot.c */
projects / qemu / blobdiff