#include "audio/audio.h"
#include "block.h"
+/*
+ * When the flag below is defined, the "less important" I/O regions
+ * will not be mapped -- this is needed because the current maximum
+ * number of I/O regions in qemu-system-arm (128) is easily reached
+ * when everything is mapped.
+ */
+#define OMAP3_REDUCE_IOREGIONS
+
//#define OMAP3_DEBUG_
#ifdef OMAP3_DEBUG_
[L3ID_IVA_PM ] = {0x00014000, 0x0400, L3TYPE_PM},
};
+#ifndef OMAP3_REDUCE_IOREGIONS
static uint32_t omap3_l3ia_read(void *opaque, target_phys_addr_t addr)
{
struct omap3_l3_initiator_agent_s *s = (struct omap3_l3_initiator_agent_s *)opaque;
omap3_l3undef_write16,
omap3_l3undef_write32,
};
+#endif
static struct omap_l3_s *omap3_l3_init(target_phys_addr_t base,
struct omap_l3_region_s *regions,
int n)
{
+#ifdef OMAP3_REDUCE_IOREGIONS
+ return NULL;
+#else
int i, iomemtype = 0;
struct omap_l3_s *bus = qemu_mallocz(sizeof(*bus) + n * sizeof(*bus->region));
}
return bus;
+#endif
}
typedef enum {
/* 48061000-48061FFF */ L4ID_I2C3_TA,
/* 48062000-48062FFF */ L4ID_USBTLL,
/* 48063000-48063FFF */ L4ID_USBTLL_TA,
- /* 48064000-48064FFF */ L4ID_HSUSBHOST,
- /* 48065000-48065FFF */ L4ID_HSUSBHOST_TA,
+ /* 48064000-480643FF */ L4ID_USBHOST,
+ /* 48064400-480647FF */ L4ID_USBHOST_OHCI,
+ /* 48064800-4806BFFF */ L4ID_USBHOST_EHCI,
+ /* 48065000-48065FFF */ L4ID_USBHOST_TA,
/* 48066000-48069FFF */
/* 4806A000-4806AFFF */ L4ID_UART1,
/* 4806B000-4806BFFF */ L4ID_UART1_TA,
[L4ID_I2C3_TA ] = {0x00061000, 0x1000, L4TYPE_TA},
[L4ID_USBTLL ] = {0x00062000, 0x1000, L4TYPE_GENERIC},
[L4ID_USBTLL_TA ] = {0x00063000, 0x1000, L4TYPE_TA},
- [L4ID_HSUSBHOST ] = {0x00064000, 0x1000, L4TYPE_GENERIC},
- [L4ID_HSUSBHOST_TA] = {0x00065000, 0x1000, L4TYPE_TA},
+ [L4ID_USBHOST ] = {0x00064000, 0x0400, L4TYPE_GENERIC},
+ [L4ID_USBHOST_OHCI] = {0x00064400, 0x0400, L4TYPE_GENERIC},
+ [L4ID_USBHOST_EHCI] = {0x00064800, 0x0400, L4TYPE_GENERIC},
+ [L4ID_USBHOST_TA ] = {0x00065000, 0x1000, L4TYPE_TA},
[L4ID_UART1 ] = {0x0006a000, 0x1000, L4TYPE_GENERIC},
[L4ID_UART1_TA ] = {0x0006b000, 0x1000, L4TYPE_TA},
[L4ID_UART2 ] = {0x0006c000, 0x1000, L4TYPE_GENERIC},
L4A_TAP,
L4A_USBHS_OTG,
L4A_USBHS_HOST,
- L4A_USBHS_TLL
+ L4A_USBHS_TLL,
+ L4A_MCSPI1,
+ L4A_MCSPI2,
+ L4A_MCSPI3,
+ L4A_MCSPI4,
+ L4A_SDMA
} omap3_l4_agent_info_id_t;
struct omap3_l4_agent_info_s {
{L4A_DSS, L4ID_DSI, 6},
/* TODO: camera */
{L4A_USBHS_OTG, L4ID_HSUSBOTG, 2},
- {L4A_USBHS_HOST, L4ID_HSUSBHOST, 2},
+ {L4A_USBHS_HOST, L4ID_USBHOST, 4},
{L4A_USBHS_TLL, L4ID_USBTLL, 2},
{L4A_UART1, L4ID_UART1, 2},
{L4A_UART2, L4ID_UART2, 2},
/* TODO: McBSP5 */
{L4A_GPTIMER10, L4ID_GPTIMER10, 2},
{L4A_GPTIMER11, L4ID_GPTIMER11, 2},
- /* TODO: SPI1 */
- /* TODO: SPI2 */
+ {L4A_MCSPI1, L4ID_MCSPI1, 2},
+ {L4A_MCSPI2, L4ID_MCSPI2, 2},
{L4A_MMC1, L4ID_MMCSDIO1, 2},
{L4A_MMC2, L4ID_MMCSDIO2, 2},
{L4A_MMC3, L4ID_MMCSDIO3, 2},
/* TODO: HDQ/1-Wire */
/* TODO: Mailbox */
- /* TODO: SPI3 */
- /* TODO: SPI4 */
- /* TODO: SDMA */
+ {L4A_MCSPI3, L4ID_MCSPI3, 2},
+ {L4A_MCSPI4, L4ID_MCSPI4, 2},
+ {L4A_SDMA, L4ID_SDMA, 2},
{L4A_CM, L4ID_CM_A, 3},
{L4A_SCM, L4ID_SCM, 2},
{L4A_TAP, L4ID_TAP, 2},
{L4A_GPIO6, L4ID_GPIO6, 2},
};
+#ifndef OMAP3_REDUCE_IOREGIONS
static uint32_t omap3_l4ta_read(void *opaque, target_phys_addr_t addr)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
omap_badwidth_write32,
omap3_l4ta_write,
};
+#endif
static struct omap_target_agent_s *omap3_l4ta_init(struct omap_l4_s *bus, int cs)
{
- int i, iomemtype;
+#ifndef OMAP3_REDUCE_IOREGIONS
+ int iomemtype;
+#endif
+ int i;
struct omap_target_agent_s *ta = 0;
const struct omap3_l4_agent_info_s *info = 0;
exit(-1);
}
+#ifndef OMAP3_REDUCE_IOREGIONS
iomemtype = l4_register_io_memory(0, omap3_l4ta_readfn,
omap3_l4ta_writefn, ta);
ta->base = omap_l4_attach(ta, i, iomemtype);
register_savevm("omap3_l4ta", ta->base >> 8, 0,
omap3_l4ta_save_state, omap3_l4ta_load_state, ta);
+#else
+ ta->base = ta->bus->base + ta->start[i].offset;
+#endif
return ta;
}
omap3_prm_write,
};
-struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,
- qemu_irq mpu_int, qemu_irq iva_int,
- struct omap_mpu_state_s *mpu)
+static struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,
+ qemu_irq mpu_int, qemu_irq iva_int,
+ struct omap_mpu_state_s *mpu)
{
int iomemtype;
struct omap3_prm_s *s = (struct omap3_prm_s *) qemu_mallocz(sizeof(*s));
omap3_cm_write,
};
-struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,
- qemu_irq mpu_int, qemu_irq dsp_int,
- qemu_irq iva_int, struct omap_mpu_state_s *mpu)
+static struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,
+ qemu_irq mpu_int, qemu_irq dsp_int,
+ qemu_irq iva_int,
+ struct omap_mpu_state_s *mpu)
{
int iomemtype;
struct omap3_cm_s *s = (struct omap3_cm_s *) qemu_mallocz(sizeof(*s));
}
struct omap_mpu_state_s *omap3530_mpu_init(unsigned long sdram_size,
- const char *core)
+ CharDriverState *chr_uart1,
+ CharDriverState *chr_uart2,
+ CharDriverState *chr_uart3)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
qemu_mallocz(sizeof(struct omap_mpu_state_s));
- ram_addr_t sram_base, q2_base, bootrom_base;
+ ram_addr_t sram_base, q2_base;
qemu_irq *cpu_irq;
- qemu_irq dma_irqs[4];
+ qemu_irq drqs[4];
int i;
s->mpu_model = omap3530;
omap_clk_init(s);
/* Memory-mapped stuff */
-
q2_base = qemu_ram_alloc(s->sdram_size);
cpu_register_physical_memory(OMAP3_Q2_BASE, s->sdram_size,
q2_base | IO_MEM_RAM);
sram_base = qemu_ram_alloc(s->sram_size);
cpu_register_physical_memory(OMAP3_SRAM_BASE, s->sram_size,
sram_base | IO_MEM_RAM);
- bootrom_base = qemu_ram_alloc(OMAP3XXX_BOOTROM_SIZE);
- cpu_register_physical_memory(OMAP3_Q1_BASE + 0x14000,
- OMAP3XXX_BOOTROM_SIZE,
- bootrom_base | IO_MEM_ROM);
- cpu_register_physical_memory(0, OMAP3XXX_BOOTROM_SIZE,
- bootrom_base | IO_MEM_ROM);
s->l4 = omap_l4_init(OMAP3_L4_BASE,
sizeof(omap3_l4_agent_info)
omap_findclk(s, "omap3_mpu_intc_iclk"));
for (i = 0; i < 4; i++)
- dma_irqs[i] =
- s->irq[omap3_dma_irq_map[i].ih][omap3_dma_irq_map[i].intr];
- s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
- omap_findclk(s, "omap3_sdma_fclk"),
- omap_findclk(s, "omap3_sdma_iclk"));
+ drqs[i] = s->irq[omap3_dma_irq_map[i].ih][omap3_dma_irq_map[i].intr];
+ s->dma = omap3_dma4_init(omap3_l4ta_init(s->l4, L4A_SDMA), s, drqs, 32,
+ omap_findclk(s, "omap3_sdma_fclk"),
+ omap_findclk(s, "omap3_sdma_iclk"));
s->port->addr_valid = omap3_validate_addr;
-
- /* Register SDRAM and SRAM ports for fast DMA transfers. */
soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
omap_findclk(s, "omap3_uart1_fclk"),
omap_findclk(s, "omap3_uart1_iclk"),
s->drq[OMAP3XXX_DMA_UART1_TX],
- s->drq[OMAP3XXX_DMA_UART1_RX], 0);
+ s->drq[OMAP3XXX_DMA_UART1_RX],
+ chr_uart1);
s->uart[1] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART2),
s->irq[0][OMAP_INT_3XXX_UART2_IRQ],
omap_findclk(s, "omap3_uart2_fclk"),
omap_findclk(s, "omap3_uart2_iclk"),
s->drq[OMAP3XXX_DMA_UART2_TX],
- s->drq[OMAP3XXX_DMA_UART2_RX], 0);
+ s->drq[OMAP3XXX_DMA_UART2_RX],
+ chr_uart2);
s->uart[2] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART3),
s->irq[0][OMAP_INT_3XXX_UART3_IRQ],
omap_findclk(s, "omap3_uart2_fclk"),
omap_findclk(s, "omap3_uart3_iclk"),
s->drq[OMAP3XXX_DMA_UART3_TX],
- s->drq[OMAP3XXX_DMA_UART3_RX], 0);
+ s->drq[OMAP3XXX_DMA_UART3_RX],
+ chr_uart3);
s->dss = omap_dss_init(s, omap3_l4ta_init(s->l4, L4A_DSS),
s->irq[0][OMAP_INT_3XXX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
NULL,NULL,NULL,NULL,NULL);
s->gpif = omap3_gpif_init();
- omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO1),
- &s->irq[0][OMAP_INT_3XXX_GPIO1_MPU_IRQ],
+ omap3_gpio_init(s, s->gpif, omap3_l4ta_init(s->l4, L4A_GPIO1),
+ s->irq[0][OMAP_INT_3XXX_GPIO1_MPU_IRQ],
NULL,NULL,0);
- omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO2),
- &s->irq[0][OMAP_INT_3XXX_GPIO2_MPU_IRQ],
+ omap3_gpio_init(s, s->gpif, omap3_l4ta_init(s->l4, L4A_GPIO2),
+ s->irq[0][OMAP_INT_3XXX_GPIO2_MPU_IRQ],
NULL,NULL,1);
- omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO3),
- &s->irq[0][OMAP_INT_3XXX_GPIO3_MPU_IRQ],
+ omap3_gpio_init(s, s->gpif, omap3_l4ta_init(s->l4, L4A_GPIO3),
+ s->irq[0][OMAP_INT_3XXX_GPIO3_MPU_IRQ],
NULL,NULL,2);
- omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO4),
- &s->irq[0][OMAP_INT_3XXX_GPIO4_MPU_IRQ],
+ omap3_gpio_init(s, s->gpif, omap3_l4ta_init(s->l4, L4A_GPIO4),
+ s->irq[0][OMAP_INT_3XXX_GPIO4_MPU_IRQ],
NULL,NULL,3);
- omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO5),
- &s->irq[0][OMAP_INT_3XXX_GPIO5_MPU_IRQ],
+ omap3_gpio_init(s, s->gpif, omap3_l4ta_init(s->l4, L4A_GPIO5),
+ s->irq[0][OMAP_INT_3XXX_GPIO5_MPU_IRQ],
NULL,NULL,4);
- omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO6),
- &s->irq[0][OMAP_INT_3XXX_GPIO6_MPU_IRQ],
+ omap3_gpio_init(s, s->gpif, omap3_l4ta_init(s->l4, L4A_GPIO6),
+ s->irq[0][OMAP_INT_3XXX_GPIO6_MPU_IRQ],
NULL,NULL,5);
omap_tap_init(omap3_l4ta_init(s->l4, L4A_TAP), s);
s->irq[0][OMAP_INT_3XXX_OHCI_IRQ],
s->irq[0][OMAP_INT_3XXX_EHCI_IRQ],
s->irq[0][OMAP_INT_3XXX_TLL_IRQ]);
+
+ s->mcspi[0] = omap_mcspi_init(omap3_l4ta_init(s->l4, L4A_MCSPI1), s, 4,
+ s->irq[0][OMAP_INT_3XXX_MCSPI1_IRQ],
+ &s->drq[OMAP3XXX_DMA_SPI1_TX0],
+ omap_findclk(s, "omap3_spi1_fclk"),
+ omap_findclk(s, "omap3_spi1_iclk"));
+ s->mcspi[1] = omap_mcspi_init(omap3_l4ta_init(s->l4, L4A_MCSPI2), s, 2,
+ s->irq[0][OMAP_INT_3XXX_MCSPI2_IRQ],
+ &s->drq[OMAP3XXX_DMA_SPI2_TX0],
+ omap_findclk(s, "omap3_spi2_fclk"),
+ omap_findclk(s, "omap3_spi2_iclk"));
+ drqs[0] = s->drq[OMAP3XXX_DMA_SPI3_TX0];
+ drqs[1] = s->drq[OMAP3XXX_DMA_SPI3_RX0];
+ drqs[2] = s->drq[OMAP3XXX_DMA_SPI3_TX1];
+ drqs[3] = s->drq[OMAP3XXX_DMA_SPI3_RX1];
+ s->mcspi[2] = omap_mcspi_init(omap3_l4ta_init(s->l4, L4A_MCSPI3), s, 2,
+ s->irq[0][OMAP_INT_3XXX_MCSPI3_IRQ],
+ drqs,
+ omap_findclk(s, "omap3_spi3_fclk"),
+ omap_findclk(s, "omap3_spi3_iclk"));
+ s->mcspi[3] = omap_mcspi_init(omap3_l4ta_init(s->l4, L4A_MCSPI4), s, 1,
+ s->irq[0][OMAP_INT_3XXX_MCSPI4_IRQ],
+ &s->drq[OMAP3XXX_DMA_SPI4_TX0],
+ omap_findclk(s, "omap3_spi4_fclk"),
+ omap_findclk(s, "omap3_spi4_iclk"));
+
return s;
}
projects / qemu / blobdiff