/* CORE_CM: base + 0x0a00 */
uint32_t cm_fclken1_core; /* 0a00 */
+ uint32_t cm_fclken2_core; /* 0a04 */
uint32_t cm_fclken3_core; /* 0a08 */
uint32_t cm_iclken1_core; /* 0a10 */
uint32_t cm_iclken2_core; /* 0a14 */
s->cm_clkstst_mpu = 0x0;
s->cm_fclken1_core = 0x0;
+ s->cm_fclken2_core = 0x0;
s->cm_fclken3_core = 0x0;
s->cm_iclken1_core = 0x42;
s->cm_iclken2_core = 0x0;
case 0x094c: return s->cm_clkstst_mpu;
/* CORE_CM */
case 0x0a00: return s->cm_fclken1_core;
+ case 0x0a04: return s->cm_fclken2_core;
case 0x0a08: return s->cm_fclken3_core;
case 0x0a10: return s->cm_iclken1_core;
case 0x0a14: return s->cm_iclken2_core;
case 0x0b10: return s->cm_iclken_sgx;
case 0x0b20: return s->cm_idlest_sgx & 0x0;
case 0x0b40: return s->cm_clksel_sgx;
+ case 0x0b44: return s->cm_sleepdep_sgx;
case 0x0b48: return s->cm_clkstctrl_sgx;
case 0x0b4c: return s->cm_clkstst_sgx;
/* WKUP_CM */
s->cm_fclken1_core = value & 0x43fffe00;
omap3_cm_fclken1_core_update(s);
break;
+ case 0xa04:
+ /* TODO: check if modifying this has any effect */
+ s->cm_fclken2_core = value;
+ break;
case 0xa08:
s->cm_fclken3_core = value & 0x7;
/* TODO: EN_USBTLL, EN_TS */
case 0xb00: s->cm_fclken_sgx = value & 0x2; break;
case 0xb10: s->cm_iclken_sgx = value & 0x1; break;
case 0xb40: s->cm_clksel_sgx = value; break; /* TODO: SGX clock */
- case 0xb44: s->cm_sleepdep_sgx = value &0x2; break;
+ case 0xb44: s->cm_sleepdep_sgx = value & 0x2; break;
case 0xb48: s->cm_clkstctrl_sgx = value & 0x3; break;
/* WKUP_CM */
case 0xc00:
qemu_put_be32(f, s->cm_clkstst_mpu);
qemu_put_be32(f, s->cm_fclken1_core);
+ qemu_put_be32(f, s->cm_fclken2_core);
qemu_put_be32(f, s->cm_fclken3_core);
qemu_put_be32(f, s->cm_iclken1_core);
qemu_put_be32(f, s->cm_iclken2_core);
s->cm_clkstst_mpu = qemu_get_be32(f);
s->cm_fclken1_core = qemu_get_be32(f);
+ s->cm_fclken2_core = qemu_get_be32(f);
s->cm_fclken3_core = qemu_get_be32(f);
s->cm_iclken1_core = qemu_get_be32(f);
s->cm_iclken2_core = qemu_get_be32(f);