*/
#include "hw.h"
#include "pci.h"
-#include "console.h"
+#include "monitor.h"
#include "net.h"
-#include "virtio-net.h"
+#include "sysemu.h"
//#define DEBUG_PCI
struct PCIBus {
+ BusState qbus;
int bus_num;
int devfn_min;
pci_set_irq_fn set_irq;
target_phys_addr_t pci_mem_base;
static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
-static int pci_irq_index;
static PCIBus *first_bus;
static void pcibus_save(QEMUFile *f, void *opaque)
return 0;
}
-PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
+PCIBus *pci_register_bus(DeviceState *parent, const char *name,
+ pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
qemu_irq *pic, int devfn_min, int nirq)
{
PCIBus *bus;
static int nbus = 0;
- bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
+ bus = FROM_QBUS(PCIBus, qbus_create(BUS_TYPE_PCI,
+ sizeof(PCIBus) + (nirq * sizeof(int)),
+ parent, name));
bus->set_irq = set_irq;
bus->map_irq = map_irq;
bus->irq_opaque = pic;
bus->devfn_min = devfn_min;
bus->nirq = nirq;
+ bus->next = first_bus;
first_bus = bus;
register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
return bus;
return 0;
}
-/* -1 for devfn means auto assign */
-PCIDevice *pci_register_device(PCIBus *bus, const char *name,
- int instance_size, int devfn,
- PCIConfigReadFunc *config_read,
- PCIConfigWriteFunc *config_write)
+/*
+ * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
+ */
+static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
{
- PCIDevice *pci_dev;
+ const char *p;
+ char *e;
+ unsigned long val;
+ unsigned long dom = 0, bus = 0;
+ unsigned slot = 0;
+
+ p = addr;
+ val = strtoul(p, &e, 16);
+ if (e == p)
+ return -1;
+ if (*e == ':') {
+ bus = val;
+ p = e + 1;
+ val = strtoul(p, &e, 16);
+ if (e == p)
+ return -1;
+ if (*e == ':') {
+ dom = bus;
+ bus = val;
+ p = e + 1;
+ val = strtoul(p, &e, 16);
+ if (e == p)
+ return -1;
+ }
+ }
- if (pci_irq_index >= PCI_DEVICES_MAX)
- return NULL;
+ if (dom > 0xffff || bus > 0xff || val > 0x1f)
+ return -1;
+
+ slot = val;
+ if (*e)
+ return -1;
+
+ /* Note: QEMU doesn't implement domains other than 0 */
+ if (dom != 0 || pci_find_bus(bus) == NULL)
+ return -1;
+
+ *domp = dom;
+ *busp = bus;
+ *slotp = slot;
+ return 0;
+}
+
+int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
+{
+ char devaddr[32];
+
+ if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
+ return -1;
+
+ return pci_parse_devaddr(devaddr, domp, busp, slotp);
+}
+
+int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
+{
+ char devaddr[32];
+
+ if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
+ return -1;
+
+ if (!strcmp(devaddr, "auto")) {
+ *domp = *busp = 0;
+ *slotp = -1;
+ /* want to support dom/bus auto-assign at some point */
+ return 0;
+ }
+
+ return pci_parse_devaddr(devaddr, domp, busp, slotp);
+}
+
+/* -1 for devfn means auto assign */
+static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
+ const char *name, int devfn,
+ PCIConfigReadFunc *config_read,
+ PCIConfigWriteFunc *config_write)
+{
if (devfn < 0) {
for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
if (!bus->devices[devfn])
return NULL;
found: ;
}
- pci_dev = qemu_mallocz(instance_size);
- if (!pci_dev)
- return NULL;
pci_dev->bus = bus;
pci_dev->devfn = devfn;
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
config_write = pci_default_write_config;
pci_dev->config_read = config_read;
pci_dev->config_write = config_write;
- pci_dev->irq_index = pci_irq_index++;
bus->devices[devfn] = pci_dev;
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
return pci_dev;
}
+PCIDevice *pci_register_device(PCIBus *bus, const char *name,
+ int instance_size, int devfn,
+ PCIConfigReadFunc *config_read,
+ PCIConfigWriteFunc *config_write)
+{
+ PCIDevice *pci_dev;
+
+ pci_dev = qemu_mallocz(instance_size);
+ pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
+ config_read, config_write);
+ return pci_dev;
+}
+static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
+{
+ return addr + pci_mem_base;
+}
+
+static void pci_unregister_io_regions(PCIDevice *pci_dev)
+{
+ PCIIORegion *r;
+ int i;
+
+ for(i = 0; i < PCI_NUM_REGIONS; i++) {
+ r = &pci_dev->io_regions[i];
+ if (!r->size || r->addr == -1)
+ continue;
+ if (r->type == PCI_ADDRESS_SPACE_IO) {
+ isa_unassign_ioport(r->addr, r->size);
+ } else {
+ cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
+ r->size,
+ IO_MEM_UNASSIGNED);
+ }
+ }
+}
+
+int pci_unregister_device(PCIDevice *pci_dev)
+{
+ int ret = 0;
+
+ if (pci_dev->unregister)
+ ret = pci_dev->unregister(pci_dev);
+ if (ret)
+ return ret;
+
+ pci_unregister_io_regions(pci_dev);
+
+ qemu_free_irqs(pci_dev->irq);
+ pci_dev->bus->devices[pci_dev->devfn] = NULL;
+ qdev_free(&pci_dev->qdev);
+ return 0;
+}
+
void pci_register_io_region(PCIDevice *pci_dev, int region_num,
uint32_t size, int type,
PCIMapIORegionFunc *map_func)
if ((unsigned int)region_num >= PCI_NUM_REGIONS)
return;
+
+ if (size & (size-1)) {
+ fprintf(stderr, "ERROR: PCI region size must be pow2 "
+ "type=0x%x, size=0x%x\n", type, size);
+ exit(1);
+ }
+
r = &pci_dev->io_regions[region_num];
r->addr = -1;
r->size = size;
*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
}
-static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
-{
- return addr + pci_mem_base;
-}
-
static void pci_update_mappings(PCIDevice *d)
{
PCIIORegion *r;
case 0x01:
case 0x02:
case 0x03:
+ case 0x06:
+ case 0x07:
case 0x08:
case 0x09:
case 0x0a:
case 0x01:
case 0x02:
case 0x03:
+ case 0x06:
+ case 0x07:
case 0x08:
case 0x09:
case 0x0a:
static void pci_info_device(PCIDevice *d)
{
+ Monitor *mon = cur_mon;
int i, class;
PCIIORegion *r;
const pci_class_desc *desc;
- term_printf(" Bus %2d, device %3d, function %d:\n",
- d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
+ monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
+ d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
- term_printf(" ");
+ monitor_printf(mon, " ");
desc = pci_class_descriptions;
while (desc->desc && class != desc->class)
desc++;
if (desc->desc) {
- term_printf("%s", desc->desc);
+ monitor_printf(mon, "%s", desc->desc);
} else {
- term_printf("Class %04x", class);
+ monitor_printf(mon, "Class %04x", class);
}
- term_printf(": PCI device %04x:%04x\n",
+ monitor_printf(mon, ": PCI device %04x:%04x\n",
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
if (d->config[PCI_INTERRUPT_PIN] != 0) {
- term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
+ monitor_printf(mon, " IRQ %d.\n",
+ d->config[PCI_INTERRUPT_LINE]);
}
if (class == 0x0604) {
- term_printf(" BUS %d.\n", d->config[0x19]);
+ monitor_printf(mon, " BUS %d.\n", d->config[0x19]);
}
for(i = 0;i < PCI_NUM_REGIONS; i++) {
r = &d->io_regions[i];
if (r->size != 0) {
- term_printf(" BAR%d: ", i);
+ monitor_printf(mon, " BAR%d: ", i);
if (r->type & PCI_ADDRESS_SPACE_IO) {
- term_printf("I/O at 0x%04x [0x%04x].\n",
- r->addr, r->addr + r->size - 1);
+ monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
+ r->addr, r->addr + r->size - 1);
} else {
- term_printf("32 bit memory at 0x%08x [0x%08x].\n",
- r->addr, r->addr + r->size - 1);
+ monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
+ r->addr, r->addr + r->size - 1);
}
}
}
}
}
-void pci_info(void)
+void pci_info(Monitor *mon)
{
pci_for_each_device(0, pci_info_device);
}
NULL
};
-typedef void (*PCINICInitFn)(PCIBus *, NICInfo *, int);
-
-static PCINICInitFn pci_nic_init_fns[] = {
- pci_ne2000_init,
- pci_i82551_init,
- pci_i82557b_init,
- pci_i82559er_init,
- pci_rtl8139_init,
- pci_e1000_init,
- pci_pcnet_init,
- virtio_net_init,
+static const char * const pci_nic_names[] = {
+ "ne2k_pci",
+ "i82551",
+ "i82557b",
+ "i82559er",
+ "rtl8139",
+ "e1000",
+ "pcnet",
+ "virtio-net-pci",
NULL
};
/* Initialize a PCI NIC. */
-void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
+PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
const char *default_model)
{
+ DeviceState *dev;
int i;
qemu_check_nic_model_list(nd, pci_nic_models, default_model);
- for (i = 0; pci_nic_models[i]; i++)
- if (strcmp(nd->model, pci_nic_models[i]) == 0)
- pci_nic_init_fns[i](bus, nd, devfn);
+ for (i = 0; pci_nic_models[i]; i++) {
+ if (strcmp(nd->model, pci_nic_models[i]) == 0) {
+ dev = qdev_create(&bus->qbus, pci_nic_names[i]);
+ qdev_set_prop_int(dev, "devfn", devfn);
+ qdev_set_netdev(dev, nd);
+ qdev_init(dev);
+ nd->private = dev;
+ return (PCIDevice *)dev;
+ }
+ }
+
+ return NULL;
}
typedef struct {
pci_default_write_config(d, address, val, len);
}
+PCIBus *pci_find_bus(int bus_num)
+{
+ PCIBus *bus = first_bus;
+
+ while (bus && bus->bus_num != bus_num)
+ bus = bus->next;
+
+ return bus;
+}
+
+PCIDevice *pci_find_device(int bus_num, int slot, int function)
+{
+ PCIBus *bus = pci_find_bus(bus_num);
+
+ if (!bus)
+ return NULL;
+
+ return bus->devices[PCI_DEVFN(slot, function)];
+}
+
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
pci_map_irq_fn map_irq, const char *name)
{
s->dev.config[0x09] = 0x00; // programming i/f
pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
s->dev.config[0x0D] = 0x10; // latency_timer
- s->dev.config[0x0E] = 0x81; // header_type
+ s->dev.config[PCI_HEADER_TYPE] =
+ PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
s->dev.config[0x1E] = 0xa0; // secondary status
s->bus = pci_register_secondary_bus(&s->dev, map_irq);
return s->bus;
}
+
+typedef struct {
+ DeviceInfo qdev;
+ pci_qdev_initfn init;
+} PCIDeviceInfo;
+
+static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
+{
+ PCIDevice *pci_dev = (PCIDevice *)qdev;
+ PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
+ PCIBus *bus;
+ int devfn;
+
+ bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
+ devfn = qdev_get_prop_int(qdev, "devfn", -1);
+ pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
+ NULL, NULL);//FIXME:config_read, config_write);
+ assert(pci_dev);
+ info->init(pci_dev);
+}
+
+void pci_qdev_register(const char *name, int size, pci_qdev_initfn init)
+{
+ PCIDeviceInfo *info;
+
+ info = qemu_mallocz(sizeof(*info));
+ info->qdev.name = qemu_strdup(name);
+ info->qdev.size = size;
+ info->init = init;
+ info->qdev.init = pci_qdev_init;
+ info->qdev.bus_type = BUS_TYPE_PCI;
+
+ qdev_register(&info->qdev);
+}
+
+PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
+{
+ DeviceState *dev;
+
+ dev = qdev_create(&bus->qbus, name);
+ qdev_set_prop_int(dev, "devfn", devfn);
+ qdev_init(dev);
+
+ return (PCIDevice *)dev;
+}
projects / qemu / blobdiff