Install keymaps from new location

[qemu] / hw / pl190.c

diff --git a/hw/pl190.c b/hw/pl190.c
index 23494d8..1085768 100644 (file)
--- a/hw/pl190.c
+++ b/hw/pl190.c
@@ -7,8 +7,7 @@
  * This code is licenced under the GPL.
  */
 
-#include "vl.h"
-#include "arm_pic.h"
+#include "sysbus.h"
 
 /* The number of virtual priority levels.  16 user vectors plus the
    unvectored IRQ.  Chained interrupts would require an additional level
@@ -17,8 +16,7 @@
 #define PL190_NUM_PRIO 17
 
 typedef struct {
-    uint32_t base;
-    DisplayState *ds;
+    SysBusDevice busdev;
     uint32_t level;
     uint32_t soft_level;
     uint32_t irq_enable;
@@ -92,7 +90,6 @@ static uint32_t pl190_read(void *opaque, target_phys_addr_t offset)
     pl190_state *s = (pl190_state *)opaque;
     int i;
 
-    offset -= s->base;
     if (offset >= 0xfe0 && offset < 0x1000) {
         return pl190_id[(offset - 0xfe0) >> 2];
     }
@@ -139,7 +136,7 @@ static uint32_t pl190_read(void *opaque, target_phys_addr_t offset)
     case 13: /* DEFVECTADDR */
         return s->vect_addr[16];
     default:
-        cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", offset);
+        hw_error("pl190_read: Bad offset %x\n", (int)offset);
         return 0;
     }
 }
@@ -148,7 +145,6 @@ static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val)
 {
     pl190_state *s = (pl190_state *)opaque;
 
-    offset -= s->base;
     if (offset >= 0x100 && offset < 0x140) {
         s->vect_addr[(offset - 0x100) >> 2] = val;
         pl190_update_vectors(s);
@@ -193,11 +189,12 @@ static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val)
         s->default_addr = val;
         break;
     case 0xc0: /* ITCR */
-        if (val)
-            cpu_abort(cpu_single_env, "pl190: Test mode not implemented\n");
+        if (val) {
+            hw_error("pl190: Test mode not implemented\n");
+        }
         break;
     default:
-        cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", offset);
+        hw_error("pl190_write: Bad offset %x\n", (int)offset);
         return;
     }
     pl190_update(s);
@@ -215,7 +212,7 @@ static CPUWriteMemoryFunc *pl190_writefn[] = {
    pl190_write
 };
 
-void pl190_reset(pl190_state *s)
+static void pl190_reset(pl190_state *s)
 {
   int i;
 
@@ -230,21 +227,24 @@ void pl190_reset(pl190_state *s)
   pl190_update_vectors(s);
 }
 
-qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq)
+static void pl190_init(SysBusDevice *dev)
 {
-    pl190_state *s;
-    qemu_irq *qi;
+    pl190_state *s = FROM_SYSBUS(pl190_state, dev);
     int iomemtype;
 
-    s = (pl190_state *)qemu_mallocz(sizeof(pl190_state));
     iomemtype = cpu_register_io_memory(0, pl190_readfn,
                                        pl190_writefn, s);
-    cpu_register_physical_memory(base, 0x00001000, iomemtype);
-    qi = qemu_allocate_irqs(pl190_set_irq, s, 32);
-    s->base = base;
-    s->irq = irq;
-    s->fiq = fiq;
+    sysbus_init_mmio(dev, 0x1000, iomemtype);
+    qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
+    sysbus_init_irq(dev, &s->irq);
+    sysbus_init_irq(dev, &s->fiq);
     pl190_reset(s);
     /* ??? Save/restore.  */
-    return qi;
 }
+
+static void pl190_register_devices(void)
+{
+    sysbus_register_dev("pl190", sizeof(pl190_state), pl190_init);
+}
+
+device_init(pl190_register_devices)