linux-user: fix ppc target_stat64 st_blocks layout

[qemu] / hw / ppc4xx_pci.c

diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index bfd2f3e..655fe86 100644 (file)
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -9,8 +9,7 @@
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
  *
  * Copyright IBM Corp. 2008
  *
@@ -21,6 +20,8 @@
  * 4xx SoCs, such as the 440EP. */
 
 #include "hw.h"
+#include "ppc.h"
+#include "ppc4xx.h"
 
 typedef target_phys_addr_t pci_addr_t;
 #include "pci.h"
@@ -31,7 +32,7 @@ typedef target_phys_addr_t pci_addr_t;
 #ifdef DEBUG
 #define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
 #else
-#define DPRINTF(fmt, args...)
+#define DPRINTF(fmt, ...)
 #endif /* DEBUG */
 
 struct PCIMasterMap {
@@ -92,7 +93,7 @@ static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
     return ppc4xx_pci->pci_state.config_reg;
 }
 
-static CPUReadMemoryFunc *pci4xx_cfgaddr_read[] = {
+static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = {
     &pci4xx_cfgaddr_readl,
     &pci4xx_cfgaddr_readl,
     &pci4xx_cfgaddr_readl,
@@ -110,19 +111,19 @@ static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
     ppc4xx_pci->pci_state.config_reg = value & ~0x3;
 }
 
-static CPUWriteMemoryFunc *pci4xx_cfgaddr_write[] = {
+static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = {
     &pci4xx_cfgaddr_writel,
     &pci4xx_cfgaddr_writel,
     &pci4xx_cfgaddr_writel,
 };
 
-static CPUReadMemoryFunc *pci4xx_cfgdata_read[] = {
+static CPUReadMemoryFunc * const pci4xx_cfgdata_read[] = {
     &pci_host_data_readb,
     &pci_host_data_readw,
     &pci_host_data_readl,
 };
 
-static CPUWriteMemoryFunc *pci4xx_cfgdata_write[] = {
+static CPUWriteMemoryFunc * const pci4xx_cfgdata_write[] = {
     &pci_host_data_writeb,
     &pci_host_data_writew,
     &pci_host_data_writel,
@@ -271,13 +272,13 @@ static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
     return value;
 }
 
-static CPUReadMemoryFunc *pci_reg_read[] = {
+static CPUReadMemoryFunc * const pci_reg_read[] = {
     &ppc4xx_pci_reg_read4,
     &ppc4xx_pci_reg_read4,
     &ppc4xx_pci_reg_read4,
 };
 
-static CPUWriteMemoryFunc *pci_reg_write[] = {
+static CPUWriteMemoryFunc * const pci_reg_write[] = {
     &ppc4xx_pci_reg_write4,
     &ppc4xx_pci_reg_write4,
     &ppc4xx_pci_reg_write4,
@@ -303,8 +304,10 @@ static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
     return slot - 1;
 }
 
-static void ppc4xx_pci_set_irq(qemu_irq *pci_irqs, int irq_num, int level)
+static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
 {
+    qemu_irq *pci_irqs = opaque;
+
     DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
     qemu_set_irq(pci_irqs[irq_num], level);
 }
@@ -364,34 +367,32 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
     PPC4xxPCIState *controller;
     int index;
     static int ppc4xx_pci_id;
+    uint8_t *pci_conf;
 
     controller = qemu_mallocz(sizeof(PPC4xxPCIState));
-    if (!controller)
-        return NULL;
 
-    controller->pci_state.bus = pci_register_bus(ppc4xx_pci_set_irq,
+    controller->pci_state.bus = pci_register_bus(NULL, "pci",
+                                                 ppc4xx_pci_set_irq,
                                                  ppc4xx_pci_map_irq,
                                                  pci_irqs, 0, 4);
 
     controller->pci_dev = pci_register_device(controller->pci_state.bus,
                                               "host bridge", sizeof(PCIDevice),
                                               0, NULL, NULL);
-    controller->pci_dev->config[0x00] = 0x14; // vendor_id
-    controller->pci_dev->config[0x01] = 0x10;
-    controller->pci_dev->config[0x02] = 0x7f; // device_id
-    controller->pci_dev->config[0x03] = 0x02;
-    controller->pci_dev->config[0x0a] = 0x80; // class_sub = other bridge type
-    controller->pci_dev->config[0x0b] = 0x06; // class_base = PCI_bridge
+    pci_conf = controller->pci_dev->config;
+    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
+    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX);
+    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 
     /* CFGADDR */
-    index = cpu_register_io_memory(0, pci4xx_cfgaddr_read,
+    index = cpu_register_io_memory(pci4xx_cfgaddr_read,
                                    pci4xx_cfgaddr_write, controller);
     if (index < 0)
         goto free;
     cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
 
     /* CFGDATA */
-    index = cpu_register_io_memory(0, pci4xx_cfgdata_read,
+    index = cpu_register_io_memory(pci4xx_cfgdata_read,
                                    pci4xx_cfgdata_write,
                                    &controller->pci_state);
     if (index < 0)
@@ -399,7 +400,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
     cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
 
     /* Internal registers */
-    index = cpu_register_io_memory(0, pci_reg_read, pci_reg_write, controller);
+    index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller);
     if (index < 0)
         goto free;
     cpu_register_physical_memory(registers, PCI_REG_SIZE, index);