#include "ppc.h"
#include "boards.h"
#include "qemu-log.h"
+#include "ide.h"
//#define HARD_DEBUG_PPC_IO
//#define DEBUG_PPC_IO
} \
} while (0)
#elif defined (DEBUG_PPC_IO)
-#define PPC_IO_DPRINTF(fmt, ...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
+#define PPC_IO_DPRINTF(fmt, ...) \
+qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
#else
#define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
#endif
static void _PPC_intack_write (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
-// printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
+#if 0
+ printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
+ value);
+#endif
}
-static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
+static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
{
uint32_t retval = 0;
if ((addr & 0xf) == 0)
retval = pic_intack_read(isa_pic);
-// printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
+#if 0
+ printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
+ retval);
+#endif
return retval;
}
#endif
}
-static CPUWriteMemoryFunc *PPC_intack_write[] = {
+static CPUWriteMemoryFunc * const PPC_intack_write[] = {
&_PPC_intack_write,
&_PPC_intack_write,
&_PPC_intack_write,
};
-static CPUReadMemoryFunc *PPC_intack_read[] = {
+static CPUReadMemoryFunc * const PPC_intack_read[] = {
&PPC_intack_readb,
&PPC_intack_readw,
&PPC_intack_readl,
static void PPC_XCSR_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
+ value);
}
static void PPC_XCSR_writew (void *opaque,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
#endif
- printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
+ value);
}
static void PPC_XCSR_writel (void *opaque,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
- printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
+ value);
}
static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
- printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
+ printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
+ retval);
return retval;
}
{
uint32_t retval = 0;
- printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
+ printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
+ retval);
#ifdef TARGET_WORDS_BIGENDIAN
retval = bswap16(retval);
#endif
{
uint32_t retval = 0;
- printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
+ printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
+ retval);
#ifdef TARGET_WORDS_BIGENDIAN
retval = bswap32(retval);
#endif
return retval;
}
-static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
+static CPUWriteMemoryFunc * const PPC_XCSR_write[] = {
&PPC_XCSR_writeb,
&PPC_XCSR_writew,
&PPC_XCSR_writel,
};
-static CPUReadMemoryFunc *PPC_XCSR_read[] = {
+static CPUReadMemoryFunc * const PPC_XCSR_read[] = {
&PPC_XCSR_readb,
&PPC_XCSR_readw,
&PPC_XCSR_readl,
return retval;
}
-static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
- target_phys_addr_t
- addr)
+static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
+ target_phys_addr_t addr)
{
if (sysctrl->contiguous_map == 0) {
/* 64 KB contiguous space for IOs */
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
#endif
- PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
+ PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
cpu_outw(NULL, addr, value);
}
#ifdef TARGET_WORDS_BIGENDIAN
ret = bswap16(ret);
#endif
- PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
+ PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
return ret;
}
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
- PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
+ PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
cpu_outl(NULL, addr, value);
}
#ifdef TARGET_WORDS_BIGENDIAN
ret = bswap32(ret);
#endif
- PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
+ PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
return ret;
}
-static CPUWriteMemoryFunc *PPC_prep_io_write[] = {
+static CPUWriteMemoryFunc * const PPC_prep_io_write[] = {
&PPC_prep_io_writeb,
&PPC_prep_io_writew,
&PPC_prep_io_writel,
};
-static CPUReadMemoryFunc *PPC_prep_io_read[] = {
+static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
&PPC_prep_io_readb,
&PPC_prep_io_readw,
&PPC_prep_io_readl,
const char *cpu_model)
{
CPUState *env = NULL, *envs[MAX_CPUS];
- char buf[1024];
+ char *filename;
nvram_t nvram;
m48t59_t *m48t59;
int PPC_io_memory;
PCIBus *pci_bus;
qemu_irq *i8259;
int ppc_boot_device;
- int index;
- BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+ DriveInfo *dinfo;
+ DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BlockDriverState *fd[MAX_FD];
sysctrl = qemu_mallocz(sizeof(sysctrl_t));
/* init CPUs */
if (cpu_model == NULL)
- cpu_model = "default";
+ cpu_model = "602";
for (i = 0; i < smp_cpus; i++) {
env = cpu_init(cpu_model);
if (!env) {
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
}
- qemu_register_reset(&cpu_ppc_reset, 0, env);
+ qemu_register_reset(&cpu_ppc_reset, env);
envs[i] = env;
}
bios_offset = qemu_ram_alloc(BIOS_SIZE);
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
- snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
- bios_size = get_image_size(buf);
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+ if (filename) {
+ bios_size = get_image_size(filename);
+ } else {
+ bios_size = -1;
+ }
if (bios_size > 0 && bios_size <= BIOS_SIZE) {
target_phys_addr_t bios_addr;
bios_size = (bios_size + 0xfff) & ~0xfff;
bios_addr = (uint32_t)(-bios_size);
cpu_register_physical_memory(bios_addr, bios_size,
bios_offset | IO_MEM_ROM);
- bios_size = load_image_targphys(buf, bios_addr, bios_size);
+ bios_size = load_image_targphys(filename, bios_addr, bios_size);
}
if (bios_size < 0 || bios_size > BIOS_SIZE) {
- hw_error("qemu: could not load PPC PREP bios '%s'\n", buf);
+ hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
+ }
+ if (filename) {
+ qemu_free(filename);
}
if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
}
i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
pci_bus = pci_prep_init(i8259);
+ /* Hmm, prep has no pci-isa bridge ??? */
+ isa_bus_new(NULL);
+ isa_bus_irqs(i8259);
// pci_bus = i440fx_init();
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
- PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
+ PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
PPC_prep_io_write, sysctrl);
cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
pci_vga_init(pci_bus, 0, 0);
// openpic = openpic_init(0x00000000, 0xF0000000, 1);
// pit = pit_init(0x40, i8259[0]);
- rtc_init(0x70, i8259[8], 2000);
+ rtc_init(2000);
serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
nb_nics1 = nb_nics;
nd_table[i].model = "ne2k_isa";
}
if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
- isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
+ isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
} else {
- pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci");
+ pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
}
}
}
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
- index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
- if (index != -1)
- hd[i] = drives_table[index].bdrv;
- else
- hd[i] = NULL;
+ hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
}
for(i = 0; i < MAX_IDE_BUS; i++) {
- isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
+ isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
hd[2 * i],
hd[2 * i + 1]);
}
- i8042_init(i8259[1], i8259[12], 0x60);
+ isa_create_simple("i8042");
DMA_init(1);
// SB16_init();
for(i = 0; i < MAX_FD; i++) {
- index = drive_get_index(IF_FLOPPY, 0, i);
- if (index != -1)
- fd[i] = drives_table[index].bdrv;
- else
- fd[i] = NULL;
+ dinfo = drive_get(IF_FLOPPY, 0, i);
+ fd[i] = dinfo ? dinfo->bdrv : NULL;
}
- fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
+ fdctrl_init_isa(fd);
/* Register speaker port */
register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
/* PCI intack location */
- PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
+ PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
PPC_intack_write, NULL);
cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
/* PowerPC control and status register group */
#if 0
- PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
+ PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
NULL);
cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
#endif
if (usb_enabled) {
- usb_ohci_init_pci(pci_bus, 3, -1);
+ usb_ohci_init_pci(pci_bus, -1);
}
m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
projects / qemu / blobdiff