Compile most Xen files only once

[qemu] / hw / pxa2xx_timer.c

diff --git a/hw/pxa2xx_timer.c b/hw/pxa2xx_timer.c
index 073806a..3725dd1 100644 (file)
--- a/hw/pxa2xx_timer.c
+++ b/hw/pxa2xx_timer.c
@@ -7,7 +7,10 @@
  * This code is licenced under the GPL.
  */
 
-#include "vl.h"
+#include "hw.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "pxa.h"
 
 #define OSMR0  0x00
 #define OSMR1  0x04
@@ -56,32 +59,31 @@ static int pxa2xx_timer4_freq[8] = {
     [5 ... 7] = 0,
 };
 
-struct pxa2xx_timer0_s {
+typedef struct {
     uint32_t value;
     int level;
     qemu_irq irq;
     QEMUTimer *qtimer;
     int num;
     void *info;
-};
+} PXA2xxTimer0;
 
-struct pxa2xx_timer4_s {
-    struct pxa2xx_timer0_s tm;
+typedef struct {
+    PXA2xxTimer0 tm;
     int32_t oldclock;
     int32_t clock;
     uint64_t lastload;
     uint32_t freq;
     uint32_t control;
-};
+} PXA2xxTimer4;
 
 typedef struct {
-    target_phys_addr_t base;
     int32_t clock;
     int32_t oldclock;
     uint64_t lastload;
     uint32_t freq;
-    struct pxa2xx_timer0_s timer[4];
-    struct pxa2xx_timer4_s *tm4;
+    PXA2xxTimer0 timer[4];
+    PXA2xxTimer4 *tm4;
     uint32_t events;
     uint32_t irq_enabled;
     uint32_t reset3;
@@ -137,8 +139,6 @@ static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
     pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
     int tm = 0;
 
-    offset -= s->base;
-
     switch (offset) {
     case OSMR3:  tm ++;
     case OSMR2:  tm ++;
@@ -205,8 +205,7 @@ static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
         return s->snapshot;
     default:
     badreg:
-        cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
-                        REG_FMT "\n", offset);
+        hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
     }
 
     return 0;
@@ -218,8 +217,6 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
     int i, tm = 0;
     pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
 
-    offset -= s->base;
-
     switch (offset) {
     case OSMR3:  tm ++;
     case OSMR2:  tm ++;
@@ -317,8 +314,7 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
         break;
     default:
     badreg:
-        cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
-                        REG_FMT "\n", offset);
+        hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
     }
 }
 
@@ -336,7 +332,7 @@ static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = {
 
 static void pxa2xx_timer_tick(void *opaque)
 {
-    struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque;
+    PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
     pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;
 
     if (i->irq_enabled & (1 << t->num)) {
@@ -354,7 +350,7 @@ static void pxa2xx_timer_tick(void *opaque)
 
 static void pxa2xx_timer_tick4(void *opaque)
 {
-    struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque;
+    PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
     pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->tm.info;
 
     pxa2xx_timer_tick(&t->tm);
@@ -364,6 +360,73 @@ static void pxa2xx_timer_tick4(void *opaque)
         pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
 }
 
+static void pxa2xx_timer_save(QEMUFile *f, void *opaque)
+{
+    pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
+    int i;
+
+    qemu_put_be32s(f, (uint32_t *) &s->clock);
+    qemu_put_be32s(f, (uint32_t *) &s->oldclock);
+    qemu_put_be64s(f, &s->lastload);
+
+    for (i = 0; i < 4; i ++) {
+        qemu_put_be32s(f, &s->timer[i].value);
+        qemu_put_be32(f, s->timer[i].level);
+    }
+    if (s->tm4)
+        for (i = 0; i < 8; i ++) {
+            qemu_put_be32s(f, &s->tm4[i].tm.value);
+            qemu_put_be32(f, s->tm4[i].tm.level);
+            qemu_put_sbe32s(f, &s->tm4[i].oldclock);
+            qemu_put_sbe32s(f, &s->tm4[i].clock);
+            qemu_put_be64s(f, &s->tm4[i].lastload);
+            qemu_put_be32s(f, &s->tm4[i].freq);
+            qemu_put_be32s(f, &s->tm4[i].control);
+        }
+
+    qemu_put_be32s(f, &s->events);
+    qemu_put_be32s(f, &s->irq_enabled);
+    qemu_put_be32s(f, &s->reset3);
+    qemu_put_be32s(f, &s->snapshot);
+}
+
+static int pxa2xx_timer_load(QEMUFile *f, void *opaque, int version_id)
+{
+    pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
+    int64_t now;
+    int i;
+
+    qemu_get_be32s(f, (uint32_t *) &s->clock);
+    qemu_get_be32s(f, (uint32_t *) &s->oldclock);
+    qemu_get_be64s(f, &s->lastload);
+
+    now = qemu_get_clock(vm_clock);
+    for (i = 0; i < 4; i ++) {
+        qemu_get_be32s(f, &s->timer[i].value);
+        s->timer[i].level = qemu_get_be32(f);
+    }
+    pxa2xx_timer_update(s, now);
+
+    if (s->tm4)
+        for (i = 0; i < 8; i ++) {
+            qemu_get_be32s(f, &s->tm4[i].tm.value);
+            s->tm4[i].tm.level = qemu_get_be32(f);
+            qemu_get_sbe32s(f, &s->tm4[i].oldclock);
+            qemu_get_sbe32s(f, &s->tm4[i].clock);
+            qemu_get_be64s(f, &s->tm4[i].lastload);
+            qemu_get_be32s(f, &s->tm4[i].freq);
+            qemu_get_be32s(f, &s->tm4[i].control);
+            pxa2xx_timer_update4(s, now, i);
+        }
+
+    qemu_get_be32s(f, &s->events);
+    qemu_get_be32s(f, &s->irq_enabled);
+    qemu_get_be32s(f, &s->reset3);
+    qemu_get_be32s(f, &s->snapshot);
+
+    return 0;
+}
+
 static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
                 qemu_irq *irqs)
 {
@@ -372,7 +435,6 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
     pxa2xx_timer_info *s;
 
     s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
-    s->base = base;
     s->irq_enabled = 0;
     s->oldclock = 0;
     s->clock = 0;
@@ -391,7 +453,11 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
 
     iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
                     pxa2xx_timer_writefn, s);
-    cpu_register_physical_memory(base, 0x00000fff, iomemtype);
+    cpu_register_physical_memory(base, 0x00001000, iomemtype);
+
+    register_savevm("pxa2xx_timer", 0, 0,
+                    pxa2xx_timer_save, pxa2xx_timer_load, s);
+
     return s;
 }
 
@@ -408,8 +474,8 @@ void pxa27x_timer_init(target_phys_addr_t base,
     pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
     int i;
     s->freq = PXA27X_FREQ;
-    s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 *
-                    sizeof(struct pxa2xx_timer4_s));
+    s->tm4 = (PXA2xxTimer4 *) qemu_mallocz(8 *
+                    sizeof(PXA2xxTimer4));
     for (i = 0; i < 8; i ++) {
         s->tm4[i].tm.value = 0;
         s->tm4[i].tm.irq = irq4;