* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "pxa.h"
#define OSMR0 0x00
#define OSMR1 0x04
[5 ... 7] = 0,
};
-struct pxa2xx_timer0_s {
+typedef struct {
uint32_t value;
int level;
qemu_irq irq;
QEMUTimer *qtimer;
int num;
void *info;
-};
+} PXA2xxTimer0;
-struct pxa2xx_timer4_s {
- struct pxa2xx_timer0_s tm;
+typedef struct {
+ PXA2xxTimer0 tm;
int32_t oldclock;
int32_t clock;
uint64_t lastload;
uint32_t freq;
uint32_t control;
-};
+} PXA2xxTimer4;
typedef struct {
- target_phys_addr_t base;
int32_t clock;
int32_t oldclock;
uint64_t lastload;
uint32_t freq;
- struct pxa2xx_timer0_s timer[4];
- struct pxa2xx_timer4_s *tm4;
+ PXA2xxTimer0 timer[4];
+ PXA2xxTimer4 *tm4;
uint32_t events;
uint32_t irq_enabled;
uint32_t reset3;
pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
int tm = 0;
- offset -= s->base;
-
switch (offset) {
case OSMR3: tm ++;
case OSMR2: tm ++;
return s->snapshot;
default:
badreg:
- cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
- REG_FMT "\n", offset);
+ hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
}
return 0;
int i, tm = 0;
pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
- offset -= s->base;
-
switch (offset) {
case OSMR3: tm ++;
case OSMR2: tm ++;
break;
default:
badreg:
- cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
- REG_FMT "\n", offset);
+ hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
}
}
static void pxa2xx_timer_tick(void *opaque)
{
- struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque;
+ PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;
if (i->irq_enabled & (1 << t->num)) {
static void pxa2xx_timer_tick4(void *opaque)
{
- struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque;
+ PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->tm.info;
pxa2xx_timer_tick(&t->tm);
pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
int i;
- qemu_put_be32s(f, &s->clock);
- qemu_put_be32s(f, &s->oldclock);
+ qemu_put_be32s(f, (uint32_t *) &s->clock);
+ qemu_put_be32s(f, (uint32_t *) &s->oldclock);
qemu_put_be64s(f, &s->lastload);
for (i = 0; i < 4; i ++) {
for (i = 0; i < 8; i ++) {
qemu_put_be32s(f, &s->tm4[i].tm.value);
qemu_put_be32(f, s->tm4[i].tm.level);
- qemu_put_be32s(f, &s->tm4[i].oldclock);
- qemu_put_be32s(f, &s->tm4[i].clock);
+ qemu_put_sbe32s(f, &s->tm4[i].oldclock);
+ qemu_put_sbe32s(f, &s->tm4[i].clock);
qemu_put_be64s(f, &s->tm4[i].lastload);
qemu_put_be32s(f, &s->tm4[i].freq);
qemu_put_be32s(f, &s->tm4[i].control);
int64_t now;
int i;
- qemu_get_be32s(f, &s->clock);
- qemu_get_be32s(f, &s->oldclock);
+ qemu_get_be32s(f, (uint32_t *) &s->clock);
+ qemu_get_be32s(f, (uint32_t *) &s->oldclock);
qemu_get_be64s(f, &s->lastload);
now = qemu_get_clock(vm_clock);
for (i = 0; i < 8; i ++) {
qemu_get_be32s(f, &s->tm4[i].tm.value);
s->tm4[i].tm.level = qemu_get_be32(f);
- qemu_get_be32s(f, &s->tm4[i].oldclock);
- qemu_get_be32s(f, &s->tm4[i].clock);
+ qemu_get_sbe32s(f, &s->tm4[i].oldclock);
+ qemu_get_sbe32s(f, &s->tm4[i].clock);
qemu_get_be64s(f, &s->tm4[i].lastload);
qemu_get_be32s(f, &s->tm4[i].freq);
qemu_get_be32s(f, &s->tm4[i].control);
pxa2xx_timer_info *s;
s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
- s->base = base;
s->irq_enabled = 0;
s->oldclock = 0;
s->clock = 0;
iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
pxa2xx_timer_writefn, s);
- cpu_register_physical_memory(base, 0x00000fff, iomemtype);
+ cpu_register_physical_memory(base, 0x00001000, iomemtype);
register_savevm("pxa2xx_timer", 0, 0,
pxa2xx_timer_save, pxa2xx_timer_load, s);
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
int i;
s->freq = PXA27X_FREQ;
- s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 *
- sizeof(struct pxa2xx_timer4_s));
+ s->tm4 = (PXA2xxTimer4 *) qemu_mallocz(8 *
+ sizeof(PXA2xxTimer4));
for (i = 0; i < 8; i ++) {
s->tm4[i].tm.value = 0;
s->tm4[i].tm.irq = irq4;