uint8_t msr; /* read only */
uint8_t scr;
uint8_t fcr;
+ uint8_t fcr_vmstate; /* we can't write directly this value
+ it has side effects */
/* NOTE: this hidden state is necessary for tx irq generation as
it can be reset while reading iir */
int thr_ipending;
* this is not in the specification but is observed on existing
* hardware. */
tmp_iir = UART_IIR_CTI;
- } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR)) {
- if (!(s->fcr & UART_FCR_FE)) {
- tmp_iir = UART_IIR_RDI;
- } else if (s->recv_fifo.count >= s->recv_fifo.itl) {
- tmp_iir = UART_IIR_RDI;
- }
+ } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
+ (!(s->fcr & UART_FCR_FE) ||
+ s->recv_fifo.count >= s->recv_fifo.itl)) {
+ tmp_iir = UART_IIR_RDI;
} else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
tmp_iir = UART_IIR_THRI;
} else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
ssp.parity = parity;
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;
- s->char_transmit_time = (ticks_per_sec / speed) * frame_size;
+ s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
#if 0
printf("speed=%d parity=%c data=%d stop=%d\n",
We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
if (s->poll_msl)
- qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + ticks_per_sec / 100);
+ qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + get_ticks_per_sec() / 100);
}
static void serial_xmit(void *opaque)
static void serial_receive_break(SerialState *s)
{
s->rbr = 0;
+ /* When the LSR_DR is set a null byte is pushed into the fifo */
+ fifo_put(s, RECV_FIFO, '\0');
s->lsr |= UART_LSR_BI | UART_LSR_DR;
serial_update_irq(s);
}
serial_receive_break(s);
}
-static void serial_save(QEMUFile *f, void *opaque)
+static void serial_pre_save(const void *opaque)
{
- SerialState *s = opaque;
-
- qemu_put_be16s(f,&s->divider);
- qemu_put_8s(f,&s->rbr);
- qemu_put_8s(f,&s->ier);
- qemu_put_8s(f,&s->iir);
- qemu_put_8s(f,&s->lcr);
- qemu_put_8s(f,&s->mcr);
- qemu_put_8s(f,&s->lsr);
- qemu_put_8s(f,&s->msr);
- qemu_put_8s(f,&s->scr);
- qemu_put_8s(f,&s->fcr);
+ SerialState *s = (void *)opaque;
+ s->fcr_vmstate = s->fcr;
}
-static int serial_load(QEMUFile *f, void *opaque, int version_id)
+static int serial_pre_load(void *opaque)
{
SerialState *s = opaque;
- uint8_t fcr = 0;
-
- if(version_id > 3)
- return -EINVAL;
+ s->fcr_vmstate = 0;
+ return 0;
+}
- if (version_id >= 2)
- qemu_get_be16s(f, &s->divider);
- else
- s->divider = qemu_get_byte(f);
- qemu_get_8s(f,&s->rbr);
- qemu_get_8s(f,&s->ier);
- qemu_get_8s(f,&s->iir);
- qemu_get_8s(f,&s->lcr);
- qemu_get_8s(f,&s->mcr);
- qemu_get_8s(f,&s->lsr);
- qemu_get_8s(f,&s->msr);
- qemu_get_8s(f,&s->scr);
-
- if (version_id >= 3)
- qemu_get_8s(f,&fcr);
+static int serial_post_load(void *opaque)
+{
+ SerialState *s = opaque;
/* Initialize fcr via setter to perform essential side-effects */
- serial_ioport_write(s, 0x02, fcr);
+ serial_ioport_write(s, 0x02, s->fcr_vmstate);
return 0;
}
+static const VMStateDescription vmstate_serial = {
+ .name = "serial",
+ .version_id = 3,
+ .minimum_version_id = 2,
+ .pre_save = serial_pre_save,
+ .pre_load = serial_pre_load,
+ .post_load = serial_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT16_V(divider, SerialState, 2),
+ VMSTATE_UINT8(rbr, SerialState),
+ VMSTATE_UINT8(ier, SerialState),
+ VMSTATE_UINT8(iir, SerialState),
+ VMSTATE_UINT8(lcr, SerialState),
+ VMSTATE_UINT8(mcr, SerialState),
+ VMSTATE_UINT8(lsr, SerialState),
+ VMSTATE_UINT8(msr, SerialState),
+ VMSTATE_UINT8(scr, SerialState),
+ VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void serial_reset(void *opaque)
{
SerialState *s = opaque;
s->mcr = UART_MCR_OUT2;
s->scr = 0;
s->tsr_retry = 0;
- s->char_transmit_time = (ticks_per_sec / 9600) * 9;
+ s->char_transmit_time = (get_ticks_per_sec() / 9600) * 9;
s->poll_msl = 0;
fifo_clear(s,RECV_FIFO);
static void serial_init_core(SerialState *s, qemu_irq irq, int baudbase,
CharDriverState *chr)
{
+ if (!chr) {
+ fprintf(stderr, "Can't create serial device, empty char device\n");
+ exit(1);
+ }
+
s->irq = irq;
s->baudbase = baudbase;
- s->chr = chr ?: qemu_chr_open("null", "null", NULL);
+ s->chr = chr;
s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
SerialState *s;
s = qemu_mallocz(sizeof(SerialState));
- if (!s)
- return NULL;
serial_init_core(s, irq, baudbase, chr);
- register_savevm("serial", base, 3, serial_save, serial_load, s);
+ vmstate_register(base, &vmstate_serial, s);
register_ioport_write(base, 8, 1, serial_ioport_write, s);
register_ioport_read(base, 8, 1, serial_ioport_read, s);
}
/* Memory mapped interface */
-uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
return serial_ioport_read(s, addr >> s->it_shift) & 0xFF;
}
-void serial_mm_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+static void serial_mm_writeb(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
{
SerialState *s = opaque;
serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
}
-uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
uint32_t val;
return val;
}
-void serial_mm_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+static void serial_mm_writew(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
{
SerialState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
}
-uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
uint32_t val;
return val;
}
-void serial_mm_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+static void serial_mm_writel(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
{
SerialState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
serial_ioport_write(s, addr >> s->it_shift, value);
}
-static CPUReadMemoryFunc *serial_mm_read[] = {
+static CPUReadMemoryFunc * const serial_mm_read[] = {
&serial_mm_readb,
&serial_mm_readw,
&serial_mm_readl,
};
-static CPUWriteMemoryFunc *serial_mm_write[] = {
+static CPUWriteMemoryFunc * const serial_mm_write[] = {
&serial_mm_writeb,
&serial_mm_writew,
&serial_mm_writel,
int s_io_memory;
s = qemu_mallocz(sizeof(SerialState));
- if (!s)
- return NULL;
s->it_shift = it_shift;
serial_init_core(s, irq, baudbase, chr);
- register_savevm("serial", base, 3, serial_save, serial_load, s);
+ vmstate_register(base, &vmstate_serial, s);
if (ioregister) {
- s_io_memory = cpu_register_io_memory(0, serial_mm_read,
+ s_io_memory = cpu_register_io_memory(serial_mm_read,
serial_mm_write, s);
cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
}
projects / qemu / blobdiff