vmstate: port cirrus_vga device

[qemu] / hw / sh7750.c

diff --git a/hw/sh7750.c b/hw/sh7750.c
index 4d1a806..cf9cf16 100644 (file)
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -23,7 +23,6 @@
  * THE SOFTWARE.
  */
 #include <stdio.h>
-#include <assert.h>
 #include "hw.h"
 #include "sh.h"
 #include "sysemu.h"
@@ -42,8 +41,12 @@ typedef struct SH7750State {
     uint32_t periph_freq;
     /* SDRAM controller */
     uint32_t bcr1;
-    uint32_t bcr2;
+    uint16_t bcr2;
+    uint16_t bcr3;
+    uint32_t bcr4;
     uint16_t rfcr;
+    /* PCMCIA controller */
+    uint16_t pcr;
     /* IO ports */
     uint16_t gpioic;
     uint32_t pctra;
@@ -66,7 +69,10 @@ typedef struct SH7750State {
     struct intc_desc intc;
 } SH7750State;
 
-
+static int inline has_bcr3_and_bcr4(SH7750State * s)
+{
+       return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
+}
 /**********************************************************************
  I/O ports
 **********************************************************************/
@@ -211,8 +217,14 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
     switch (addr) {
     case SH7750_BCR2_A7:
        return s->bcr2;
+    case SH7750_BCR3_A7:
+       if(!has_bcr3_and_bcr4(s))
+           error_access("word read", addr);
+       return s->bcr3;
     case SH7750_FRQCR_A7:
        return 0;
+    case SH7750_PCR_A7:
+       return s->pcr;
     case SH7750_RFCR_A7:
        fprintf(stderr,
                "Read access to refresh count register, incrementing\n");
@@ -221,6 +233,11 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
        return porta_lines(s);
     case SH7750_PDTRB_A7:
        return portb_lines(s);
+    case SH7750_RTCOR_A7:
+    case SH7750_RTCNT_A7:
+    case SH7750_RTCSR_A7:
+       ignore_access("word read", addr);
+       return 0;
     default:
        error_access("word read", addr);
        assert(0);
@@ -235,6 +252,9 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
     case SH7750_BCR1_A7:
        return s->bcr1;
     case SH7750_BCR4_A7:
+       if(!has_bcr3_and_bcr4(s))
+           error_access("long read", addr);
+       return s->bcr4;
     case SH7750_WCR1_A7:
     case SH7750_WCR2_A7:
     case SH7750_WCR3_A7:
@@ -271,19 +291,19 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
     }
 }
 
+#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
+                       && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
 static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
                              uint32_t mem_value)
 {
-    switch (addr) {
-       /* PRECHARGE ? XXXXX */
-    case SH7750_PRECHARGE0_A7:
-    case SH7750_PRECHARGE1_A7:
+
+    if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
        ignore_access("byte write", addr);
        return;
-    default:
-       error_access("byte write", addr);
-       assert(0);
     }
+
+    error_access("byte write", addr);
+    assert(0);
 }
 
 static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
@@ -298,8 +318,15 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
         s->bcr2 = mem_value;
         return;
     case SH7750_BCR3_A7:
-    case SH7750_RTCOR_A7:
+       if(!has_bcr3_and_bcr4(s))
+           error_access("word write", addr);
+       s->bcr3 = mem_value;
+       return;
+    case SH7750_PCR_A7:
+       s->pcr = mem_value;
+       return;
     case SH7750_RTCNT_A7:
+    case SH7750_RTCOR_A7:
     case SH7750_RTCSR_A7:
        ignore_access("word write", addr);
        return;
@@ -343,6 +370,10 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
         s->bcr1 = mem_value;
         return;
     case SH7750_BCR4_A7:
+       if(!has_bcr3_and_bcr4(s))
+           error_access("long write", addr);
+       s->bcr4 = mem_value;
+       return;
     case SH7750_WCR1_A7:
     case SH7750_WCR2_A7:
     case SH7750_WCR3_A7:
@@ -403,13 +434,13 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static CPUReadMemoryFunc *sh7750_mem_read[] = {
+static CPUReadMemoryFunc * const sh7750_mem_read[] = {
     sh7750_mem_readb,
     sh7750_mem_readw,
     sh7750_mem_readl
 };
 
-static CPUWriteMemoryFunc *sh7750_mem_write[] = {
+static CPUWriteMemoryFunc * const sh7750_mem_write[] = {
     sh7750_mem_writeb,
     sh7750_mem_writew,
     sh7750_mem_writel
@@ -657,13 +688,13 @@ static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static CPUReadMemoryFunc *sh7750_mmct_read[] = {
+static CPUReadMemoryFunc * const sh7750_mmct_read[] = {
     invalid_read,
     invalid_read,
     sh7750_mmct_readl
 };
 
-static CPUWriteMemoryFunc *sh7750_mmct_write[] = {
+static CPUWriteMemoryFunc * const sh7750_mmct_write[] = {
     invalid_write,
     invalid_write,
     sh7750_mmct_writel
@@ -678,8 +709,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
     s = qemu_mallocz(sizeof(SH7750State));
     s->cpu = cpu;
     s->periph_freq = 60000000; /* 60MHz */
-    sh7750_io_memory = cpu_register_io_memory(0,
-                                             sh7750_mem_read,
+    sh7750_io_memory = cpu_register_io_memory(sh7750_mem_read,
                                              sh7750_mem_write, s);
     cpu_register_physical_memory_offset(0x1f000000, 0x1000,
                                         sh7750_io_memory, 0x1f000000);
@@ -694,8 +724,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
     cpu_register_physical_memory_offset(0xffc00000, 0x1000,
                                         sh7750_io_memory, 0x1fc00000);
 
-    sh7750_mm_cache_and_tlb = cpu_register_io_memory(0,
-                                                    sh7750_mmct_read,
+    sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read,
                                                     sh7750_mmct_write, s);
     cpu_register_physical_memory(0xf0000000, 0x08000000,
                                 sh7750_mm_cache_and_tlb);