}
typedef struct {
- CPUReadMemoryFunc *r[3];
- CPUWriteMemoryFunc *w[3];
+ CPUReadMemoryFunc * const r[3];
+ CPUWriteMemoryFunc * const w[3];
} MemOp;
static MemOp sh_pci_reg = {
};
PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
- qemu_irq *pic, int devfn_min, int nirq)
+ void *opaque, int devfn_min, int nirq)
{
SHPCIC *p;
int mem, reg, iop;
p = qemu_mallocz(sizeof(SHPCIC));
- p->bus = pci_register_bus(set_irq, map_irq, pic, devfn_min, nirq);
+ p->bus = pci_register_bus(NULL, "pci",
+ set_irq, map_irq, opaque, devfn_min, nirq);
p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
-1, NULL, NULL);
- reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p);
- iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p);
- mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p);
+ reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p);
+ iop = cpu_register_io_memory(sh_pci_iop.r, sh_pci_iop.w, p);
+ mem = cpu_register_io_memory(sh_pci_mem.r, sh_pci_mem.w, p);
cpu_register_physical_memory(0x1e200000, 0x224, reg);
cpu_register_physical_memory(0x1e240000, 0x40000, iop);
cpu_register_physical_memory(0x1d000000, 0x1000000, mem);
cpu_register_physical_memory(0xfd000000, 0x1000000, mem);
pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI);
- pci_config_set_device_id(p->dev->config, 0x350e); // SH7751R
+ pci_config_set_device_id(p->dev->config, PCI_DEVICE_ID_HITACHI_SH7751R);
p->dev->config[0x04] = 0x80;
p->dev->config[0x05] = 0x00;
p->dev->config[0x06] = 0x90;