linux-user: fix ppc target_stat64 st_blocks layout

[qemu] / hw / sh_pci.c

diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index e849634..ea8635d 100644 (file)
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -29,9 +29,6 @@
 typedef struct {
     PCIBus *bus;
     PCIDevice *dev;
-    uint32_t regbase;
-    uint32_t iopbase;
-    uint32_t membase;
     uint32_t par;
     uint32_t mbr;
     uint32_t iobr;
@@ -40,7 +37,6 @@ typedef struct {
 static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
 {
     SHPCIC *pcic = p;
-    addr -= pcic->regbase;
     switch(addr) {
     case 0 ... 0xfc:
         cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
@@ -63,7 +59,6 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
 static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
 {
     SHPCIC *pcic = p;
-    addr -= pcic->regbase;
     switch(addr) {
     case 0 ... 0xfc:
         return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
@@ -78,13 +73,13 @@ static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
 static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr,
                                uint32_t val, int size)
 {
-    pci_data_write(pcic->bus, addr - pcic->membase + pcic->mbr, val, size);
+    pci_data_write(pcic->bus, addr + pcic->mbr, val, size);
 }
 
 static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr,
                                  int size)
 {
-    return pci_data_read(pcic->bus, addr - pcic->membase + pcic->mbr, size);
+    return pci_data_read(pcic->bus, addr + pcic->mbr, size);
 }
 
 static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val)
@@ -119,7 +114,7 @@ static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr)
 
 static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr)
 {
-    return addr - pcic->iopbase + pcic->iobr;
+    return addr + pcic->iobr;
 }
 
 static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val)
@@ -153,8 +148,8 @@ static uint32_t sh_pci_inl (void *p, target_phys_addr_t addr)
 }
 
 typedef struct {
-    CPUReadMemoryFunc *r[3];
-    CPUWriteMemoryFunc *w[3];
+    CPUReadMemoryFunc * const r[3];
+    CPUWriteMemoryFunc * const w[3];
 } MemOp;
 
 static MemOp sh_pci_reg = {
@@ -173,30 +168,29 @@ static MemOp sh_pci_iop = {
 };
 
 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
-                            qemu_irq *pic, int devfn_min, int nirq)
+                            void *opaque, int devfn_min, int nirq)
 {
     SHPCIC *p;
     int mem, reg, iop;
 
     p = qemu_mallocz(sizeof(SHPCIC));
-    p->bus = pci_register_bus(set_irq, map_irq, pic, devfn_min, nirq);
+    p->bus = pci_register_bus(NULL, "pci",
+                              set_irq, map_irq, opaque, devfn_min, nirq);
 
     p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
                                  -1, NULL, NULL);
-    p->regbase = 0x1e200000;
-    p->iopbase = 0x1e240000;
-    p->membase = 0xfd000000;
-    reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p);
-    mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p);
-    iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p);
-    cpu_register_physical_memory(p->regbase, 0x224, reg);
-    cpu_register_physical_memory(p->iopbase, 0x40000, iop);
-    cpu_register_physical_memory(p->membase, 0x1000000, mem);
-
-    p->dev->config[0x00] = 0x54; // HITACHI
-    p->dev->config[0x01] = 0x10; //
-    p->dev->config[0x02] = 0x0e; // SH7751R
-    p->dev->config[0x03] = 0x35; //
+    reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p);
+    iop = cpu_register_io_memory(sh_pci_iop.r, sh_pci_iop.w, p);
+    mem = cpu_register_io_memory(sh_pci_mem.r, sh_pci_mem.w, p);
+    cpu_register_physical_memory(0x1e200000, 0x224, reg);
+    cpu_register_physical_memory(0x1e240000, 0x40000, iop);
+    cpu_register_physical_memory(0x1d000000, 0x1000000, mem);
+    cpu_register_physical_memory(0xfe200000, 0x224, reg);
+    cpu_register_physical_memory(0xfe240000, 0x40000, iop);
+    cpu_register_physical_memory(0xfd000000, 0x1000000, mem);
+
+    pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI);
+    pci_config_set_device_id(p->dev->config, PCI_DEVICE_ID_HITACHI_SH7751R);
     p->dev->config[0x04] = 0x80;
     p->dev->config[0x05] = 0x00;
     p->dev->config[0x06] = 0x90;
@@ -204,4 +198,3 @@ PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 
     return p->bus;
 }
-