* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sh.h"
+#include "qemu-timer.h"
//#define DEBUG_TIMER
#define TIMER_FEAT_CAPT (1 << 0)
#define TIMER_FEAT_EXTCLK (1 << 1)
+#define OFFSET_TCOR 0
+#define OFFSET_TCNT 1
+#define OFFSET_TCR 2
+#define OFFSET_TCPR 3
+
typedef struct {
ptimer_state *timer;
uint32_t tcnt;
uint32_t tcpr;
int freq;
int int_level;
+ int old_level;
int feat;
int enabled;
qemu_irq irq;
static void sh_timer_update(sh_timer_state *s)
{
-#if 0 /* not yet */
- /* Update interrupts. */
- if (s->int_level && (s->tcr & TIMER_TCR_UNIE)) {
- qemu_irq_raise(s->irq);
- } else {
- qemu_irq_lower(s->irq);
- }
-#endif
+ int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
+
+ if (new_level != s->old_level)
+ qemu_set_irq (s->irq, new_level);
+
+ s->old_level = s->int_level;
+ s->int_level = new_level;
}
-uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
{
sh_timer_state *s = (sh_timer_state *)opaque;
switch (offset >> 2) {
- case 0:
+ case OFFSET_TCOR:
return s->tcor;
- case 1:
+ case OFFSET_TCNT:
return ptimer_get_count(s->timer);
- case 2:
+ case OFFSET_TCR:
return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
- case 3:
+ case OFFSET_TCPR:
if (s->feat & TIMER_FEAT_CAPT)
return s->tcpr;
default:
- cpu_abort (cpu_single_env, "sh_timer_read: Bad offset %x\n",
- (int)offset);
+ hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
return 0;
}
}
int freq;
switch (offset >> 2) {
- case 0:
+ case OFFSET_TCOR:
s->tcor = value;
ptimer_set_limit(s->timer, s->tcor, 0);
break;
- case 1:
+ case OFFSET_TCNT:
s->tcnt = value;
ptimer_set_count(s->timer, s->tcnt);
break;
- case 2:
+ case OFFSET_TCR:
if (s->enabled) {
/* Pause the timer if it is running. This may cause some
inaccuracy dure to rounding, but avoids a whole lot of other
case 4: freq >>= 10; break;
case 6:
case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
- default: cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved TPSC value\n"); break;
+ default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
}
switch ((value & TIMER_TCR_CKEG) >> 3) {
case 0: break;
case 1:
case 2:
case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
- default: cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved CKEG value\n"); break;
+ default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
}
switch ((value & TIMER_TCR_ICPE) >> 6) {
case 0: break;
case 2:
case 3: if (s->feat & TIMER_FEAT_CAPT) break;
- default: cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved ICPE value\n"); break;
+ default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
}
if ((value & TIMER_TCR_UNF) == 0)
s->int_level = 0;
value &= ~TIMER_TCR_UNF;
if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
- cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved ICPF value\n");
+ hw_error("sh_timer_write: Reserved ICPF value\n");
value &= ~TIMER_TCR_ICPF; /* capture not supported */
if (value & TIMER_TCR_RESERVED)
- cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved TCR bits set\n");
+ hw_error("sh_timer_write: Reserved TCR bits set\n");
s->tcr = value;
ptimer_set_limit(s->timer, s->tcor, 0);
ptimer_set_freq(s->timer, freq);
ptimer_run(s->timer, 0);
}
break;
- case 3:
+ case OFFSET_TCPR:
if (s->feat & TIMER_FEAT_CAPT) {
s->tcpr = value;
break;
}
default:
- cpu_abort (cpu_single_env, "sh_timer_write: Bad offset %x\n",
- (int)offset);
+ hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
}
sh_timer_update(s);
}
sh_timer_update(s);
}
-static void *sh_timer_init(uint32_t freq, int feat)
+static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
{
sh_timer_state *s;
QEMUBH *bh;
s->tcor = 0xffffffff;
s->tcnt = 0xffffffff;
s->tcpr = 0xdeadbeef;
- s->tcor = 0;
+ s->tcr = 0;
s->enabled = 0;
+ s->irq = irq;
bh = qemu_bh_new(sh_timer_tick, s);
s->timer = ptimer_init(bh);
+
+ sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
+ sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
+ sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
+ sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr);
/* ??? Save/restore. */
return s;
}
int level[3];
uint32_t tocr;
uint32_t tstr;
- target_phys_addr_t base;
int feat;
} tmu012_state;
#ifdef DEBUG_TIMER
printf("tmu012_read 0x%lx\n", (unsigned long) offset);
#endif
- offset -= s->base;
if (offset >= 0x20) {
if (!(s->feat & TMU012_FEAT_3CHAN))
- cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
- (int)offset);
+ hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
return sh_timer_read(s->timer[2], offset - 0x20);
}
if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
return s->tocr;
- cpu_abort (cpu_single_env, "tmu012_write: Bad offset %x\n",
- (int)offset);
+ hw_error("tmu012_write: Bad offset %x\n", (int)offset);
return 0;
}
#ifdef DEBUG_TIMER
printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
#endif
- offset -= s->base;
if (offset >= 0x20) {
if (!(s->feat & TMU012_FEAT_3CHAN))
- cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
- (int)offset);
+ hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
sh_timer_write(s->timer[2], offset - 0x20, value);
return;
}
sh_timer_start_stop(s->timer[2], value & (1 << 2));
else
if (value & (1 << 2))
- cpu_abort (cpu_single_env, "tmu012_write: Bad channel\n");
+ hw_error("tmu012_write: Bad channel\n");
s->tstr = value;
return;
}
}
-static CPUReadMemoryFunc *tmu012_readfn[] = {
+static CPUReadMemoryFunc * const tmu012_readfn[] = {
tmu012_read,
tmu012_read,
tmu012_read
};
-static CPUWriteMemoryFunc *tmu012_writefn[] = {
+static CPUWriteMemoryFunc * const tmu012_writefn[] = {
tmu012_write,
tmu012_write,
tmu012_write
};
-void tmu012_init(uint32_t base, int feat, uint32_t freq)
+void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
+ qemu_irq ch0_irq, qemu_irq ch1_irq,
+ qemu_irq ch2_irq0, qemu_irq ch2_irq1)
{
int iomemtype;
tmu012_state *s;
int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
s = (tmu012_state *)qemu_mallocz(sizeof(tmu012_state));
- s->base = base;
s->feat = feat;
- s->timer[0] = sh_timer_init(freq, timer_feat);
- s->timer[1] = sh_timer_init(freq, timer_feat);
+ s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
+ s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
if (feat & TMU012_FEAT_3CHAN)
- s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT);
- iomemtype = cpu_register_io_memory(0, tmu012_readfn,
+ s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
+ ch2_irq0); /* ch2_irq1 not supported */
+ iomemtype = cpu_register_io_memory(tmu012_readfn,
tmu012_writefn, s);
- cpu_register_physical_memory(base, 0x00001000, iomemtype);
+ cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype);
+ cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype);
/* ??? Save/restore. */
}
projects / qemu / blobdiff