* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sun4m.h"
+#include "console.h"
+
//#define DEBUG_IRQ_COUNT
//#define DEBUG_IRQ
#define MAX_CPUS 16
#define MAX_PILS 16
+struct SLAVIO_CPUINTCTLState;
+
typedef struct SLAVIO_INTCTLState {
- uint32_t intreg_pending[MAX_CPUS];
uint32_t intregm_pending;
uint32_t intregm_disabled;
uint32_t target_cpu;
#endif
qemu_irq *cpu_irqs[MAX_CPUS];
const uint32_t *intbit_to_level;
- uint32_t cputimer_bit;
+ uint32_t cputimer_lbit, cputimer_mbit;
uint32_t pil_out[MAX_CPUS];
+ struct SLAVIO_CPUINTCTLState *slaves[MAX_CPUS];
} SLAVIO_INTCTLState;
+typedef struct SLAVIO_CPUINTCTLState {
+ uint32_t intreg_pending;
+ SLAVIO_INTCTLState *master;
+ uint32_t cpu;
+} SLAVIO_CPUINTCTLState;
+
#define INTCTL_MAXADDR 0xf
#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
-#define INTCTLM_MAXADDR 0x13
-#define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
-#define INTCTLM_MASK 0x1f
-static void slavio_check_interrupts(void *opaque);
+#define INTCTLM_SIZE 0x14
+#define MASTER_IRQ_MASK ~0x0fa2007f
+#define MASTER_DISABLE 0x80000000
+#define CPU_SOFTIRQ_MASK 0xfffe0000
+#define CPU_HARDIRQ_MASK 0x0000fffe
+#define CPU_IRQ_INT15_IN 0x0004000
+#define CPU_IRQ_INT15_MASK 0x80000000
+
+static void slavio_check_interrupts(SLAVIO_INTCTLState *s);
// per-cpu interrupt controller
static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
{
- SLAVIO_INTCTLState *s = opaque;
+ SLAVIO_CPUINTCTLState *s = opaque;
uint32_t saddr, ret;
- int cpu;
- cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
- saddr = (addr & INTCTL_MAXADDR) >> 2;
+ saddr = addr >> 2;
switch (saddr) {
case 0:
- ret = s->intreg_pending[cpu];
+ ret = s->intreg_pending;
break;
default:
ret = 0;
return ret;
}
-static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
{
- SLAVIO_INTCTLState *s = opaque;
+ SLAVIO_CPUINTCTLState *s = opaque;
uint32_t saddr;
- int cpu;
- cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
- saddr = (addr & INTCTL_MAXADDR) >> 2;
+ saddr = addr >> 2;
DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
switch (saddr) {
case 1: // clear pending softints
- if (val & 0x4000)
- val |= 80000000;
- val &= 0xfffe0000;
- s->intreg_pending[cpu] &= ~val;
- slavio_check_interrupts(s);
- DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
+ if (val & CPU_IRQ_INT15_IN)
+ val |= CPU_IRQ_INT15_MASK;
+ val &= CPU_SOFTIRQ_MASK;
+ s->intreg_pending &= ~val;
+ slavio_check_interrupts(s->master);
+ DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
+ s->intreg_pending);
break;
case 2: // set softint
- val &= 0xfffe0000;
- s->intreg_pending[cpu] |= val;
- slavio_check_interrupts(s);
- DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
+ val &= CPU_SOFTIRQ_MASK;
+ s->intreg_pending |= val;
+ slavio_check_interrupts(s->master);
+ DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
+ s->intreg_pending);
break;
default:
break;
}
static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
- slavio_intctl_mem_readl,
- slavio_intctl_mem_readl,
+ NULL,
+ NULL,
slavio_intctl_mem_readl,
};
static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
- slavio_intctl_mem_writel,
- slavio_intctl_mem_writel,
+ NULL,
+ NULL,
slavio_intctl_mem_writel,
};
SLAVIO_INTCTLState *s = opaque;
uint32_t saddr, ret;
- saddr = (addr & INTCTLM_MAXADDR) >> 2;
+ saddr = addr >> 2;
switch (saddr) {
case 0:
- ret = s->intregm_pending & 0x7fffffff;
+ ret = s->intregm_pending & ~MASTER_DISABLE;
break;
case 1:
- ret = s->intregm_disabled;
+ ret = s->intregm_disabled & MASTER_IRQ_MASK;
break;
case 4:
ret = s->target_cpu;
return ret;
}
-static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
{
SLAVIO_INTCTLState *s = opaque;
uint32_t saddr;
- saddr = (addr & INTCTLM_MASK) >> 2;
+ saddr = addr >> 2;
DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
switch (saddr) {
case 2: // clear (enable)
// Force clear unused bits
- val &= ~0x4fb2007f;
+ val &= MASTER_IRQ_MASK;
s->intregm_disabled &= ~val;
- DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
+ DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
+ s->intregm_disabled);
slavio_check_interrupts(s);
break;
case 3: // set (disable, clear pending)
// Force clear unused bits
- val &= ~0x4fb2007f;
+ val &= MASTER_IRQ_MASK;
s->intregm_disabled |= val;
s->intregm_pending &= ~val;
slavio_check_interrupts(s);
- DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
+ DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
+ s->intregm_disabled);
break;
case 4:
s->target_cpu = val & (MAX_CPUS - 1);
}
static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
- slavio_intctlm_mem_readl,
- slavio_intctlm_mem_readl,
+ NULL,
+ NULL,
slavio_intctlm_mem_readl,
};
static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
- slavio_intctlm_mem_writel,
- slavio_intctlm_mem_writel,
+ NULL,
+ NULL,
slavio_intctlm_mem_writel,
};
int i;
for (i = 0; i < MAX_CPUS; i++) {
- term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
+ term_printf("per-cpu %d: pending 0x%08x\n", i,
+ s->slaves[i]->intreg_pending);
}
- term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
+ term_printf("master: pending 0x%08x, disabled 0x%08x\n",
+ s->intregm_pending, s->intregm_disabled);
}
void slavio_irq_info(void *opaque)
#endif
}
-static void slavio_check_interrupts(void *opaque)
+static void slavio_check_interrupts(SLAVIO_INTCTLState *s)
{
- SLAVIO_INTCTLState *s = opaque;
uint32_t pending = s->intregm_pending, pil_pending;
unsigned int i, j;
DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
for (i = 0; i < MAX_CPUS; i++) {
pil_pending = 0;
- if (pending && !(s->intregm_disabled & 0x80000000) &&
+ if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
(i == s->target_cpu)) {
for (j = 0; j < 32; j++) {
if (pending & (1 << j))
pil_pending |= 1 << s->intbit_to_level[j];
}
}
- pil_pending |= (s->intreg_pending[i] >> 16) & 0xfffe;
+ pil_pending |= (s->slaves[i]->intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
for (j = 0; j < MAX_PILS; j++) {
if (pil_pending & (1 << j)) {
s->irq_count[pil]++;
#endif
s->intregm_pending |= mask;
- s->intreg_pending[s->target_cpu] |= 1 << pil;
+ s->slaves[s->target_cpu]->intreg_pending |= 1 << pil;
} else {
s->intregm_pending &= ~mask;
- s->intreg_pending[s->target_cpu] &= ~(1 << pil);
+ s->slaves[s->target_cpu]->intreg_pending &= ~(1 << pil);
}
slavio_check_interrupts(s);
}
DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
- if (level)
- s->intreg_pending[cpu] |= s->cputimer_bit;
- else
- s->intreg_pending[cpu] &= ~s->cputimer_bit;
+ if (level) {
+ s->intregm_pending |= s->cputimer_mbit;
+ s->slaves[cpu]->intreg_pending |= s->cputimer_lbit;
+ } else {
+ s->intregm_pending &= ~s->cputimer_mbit;
+ s->slaves[cpu]->intreg_pending &= ~s->cputimer_lbit;
+ }
slavio_check_interrupts(s);
}
int i;
for (i = 0; i < MAX_CPUS; i++) {
- qemu_put_be32s(f, &s->intreg_pending[i]);
+ qemu_put_be32s(f, &s->slaves[i]->intreg_pending);
}
qemu_put_be32s(f, &s->intregm_pending);
qemu_put_be32s(f, &s->intregm_disabled);
return -EINVAL;
for (i = 0; i < MAX_CPUS; i++) {
- qemu_get_be32s(f, &s->intreg_pending[i]);
+ qemu_get_be32s(f, &s->slaves[i]->intreg_pending);
}
qemu_get_be32s(f, &s->intregm_pending);
qemu_get_be32s(f, &s->intregm_disabled);
int i;
for (i = 0; i < MAX_CPUS; i++) {
- s->intreg_pending[i] = 0;
+ s->slaves[i]->intreg_pending = 0;
}
- s->intregm_disabled = ~0xffb2007f;
+ s->intregm_disabled = ~MASTER_IRQ_MASK;
s->intregm_pending = 0;
s->target_cpu = 0;
slavio_check_interrupts(s);
{
int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
SLAVIO_INTCTLState *s;
+ SLAVIO_CPUINTCTLState *slave;
s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
if (!s)
s->intbit_to_level = intbit_to_level;
for (i = 0; i < MAX_CPUS; i++) {
- slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
+ slave = qemu_mallocz(sizeof(SLAVIO_CPUINTCTLState));
+ if (!slave)
+ return NULL;
+
+ slave->cpu = i;
+ slave->master = s;
+
+ slavio_intctl_io_memory = cpu_register_io_memory(0,
+ slavio_intctl_mem_read,
+ slavio_intctl_mem_write,
+ slave);
cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
slavio_intctl_io_memory);
+
+ s->slaves[i] = slave;
s->cpu_irqs[i] = parent_irq[i];
}
- slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
+ slavio_intctlm_io_memory = cpu_register_io_memory(0,
+ slavio_intctlm_mem_read,
+ slavio_intctlm_mem_write,
+ s);
cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
- register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
+ register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
+ slavio_intctl_load, s);
qemu_register_reset(slavio_intctl_reset, s);
*irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
*cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
- s->cputimer_bit = 1 << s->intbit_to_level[cputimer];
+ s->cputimer_mbit = 1 << cputimer;
+ s->cputimer_lbit = 1 << intbit_to_level[cputimer];
slavio_intctl_reset(s);
return s;
}
-
projects / qemu / blobdiff