/*
* QEMU Sparc SLAVIO interrupt controller emulation
- *
+ *
* Copyright (c) 2003-2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sun4m.h"
+#include "console.h"
+
//#define DEBUG_IRQ_COUNT
//#define DEBUG_IRQ
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
*
* There is a system master controller and one for each cpu.
- *
+ *
*/
#define MAX_CPUS 16
+#define MAX_PILS 16
+
+struct SLAVIO_CPUINTCTLState;
typedef struct SLAVIO_INTCTLState {
- uint32_t intreg_pending[MAX_CPUS];
uint32_t intregm_pending;
uint32_t intregm_disabled;
uint32_t target_cpu;
#ifdef DEBUG_IRQ_COUNT
uint64_t irq_count[32];
#endif
- CPUState *cpu_envs[MAX_CPUS];
+ qemu_irq *cpu_irqs[MAX_CPUS];
+ const uint32_t *intbit_to_level;
+ uint32_t cputimer_lbit, cputimer_mbit;
+ uint32_t pil_out[MAX_CPUS];
+ struct SLAVIO_CPUINTCTLState *slaves[MAX_CPUS];
} SLAVIO_INTCTLState;
+typedef struct SLAVIO_CPUINTCTLState {
+ uint32_t intreg_pending;
+ SLAVIO_INTCTLState *master;
+ uint32_t cpu;
+} SLAVIO_CPUINTCTLState;
+
#define INTCTL_MAXADDR 0xf
-#define INTCTLM_MAXADDR 0xf
-static void slavio_check_interrupts(void *opaque);
+#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
+#define INTCTLM_SIZE 0x14
+#define MASTER_IRQ_MASK ~0x0fa2007f
+#define MASTER_DISABLE 0x80000000
+#define CPU_SOFTIRQ_MASK 0xfffe0000
+#define CPU_HARDIRQ_MASK 0x0000fffe
+#define CPU_IRQ_INT15_IN 0x0004000
+#define CPU_IRQ_INT15_MASK 0x80000000
+
+static void slavio_check_interrupts(SLAVIO_INTCTLState *s);
// per-cpu interrupt controller
static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
{
- SLAVIO_INTCTLState *s = opaque;
- uint32_t saddr;
- int cpu;
+ SLAVIO_CPUINTCTLState *s = opaque;
+ uint32_t saddr, ret;
- cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
- saddr = (addr & INTCTL_MAXADDR) >> 2;
+ saddr = addr >> 2;
switch (saddr) {
case 0:
- return s->intreg_pending[cpu];
+ ret = s->intreg_pending;
+ break;
default:
- break;
+ ret = 0;
+ break;
}
- return 0;
+ DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, ret);
+
+ return ret;
}
-static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
{
- SLAVIO_INTCTLState *s = opaque;
+ SLAVIO_CPUINTCTLState *s = opaque;
uint32_t saddr;
- int cpu;
- cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
- saddr = (addr & INTCTL_MAXADDR) >> 2;
+ saddr = addr >> 2;
+ DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
switch (saddr) {
case 1: // clear pending softints
- if (val & 0x4000)
- val |= 80000000;
- val &= 0xfffe0000;
- s->intreg_pending[cpu] &= ~val;
- DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
- break;
+ if (val & CPU_IRQ_INT15_IN)
+ val |= CPU_IRQ_INT15_MASK;
+ val &= CPU_SOFTIRQ_MASK;
+ s->intreg_pending &= ~val;
+ slavio_check_interrupts(s->master);
+ DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
+ s->intreg_pending);
+ break;
case 2: // set softint
- val &= 0xfffe0000;
- s->intreg_pending[cpu] |= val;
- slavio_check_interrupts(s);
- DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
- break;
+ val &= CPU_SOFTIRQ_MASK;
+ s->intreg_pending |= val;
+ slavio_check_interrupts(s->master);
+ DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
+ s->intreg_pending);
+ break;
default:
- break;
+ break;
}
}
static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
- slavio_intctl_mem_readl,
- slavio_intctl_mem_readl,
+ NULL,
+ NULL,
slavio_intctl_mem_readl,
};
static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
- slavio_intctl_mem_writel,
- slavio_intctl_mem_writel,
+ NULL,
+ NULL,
slavio_intctl_mem_writel,
};
static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
{
SLAVIO_INTCTLState *s = opaque;
- uint32_t saddr;
+ uint32_t saddr, ret;
- saddr = (addr & INTCTLM_MAXADDR) >> 2;
+ saddr = addr >> 2;
switch (saddr) {
case 0:
- return s->intregm_pending & 0x7fffffff;
+ ret = s->intregm_pending & ~MASTER_DISABLE;
+ break;
case 1:
- return s->intregm_disabled;
+ ret = s->intregm_disabled & MASTER_IRQ_MASK;
+ break;
case 4:
- return s->target_cpu;
+ ret = s->target_cpu;
+ break;
default:
- break;
+ ret = 0;
+ break;
}
- return 0;
+ DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
+
+ return ret;
}
-static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
{
SLAVIO_INTCTLState *s = opaque;
uint32_t saddr;
- saddr = (addr & INTCTLM_MAXADDR) >> 2;
+ saddr = addr >> 2;
+ DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
switch (saddr) {
case 2: // clear (enable)
- // Force clear unused bits
- val &= ~0x4fb2007f;
- s->intregm_disabled &= ~val;
- DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
- slavio_check_interrupts(s);
- break;
+ // Force clear unused bits
+ val &= MASTER_IRQ_MASK;
+ s->intregm_disabled &= ~val;
+ DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
+ s->intregm_disabled);
+ slavio_check_interrupts(s);
+ break;
case 3: // set (disable, clear pending)
- // Force clear unused bits
- val &= ~0x4fb2007f;
- s->intregm_disabled |= val;
- s->intregm_pending &= ~val;
- DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
- break;
+ // Force clear unused bits
+ val &= MASTER_IRQ_MASK;
+ s->intregm_disabled |= val;
+ s->intregm_pending &= ~val;
+ slavio_check_interrupts(s);
+ DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
+ s->intregm_disabled);
+ break;
case 4:
- s->target_cpu = val & (MAX_CPUS - 1);
- DPRINTF("Set master irq cpu %d\n", s->target_cpu);
- break;
+ s->target_cpu = val & (MAX_CPUS - 1);
+ slavio_check_interrupts(s);
+ DPRINTF("Set master irq cpu %d\n", s->target_cpu);
+ break;
default:
- break;
+ break;
}
}
static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
- slavio_intctlm_mem_readl,
- slavio_intctlm_mem_readl,
+ NULL,
+ NULL,
slavio_intctlm_mem_readl,
};
static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
- slavio_intctlm_mem_writel,
- slavio_intctlm_mem_writel,
+ NULL,
+ NULL,
slavio_intctlm_mem_writel,
};
int i;
for (i = 0; i < MAX_CPUS; i++) {
- term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
+ term_printf("per-cpu %d: pending 0x%08x\n", i,
+ s->slaves[i]->intreg_pending);
}
- term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
+ term_printf("master: pending 0x%08x, disabled 0x%08x\n",
+ s->intregm_pending, s->intregm_disabled);
}
void slavio_irq_info(void *opaque)
for (i = 0; i < 32; i++) {
count = s->irq_count[i];
if (count > 0)
- term_printf("%2d: %lld\n", i, count);
+ term_printf("%2d: %" PRId64 "\n", i, count);
}
#endif
}
-static const uint32_t intbit_to_level[32] = {
- 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
- 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
-};
-
-static void slavio_check_interrupts(void *opaque)
+static void slavio_check_interrupts(SLAVIO_INTCTLState *s)
{
- CPUState *env;
- SLAVIO_INTCTLState *s = opaque;
- uint32_t pending = s->intregm_pending;
- unsigned int i, j, max = 0;
+ uint32_t pending = s->intregm_pending, pil_pending;
+ unsigned int i, j;
pending &= ~s->intregm_disabled;
- if (pending && !(s->intregm_disabled & 0x80000000)) {
- for (i = 0; i < 32; i++) {
- if (pending & (1 << i)) {
- if (max < intbit_to_level[i])
- max = intbit_to_level[i];
- }
- }
- env = s->cpu_envs[s->target_cpu];
- if (!env) {
- DPRINTF("No CPU %d, not triggered (pending %x)\n", s->target_cpu, pending);
- }
- else {
- if (env->halted)
- env->halted = 0;
- if (env->interrupt_index == 0) {
- DPRINTF("Triggered CPU %d pil %d\n", s->target_cpu, max);
-#ifdef DEBUG_IRQ_COUNT
- s->irq_count[max]++;
-#endif
- env->interrupt_index = TT_EXTINT | max;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
- }
- else
- DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
- }
- }
- else
- DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
-
+ DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
for (i = 0; i < MAX_CPUS; i++) {
- max = 0;
- env = s->cpu_envs[i];
- if (!env)
- continue;
- for (j = 17; j < 32; j++) {
- if (s->intreg_pending[i] & (1 << j)) {
- if (max < j - 16)
- max = j - 16;
+ pil_pending = 0;
+ if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
+ (i == s->target_cpu)) {
+ for (j = 0; j < 32; j++) {
+ if (pending & (1 << j))
+ pil_pending |= 1 << s->intbit_to_level[j];
}
}
- if (max > 0) {
- if (env->halted)
- env->halted = 0;
- if (env->interrupt_index == 0) {
- DPRINTF("Triggered softint %d for cpu %d (pending %x)\n", max, i, pending);
-#ifdef DEBUG_IRQ_COUNT
- s->irq_count[max]++;
-#endif
- env->interrupt_index = TT_EXTINT | max;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ pil_pending |= (s->slaves[i]->intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
+
+ for (j = 0; j < MAX_PILS; j++) {
+ if (pil_pending & (1 << j)) {
+ if (!(s->pil_out[i] & (1 << j)))
+ qemu_irq_raise(s->cpu_irqs[i][j]);
+ } else {
+ if (s->pil_out[i] & (1 << j))
+ qemu_irq_lower(s->cpu_irqs[i][j]);
}
}
+ s->pil_out[i] = pil_pending;
}
}
* "irq" here is the bit number in the system interrupt register to
* separate serial and keyboard interrupts sharing a level.
*/
-void slavio_pic_set_irq(void *opaque, int irq, int level)
+static void slavio_set_irq(void *opaque, int irq, int level)
{
SLAVIO_INTCTLState *s = opaque;
+ uint32_t mask = 1 << irq;
+ uint32_t pil = s->intbit_to_level[irq];
- DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
- if (irq < 32) {
- uint32_t mask = 1 << irq;
- uint32_t pil = intbit_to_level[irq];
- if (pil > 0) {
- if (level) {
- s->intregm_pending |= mask;
- s->intreg_pending[s->target_cpu] |= 1 << pil;
- }
- else {
- s->intregm_pending &= ~mask;
- s->intreg_pending[s->target_cpu] &= ~(1 << pil);
- }
- }
+ DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
+ level);
+ if (pil > 0) {
+ if (level) {
+#ifdef DEBUG_IRQ_COUNT
+ s->irq_count[pil]++;
+#endif
+ s->intregm_pending |= mask;
+ s->slaves[s->target_cpu]->intreg_pending |= 1 << pil;
+ } else {
+ s->intregm_pending &= ~mask;
+ s->slaves[s->target_cpu]->intreg_pending &= ~(1 << pil);
+ }
+ slavio_check_interrupts(s);
}
- slavio_check_interrupts(s);
}
-void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
+static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
{
SLAVIO_INTCTLState *s = opaque;
- DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level);
- if (cpu == (unsigned int)-1) {
- slavio_pic_set_irq(opaque, irq, level);
- return;
- }
- if (irq < 32) {
- uint32_t pil = intbit_to_level[irq];
- if (pil > 0) {
- if (level) {
- s->intreg_pending[cpu] |= 1 << pil;
- }
- else {
- s->intreg_pending[cpu] &= ~(1 << pil);
- }
- }
+ DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
+
+ if (level) {
+ s->intregm_pending |= s->cputimer_mbit;
+ s->slaves[cpu]->intreg_pending |= s->cputimer_lbit;
+ } else {
+ s->intregm_pending &= ~s->cputimer_mbit;
+ s->slaves[cpu]->intreg_pending &= ~s->cputimer_lbit;
}
+
slavio_check_interrupts(s);
}
{
SLAVIO_INTCTLState *s = opaque;
int i;
-
+
for (i = 0; i < MAX_CPUS; i++) {
- qemu_put_be32s(f, &s->intreg_pending[i]);
+ qemu_put_be32s(f, &s->slaves[i]->intreg_pending);
}
qemu_put_be32s(f, &s->intregm_pending);
qemu_put_be32s(f, &s->intregm_disabled);
return -EINVAL;
for (i = 0; i < MAX_CPUS; i++) {
- qemu_get_be32s(f, &s->intreg_pending[i]);
+ qemu_get_be32s(f, &s->slaves[i]->intreg_pending);
}
qemu_get_be32s(f, &s->intregm_pending);
qemu_get_be32s(f, &s->intregm_disabled);
qemu_get_be32s(f, &s->target_cpu);
+ slavio_check_interrupts(s);
return 0;
}
int i;
for (i = 0; i < MAX_CPUS; i++) {
- s->intreg_pending[i] = 0;
+ s->slaves[i]->intreg_pending = 0;
}
- s->intregm_disabled = ~0xffb2007f;
+ s->intregm_disabled = ~MASTER_IRQ_MASK;
s->intregm_pending = 0;
s->target_cpu = 0;
+ slavio_check_interrupts(s);
}
-void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env)
-{
- SLAVIO_INTCTLState *s = opaque;
- s->cpu_envs[cpu] = env;
-}
-
-void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
+void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
+ const uint32_t *intbit_to_level,
+ qemu_irq **irq, qemu_irq **cpu_irq,
+ qemu_irq **parent_irq, unsigned int cputimer)
{
int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
SLAVIO_INTCTLState *s;
+ SLAVIO_CPUINTCTLState *slave;
s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
if (!s)
return NULL;
+ s->intbit_to_level = intbit_to_level;
for (i = 0; i < MAX_CPUS; i++) {
- slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
- cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
+ slave = qemu_mallocz(sizeof(SLAVIO_CPUINTCTLState));
+ if (!slave)
+ return NULL;
+
+ slave->cpu = i;
+ slave->master = s;
+
+ slavio_intctl_io_memory = cpu_register_io_memory(0,
+ slavio_intctl_mem_read,
+ slavio_intctl_mem_write,
+ slave);
+ cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
+ slavio_intctl_io_memory);
+
+ s->slaves[i] = slave;
+ s->cpu_irqs[i] = parent_irq[i];
}
- slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
- cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory);
+ slavio_intctlm_io_memory = cpu_register_io_memory(0,
+ slavio_intctlm_mem_read,
+ slavio_intctlm_mem_write,
+ s);
+ cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
- register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
+ register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
+ slavio_intctl_load, s);
qemu_register_reset(slavio_intctl_reset, s);
+ *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
+
+ *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
+ s->cputimer_mbit = 1 << cputimer;
+ s->cputimer_lbit = 1 << intbit_to_level[cputimer];
slavio_intctl_reset(s);
return s;
}
-
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