microblaze: linux-user support.

[qemu] / hw / sparc32_dma.c

diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
index f26b4be..6893b88 100644 (file)
--- a/hw/sparc32_dma.c
+++ b/hw/sparc32_dma.c
@@ -21,7 +21,9 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */
-#include "vl.h"
+#include "hw.h"
+#include "sparc32_dma.h"
+#include "sun4m.h"
 
 /* debug DMA */
 //#define DEBUG_DMA
@@ -35,15 +37,17 @@
  */
 
 #ifdef DEBUG_DMA
-#define DPRINTF(fmt, args...) \
-do { printf("DMA: " fmt , ##args); } while (0)
+#define DPRINTF(fmt, ...)                               \
+    do { printf("DMA: " fmt , ## __VA_ARGS__); } while (0)
 #else
-#define DPRINTF(fmt, args...)
+#define DPRINTF(fmt, ...)
 #endif
 
 #define DMA_REGS 4
 #define DMA_SIZE (4 * sizeof(uint32_t))
-#define DMA_MAXADDR (DMA_SIZE - 1)
+/* We need the mask, because one instance of the device is not page
+   aligned (ledma, start address 0x0010) */
+#define DMA_MASK (DMA_SIZE - 1)
 
 #define DMA_VER 0xa0000000
 #define DMA_INTR 1
@@ -58,13 +62,12 @@ typedef struct DMAState DMAState;
 struct DMAState {
     uint32_t dmaregs[DMA_REGS];
     qemu_irq irq;
-    void *iommu, *dev_opaque;
-    void (*dev_reset)(void *dev_opaque);
-    qemu_irq *pic;
+    void *iommu;
+    qemu_irq dev_reset;
 };
 
 /* Note: on sparc, the lance 16 bit bus is swapped */
-void ledma_memory_read(void *opaque, target_phys_addr_t addr, 
+void ledma_memory_read(void *opaque, target_phys_addr_t addr,
                        uint8_t *buf, int len, int do_bswap)
 {
     DMAState *s = opaque;
@@ -85,7 +88,7 @@ void ledma_memory_read(void *opaque, target_phys_addr_t addr,
     }
 }
 
-void ledma_memory_write(void *opaque, target_phys_addr_t addr, 
+void ledma_memory_write(void *opaque, target_phys_addr_t addr,
                         uint8_t *buf, int len, int do_bswap)
 {
     DMAState *s = opaque;
@@ -119,12 +122,12 @@ static void dma_set_irq(void *opaque, int irq, int level)
 {
     DMAState *s = opaque;
     if (level) {
-        DPRINTF("Raise ESP IRQ\n");
+        DPRINTF("Raise IRQ\n");
         s->dmaregs[0] |= DMA_INTR;
         qemu_irq_raise(s->irq);
     } else {
         s->dmaregs[0] &= ~DMA_INTR;
-        DPRINTF("Lower ESP IRQ\n");
+        DPRINTF("Lower IRQ\n");
         qemu_irq_lower(s->irq);
     }
 }
@@ -156,7 +159,7 @@ static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
     DMAState *s = opaque;
     uint32_t saddr;
 
-    saddr = (addr & DMA_MAXADDR) >> 2;
+    saddr = (addr & DMA_MASK) >> 2;
     DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
             s->dmaregs[saddr]);
 
@@ -168,7 +171,7 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
     DMAState *s = opaque;
     uint32_t saddr;
 
-    saddr = (addr & DMA_MAXADDR) >> 2;
+    saddr = (addr & DMA_MASK) >> 2;
     DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
             s->dmaregs[saddr], val);
     switch (saddr) {
@@ -178,7 +181,8 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
             qemu_irq_lower(s->irq);
         }
         if (val & DMA_RESET) {
-            s->dev_reset(s->dev_opaque);
+            qemu_irq_raise(s->dev_reset);
+            qemu_irq_lower(s->dev_reset);
         } else if (val & DMA_DRAIN_FIFO) {
             val &= ~DMA_DRAIN_FIFO;
         } else if (val == 0)
@@ -196,14 +200,14 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 }
 
 static CPUReadMemoryFunc *dma_mem_read[3] = {
-    dma_mem_readl,
-    dma_mem_readl,
+    NULL,
+    NULL,
     dma_mem_readl,
 };
 
 static CPUWriteMemoryFunc *dma_mem_write[3] = {
-    dma_mem_writel,
-    dma_mem_writel,
+    NULL,
+    NULL,
     dma_mem_writel,
 };
 
@@ -238,14 +242,12 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id)
 }
 
 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
-                       void *iommu, qemu_irq **dev_irq)
+                       void *iommu, qemu_irq **dev_irq, qemu_irq **reset)
 {
     DMAState *s;
     int dma_io_memory;
 
     s = qemu_mallocz(sizeof(DMAState));
-    if (!s)
-        return NULL;
 
     s->irq = parent_irq;
     s->iommu = iommu;
@@ -254,17 +256,10 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
     cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
 
     register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
-    qemu_register_reset(dma_reset, s);
+    qemu_register_reset(dma_reset, 0, s);
     *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
 
-    return s;
-}
-
-void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque),
-                                void *dev_opaque)
-{
-    DMAState *s = opaque;
+    *reset = &s->dev_reset;
 
-    s->dev_reset = dev_reset;
-    s->dev_opaque = dev_opaque;
+    return s;
 }